An FPGA-based parameter calculation optimization system and method

Abstract

The present invention relates to the field of radio frequency technology, and provides a parameter calculation optimization system and method based on FPGA. The parameter calculation optimization system is integrated in a field programmable gate array and includes a multi-stage calculation pipeline module, a multi-stage cache module, and a control module. The multi-stage calculation pipeline module decomposes and sorts the impedance matching parameter calculation process, reads the parameters required for calculation from the multi-stage cache module, and executes the decomposed calculation steps according to the sorting, finally obtaining the impedance matching parameter calculation result. The multi-stage cache module caches the parameters required for the multi-stage calculation pipeline module to execute the corresponding sorted calculation steps. The control module coordinates the read and write operations of the multi-stage calculation pipeline module and the multi-stage cache module, controls the parameter transfer and the start of the decomposed calculation steps. The present invention reduces the calculation complexity, ensures the consistency of the timestamps of different parameter calculation results, realizes the synchronous output of parameters, significantly reduces the calculation delay, and improves the system performance.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency technology, and particularly to a parameter calculation optimization system and method based on FPGA. Background Art

[0002] In a radio frequency plasma system, a radio frequency power supply provides energy for a reaction chamber to initiate plasma. In order to effectively load the power of the radio frequency power supply to the reaction chamber, the output impedance of the power supply needs to be matched with the impedance of the reaction chamber. Usually, a matcher is added between the radio frequency power supply and the reaction chamber to achieve impedance matching. The matcher includes a sensor, an arithmetic unit, and an execution unit. The matcher works on the transmission line between the radio frequency power supply and the reaction chamber. The sensor monitors the amplitude, phase angle, and frequency values of voltage and current in real time, and transmits these parameters to the arithmetic unit to calculate impedance admittance, forward power, reflected power, etc. The execution unit controls a variable capacitor according to the calculation result to achieve impedance matching.

[0003] The matching process involves various parameter calculations, specifically including resistance, reactance, conductance, susceptance, phase difference, reflection coefficient, etc. These parameter calculations are characterized by high computational complexity and asynchronous timestamps, which increase the overall calculation delay. The parameters calculated faster (such as the phase difference) will be overwritten by new data, resulting in the output parameters not belonging to the same dataset at the same moment, affecting subsequent analysis and applications. Summary of the Invention

[0004] The present invention provides a parameter calculation optimization system and method based on FPGA to solve the defects of high computational complexity and asynchronous timestamps in the prior art. The present invention reduces the computational complexity, ensures that the timestamps of different parameter calculation results are consistent, realizes synchronous output of parameters, significantly reduces the calculation delay, and improves the system performance.

[0005] The present invention provides a parameter calculation optimization system based on FPGA. The parameter calculation optimization system is integrated in a field programmable gate array and includes a multi-stage calculation pipeline module, a multi-stage cache module, and a control module. The multi-stage calculation pipeline module is used to decompose and sort the impedance matching parameter calculation process, read the parameters required for calculation from the multi-stage cache module, and execute the decomposition calculation steps according to the sorting, and finally obtain the impedance matching parameter calculation result. Parallel calculation of different parameters is supported in the same-level calculation steps. The multi-stage cache module is used to cache the parameters required for the multi-stage calculation pipeline module to execute the corresponding sorting calculation steps. The control module is used to coordinate the read and write operations of the multi-stage calculation pipeline module and the multi-stage cache module, control parameter transfer, and start the decomposition calculation steps.

[0006] A parameter calculation optimization system based on FPGA provided by the present invention, wherein the multi-stage calculation pipeline module includes multi-stage sub-calculation modules; the multi-stage cache module includes multi-stage sub-cache modules; the multi-stage sub-calculation modules and the multi-stage sub-cache modules correspond to each other one by one; the control module is specifically used for generating read signals, write signals and calculation start signals; the sub-cache module is used for writing the parameters required by the current-stage sub-calculation module when the write signal is valid; the sub-calculation module is used for reading parameters from the current-stage sub-cache module when the read signal is valid; and when the calculation start signal is valid, starting to execute the parameter calculation steps of the current stage to obtain the parameter calculation results of the current stage.

[0007] A parameter calculation optimization system based on FPGA provided by the present invention, the parameter calculation results of the current-stage sub-calculation unit are used to be transferred to the next-stage sub-calculation module and / or the sub-cache module.

[0008] A parameter calculation optimization system based on FPGA provided by the present invention, the read signal, the write signal and the calculation start signal are all valid at high or low levels.

[0009] A parameter calculation optimization system based on FPGA provided by the present invention, the multi-stage calculation pipeline module is specifically used for dividing the impedance matching parameter calculation process into ten calculation steps, and the calculation types include numerical operations, function calculations, iterative algorithms and complex number operations.

[0010] The present invention also provides a parameter calculation optimization method based on FPGA, including: decomposing and sorting the impedance matching parameter calculation process, reading the parameters required for the calculation, and executing the decomposed calculation steps according to the sorting to finally obtain the impedance matching parameter calculation results; supporting parallel calculations of different parameters in the same-level calculation steps; caching the parameters required for executing the corresponding sorted calculation steps; coordinating read and write operations, and controlling the parameter transfer and the start of the decomposed calculation steps.

[0011] The present invention also provides a matcher, including the above-mentioned parameter calculation optimization system based on FPGA.

[0012] The present invention also provides a radio frequency plasma system, including the above-mentioned matcher, radio frequency power supply and reaction chamber.

[0013] The present invention also provides an electronic device, including a memory, a processor and a computer program stored on the memory and running on the processor, and when the processor executes the computer program, it implements the parameter calculation optimization method based on FPGA as described in any one of the above.

[0014] The present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the FPGA-based parameter calculation optimization method as described in any one of the above.

[0015] The present invention provides an FPGA-based parameter calculation optimization system and method. The parameter calculation optimization system is integrated in a field programmable gate array and includes a multi-stage calculation pipeline module, a multi-stage cache module, and a control module. The multi-stage calculation pipeline module decomposes and sorts the impedance matching parameter calculation process, reads the parameters required for calculation from the multi-stage cache module, and executes the decomposed calculation steps according to the sorting, finally obtaining the impedance matching parameter calculation result. Parallel calculation of different parameters is supported in the same-level calculation steps. The multi-stage cache module caches the parameters required for the multi-stage calculation pipeline module to execute the corresponding sorted calculation steps. The control module coordinates the read and write operations of the multi-stage calculation pipeline module and the multi-stage cache module, controls the parameter transfer, and starts the decomposed calculation steps. The present invention reduces the calculation complexity, ensures the consistency of the timestamps of different parameter calculation results, realizes the synchronous output of parameters, significantly reduces the calculation delay, and improves the system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 It is a schematic structural diagram of an FPGA-based parameter calculation optimization system provided by the present invention.

[0018] Figure 2 It is a schematic principle diagram of an FPGA-based parameter calculation optimization system provided by the present invention.

[0019] Figure 3 It is a schematic flowchart of an FPGA-based parameter calculation optimization method provided by the present invention.

[0020] Figure 4 It is a schematic structural diagram of an electronic device provided by the present invention.

[0021] Reference Signs:

[0022] 1: Multi-stage calculation pipeline module; 2: Multi-stage cache module; 3: Control module. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] To make the objectives, technical solutions and advantages of the present invention more clear, the following will clearly and completely describe the technical solutions in the present invention in conjunction with the accompanying drawings in the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without making creative efforts fall within the scope of protection of the present invention.

[0024] The matcher involves various parameter calculations during the impedance matching process, specifically including resistance, reactance, conductance, susceptance, phase difference, reflection coefficient, etc. The calculations of these parameters have the following characteristics:

[0025] High computational complexity: The calculation of some parameters such as the reflection coefficient involves complex operation processes (such as the calculation of each factor in the division operation), increasing the overall calculation delay.

[0026] Timestamp out-of-sync: Parameters calculated faster (such as the phase difference) will be overwritten by new data, resulting in the output parameters not belonging to the data set at the same moment, affecting subsequent analysis and applications.

[0027] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a parameter calculation optimization system based on FPGA provided by the present invention.

[0028] The present invention provides a parameter calculation optimization system based on FPGA. The parameter calculation optimization system is integrated in a field programmable gate array and includes a multi-stage calculation pipeline module 1, a multi-stage cache module 2, and a control module 3. The multi-stage calculation pipeline module 1 is used to decompose and sort the impedance matching parameter calculation process, read the parameters required for the calculation from the multi-stage cache module 2, and execute the decomposed calculation steps according to the sorting, and finally obtain the impedance matching parameter calculation result; parallel calculation of different parameters is supported in the same-level calculation steps. The multi-stage cache module 2 is used to cache the parameters required for the multi-stage calculation pipeline module 1 to execute the corresponding sorting calculation steps. The control module 3 is used to coordinate the read and write operations of the multi-stage calculation pipeline module 1 and the multi-stage cache module 2, and control the parameter transfer and the start of the decomposed calculation steps.

[0029] This embodiment details the specific implementation of a parameter calculation optimization system based on FPGA. The system is integrated in a field programmable gate array (FPGA) to improve the calculation efficiency of impedance matching parameters in a radio frequency plasma system. The system includes a multi-stage calculation pipeline module 1, a multi-stage cache module 2, and a control module 3.

[0030] The multi - level calculation pipeline module 1 is the core of the system. It decomposes the complex impedance matching parameter calculation process into multiple independent calculation steps. These steps are sorted according to the calculation dependency relationship and a pipeline is constructed to ensure the correctness and efficiency of the calculation. For example, when calculating the resistance R and reactance X, the formulas and can be used. Where Z is the impedance, is the phase difference. The pipeline module reads the necessary parameters, such as the impedance Z and the phase difference , from the multi - level cache module 2 and executes the decomposed calculation steps. In the same - level calculation steps, the calculations of different parameters can be executed in parallel to further improve the calculation speed. The multi - level cache module 2 is used to cache the parameters required by the multi - level calculation pipeline module 1 when executing the corresponding sorted calculation steps. The cache module adopts the first - in - first - out (FIFO) strategy to ensure the timeliness of the parameters and the continuity of the calculation. The cache depth is dynamically adjusted according to the latency of the pipeline to prevent data overflow and save hardware resources. The control module 3 is responsible for coordinating the read and write operations between the multi - level calculation pipeline module 1 and the multi - level cache module 2. It controls the transfer of parameters and the start of the decomposed calculation steps to ensure data synchronization and calculation correctness. The control module 3 manages the data flow and calculation process through internal logic and timing control, enabling the entire system to operate efficiently and stably.

[0031] Through this design, the system of this embodiment can achieve efficient parameter calculation optimization on the FPGA, and is particularly suitable for application scenarios that require real - time processing and high - precision calculation, such as impedance matching of radio - frequency plasma systems.

[0032] Compared with the prior art, the beneficial effects of the present invention are:

[0033] Synchronous output: Adopting the FIFO cache mechanism to ensure that the timestamps of the calculation results of different parameters are consistent and achieve synchronous output of parameters.

[0034] Accelerated calculation: By means of pipeline design and re - sorting to optimize the calculation process, significantly reducing the calculation latency and improving the system performance.

[0035] Please refer to Figure 2 , Figure 2 which is the schematic diagram of the principle of a parameter calculation optimization system based on FPGA provided by the present invention.

[0036] As a preferred embodiment, the multi-stage computing pipeline module 1 includes multi-stage sub-computing modules; the multi-stage cache module 2 includes multi-stage sub-cache modules; the multi-stage sub-computing modules and the multi-stage sub-cache modules correspond one by one; the control module 3 is specifically configured to generate read signals, write signals, and calculation start signals; the sub-cache module is used to write the parameters required by the current-stage sub-computing module when the write signal is valid; the sub-computing module is used to read parameters from the current-stage sub-cache module when the read signal is valid; and when the calculation start signal is valid, start executing the parameter calculation steps of the current stage to obtain the parameter calculation result of the current stage.

[0037] In this embodiment, the multi-stage computing pipeline module 1 is composed of multiple sub-computing modules, and each sub-computing module is responsible for executing a specific computing task. Similarly, the multi-stage cache module 2 is composed of multiple sub-cache modules, and each sub-cache module is used to store the parameters required by the corresponding sub-computing module. Each sub-computing module corresponds one by one with its corresponding sub-cache module to ensure the accurate transfer of parameters and the smooth progress of calculations.

[0038] The function of the control module 3 in this embodiment is to generate read signals, write signals, and calculation start signals. The read signal is used to instruct the sub-computing module to read parameters from its corresponding sub-cache module, the write signal is used to instruct the sub-cache module to write the parameters required by the current-stage sub-computing module, and the calculation start signal is used to start the calculation process of the sub-computing module.

[0039] The specific operation process is as follows: when the control module 3 issues a write signal, the parameters required for the calculation are written into the current-stage sub-cache module. These parameters may include voltage amplitude values , current amplitude values , and phase differences , etc. When the read signal is valid, the sub-computing module reads these parameters from its corresponding current-stage sub-cache module. For example, if the sub-computing module is responsible for calculating the resistance R, it will use the formula to calculate the result.

[0040] Once the calculation start signal is valid, the sub-computing module starts to execute its calculation task. After the calculation is completed, the result can be used for the next-stage calculation or output to an external system. This modular design allows the system to flexibly handle different computing tasks and can adapt to different computing requirements by increasing or decreasing the number of sub-computing modules and sub-cache modules.

[0041] Through this design, the system of this embodiment can achieve efficient parameter calculation while maintaining a high degree of flexibility and scalability. This makes the system particularly suitable for application scenarios that require fast and accurate calculations.

[0042] As a preferred embodiment, the parameter calculation result of the current - level sub - computing unit is used to be transmitted to the next - level sub - computing module and / or sub - cache module.

[0043] In this embodiment, the transmission mechanism of the parameter calculation result between different sub - computing modules and sub - cache modules will be further described in detail. After each level of sub - computing module completes its computing task, its result is not only used for the output of the current level, but can also be transmitted to the next - level sub - computing module and / or sub - cache module for further computing use.

[0044] For example, consider a multi - stage pipeline computing process, where the first - level sub - computing module is responsible for calculating the phase difference between voltage and current , using the formula . Where and are the phases of voltage and current respectively. The calculated phase difference will be transmitted to the second - level sub - computing module, which may be responsible for calculating .

[0045] Of course, after receiving the calculation result of the first - level module, the second - level sub - computing module can also read the phase difference from its corresponding sub - cache module when the calculation start signal is valid, and start to calculate . can be used in other parts of the system, such as used by control module 3 to adjust system parameters, or transmitted to the third - level sub - computing module for further calculation.

[0046] In addition, to improve the flexibility and efficiency of the system, the sub - cache module can be designed to support the temporary storage and fast access of parameters. In this way, even if there are short - term delays or interruptions during the computing process, the system can resume computing from the breakpoint without having to start the entire computing process again.

[0047] Through this design, the system of this embodiment can effectively utilize the parameter calculation results, reduce repeated calculations, and improve computing efficiency. At the same time, this modular and pipeline - type computing architecture also makes the system easy to expand and maintain, and is suitable for various application scenarios that require efficient parameter calculation.

[0048] As a preferred embodiment, the read signal, write signal, and calculation start signal are all valid at high or low levels.

[0049] In this embodiment, the specific working mechanism of the read signal, write signal, and calculation start signal when they are valid at high level will be elaborated in detail. Control module 3 is responsible for generating these signals to ensure the correct reading and writing of data and the accurate execution of calculation steps.

[0050] When the read signal rd_en is at a high level, the sub-computation module reads the necessary parameters from its corresponding sub-buffer module. For example, if it is necessary to calculate the resistance R, the sub-computation module will, under the trigger of the high-level read signal, read the voltage amplitude value , the current amplitude value and the phase difference from the sub-buffer module, and then use the formula to calculate the resistance value.

[0051] Similarly, when the write signal wr_en is at a high level, the sub-buffer module will receive the calculation result from the previous-level sub-computation module and store it for use by the next-level sub-computation module. For example, if the sub-computation module calculates the phase difference , this result will be written into the sub-buffer module under the trigger of the high-level write signal.

[0052] When the calculation enable signal is valid at a high level, the sub-computation module starts to execute its calculation task. For example, once the sub-computation module receives all the necessary parameters and the calculation enable signal becomes high, it will start to calculate, such as using the formula to calculate the transmitted power .

[0053] This signal design with a high-level active simplifies the signal processing logic because the high level usually represents the active or enabled state. In FPGA design, this can be achieved by setting the clock signal of the flip-flop to be triggered at a high level, ensuring that data reading, writing, and calculation operations are performed during the high level of the signal.

[0054] In addition, the signal design with a high-level active helps to reduce signal glitches and jitters, improving the stability and reliability of the system. In the actual FPGA implementation, these signals can be generated and controlled through logic gate circuits and flip-flops to ensure the precise timing of the signals and the coordinated operation of the system. In this way, the system of this embodiment can efficiently and accurately execute the parameter calculation task and is applicable to application scenarios that require fast response and high-precision calculation.

[0055] As a preferred embodiment, the multi-stage calculation pipeline module 1 is specifically configured to divide the impedance matching parameter calculation process into ten calculation steps, and the calculation types include numerical operations, function calculations, iterative algorithms, and complex number operations.

[0056] After receiving the amplitude values and phase values of the voltage and current, the system needs to calculate the following parameters: resistance, reactance, conductance, susceptance, voltage-current phase difference, sine and cosine values of the phase difference, reflection coefficient and its real and imaginary parts, transmitted power, forward power, and reflected power.

[0057] For the signals at a certain moment, the time required to calculate the above parameters is different. For example, the phase difference only requires the output of combinational logic and the calculation of trigonometric functions, multiplication, division, square root and other operations, which takes a long time. As a result, when outputting the parameters, they are not output at the same moment. In continuous signal acquisition and calculation, if the parameters with shorter time delays are not cached, the parameters at the current moment will be overwritten by the parameters at subsequent moments, and the final obtained parameters will not have the same timestamp.

[0058] First, it is necessary to perform calculation reordering and pipeline splitting according to the parameter formula. In this embodiment, the calculation process of the impedance matching parameters is divided into ten specific calculation steps, and each step is responsible for different types of calculation tasks, including numerical operations, function calculations, iterative algorithms, and complex number operations.

[0059] In the first-level pipeline, the input valid bit input_valid is set high, s1_data is set high, and the first-level sub-calculation module needs to calculate the impedance Z, admittance Y, and phase difference , using the formula , and . This step involves division operations and requires a pipelined divider to improve the speed. This level also needs to use the first-level sub-cache module stage1 to cache the voltage amplitude value V mag , the current amplitude value I mag , and the phase difference . When the divider completes the calculation, the first-level calculation start signal s1_valid is set high, the impedance Z and admittance Y are output, and s2_data is set high. The first-level sub-calculation module reads the voltage amplitude value, current amplitude value, and phase difference in the first-level first-level sub-cache module FIFO_S1, sends them to the next-level sub-calculation module stage2, and writes them to the next-level sub-cache module FIFO_S2. din is the input of the sub-calculation module, and dout is the output of the sub-calculation module.

[0060] In the second-level pipeline, the second-level sub-calculation module needs to calculate the sine and cosine values of the phase angle, using the CORDIC algorithm to calculate and . After the calculation is completed, the second-level calculation start signal s2_valid is set high, the sine and cosine values are output, and s3_data is set high. The second-level sub-calculation module reads the voltage amplitude value, current amplitude value, phase difference, impedance, and admittance in the second-level sub-cache module FIFO_S2, sends them to the third-level sub-calculation module, and writes them to the third-level sub-cache module.

[0061] In the third-level pipeline, the third-level sub-calculation module needs to calculate the resistance R, reactance X, conductance G a and susceptance B b , as well as the factors required for subsequent calculations , z2 , use the formula , , and . All these steps are multiplication operations and require the same number of clock cycles, so they are calculated in the first-level pipeline. After the multiplication operation is completed, the third-level calculation start signal is set high, the calculation result is output, and the data in the third-level sub-cache module is read, sent to the fourth-level sub-calculation module, and written into the fourth-level sub-cache module.

[0062] In the fourth-level pipeline, the fourth-level sub-calculation module needs to calculate the factors of the real and imaginary parts of the reflection coefficient, that is, the numerator and denominator, which are addition and subtraction operations. After the calculation is completed, the fourth-level calculation start signal is set high, the calculation result is output, and the data in the fourth-level sub-cache module is read, sent to the fifth-level sub-calculation module, and written into the fifth-level sub-cache module.

[0063] In the fifth-level pipeline, the fifth-level sub-calculation module needs to calculate the real and imaginary parts of the reflection coefficient, using the formula and . This step is a division operation, and a pipelined divider is used to improve the operation speed. After the calculation is completed, the fifth-level calculation start signal is set high, the calculation result is output, and the data in the fifth-level sub-cache module is read, sent to the sixth-level sub-calculation module, and written into the sixth-level sub-cache module. Some calculation factors do not participate in the subsequent calculations, and this data is discarded after the end of this level of pipeline to save hardware resources.

[0064] In the sixth-level pipeline, the sixth-level sub-calculation module needs to calculate the reflection coefficient, using the formula , that is, a square root operation, and the CORDIC algorithm is used to calculate the square root. After the calculation is completed, the sixth-level calculation start signal is set high, the calculation result is output, and the data in the sixth-level sub-cache module is read, sent to the seventh-level sub-calculation module, and written into the seventh-level sub-cache module.

[0065] In the seventh-level pipeline, the seventh-level sub-calculation module needs to calculate the square value of the reflection coefficient and the transmitted power , use the formula , and this step is a multiplication operation. After the calculation is completed, the seventh-level calculation start signal is set high, the calculation result is output, and the data in the seventh-level sub-cache module is read, sent to the eighth-level sub-calculation module, and written into the eighth-level sub-cache module.

[0066] In the eighth-level pipeline, the eighth-level sub-calculation module needs to calculate the denominator of the forward power, which is a subtraction operation. After the calculation is completed, the eighth-level calculation start signal is set high, the calculation result is output, and the data in the eighth-level sub-cache module is read, sent to the ninth-level sub-calculation module, and written into the ninth-level sub-cache module.

[0067] In the ninth - stage pipeline, the ninth - stage sub - calculation module needs to calculate the forward power , using the formula . This step is a division operation, and a pipelined divider is used to improve the operation speed. After the calculation is completed, the ninth - stage calculation start signal is set high, the calculation result is output, the data in the ninth - stage sub - cache module is read, sent to the tenth - stage sub - calculation module, and written into the tenth - stage sub - cache module. And the calculation factor is discharged from the pipeline to save hardware resources.

[0068] In the tenth - stage pipeline, the tenth - stage sub - calculation module needs to calculate the reflected power , using the formula . This step is a multiplication operation. This stage is the last stage of the pipeline. After the calculation is completed, the tenth - stage calculation start signal is set high, the calculation result is output, other parameters in the tenth - stage sub - cache module are read, and output simultaneously, realizing the function of synchronous output of parameter timestamps.

[0069] Next, the parameter calculation optimization method based on FPGA provided by the present invention is described. The parameter calculation optimization method based on FPGA described below can be correspondingly referred to the parameter calculation optimization system based on FPGA described above.

[0070] Please refer to Figure 3 , Figure 3 , which is a schematic flow chart of a parameter calculation optimization method based on FPGA provided by the present invention.

[0071] The present invention also provides a parameter calculation optimization method based on FPGA, including:

[0072] 301: Decompose and sort the impedance - matching parameter calculation process, read the parameters required for the calculation, and execute the decomposed calculation steps according to the sort, and finally obtain the impedance - matching parameter calculation result; support parallel calculation of different parameters in the same - level calculation steps;

[0073] 302: Cache the parameters required to execute the corresponding sorted calculation steps;

[0074] 303: Coordinate read - write operations, control parameter transfer, and start of the decomposed calculation steps.

[0075] Next, the matcher provided by the present invention is described. The matcher described below can be correspondingly referred to the parameter calculation optimization system based on FPGA described above.

[0076] The present invention also provides a matcher, including the above - mentioned parameter calculation optimization system based on FPGA.

[0077] The radio frequency plasma system provided by the present invention will be described below. The radio frequency plasma system described below can be correspondingly referred to the FPGA-based parameter calculation optimization system described above.

[0078] The present invention also provides a radio frequency plasma system, including the above-mentioned matcher, radio frequency power supply and reaction chamber.

[0079] Figure 4 The structural schematic diagram of an electronic device is exemplified, as Figure 4 shown, the electronic device may include: a processor 401, a communication interface 402, a memory 403, and a communication bus 404. Among them, the processor 401, the communication interface 402, and the memory 403 complete mutual communication through the communication bus 404. The processor 401 can call the logical instructions in the memory 403 to execute the FPGA-based parameter calculation optimization method, which includes: decomposing and sorting the impedance matching parameter calculation process, reading the parameters required for the calculation, and performing the decomposed calculation steps according to the sorting, and finally obtaining the impedance matching parameter calculation result; supporting parallel calculation of different parameters in the same-level calculation steps; caching the parameters required for executing the corresponding sorting calculation steps; coordinating read and write operations, controlling parameter transfer and the start of the decomposed calculation steps.

[0080] In addition, when the logical instructions in the above-mentioned memory 403 can be implemented in the form of software functional units and sold or used as an independent product, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0081] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the FPGA-based parameter calculation optimization method provided by the above-mentioned various methods. The method includes: decomposing and sorting the impedance matching parameter calculation process, reading the parameters required for the calculation, and performing the decomposed calculation steps according to the sorting to finally obtain the impedance matching parameter calculation result; supporting parallel calculation of different parameters in the same-level calculation steps; caching the parameters required for executing the corresponding sorted calculation steps; coordinating the read and write operations, and controlling the parameter transfer and the start of the decomposed calculation steps.

[0082] In another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it is used to execute the FPGA-based parameter calculation optimization method provided by the above-mentioned various methods. The method includes: decomposing and sorting the impedance matching parameter calculation process, reading the parameters required for the calculation, and performing the decomposed calculation steps according to the sorting to finally obtain the impedance matching parameter calculation result; supporting parallel calculation of different parameters in the same-level calculation steps; caching the parameters required for executing the corresponding sorted calculation steps; coordinating the read and write operations, and controlling the parameter transfer and the start of the decomposed calculation steps.

[0083] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative efforts.

[0084] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the above technical solutions, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A parameter calculation optimization system based on FPGA, characterized in that: The parameter calculation optimization system is integrated into a field programmable gate array, and includes a multi-level calculation pipeline module, a multi-level cache module and a control module; The multi-level calculation pipeline module is used to decompose and sort the impedance matching parameter calculation process, read the parameters required for calculation from the multi-level cache module, and perform the decomposed calculation steps in order, and finally obtain the impedance matching parameter calculation results; support parallel calculation of different parameters in the same level calculation steps; The multi-level cache module is used to cache the parameters required by the multi-level calculation pipeline module to execute the corresponding sorting calculation steps; the multi-level cache module adopts a first-in-first-out strategy, and the cache depth is dynamically adjusted according to the delay of the pipeline; The control module is used to coordinate the read and write operations of the multi-level computing pipeline module and the multi-level cache module, and control the parameter transfer and the start of the decomposition computing steps; The multi-level computing pipeline module includes multi-level sub-computing modules; the multi-level cache module includes multi-level sub-cache modules; the multi-level sub-computing modules correspond to the multi-level sub-cache modules one by one; The control module is specifically used to generate a read signal, a write signal and a calculation start signal; The sub-cache module is used to write the parameters required by the sub-computing module of the current level when the write signal is valid; The sub-calculation module is used for reading parameters from the sub-cache module at the current level when the read signal is valid; When the calculation start signal is valid, the parameter calculation step of the current level is started to obtain the parameter calculation result of the current level; The multi-stage calculation pipeline module is specifically used to divide the impedance matching parameter calculation process into ten stages of calculation steps, and the calculation types include numerical calculation, function calculation, iterative algorithm and complex number calculation.

2. The FPGA-based parameter calculation optimization system according to claim 1, characterized in that: The parameter calculation results of the sub-computing units at the current level are used to be transmitted to the sub-computing modules and / or the sub-cache modules at the next level.

3. The FPGA-based parameter calculation optimization system according to claim 1, characterized in that: The read signal, the write signal and the calculation start signal are all effective at a high or low level.

4. A parameter calculation optimization method based on FPGA, characterized in that: include: The impedance matching parameter calculation process is decomposed and sorted through a multi-level calculation pipeline module, the parameters required for the calculation are read, and the decomposed calculation steps are executed in order to finally obtain the impedance matching parameter calculation results; the parallel calculation of different parameters is supported in the same level calculation steps; Parameters required for executing the corresponding sorting calculation steps are cached through a multi-level cache module; the multi-level cache module adopts a first-in-first-out strategy, and the cache depth is dynamically adjusted according to the delay of the pipeline; Coordinate read and write operations through the control module, control parameter transfer and the initiation of decomposition calculation steps; The multi-level computing pipeline module includes multi-level sub-computing modules; the multi-level cache module includes multi-level sub-cache modules; the multi-level sub-computing modules correspond to the multi-level sub-cache modules one by one; The control module is specifically used to generate a read signal, a write signal and a calculation start signal; The sub-cache module is used to write the parameters required by the sub-computing module of the current level when the write signal is valid; The sub-calculation module is used for reading parameters from the sub-cache module at the current level when the read signal is valid; When the calculation start signal is valid, the parameter calculation step of the current level is started to obtain the parameter calculation result of the current level; The multi-stage calculation pipeline module is specifically used to divide the impedance matching parameter calculation process into ten stages of calculation steps, and the calculation types include numerical calculation, function calculation, iterative algorithm and complex number calculation.

5. A matcher, characterized in that: The invention comprises the FPGA-based parameter calculation and optimization system as described in any one of claims 1 to 3.

6. A radio frequency plasma system, characterized in that: It comprises the matcher, radio frequency power supply and reaction chamber as described in claim 5.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the FPGA-based parameter calculation optimization method as claimed in claim 4 is implemented.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the FPGA-based parameter calculation optimization method as claimed in claim 4 is implemented.

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