A parallel optimization method for FPGA static timing analysis

Abstract

The present application belongs to the field of electronic design automation and static timing analysis, and particularly relates to a parallel optimization method for FPGA static timing analysis, aiming at solving the problems of low calculation efficiency and long compilation time in the prior art. The method comprises: memory layout optimization of a timing graph and timing constraints according to a constructed FPGA-oriented STA data structure; task decomposition, and parallel execution of the calculation tasks of nodes and edges of each level by multiple parallel kernels, and sequential execution of different levels by a single CPU thread; during execution, the timing graph is traversed to mark nodes and edges to be updated; through bidirectional traversal calculation, the effective arrival time of a node and the effective requirement time of the node are obtained, the critical path in FPGA timing static analysis is determined, and a parallel optimization report for FPGA static timing analysis is generated. The present application improves the calculation efficiency in static timing analysis and shortens the compilation time.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of electronic design automation and static timing analysis, and particularly relates to a parallel optimization method for FPGA static timing analysis. BACKGROUND

[0002] With the rapid growth of integrated circuit design scale, especially in the field of FPGA, the increase of design complexity and timing constraints makes static timing analysis (STA) a critical design verification link. STA is a core tool for evaluating whether a digital circuit design meets timing requirements, and is widely used in the placement and routing process of FPGA to ensure that the circuit operates correctly within the predetermined clock cycle. However, with the increase of design scale and the diversification of clock domains and timing angles, the computational complexity of STA also increases significantly, which in turn leads to the prolongation of FPGA compilation time.

[0003] Currently, traditional STA relies mainly on single-threaded CPU processing. In complex FPGA designs, single-threaded processing cannot meet the demand for fast verification, resulting in low analysis efficiency. In addition, although the parallel computing capability of GPU is superior in some computationally intensive tasks, in STA tasks, due to the bottleneck of data transmission, GPU does not fully exert its potential advantages. Specifically, the data format conversion between CPU and GPU is cumbersome, and the data copying time between main memory and video memory is long, which often offsets the acceleration effect of GPU kernel computation. STA tasks have strong data dependency and require frequent data access and synchronization, which makes GPU inefficient in processing these tasks.

[0004] Therefore, although some existing methods attempt to use GPU to accelerate static timing analysis and show the advantage of GPU in kernel computation speed, due to the limitation of data transmission and synchronization overhead, the overall performance improvement is limited. At the same time, making full use of the parallel computing capability of multi-core CPU and combining the computing advantages of GPU, avoiding the overhead of frequent data transmission between different storage units, has become a more potential direction for accelerating STA.

[0005] Therefore, how to effectively utilize the parallel computing capability of multi-core CPU and combine the computing advantages of GPU, optimize the processing flow of STA, and reduce the data synchronization and transmission overhead in timing analysis, has become an important challenge in the field of electronic design automation (EDA). By improving the running efficiency of STA, the time of FPGA design verification can be significantly shortened, and the quality of design optimization can be further improved. SUMMARY

[0006] In order to solve the above problems in the prior art, that is, to solve the problems of low calculation efficiency and long compilation time in the prior art static timing analysis, especially for the insufficient efficiency of single-thread CPU processing in complex FPGA design, and the limited performance improvement of GPU parallel computing due to data transmission bottleneck, the present application provides a parallel optimization method for FPGA static timing analysis, which comprises the following steps:

[0007] In step S1, the timing diagram and timing constraints of FPGA static timing analysis are obtained, and the memory layout optimization is performed on the timing diagram and the timing constraints according to the constructed FPGA-oriented STA data structure; the timing diagram comprises nodes, edges, delay models and timing analysis results;

[0008] In step S2, the task decomposition is performed on the timing diagram after the memory layout optimization, and the calculation tasks of the nodes and edges in each level are allocated to multiple parallel kernels for parallel execution, and the different levels are allocated to a single CPU thread for sequential execution; the parallel kernel comprises a CPU core and a GPU core;

[0009] In step S3, during execution, the timing diagram is traversed through a preset traversal strategy, and the nodes and edges to be updated are marked; the preset traversal strategy comprises full update and incremental update;

[0010] In step S4, in combination with the parallel computing strategy, the effective arrival time of the node and the effective requirement time of the node are obtained through bidirectional traversal calculation; the critical path in the FPGA timing static analysis is determined according to the effective arrival time of the node and the effective requirement time of the node, and then the parallel optimization report of the FPGA static timing analysis is generated.

[0011] In some preferred embodiments, the memory layout optimization is performed on the timing diagram and the timing constraints according to the constructed FPGA-oriented STA data structure, and the method comprises the following steps:

[0012] The structure of the timing diagram is optimized into a hierarchical structure, and the data of the timing diagram is stored in an array structure body, and only static node information and edge information are stored;

[0013] The timing diagram is stored as a bidirectional edge timing diagram when stored.

[0014] In some preferred embodiments, the timing diagram verification and hierarchical query step is further included after the memory layout optimization and before the task decomposition:

[0015] According to the hierarchical traversal order of the timing diagram after the memory layout optimization, the data is initialized and accessed to verify that the data access order during traversal is consistent with the storage order in the memory.

[0016] In some preferred embodiments, the task decomposition is performed on the memory layout optimized time sequence diagram, and the method is as follows:

[0017] The nodes to be processed in the memory layout optimized time sequence diagram are obtained, and parallel kernel parameters are assigned. A related function library is used to perform task decomposition on the memory layout optimized time sequence diagram; the related function library includes TBB and CUDA.

[0018] The task decomposition on the memory layout optimized time sequence diagram includes fine-grained task decomposition and coarse-grained task decomposition.

[0019] The fine-grained task decomposition is to divide each level of the memory layout optimized time sequence diagram into different fine-grained tasks, and to assign the calculation tasks of the nodes and edges of each level to multiple parallel kernels for parallel execution; the fine-grained tasks include arrival time pre-traversal, arrival time traversal, demand time pre-traversal, demand time traversal, relaxation update, and state reset.

[0020] The coarse-grained task decomposition is to sequentially execute different levels of the memory layout optimized time sequence diagram by a single CPU thread.

[0021] In some preferred embodiments, the full update is to completely re-analyze the time sequence diagram by using serial traversal each time the update is called; the full update is used in the initialization construction and reset phase.

[0022] The incremental update is to mark invalid edges and nodes to be updated during the previous round of traversal, to only traverse the nodes marked to be updated and to determine the nodes to be added to the update queue according to the invalid edges during the arrival time and demand time traversal, to calculate the relaxation values of the modified nodes and to perform update; the modified nodes are the nodes whose relaxation values in the update queue change during the traversal calculation; the incremental update is used in the parallel calculation phase.

[0023] In some preferred embodiments, the valid arrival time of a node is obtained, and the method is as follows:

[0024] In step S411, the arrival time of all input pins is initialized based on the time sequence constraints.

[0025] In step S412, the delay time of each edge is added to the arrival time of the source node of the edge to calculate the arrival time of the edge.

[0026] In step S413, the maximum setup time or minimum hold time of all input edge arrival times is calculated at each downstream node, and is stored as the node arrival time.

[0027] Step S414, judging whether the step S3 is incremental update, if not, executing the steps S412-S413 in a loop until the valid arrival time of all nodes is obtained, otherwise, executing the steps S412-S413 in a loop until the valid arrival time of the node in the update queue is obtained.

[0028] In some preferred embodiments, the valid requirement time of all nodes is obtained by:

[0029] Step S421, initializing the time requirement of all output pins according to the timing constraints;

[0030] Step S422, subtracting the delay time of each edge from the requirement time of the sink node of the edge to calculate the requirement time of the edge;

[0031] Step S423, calculating the minimum setup time or the maximum hold time of the requirement time of all input edges in each upstream node and storing it as the node requirement time;

[0032] Step S424, judging whether the step S3 is incremental update, if not, executing the steps S422-S423 in a loop until the valid requirement time of all nodes is obtained, otherwise, executing the steps S422-S423 in a loop until the valid requirement time of the node in the update queue is obtained.

[0033] In some preferred embodiments, when calculating the valid arrival time of all nodes or the valid requirement time of all nodes, a parallel computing strategy is used for parallel execution:

[0034] By processing the timing graph in stages, one level is processed at a time, and two parallel kernel clusters are allocated in each level, one of which is responsible for segmented addition and the other is responsible for segmented maximum reduction;

[0035] The processing procedure of the parallel kernel cluster responsible for segmented addition is that each kernel in the parallel kernel cluster is assigned an edge, and one edge calculation is performed to obtain the arrival time of the edge or the requirement time of the edge;

[0036] The processing procedure of the parallel kernel cluster responsible for segmented maximum reduction is that each parallel kernel in the parallel kernel cluster is assigned to a sink node of a current level, all arrival times or requirement times of edges related to the sink node are traversed, and a maximum reduction operation is performed to obtain the final arrival time or requirement time.

[0037] In some preferred embodiments, according to the valid arrival time of all nodes and the valid requirement time of all nodes, the critical path in the FPGA timing static analysis is determined by:

[0038] The difference between the effective arrival time and the effective demand time of all nodes in each path is calculated, and the path corresponding to the zero difference or the minimum difference is taken as the critical path.

[0039] In some preferred embodiments, a parallel optimization report of FPGA static timing analysis is generated by recording and extracting the parameter values of all intermediate links after all critical path calculations are completed in parallel computing, and generating a readable parallel optimization report of FPGA static timing analysis.

[0040] The present application has the following beneficial effects:

[0041] The present application optimizes memory access efficiency, reduces synchronization overhead, improves concurrency performance, improves FPGA static timing analysis parallel computing efficiency by several times, shortens compilation time, and significantly improves timing analysis performance in large-scale FPGA design, which can better meet the efficient analysis requirements of timing in modern FPGA design.

[0042] 1) The present application constructs a hierarchical memory layout to ensure that the nodes and edges of each layer are stored continuously in memory, matching the access order during traversal and reducing the probability of cache invalidation. Through such memory optimization layout, the efficiency of kernel data access is improved, especially in multi-core parallel processing, each kernel can quickly obtain the required data, further accelerating the timing analysis process. Compared with the prior art, the memory layout of the present application is more targeted and can significantly improve the data access speed in the timing analysis process;

[0043] 2) The present application adopts a parallel processing mode without explicit synchronization, avoiding the thread synchronization overhead caused by lock operation in traditional methods. Through fine-grained allocation of tasks, each thread is only responsible for independent node and edge calculation, avoiding the case of multiple threads competing for the same data, thereby further improving the concurrency performance. Compared with the existing parallel algorithm relying on the lock mechanism, the scheme of the present application can more effectively utilize multi-core resources, improving the efficiency of parallel execution;

[0044] 3) The existing static timing analysis method usually relies on single-thread or limited parallel computing, resulting in low efficiency when facing complex FPGA design. The present application greatly improves the utilization of multi-core CPU and GPU through the strategy of intra-layer parallel processing and inter-layer sequential execution of timing diagrams. The node and edge tasks in each layer are executed by multiple parallel kernels, reducing the waiting time of calculation and fully utilizing the parallel computing capability of modern multi-core processors. Compared with the prior art, the overall computing efficiency of FPGA static timing analysis is improved by 2.9 times, especially in large-scale FPGA design;

[0045] 4)The present application ensures the accuracy of the timing analysis by calculating the maximum arrival time and the minimum required time of the nodes through forward and backward traversal respectively, and determining the critical path by comparison. Compared with the existing single CPU thread or partial parallel scheme, the present application combines parallel computing and sequential execution, ensuring the balance between intra-layer parallelism and inter-layer dependence, which can not only accelerate the calculation, but also avoid the data inconsistency problem caused by concurrency, thereby improving the overall accuracy of the timing analysis. In addition, the combination of inter-layer sequential execution makes the method have greater flexibility when dealing with complex FPGA designs;

[0046] 5)With the increase of the complexity of FPGA design, the performance bottleneck of the prior art on large-scale design is more and more obvious. The present application can effectively meet the timing analysis requirements in complex FPGA design by fine-grained parallelism within the hierarchy and coarse-grained sequential execution between layers, greatly shortening the analysis time. Compared with the traditional method, the timing analysis performance of the present application in large-scale FPGA design is improved by several times or more, which can better meet the efficient analysis requirements of modern FPGA design for timing. BRIEF DESCRIPTION OF DRAWINGS

[0047] Other features, objects, and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments, made with reference to the following drawings.

[0048] Figure 1 is a flowchart of a parallel optimization method for FPGA static timing analysis according to an embodiment of the present application;

[0049] Figure 2 is a flowchart of a parallel optimization method for FPGA static timing analysis according to an embodiment of the present application;

[0050] Figure 3 is a schematic diagram of critical path parallel calculation according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical scheme and advantages of the present application more clear, the technical scheme of the embodiments of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0052] The application will be further described in detail below in conjunction with the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, it should be noted that only the parts related to the application are shown in the drawings for ease of description.

[0053] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0054] A parallel optimization method for FPGA static timing analysis according to a first embodiment of the application, as shown in Figure 1 The method comprises the following steps:

[0055] Step S1, obtaining a timing diagram and timing constraints of FPGA static timing analysis; performing memory layout optimization on the timing diagram and the timing constraints according to the FPGA-oriented STA data structure constructed; the timing diagram comprises nodes, edges, delay models, and timing analysis results;

[0056] Step S2, task decomposition is performed on the timing diagram after memory layout optimization, and after decomposition, the calculation tasks of the nodes and edges within each level are distributed to multiple parallel kernels for parallel execution, and different levels are distributed to a single CPU thread for sequential execution; the parallel kernel comprises a CPU core and a GPU core;

[0057] Step S3, during execution, the timing diagram is traversed through a preset traversal strategy, and the nodes and edges to be updated are marked; the preset traversal strategy comprises full update and incremental update;

[0058] Step S4, in combination with the parallel computing strategy, the effective arrival time of the node and the effective requirement time of the node are obtained through bidirectional traversal calculation; the critical path in the FPGA timing static analysis is determined according to the effective arrival time of the node and the effective requirement time of the node, and then a parallel optimization report of FPGA static timing analysis is generated.

[0059] In order to more clearly illustrate the parallel optimization method for FPGA static timing analysis, the following will be described in conjunction with the drawings Figure 2 The steps of the method according to an embodiment of the application will be described in detail.

[0060] The application aims to optimize the processing flow of STA by fully utilizing the parallel computing capability of multi-core CPU and combining the computing advantage of GPU, reduce the overhead of data synchronization and transmission, thereby significantly improving the speed of static timing analysis, shortening the time of FPGA design verification, and further improving the quality and efficiency of design optimization. Specifically as follows:

[0061] In step S1, a timing diagram and timing constraints of static timing analysis of the FPGA are acquired, and the timing diagram and the timing constraints are subjected to memory layout optimization according to the FPGA-oriented STA data structure constructed;

[0062] In the embodiment, the specific process of the memory layout optimization is as follows:

[0063] In step S101, the FPGA-oriented STA data structure includes two parts of the timing diagram and the timing constraints (i.e., the STA data structure includes a timing diagram data structure and a timing constraint data structure). The timing diagram part contains nodes (including node types, source nodes and sink nodes), edges (including edge types, input and output edges), delay models (including maximum and minimum delays of edges, setup time, hold time, etc.), and timing analysis results (including but not limited to data arrival time, data demand time, clock start and clock capture time, offset time of setup time and hold time). The timing constraint part contains but is not limited to constants, maximum input and output constraints, minimum input and output constraints, setup time constraints and hold time constraints, etc. The data structure corresponding operations include but are not limited to adding, deleting, modifying, inquiring, verifying and remapping, etc. The optimized data structure of the timing diagram and the timing constraints is simultaneously oriented to parallel kernels (parallel kernels include CPU cores and GPU cores): taking the CPU cores and the GPU cores as examples, the data structure not only optimizes the memory access efficiency, but also specially considers the demand of CPU and GPU parallel computing. By adopting a unified memory format, the timing diagram and the timing constraint data structure can simultaneously support direct access and calculation of the CPU and the GPU, avoiding the bottleneck caused by traditional data transmission. This design greatly improves the efficiency of parallel computing and ensures the cooperative work of the CPU and the GPU in the timing analysis process.

[0064] Step S102, the data of the timing diagram is stored in an array structure and established, that is, all data of a specific field (such as node type, edge type, etc.) is kept in continuous memory, which can enable memory ordering optimization, greatly improve cache behavior, and improve data access efficiency. The structure of the timing diagram is stored and established in a hierarchical manner, that is, all nodes and edges are stored according to the topological hierarchy to ensure that the node and edge data of the same layer are continuously distributed in the memory block. This memory layout optimization not only improves the cache hit rate of the CPU, but also enables the GPU kernel to efficiently process these data. In the process of parallel computing, the GPU kernel can directly access these continuously stored data, and by performing batch computing tasks (such as delay calculation of edges, parallel traversal of node arrival time, etc.), the execution of timing analysis is accelerated. In particular, the GPU can parallelly process a large number of computing tasks on nodes and edges, and fully utilize the large-scale parallel computing capability of the GPU in the traversal and relaxation update of the timing diagram. This design greatly reduces the overhead of data transmission, because the GPU can directly access the optimized data structure stored in the memory, avoiding frequent data copying and conversion. The node storage includes but is not limited to node type, arrival time, required time, etc., and the edge storage includes but is not limited to delay, starting node and ending node, etc. The GPU kernel can be parallelly processed by an efficient memory access mode without performing complex memory remapping operations. The timing diagram is a directed graph during establishment, but is actually stored as a bidirectional edge, which can greatly simplify the forward or backward traversal operation in the subsequent link of the timing diagram, so that the GPU can perform these tasks with minimal delay and higher throughput. The data structure of the timing diagram only stores static connection information and node information. Other dynamic information (edge delay, node arrival time or required time, etc.) is stored separately to support dynamic updating and reading in parallel computing. The addition of the GPU kernel makes the parallel processing within the layer more efficient, while also ensuring balanced distribution of computing load when processing large-scale designs, further improving the efficiency of overall timing analysis. Because most behaviors operating on the timing diagram only require read-only access to the timing diagram, the GPU can fully utilize its advantages to handle a large number of computing tasks without interfering with the use of other computing resources.

[0065] Step S103: The timing constraints store all timing constraints applied during timing analysis, such as setup constraints, hold constraints, maximum and minimum input constraints, maximum and minimum output constraints, setup clock constraints, hold clock constraints, early source delay, late source delay, etc. These constraint data are uniformly stored in memory for efficient access and processing. In the process of parallel computing, the GPU kernel can directly process these constraints and perform parallel traversal and update with other data of the timing diagram (such as arrival time, required time).

[0066] Step S104: The netlist and constraint files of the FPGA, including but not limited to.eblif files and.sdc files, are parsed for timing graph and timing constraint information, and memory layout optimization is performed according to the above steps of constructing data structures, and timing graph verification and hierarchical query are performed to ensure the correctness of the timing graph and the hierarchy. The timing graph verification and hierarchical query are initialized to access the data according to the hierarchical traversal order of the timing graph, ensuring that the data access order during traversal is consistent with the storage order in memory, thereby reducing the probability of cache invalidation and improving processing performance.

[0067] Step S2, the task decomposition is performed on the timing graph after the memory layout optimization, and the calculation tasks of the nodes and edges in each level are allocated to multiple parallel kernels for execution, and a single CPU thread is allocated to different levels for sequential execution. Specifically, the calculation tasks of the nodes and edges in each level are calculated by multiple parallel kernels, including CPU cores and GPU kernels. Such design ensures the full utilization of CPU and GPU computing resources, especially when processing large-scale timing analysis tasks, which can accelerate the calculation and avoid resource idling.

[0068] In this embodiment, the task decomposition includes two parts: fine-grained task allocation and coarse-grained task allocation.

[0069] Fine-grained task allocation is to divide each level of the timing graph after memory layout optimization into six fine-grained tasks, namely arrival time pre-traversal, arrival time traversal, demand time pre-traversal, demand time traversal, relaxation update, and state reset. These six main tasks are executed by GPU kernels in parallel because they involve a large number of node traversals and calculations, which can be efficiently handled by GPU. Specifically, GPU kernels can handle multiple nodes and edge data simultaneously through efficient parallel computing capabilities, thereby significantly improving computing speed, while the remaining operations involving conditional judgment, recursion, and large-scale call access operations, scheduling, and synchronization are performed by CPU cores.

[0070] Each parallel kernel is responsible for calculating all nodes or edges in the layer, avoiding data competition between threads, and improving computing efficiency. The arrival time pre-traversal is to traverse the starting node and perform pre-traversal (i.e., set the constraints of the starting node) to set the arrival time of the starting point. The arrival time traversal is to traverse all nodes in the timing graph and calculate the arrival time of the nodes level by level. The demand time pre-traversal is to traverse the logical output nodes and set the demand time of these nodes (i.e., the time constraints of logical output). The demand time traversal is to traverse from the logical output to the starting point level by level to calculate the demand time of the nodes. The relaxation update is to traverse the relaxation values of all nodes for timing optimization. The state reset is to reset the states of the nodes and edges to prepare for the next task analysis.

[0071] The coarse-grained task allocation refers to the sequential execution by a single CPU thread between different levels of the time sequence diagram completed by the memory layout optimization. The nodes and edges of each level depend on the calculation results of the previous level. Since the CPU core has a great advantage in executing tasks with strong dependency, when calculating the critical path of the time sequence diagram, the calculation results of the previous level need to be passed and processed step by step. Therefore, the sequential execution between levels avoids the data dependency problem across levels and ensures the correctness of the overall time sequence analysis.

[0072] The specific process is: initialization and node preparation will be performed before traversal, that is, all nodes are prepared in advance, and the nodes that need to be processed are recorded. Then, appropriate parallel kernel parameters are allocated (in this embodiment, the CPU is set to use 20 CPU cores, and the GPU is set to use 512 GPU cores), and a related function library (in this embodiment, TBB and CUDA are preferred, but not limited to TBB and CUDA) is used to execute the above task decomposition strategy in the time sequence diagram completed by the memory layout optimization.

[0073] Step S3, in execution, the time sequence diagram is traversed by a preset traversal strategy to mark the nodes and edges to be updated; the preset traversal strategy includes full update and incremental update.

[0074] In this embodiment, the traversal strategy includes full update and incremental update. The full update refers to completely reanalyzing the time sequence diagram by serial traversal each time the function is called, which is mainly used in the initialization construction and reset phase. The incremental update refers to incrementally analyzing the time sequence diagram, which is mainly used in the parallel traversal calculation phase. Through incremental update, invalid nodes can be processed in advance, and those nodes and edges that need to be updated are marked. In this way, when entering the bidirectional traversal, only the parts that need to be updated will be calculated, rather than indiscriminately calculating the entire graph, thereby improving the calculation efficiency and reducing unnecessary time and resource consumption.

[0075] The specific process of the incremental update strategy is: 1. Edge invalidation and node preparation: first, the edges invalidated in the previous round of traversal are recorded, and it is marked which nodes need to be updated. 2. Incremental arrival time and demand time traversal: only traverse the nodes marked as needing to be updated, and decide which nodes need to be added to the update queue according to the invalidated edges. 3. Relaxation update: calculate the modified nodes (i.e. the update queue includes all nodes that need to be recalculated, which may be directly marked or derived through dependency relationships. For example, if an edge is invalidated, the nodes connected to the edge need to be recalculated. In actual execution of the update, the nodes in the update queue are traversed and recalculated one by one. During the recalculation process, the relaxation value of some nodes may change, and these nodes are "modified nodes". Therefore, "modified nodes" are dynamically determined, and they are the nodes in the update queue whose relaxation values change during actual calculation, i.e. the nodes whose relaxation values change during traversal calculation). Through the above process, unnecessary node updates can be reduced, and a small number of changes in the timing diagram can be processed more efficiently without completely re-traversing the entire graph each time to speed up the analysis time of the STA.

[0076] The timing diagram in the incremental update process is executed according to the coarse-grained and fine-grained tasks in step S2 to ensure that the dependencies between layers do not cause data race and synchronization problems.

[0077] In step S4, the valid arrival time of the node and the valid demand time of the node are obtained through bidirectional traversal calculation combined with the parallel computing strategy; the critical path in the FPGA timing static analysis is determined according to the valid arrival time of the node and the valid demand time of the node, and then a parallel optimization report for FPGA static timing analysis is generated.

[0078] In this embodiment, the bidirectional traversal calculation is performed in two stages of forward traversal and reverse traversal in the critical path calculation process. In forward (first) traversal, the timing diagram is traversed from the input pin point to the output pin point, and the arrival time is calculated, and the following operations are performed:

[0079] In step S411, the arrival time of all input pins is initialized based on the timing constraints (usually 0);

[0080] In step S412, the delay time of each edge is added to the arrival time of the source node of the edge to calculate the arrival time of the edge;

[0081] In step S413, the maximum setup time or minimum hold time of all input edge arrival times is calculated at each downstream node, and is stored as the node arrival time;

[0082] Step S414, judging whether step S3 is incremental update, if not, executing step S412-S413 in a loop until obtaining valid arrival time of all nodes, otherwise, executing step S412-S413 in a loop until obtaining valid arrival time of nodes in the update queue.

[0083] In backward (second) traversal, the timing diagram is traversed from output pin to input pin, and the following operations are performed:

[0084] Step S421, initializing time of all output pin requirements according to the timing constraints (generally, target clock cycle of establishing analysis is established);

[0085] Step S422, subtracting delay time of each edge from requirement time of convergent node of the edge to calculate requirement time of the edge;

[0086] Step S423, calculating minimum setup time or maximum hold time of all input edge requirement time in each upstream node (i.e. requirement time and arrival time each contain setup time and hold time, setup time is minimum value that needs to be met, and hold time is maximum value that needs to be met. Finally, maximum value and minimum value of requirement time and maximum value and minimum value of arrival time are stored. It is equivalent to minimum requirement time, maximum requirement time, minimum arrival time and maximum arrival time), and storing it as node requirement time;

[0087] Step S424, judging whether step S3 is incremental update, if not, executing step S422-S423 in a loop until obtaining valid requirement time of all nodes, otherwise, executing step S422-S423 in a loop until obtaining valid requirement time of nodes in the update queue.

[0088] In the above calculation of requirement time or arrival time, the timing diagram is processed by hierarchical calculation, one level is processed each time, and two kinds of parallel kernel clusters (GPU is adopted in the embodiment) are allocated to realize it, a certain number of parallel kernels (512 is set in the embodiment according to actual size of the circuit) are in each parallel kernel cluster, such as Figure 3The first parallel kernel cluster is responsible for segment addition, in which each parallel kernel is assigned an edge and calculates the arrival time of the edge, see equation (1), or the required time (not given here), by adding the arrival time of the source node of the previous layer and the delay time of the edge of the layer. This operation is parallelized so that each kernel in the parallel kernel cluster performs edge calculation once. The second parallel kernel cluster is responsible for segment maximum reduction, in which each parallel kernel is assigned a sink node of the current layer. The kernel traverses the arrival time (or required time) of all edges associated with the sink node and performs a maximum reduction operation (see equation (2)) to obtain the final arrival time (or required time) of the sink node. This strategy takes full advantage of the parallel computing power of all available parallel kernels, parallelizes the calculation of edge arrival time (or required time), and makes the calculation of each edge substantially the same, so the load is well balanced. This strategy also ensures the merging and cache optimization of memory access, thereby improving the overall processing efficiency and significantly speeding up the static timing analysis process.

[0089]

[0090]

[0091]

[0092] wherein EAT represents the arrival time of the edge, SO represents the arrival time of the source node, ED represents the delay time of the edge, SIAT represents the arrival time of the sink node, I represents the layer number, n represents the number of nodes in the current layer, and k represents the number of edges connected to the current kth node. e wherein EAT represents the arrival time of the edge, SO represents the arrival time of the source node, ED represents the delay time of the edge, SIAT represents the arrival time of the sink node, I represents the layer number, n represents the number of nodes in the current layer, and k represents the number of edges connected to the current kth node.

[0093] By comparing the arrival time and the required time, the critical path in the FPGA static timing analysis is determined. The path corresponding to the critical path is the path with the arrival time and the required time difference being zero or minimum. The method of critical path calculation is: relaxation value = arrival time - required time, if the relaxation value is negative, it means that the timing of the path does not meet the requirements, which is a potential timing problem. The critical path is the path with the relaxation value being zero or negative, which determines the slowest timing of the system.

[0094] After all the critical path calculations are completed in parallel computing, the parameter values of all intermediate links (in this embodiment, the maximum, minimum, median and average values of the time of six fine-grained tasks, the speedup ratio of each task time, the critical path calculation time, etc.) are recorded and extracted, and a readable parallel optimization report of FPGA static timing analysis is generated. The report can provide analysis of setup time and hold time, generate a worst path report, analyze arrival time, required time, relaxation and other optimization contents, and report information of unconstrained nodes, so as to facilitate users to compare the detailed results of static timing analysis after parallel optimization, help them intuitively understand the timing state of different paths in the timing diagram, and thus optimize and improve the design.

[0095] The second embodiment of the application is a parallel optimization system for FPGA static timing analysis, which comprises:

[0096] A memory layout optimization module configured to obtain a timing graph and timing constraints of FPGA static timing analysis, and perform memory layout optimization on the timing graph and the timing constraints according to the constructed FPGA-oriented STA data structure;

[0097] A task decomposition module configured to perform task decomposition on the timing graph after memory layout optimization, and distribute the calculation tasks of each level of nodes and edges to multiple CPU cores for parallel execution and different levels to a single CPU thread for sequential execution;

[0098] A traversal module configured to traverse the timing graph during execution; the traversal strategy includes full update and incremental update;

[0099] A static timing analysis module configured to obtain effective arrival time of nodes and effective required time of nodes by bidirectional traversal calculation in combination with the parallel computing strategy, determine the critical path in FPGA timing static analysis according to the effective arrival time of nodes and the effective required time of nodes, and further generate a parallel optimization report of FPGA static timing analysis.

[0100] The skilled person in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related description of the above-described system can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0101] It should be noted that the above embodiment provides a parallel optimization system for FPGA static timing analysis, and only the division of the above functional modules is exemplified. In actual application, the above functions can be completed by different functional modules according to needs, that is, the modules or steps in the embodiment of the application are further decomposed or combined, for example, the modules of the above embodiment can be combined into one module, or can be further split into multiple sub-modules to complete all or part of the functions described above. The names of the modules and steps involved in the embodiments of the application are only for distinguishing the respective modules and steps, and are not considered as improper limitation of the application.

[0102] The third embodiment of the electronic device comprises at least one processor and a memory in communication connection with the at least one processor, wherein the memory stores instructions executable by the processor, and the instructions are used to be executed by the processor to implement the parallel optimization method for FPGA static timing analysis.

[0103] The fourth embodiment of the computer readable storage medium stores computer instructions, and the computer instructions are used to be executed by the computer to implement the parallel optimization method for FPGA static timing analysis.

[0104] The skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the electronic device and the computer readable storage medium described above and the related description can refer to the corresponding process in the foregoing method examples, which will not be described here.

[0105] Those skilled in the art should be aware that the modules, method steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware, computer software or a combination of the two. The programs corresponding to the software modules and method steps can be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. In order to clearly illustrate the interchangeability of electronic hardware and software, the components and steps of the examples have been generally described in the above description. Whether the functions are performed by electronic hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the application.

[0106] The terms "first", "second", and the like are used to distinguish similar objects, not to describe or indicate a particular order or sequence.

[0107] The term "comprising" or any other similar word is intended to encompass the inclusion of one or more steps, features, or elements but not to the exclusion of any other steps, features, or elements. The term "comprising" therefore indicates that the inclusion of one or more steps, features, or elements is not a requirement for the process, method, article, or apparatus / apparatus to fall within the scope of the present application.

[0108] So far, the technical solutions of the present application have been described in combination with the preferred embodiments shown in the drawings, but it is easy for those skilled in the art to understand that the protection scope of the present application is obviously not limited to these specific embodiments. Those skilled in the art can make equivalent changes or replacements to the related technical features without deviating from the principles of the present application, and the technical solutions after these changes or replacements will all fall within the protection scope of the present application.

Claims

1. A parallel optimization method for FPGA static timing analysis, characterized in that, The method comprises the following steps: Step S1, obtaining a timing diagram and timing constraints of FPGA static timing analysis; performing memory layout optimization on the timing diagram and the timing constraints according to an FPGA-oriented STA data structure; the timing diagram comprises nodes, edges, delay models and timing analysis results; Step S2, task decomposition is performed on the timing diagram after memory layout optimization, and the calculation tasks of the nodes and edges in each level are distributed to multiple parallel kernels for parallel execution, and different levels are distributed to a single CPU thread for sequential execution; the parallel kernel comprises a CPU core and a GPU core; Step S3, during execution, the timing diagram is traversed through a preset traversal strategy, and the nodes and edges to be updated are marked; the preset traversal strategy comprises full update and incremental update; Step S4, in combination with the parallel computing strategy, the effective arrival time of the node and the effective demand time of the node are obtained through bidirectional traversal calculation; the critical path in the FPGA timing static analysis is determined according to the effective arrival time of the node and the effective demand time of the node, and then a parallel optimization report of the FPGA static timing analysis is generated; The memory layout optimization is performed on the timing diagram and the timing constraints according to the FPGA-oriented STA data structure, and the method is as follows: The structure of the timing diagram is optimized into a hierarchical structure, and the data of the timing diagram is stored in an array structure and only stores static node information and edge information; The timing diagram is stored as a bidirectional edge timing diagram when stored.

2. The parallel optimization method for static timing analysis of FPGA according to claim 1, wherein, Before task decomposition after memory layout optimization, the timing diagram verification and hierarchical query step is further included: According to the hierarchical traversal order of the timing diagram after memory layout optimization, the data is initialized and accessed to verify that the data access order during traversal is consistent with the storage order in the memory.

3. The parallel optimization method for static timing analysis of FPGA according to claim 2, wherein, The method for task decomposition of the timing diagram after memory layout optimization is as follows: The nodes to be processed in the timing diagram after memory layout optimization are obtained, and parallel kernel parameters are distributed, and a related function library is used to perform task decomposition on the timing diagram after memory layout optimization; the related function library comprises TBB and CUDA; The task decomposition of the timing diagram after memory layout optimization comprises fine-grained task decomposition and coarse-grained task decomposition; The fine-grained task decomposition is that each level of the timing diagram after memory layout optimization is divided into different fine-grained tasks, and the calculation tasks of the nodes and edges in each level are distributed to multiple parallel kernels for parallel execution; the fine-grained tasks comprise arrival time pre-traversal, arrival time traversal, demand time pre-traversal, demand time traversal, relaxation update and state reset; The coarse-grained task decomposition is that different levels of the timing diagram after memory layout optimization are sequentially executed by a single CPU thread.

4. The parallel optimization method for static timing analysis of FPGA according to claim 1, wherein, The full update is that each call completely reanalyzes the timing diagram in a serial traversal manner; the full update is used for initialization construction and reset phase; The incremental update is that in the previous traversal process, invalid edges and nodes to be updated are marked. In the arrival time and demand time traversal, only the nodes marked as to be updated are traversed, and the nodes needing to be added to the update queue are determined according to the invalid edges; the relaxation values of the modified nodes are calculated and updated; The modified node is a node whose relaxation value changes in the update queue during the traversal calculation; and the incremental update is used for the parallel calculation stage.

5. The parallel optimization method for static timing analysis of FPGA according to claim 4, wherein, The valid arrival time of a node is obtained by the following method: Step S411, initializing the arrival time of all input pins based on the timing constraint; Step S412, adding the delay time of each edge to the arrival time of the source node of the edge to calculate the arrival time of the edge; Step S413, calculating the maximum setup time or minimum hold time of all input edge arrival times at each downstream node and storing it as the node arrival time; Step S414, determining whether to perform incremental update in step S3, if not, performing steps S412-S413 in a loop until the valid arrival time of all nodes is obtained, otherwise, performing steps S412-S413 in a loop until the valid arrival time of the nodes in the update queue is obtained.

6. The parallel optimization method for static timing analysis of FPGA according to claim 5, wherein, The valid demand time of a node is obtained by the following method: Step S421, initializing the demand time of all output pins based on the timing constraint; Step S422, subtracting the delay time of each edge from the demand time of the sink node of the edge to calculate the demand time of the edge; Step S423, calculating the minimum setup time or maximum hold time of all input edge demand times at each upstream node and storing it as the node demand time; Step S424, determining whether to perform incremental update in step S3, if not, performing steps S422-S423 in a loop until the valid demand time of all nodes is obtained, otherwise, performing steps S422-S423 in a loop until the valid demand time of the nodes in the update queue is obtained.

7. The parallel optimization method for static timing analysis of FPGA according to claim 6, wherein, In the calculation of the valid arrival time of all nodes or the valid demand time of all nodes, a parallel calculation strategy is used for parallel execution: By processing the timing diagram in stages, one level is processed at a time, and two parallel kernel clusters are allocated in each level, one of which is responsible for segmented addition and the other is responsible for segmented maximum reduction; The processing process of the parallel kernel cluster responsible for segmented addition is that each kernel in the parallel kernel cluster is assigned an edge, and one edge calculation is performed to obtain the arrival time of the edge or the demand time of the edge; The processing process of the parallel kernel cluster responsible for segmented maximum reduction is that each parallel kernel in the parallel kernel cluster is assigned to a sink node of a current level, and the arrival time or demand time of all edges related to the sink node is traversed, and a maximum reduction operation is performed to obtain the final arrival time or demand time.

8. The parallel optimization method for static timing analysis of FPGA according to claim 7, wherein, According to the valid arrival time of all nodes and the valid demand time of all nodes, a critical path in FPGA timing static analysis is determined by the following method: The difference between the valid arrival time and the valid demand time of all nodes in each path is calculated, and the path corresponding to the zero difference or the minimum difference is taken as the critical path.

9. The parallel optimization method for static timing analysis of an FPGA according to claim 8, wherein, The parallel optimization report of FPGA static timing analysis is generated, and the method is as follows: After the parallel calculation completes all critical path calculations, the parameter values of all intermediate links are recorded and extracted to generate a readable parallel optimization report of FPGA static timing analysis.

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