Neural network model calculation amount evaluation method and device based on directed acyclic graph

Abstract

The invention discloses a method and equipment for evaluating the calculation amount of a neural network model based on a directed acyclic graph, and is applied to the technical field of computers, and the method comprises the steps: judging whether the neural network model meets a directed acyclic condition, and obtaining an operator topological sequence if the neural network model meets the directed acyclic condition; judging whether the neural network model is a full-state shape neural network model or not, and if yes, calculating an operand of each operator according to an operator topological sequence of the neural network model; and the operands of each operator are accumulated and summed to obtain the calculated amount of the neural network model. In this way, the calculated amount demand can be accurately determined before model deployment, the chip resources are allocated in advance according to the accurate calculated amount demand, and the problem of waste caused by excessive resource configuration or low efficiency caused by insufficient resources is avoided.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and further to the field of model computational complexity evaluation technology, and in particular to a method and device for evaluating the computational complexity of a neural network model based on a directed acyclic graph. Background Art

[0002] In the field of deep learning, evaluating the computational requirements of neural network models is an important but complex task. Traditional computational requirements evaluation methods often rely on empirical estimates or actual operation tests. These methods are not only time-consuming and labor-intensive, but also lack precision and are easily interfered by subjective factors. They cannot provide computational requirements analysis before model deployment, affecting the resource planning of computing chips. With the increasing complexity of current neural network models, it is particularly important to accurately evaluate the model's computational requirements to ensure the efficiency of reasoning after model deployment. Summary of the invention

[0003] In view of this, the present application discloses a method and device for evaluating the computational complexity of a neural network model based on a directed acyclic graph.

[0004] According to a first aspect of the present application, a method for evaluating the computational amount of a neural network model based on a directed acyclic graph is disclosed, which is applied to an evaluation system. The method comprises:

[0005] Determine whether the neural network model satisfies the directed acyclic condition. If so, obtain its operator topological sequence. Determine whether the neural network model is a full static shape neural network model. If so, calculate the number of operations of each operator according to its operator topological sequence. Accumulate and sum the number of operations of each operator to obtain the computational amount of the neural network model.

[0006] In some implementations of the first aspect, determining whether the neural network model satisfies the directed acyclic condition, and obtaining its operator topology sequence if satisfied, includes:

[0007] Perform topological sorting on the neural network model. If the topological sorting can be completed, it is determined that the neural network model meets the directed acyclic condition and its operator topological sequence is obtained.

[0008] In some implementations of the first aspect, determining whether the neural network model is a full static shape neural network model includes:

[0009] Determine whether the shape of each operator in the neural network model is a fixed shape. If so, it is a full staticshape neural network model.

[0010] In some implementations of the first aspect, calculating the number of operations of each operator according to its operator topology sequence includes:

[0011] According to the operator topology sequence and the calculation formula corresponding to the operator implementation code, the operand of each operator is calculated; wherein the operator implementation code includes: convolution operator, activation function, and fully connected operator.

[0012] In some possible implementations of the first aspect, the calculation formula corresponding to the implementation code of the convolution operator is as follows:

[0013]

[0014] Among them, X is the input data, shape is [h,w,c]; Y is the output data, shape is [h,w,c]; W is the convolution kernel, shape is [k,k,c]; b is the bias value of the convolution kernel, each convolution kernel corresponds to 1 bias value; s is s convolution kernels with the same data size; Y i,j,r is the value of the i-th row, j-th column, and r-th channel of Y; W r,m,n,t is the value of the rth convolution kernel, the mth row, nth column, and tth channel; X i+m,j+n,t is the value of the t-th channel in the (i+m)-th row, (j+n)-th column of the input; br is the bias value corresponding to the r-th convolution kernel.

[0015] In some implementations of the first aspect, the activation function includes a relu operator, and a calculation formula corresponding to the implementation code of the relu operator is as follows:

[0016] Y i =max(0, X i ), i∈[1,n];

[0017] Among them, X is the input data, with a total of n elements; Y is the output data, with the same shape as X.

[0018] In some implementations of the first aspect, the activation function includes a softmax operator, and a calculation formula corresponding to an implementation code of the softmax operator includes:

[0019]

[0020] Among them, X is the input data, with a total of n elements; Y is the output data, with the same shape as X;

[0021] The calculation formula corresponding to the implementation code of the softmax operator also includes:

[0022]

[0023] Among them, X is the input data, with a total of n elements; Y is the output data, with the same shape as X; E is the intermediate data, with the same shape as X.

[0024] In some possible implementations of the first aspect, the calculation formula corresponding to the implementation code of the full connection operator is as follows:

[0025]

[0026] Among them, X is the input data, with a total of m elements; Y is the output data, with a total of n elements; W is the weight, with a total of m rows and n columns; b is the bias value, with a total of n elements.

[0027] According to a second aspect of the present application, an electronic device is disclosed. The electronic device includes: at least one processor; and a memory connected to the at least one processor in communication; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method described above.

[0028] According to a third aspect of the present application, a non-transitory computer-readable storage medium storing computer instructions is disclosed, where the computer instructions are used to cause a computer to execute the method described above.

[0029] In this application, by analyzing the neural network model that meets the conditions of the directed acyclic computational graph, the computing power required for the model after deployment is accurately obtained through rigorous calculations, thus overcoming the drawbacks of the traditional method of relying on empirical estimation and actual operation tests. There is no need to spend a lot of time and energy on tedious testing processes, and chip resources can be allocated in advance based on accurate computing power data, thus avoiding waste caused by over-allocation of resources or inefficiency caused by insufficient resources.

[0030] It should be understood that the contents described in the Summary of the Invention are not intended to limit the key or important features of the embodiments of the present application, nor are they intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features, advantages and aspects of the embodiments of the present application will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present application. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, among which:

[0032] Figure 1 A flow chart of a method for evaluating the computational amount of a neural network model based on a directed acyclic graph disclosed in an embodiment of the present application is shown;

[0033] Figure 2 A block diagram of an exemplary electronic device capable of implementing embodiments of the present application is shown. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0035] In addition, the term "and / or" in this article is only a description of the association relationship between the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0036] In response to the problems mentioned in the background technology, the present application discloses a method and device for evaluating the computational complexity of a neural network model based on a directed acyclic graph.

[0037] Specifically, determine whether the neural network model satisfies the directed acyclic condition, and if so, obtain its operator topological sequence; determine whether the neural network model is a full static shape neural network model, and if so, calculate the number of operations of each operator according to its operator topological sequence; accumulate and sum the number of operations of each operator to obtain the computational amount of the neural network model.

[0038] In this way, the drawbacks of traditional methods that rely on empirical estimation and actual operation tests can be overcome. There is no need to spend a lot of time and energy on tedious testing processes. The computing requirements can be accurately determined before model deployment, and chip resources can be allocated in advance based on the accurate computing requirements, avoiding waste caused by over-allocation of resources or inefficiency caused by insufficient resources.

[0039] The following is a more detailed description of the method and device for evaluating the computational amount of a neural network model based on a directed acyclic graph provided by the present application in conjunction with the accompanying drawings and specific embodiments.

[0040] First of all, it should be noted that the meanings of some English words and English abbreviations involved in the embodiments of the present application are as follows:

[0041] Shape: The shape of the tensor.

[0042] Dynamic shape: The shape of the tensor can change dynamically at runtime according to the actual input data.

[0043] static shape: static shape, the tensor shape is determined during the computational graph construction phase and will not change during subsequent calculations.

[0044] kernel: convolution kernel.

[0045] Padding: Pixels or elements that are filled at the edge of the data before performing a convolution operation on an image or other data.

[0046] bias: bias.

[0047] DAG: Directed Acyclic Graph, directed acyclic graph;

[0048] OPs: Operations, calculation unit, number of operations / operands, including integer operations, logical operations, floating-point operations, etc.

[0049] TOPs: Tera Operations, unit of computing power, trillion operations / trillion operations.

[0050] Figure 1 A flowchart of a method for evaluating the computational amount of a neural network model based on a directed acyclic graph disclosed in an embodiment of the present application is shown; Figure 1 As shown, the evaluation method 100 of the computational amount of a neural network model based on a directed acyclic graph may include the following steps:

[0051] S110, determining whether the neural network model satisfies the directed acyclic condition, and if so, obtaining its operator topology sequence.

[0052] Specifically, the neural network model is topologically sorted. If the topological sorting can be completed, it is determined that the neural network model satisfies the directed acyclic condition, and its operator topological sequence is obtained.

[0053] S120, determining whether the neural network model is a full static shape neural network model, and if so, calculating the number of operations of each operator according to its operator topology sequence.

[0054] Specifically, determine whether the shape of each operator in the neural network model is a fixed shape. If so, it is a full static shape neural network model; if so, calculate the operand of each operator according to its operator topology sequence and the calculation formula corresponding to the operator implementation code; wherein the operator implementation code may include: convolution operator, activation function, and fully connected operator.

[0055] Furthermore, the calculation formula corresponding to the implementation code of the convolution operator can be shown as follows:

[0056]

[0057] Where X is the input data, with a shape of [h, w, c]; Y is the output data, with a shape of [h, w, c]; W is the convolution kernel, with a shape of [k, k, c]; b is the bias value of the convolution kernel, and each convolution kernel corresponds to 1 bias value; s is s convolution kernels with the same data size; Y i,j,r is the value of the i-th row, j-th column, and r-th channel of Y; W r,m,n,t is the value of the rth convolution kernel, the mth row, nth column, and tth channel; X i+m,j+n,t is the value of the t-th channel in the (i+m)-th row, (j+n)-th column of the input; br is the bias value corresponding to the r-th convolution kernel.

[0058] Furthermore, the activation function may include a relu operator, and the calculation formula corresponding to the implementation code of the relu operator may be as follows:

[0059] Y i =max(0, X i ), i∈[1,n];

[0060] Among them, X is the input data, with a total of n elements; Y is the output data, with the same shape as X.

[0061] Furthermore, the activation function may include a softmax operator, and the calculation formula corresponding to the implementation code of the softmax operator may be as follows:

[0062]

[0063] Among them, X is the input data, with a total of n elements; Y is the output data, with the same shape as X.

[0064] Furthermore, the softmax operator may also be an optimized softmax operator, and the calculation formula corresponding to the implementation code of the optimized softmax operator may be as follows:

[0065]

[0066]

[0067] Among them, X is the input data, with a total of n elements; Y is the output data, with the same shape as X; E is the intermediate data, with the same shape as X.

[0068] Furthermore, the calculation formula corresponding to the implementation code of the full connection operator can be shown as follows:

[0069]

[0070] Among them, X is the input data, with a total of m elements; Y is the output data, with a total of n elements; W is the weight, with a total of m rows and n columns; b is the bias value, with a total of n elements.

[0071] According to the embodiments of the present application, by implementing the calculation formula corresponding to the code, a relatively accurate number of operations of each operator can be obtained, providing a reliable data basis for the subsequent calculation of the computational amount of the neural network model.

[0072] S130, summing up the operands of each operator to obtain the computational complexity of the neural network model.

[0073] According to the embodiments of the present application, on the basis of obtaining reliable operator operands in a relatively rigorous manner, all operator operands are further accumulated and summed to obtain a relatively accurate and rigorous calculation amount of the neural network model, which can provide a reliable basis for the allocation of chip resources.

[0074] The above content is further described below with reference to a specific embodiment.

[0075] S110, determining whether the neural network model satisfies the directed acyclic condition, and if so, obtaining its operator topology sequence.

[0076] The neural network model is a computational graph structure. Each node is a clear operator that determines whether the directed acyclic condition is met, that is, whether the graph is a DAG.

[0077] Perform topological sorting on the graph. If the topological sorting can be completed, it means that the graph is a DAG; if it is found that some nodes cannot be sorted during the sorting process, it means that there is a cycle and it is not a DAG, that is, it does not meet the directed acyclic condition.

[0078] S120, determining whether the neural network model is a full static shape neural network model, and if so, calculating the number of operations of each operator according to its operator topology sequence.

[0079] In the neural network model, each operator can only be a dynamic shape or a static shape, which can be distinguished by the attributes or descriptions of the operator. If the shape of an operator is fixed, it is a static shape operator, otherwise it is a dynamic shape operator. If a dynamic shape operator exists, no calculation is performed.

[0080] S130, summing up the operands of each operator to obtain the computational complexity of the neural network model.

[0081] Through S120, a topologically sorted operator sequence of a neural network model can be obtained. According to the operator sequence, the operands are calculated one by one and accumulated to obtain the calculation amount of the entire neural network model.

[0082] Among them, the implementation codes of all operators have clear mathematical definitions and calculation formulas (operators with the same function have equivalent calculation formulas, but different formulas and are counted as two different operators), and the operator implementation codes can calculate clear OP times.

[0083] In the following formulas, unless otherwise specified, all parameters are positive integers.

[0084] (1) Taking the convolution operator with a step size of 1, a kernel width and height of 3, and a padding of 1 as an example, the calculation steps are explained.

[0085] The corresponding mathematical formula is:

[0086]

[0087] in:

[0088] X: input data, shape is [h,w,c];

[0089] Y: output data, shape is [h,w,c];

[0090] W: convolution kernel, shape is [k, k, c];

[0091] b: The bias value of the convolution kernel. Each convolution kernel corresponds to one bias value.

[0092] s: s convolution kernels with the same data size;

[0093] h, w, c: The input data is three-dimensional data, with height h, width w, and number of channels c;

[0094] k, k, c: The convolution kernel data is three-dimensional data with a height of k, a width of k, and a number of channels of c (the number of channels is the same as the number of channels of the input data);

[0095] Yi,j,r: the value of the i-th row, j-th column, and r-th channel of Y;

[0096] Wr,m,n,t: the value of the rth convolution kernel, the mth row, nth column, and tth channel;

[0097] Xi+m,j+n,t: the value of the tth channel in the (i+m)th row, (j+n)th column of the input;

[0098] br: The bias value corresponding to the rth convolution kernel.

[0099] Calculation analysis:

[0100] Involving two basic operations, multiplication and addition, it can be analyzed that the operator requires a total of shwkkc additions and shwkkc multiplications, a total of 2shwkkc OPs.

[0101] (2) Take the relu operator as an example

[0102] Y i =max(0, X i ), i∈[1,n]

[0103] in:

[0104] X: input data, which can be of any dimension, with a total of n elements;

[0105] Y: output data, the shape is the same as X.

[0106] Calculation analysis:

[0107] It involves a basic operation of finding the maximum value. It can be analyzed that the operator needs to find the maximum value n times in total, a total of n OPs.

[0108] (3) Take the softmax operator as an example (e is the base of the natural logarithm).

[0109]

[0110] in:

[0111] X: input data, which can be of any dimension, with a total of n elements;

[0112] Y: output data, the shape is the same as X.

[0113] Calculation analysis:

[0114] Involving three basic operations: exponentiation, addition, and division, we can analyze that for each value in X, the numerator needs to be exponentiated once, the denominator needs n exponentiations and (n-1) additions, and the fraction needs one division, which requires a total of 1+n+n-1+1=(2n+1) OPs. Therefore, the operator requires a total of (2n+1)n OPs.

[0115] (4) Take the optimized softmax operator as an example.

[0116] The same function (such as softmax) has multiple computational implementations, and different implementations have different operators.

[0117]

[0118] in:

[0119] X: input data, which can be of any dimension, with a total of n elements;

[0120] Y: output data, the shape is the same as X;

[0121] E: intermediate data, with the same shape as X;

[0122] S: The sum of all elements in E.

[0123] Calculation analysis:

[0124] These three formulas are equivalent to the formula in (3), but the formulas are not the same and correspond to different calculation implementations, so they should be analyzed as another operator; the first formula contains a power operation, with a total of n OPs; the second formula contains an addition operation, with a total of (n-1) OPs; the third formula contains a division operation, with a total of n OPs; a total of n+n-1+n=(3n-1) OPs.

[0125] (5) Taking the fully connected operator as an example

[0126]

[0127] in:

[0128] X: input data, one-dimensional data, with a total of m elements;

[0129] Y: output data, one-dimensional data, a total of n elements;

[0130] W: weight, two-dimensional data, m rows and n columns;

[0131] b: bias value, one-dimensional data, with n elements in total.

[0132] Calculation analysis:

[0133] Involving two basic operations, multiplication and addition, it can be analyzed that the operator requires a total of m×n multiplications and m×n additions, a total of 2mn OPs.

[0134] The above specific embodiment calculates the OP number of each operator by analyzing the calculation formula corresponding to the operator in the model, thereby obtaining the calculation amount of the entire model. It is applicable to various types of neural network operators, including full connection, convolution, activation function, etc. The calculation principle is the same as above and has wide applicability.

[0135] During the hardware planning stage, the performance of the model on a specific computing chip (GPU / NPU, etc.) can be calculated based on the model's computational load and the computing power of the computing chip (usually measured in TOPS), which can better assist the computing chip in planning computing resources.

[0136] According to the embodiments of the present application, the following technical effects are achieved:

[0137] By analyzing the neural network model that meets the conditions of the directed acyclic computational graph and through rigorous calculations, the computing power required for the model after deployment is accurately obtained, overcoming the shortcomings of traditional methods that rely on empirical estimates and actual operation tests. There is no need to spend a lot of time and energy on tedious testing processes. Chip resources can be allocated in advance based on accurate computing power data, avoiding waste caused by over-allocation of resources or inefficiency caused by insufficient resources.

[0138] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present application.

[0139] According to an embodiment of the present application, the present application also discloses an electronic device and a readable storage medium.

[0140] Figure 2 A block diagram of an exemplary electronic device capable of implementing embodiments of the present application is shown.

[0141] The electronic device 200 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device 200 may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or required herein.

[0142] The electronic device 200 includes a computing unit 201, which can perform various appropriate actions and processes according to a computer program stored in the ROM 202 or a computer program loaded from the storage unit 208 into the RAM 203. In the RAM 203, various programs and data required for the operation of the electronic device 200 can also be stored. The computing unit 201, the ROM 202, and the RAM 203 are connected to each other via a bus 204. An I / O interface 205 is also connected to the bus 204.

[0143] A number of components in the electronic device 200 are connected to the I / O interface 205, including: an input unit 206, such as a keyboard, a mouse, etc.; an output unit 207, such as various types of displays, speakers, etc.; a storage unit 208, such as a disk, an optical disk, etc.; and a communication unit 209, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 209 allows the electronic device 200 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0144] The computing unit 201 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 201 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 201 performs the various methods and processes described above, such as method 100. For example, in some embodiments, the method 100 may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 208. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 200 via ROM 202 and / or communication unit 209. When the computer program is loaded into RAM 203 and executed by the computing unit 201, one or more steps of the method 100 described above may be performed. Alternatively, in other embodiments, the computing unit 201 may be configured to perform the method 100 in any other appropriate manner (e.g., by means of firmware).

[0145] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0146] The program code for implementing the method of the present application can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, implements the functions / operations specified in the flow chart and / or block diagram. The program code can be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0147] In the context of the present application, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0148] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0149] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0150] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0151] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this application can be executed in parallel, sequentially or in different orders, as long as the expected results of the technical solution disclosed in this application can be achieved, and this document is not limited here.

[0152] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this application should be included in the protection scope of this application.

Claims

1. A method for evaluating the computational amount of a neural network model based on a directed acyclic graph, applied to an evaluation system, characterized in that: The method comprises: Determine whether the neural network model meets the directed acyclic condition, and if so, obtain its operator topology sequence; Determine whether the neural network model is a full static shape neural network model, and if so, calculate the number of operations of each operator according to its operator topology sequence; The operands of each operator are accumulated and summed to obtain the computational complexity of the neural network model.

2. The method according to claim 1, characterized in that The step of judging whether the neural network model satisfies the directed acyclic condition and obtaining its operator topology sequence if it satisfies the condition includes: The neural network model is topologically sorted. If the topological sorting can be completed, it is determined that the neural network model satisfies the directed acyclic condition, and its operator topological sequence is obtained.

3. The method according to claim 1, characterized in that The determining whether the neural network model is a full static shape neural network model includes: Determine whether the shape of each operator in the neural network model is a fixed shape. If so, it is a full static shape neural network model.

4. The method according to claim 1, characterized in that: The step of calculating the number of operations of each operator according to its operator topology sequence includes: According to the operator topology sequence and the calculation formula corresponding to the operator implementation code, the operand of each operator is calculated; wherein the operator implementation code includes: convolution operator, activation function, and fully connected operator.

5. The method according to claim 4, characterized in that The calculation formula corresponding to the implementation code of the convolution operator is as follows: Among them, X is the input data, shape is [h,w,c]; Y is the output data, shape is [h,w,c]; W is the convolution kernel, shape is [k,k,c]; b is the bias value of the convolution kernel, each convolution kernel corresponds to 1 bias value; s is s convolution kernels with the same data size; Y i,j,r is the value of the i-th row, j-th column, and r-th channel of Y; W r,m,n,t is the value of the rth convolution kernel, the mth row, nth column, and tth channel; X i+m,j+n,t is the value of the t-th channel in the (i+m)-th row, (j+n)-th column of the input; br is the bias value corresponding to the r-th convolution kernel.

6. The method according to claim 4, characterized in that The activation function includes a relu operator, and the calculation formula corresponding to the implementation code of the relu operator is as follows: Y i =max(0,X i ),i∈[1,n]; Among them, X is the input data, with a total of n elements; Y is the output data, with the same shape as X.

7. The method according to claim 4, characterized in that The activation function includes a softmax operator, and the calculation formula corresponding to the implementation code of the softmax operator includes: Among them, X is the input data, with a total of n elements; Y is the output data, with the same shape as X; The calculation formula corresponding to the implementation code of the softmax operator also includes: Among them, X is the input data, with a total of n elements; Y is the output data, with the same shape as X; E is the intermediate data, with the same shape as X.

8. The method according to claim 4, characterized in that The calculation formula corresponding to the implementation code of the fully connected operator is as follows: Among them, X is the input data, with a total of m elements; Y is the output data, with a total of n elements; W is the weight, with a total of m rows and n columns; b is the bias value, with a total of n elements.

9. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 8.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-8.

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