Display device

Abstract

According to an embodiment of the present disclosure, a display device includes: a display panel having a display area and a non-display area; a plurality of pixels disposed in the display area; a light emitting element disposed in each of the plurality of pixels; a driving transistor disposed in each of the plurality of pixels and electrically connected to the light emitting element; and a common circuit disposed in the non-display area and electrically connected to a node between the light emitting element and the driving transistor.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0137875 filed on October 16, 2023, in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present invention relates to a display device, and more particularly, to a display device capable of realizing fine pixels. Background Art

[0003] A head-mounted display (HMD) is a visual display device that is worn on the user's head in the form of glasses or a helmet and focuses images at a close distance in front of the user's eyes. HMD can realize virtual reality (VR) or augmented reality (AR).

[0004] HMD uses multiple lenses to magnify the image displayed by the small display unit. Therefore, the display unit used in the HMD needs to provide a high-resolution image (for example, an image with a resolution of 3000 pixels per inch (PPI) or more). To achieve this goal, organic light emitting diodes (OLED) on silicon (OLEDoS) are used as display units for HMDs. OLEDoS is a device that displays images by placing OLEDs on a semiconductor wafer substrate on which complementary metal oxide semiconductors (CMOS) are arranged. Summary of the invention

[0005] Aspects of the present disclosure provide a display device capable of realizing fine pixels.

[0006] However, aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] According to an embodiment of the present disclosure, a display device includes: a display panel having a display area and a non-display area; a plurality of pixels arranged in the display area; a light-emitting element arranged in each of the plurality of pixels; a driving transistor arranged in each of the plurality of pixels and electrically connected to the light-emitting element; and a common circuit arranged in the non-display area and electrically connected to a node between the light-emitting element and the driving transistor.

[0008] In an embodiment, the common circuit may be electrically connected to the nodes via a common line.

[0009] In an embodiment, the common circuit may include an initialization transistor electrically connected to the node and receiving the common voltage and the initialization gate signal.

[0010] In an embodiment, the initialization transistor may be electrically connected between the node and a common voltage line transmitting a common voltage, and the initialization gate signal may be applied to a gate electrode of the initialization transistor.

[0011] In an embodiment, each of the plurality of pixels may further include: a switching transistor electrically connected between the data line and the gate electrode of the driving transistor; and an emission control transistor electrically connected between the source electrode of the driving transistor and a driving voltage line transmitting a driving voltage.

[0012] In an embodiment, the write gate signal may be input to the gate electrode of the switching transistor, and the emission signal may be input to the gate electrode of the emission control transistor.

[0013] In an embodiment, the display device further includes a gate driver transmitting an initialization gate signal to a common circuit and transmitting a write gate signal and an emission signal to each of the plurality of pixels.

[0014] In an embodiment, during the initialization period, each of the emission signal, the write gate signal, and the initialization gate signal may have an active level, and a reference voltage may be applied to the data line.

[0015] In an embodiment, the write gate signal may have an inactive level during a portion of the initialization period before the end of the initialization period.

[0016] In an embodiment, during the threshold voltage detection period after the initialization period, the initialization gate signal may have an active level, each of the emission signal and the write gate signal may have an inactive level, and a reference voltage may be applied to the data line.

[0017] In an embodiment, the data voltage may be applied to the data line during a portion of the threshold voltage detection period before the threshold voltage detection period ends.

[0018] In an embodiment, during a data write period after a threshold voltage detection period, each of a write gate signal and an initialization gate signal may have an active level, an emission signal may have an inactive level, and a data voltage may be applied to a data line.

[0019] In an embodiment, before the data write cycle ends, during a portion of the data write cycle, the write gate signal may have a non-active level, and the reference voltage may be applied to the data line.

[0020] In an embodiment, during an emission period after a data write period, the emission signal may have an active level, the write gate signal may have an inactive level, and the initialization gate signal may have an inactive level, and a reference voltage may be applied to the data line.

[0021] In an embodiment, after the emission cycle starts, the initialization gate signal may have an active level during a portion of the emission cycle.

[0022] In an embodiment, the reference voltage, the driving voltage, and the common voltage may be direct current (DC) voltages.

[0023] In an embodiment, the reference voltage may be greater than the common voltage and less than the driving voltage.

[0024] In an embodiment, each of the plurality of pixels may further include: a first capacitor electrically connected between the gate electrode and the source electrode of the driving transistor; and a second capacitor electrically connected between the source electrode of the driving transistor and the driving voltage line.

[0025] In an embodiment, a ratio of the capacitance of the second capacitor to the capacity of the first capacitor may be approximately 2:1.

[0026] In an embodiment, the initialization transistor and the drive transistor may be opposite type transistors.

[0027] In an embodiment, the common circuit may include a plurality of initialization transistors electrically connected in series between the node and a common voltage line transmitting a common voltage.

[0028] In an embodiment, the common circuit may include: a first common circuit disposed on one side of the non-display area and electrically connected to the node; and a second common circuit disposed on the other side of the non-display area and electrically connected to the node.

[0029] According to the above and other embodiments of the present disclosure, because multiple pixels share a single common circuit, the number of transistors required for each pixel can be reduced. As a result, the size of the pixel can be reduced, making it possible to achieve fine pixels.

[0030] It should be noted that the effects of the present disclosure are not limited to the above, and other effects of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 is a schematic exploded perspective view showing a display device according to an embodiment of the present disclosure;

[0033] Figure 2 It shows Figure 1 A schematic layout diagram of an exemplary display panel;

[0034] Figure 3 It shows Figure 2 A schematic diagram of an exemplary pixel and an equivalent circuit of a sub-common circuit connected to the exemplary pixel;

[0035] Figure 4 It shows Figure 3 An exemplary timing diagram of an emission signal, a write gate signal, an initialization gate signal, a reference voltage, and a data voltage;

[0036] Figure 5 It shows that Figure 4 During the initialization cycle Figure 3 A schematic diagram of an equivalent circuit showing the operation of the display device;

[0037] Figure 6 It shows that Figure 4 The threshold voltage during the detection cycle Figure 3 A schematic diagram of an equivalent circuit showing the operation of the display device;

[0038] Figure 7 It shows that Figure 4 During the data write cycle Figure 3 A schematic diagram of an equivalent circuit showing the operation of the display device;

[0039] Figure 8 It shows that Figure 4 During the launch cycle Figure 3 A schematic diagram of an equivalent circuit showing the operation of the display device;

[0040] Fig. 9 It shows Figure 2 A schematic diagram of another exemplary pixel and an equivalent circuit of a sub-common circuit connected to the exemplary pixel;

[0041] Fig.10 It shows Figure 2 A schematic diagram of another exemplary pixel and an equivalent circuit of a sub-common circuit connected to the exemplary pixel; and

[0042] Fig.11 yes Figure 1 Schematic layout diagram of another exemplary display panel. DETAILED DESCRIPTION

[0043] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. However, the present disclosure may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be exhaustive and complete, and will convey the scope of the present invention to those skilled in the art.

[0044] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it may be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, like reference numerals and / or characters may indicate like components. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

[0045] Although the terms "first", "second", etc. can be used here to describe each element, these elements should not be limited by these terms. These terms can be used to distinguish an element from another element. Therefore, without departing from the teaching of one or more embodiments, the first element discussed below can be referred to as the second element. Describing an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. can also be used to distinguish between different classes or different groups of elements in this article. For simplicity, the terms "first", "second", etc. can respectively represent "first class (or first group)", "second class (or second group)", etc.

[0046] The features of the various embodiments of the present disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, various interactions and operations are technically possible. The various embodiments may be implemented individually or in combination.

[0047] When an element is referred to as being "connected to" or "coupled to" another element, it may be directly connected or coupled to the other element or there may be intervening elements or layers. However, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements.

[0048] The term "and / or" includes all combinations of one or more that can be defined by the relevant configuration. For example, "A and / or B" can be understood to mean "A, B, or A and B".

[0049] For the purpose of the present disclosure, the phrase “at least one of A and B” may be interpreted as only A, only B, or any combination of A and B. In addition, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z.

[0050] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless explicitly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formalized sense.

[0051] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0052] Figure 1 is a schematic exploded perspective view showing a display device 10 according to an embodiment of the present disclosure. Figure 2 It shows Figure 1 Schematic layout diagram of an exemplary display panel 100.

[0053] Reference Figure 1 and Figure 2 , the display device 10 may be a device for displaying a moving or still image. The display device 10 may be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notepads, e-book readers, portable multimedia players (PMPs), navigation systems, or ultra-mobile PCs (UMPCs). For example, the display device 10 may be used as a display unit for a television (TV), a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. In another example, the display device 100 may be applied to a smart watch, a watch phone, or an HMD for realizing virtual reality or augmented reality.

[0054] The display device 10 may include a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , a timing controller 400 , and a power supply circuit 500 .

[0055] The heat dissipation layer 200 may overlap the display panel 100 in the third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on a surface of the display panel 100 (e.g., disposed on a rear surface of the display panel 100). The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. In an embodiment, the heat dissipation layer 200 may include a metal layer of a material having high thermal conductivity such as silver (Ag), copper (Cu), or aluminum (Al), or graphite.

[0056] The circuit board 300 may be electrically connected to one or more pads of the display panel 100 via a conductive adhesive material such as an anisotropic conductive film. For example, the circuit board 300 may be a flexible printed circuit board (FPCB) or a flexible film. Figure 1The circuit board 300 is shown unfolded, but the circuit board 300 may be folded. In the case where the circuit board 300 is folded, a first end of the circuit board 300 may be disposed on the rear surface of the display panel 100. The first end of the circuit board 300 may be opposite to a second end of the circuit board 300 connected to one or more pads of the display panel 100 via a conductive adhesive.

[0057] The timing controller 400 may receive digital video data and timing signals from the outside. The timing controller 400 may generate a gate control signal, an emission control signal and / or a data control signal according to the timing signal. The timing controller 400 may output the gate control signal and the emission control signal to the gate driver GD and output the digital video data and the data control signal to the data driver DD.

[0058] The power supply circuit 500 may generate one or more panel driving voltages based on an external power supply voltage. For example, the power supply circuit 500 may generate a driving voltage, a first common voltage, a second common voltage and / or an initialization voltage and may supply the generated voltages to the display panel 100.

[0059] The timing controller 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and may be attached to a surface of the circuit board 300. A gate control signal, an emission control signal, digital video data, and / or a data control signal from the timing controller 400 may be supplied to the display panel 100 through the circuit board 300. A driving voltage, a first common voltage, a second common voltage, and / or an initialization voltage from the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0060] The display panel 100 may have a shape similar to a rectangle in a plan view. For example, the display panel 100 may have a planar shape similar to a rectangle with a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. The angle at which the short side in the first direction DR1 intersects with the long side in the second direction DR2 may be formed with a curvature (e.g., a predetermined or optional curvature) or may be formed as a right angle. The shape of the display panel 100 is not limited to a rectangular shape and may have various shapes, such as similar to other polygons, a circle, an ellipse, etc. The shape of the display device 10 conforms to the shape of the display panel 100, but the present invention is not limited thereto.

[0061] like Figure 2 As shown in , the display panel 100 may include a display area DA where an image is displayed and a non-display area NDA where no image is displayed.

[0062] One or more pixels PX, one or more write gate lines GWL, one or more common lines CL, and / or one or more data lines DL may be provided in the display area DA of the display panel 100. Each of the pixels PX may include a light emitting element ED (refer to Figure 3 ). The pixels PX may be arranged in a matrix form in the first direction DR1 and the second direction DR2.

[0063] Each of the pixels PX may be connected to a write gate line GWL, a common line CL, an emission line EML, and a data line DL. The write gate line GWL may extend in a first direction DR1, and the pixels PX aligned in an extension direction of the write gate line GWL (e.g., first direction DR1) on one horizontal line may be connected to the same write gate line GWL, the same common line CL, and the same emission line EML. In addition, the pixels PX on one horizontal line may be connected to different data lines DL.

[0064] The gate driver GD, the data driver DD, the common circuit CMC, and / or one or more initialization gate lines GIL may be disposed in the non-display area NDA of the display panel 100 .

[0065] like Figure 2 As depicted in , the gate driver GD can be connected to the common circuit CMC. For example, the gate driver GD can be connected to the common circuit CMC through one or more initialization gate lines GIL. The gate driver GD generates one or more write signals and one or more initialization gate signals based on the gate control signal from the timing controller 400, and can generate one or more emission signals based on the emission control signal from the timing controller 400. The gate driver GD can supply the generated initialization gate signal to the common circuit CMC. For example, the gate driver GD can supply the initialization gate signal to the common circuit CMC through the initialization gate line GIL. In addition, the gate driver GD can supply the write gate signal to the pixel PX through the write gate line GWL, and can also supply the emission signal to the pixel PX through the emission line EML.

[0066] In one embodiment, because a plurality of pixels PX can share a single common circuit CMC, the number of transistors required for each of the pixels PX can be reduced. As a result, the size of the pixels PX can be reduced, which enables fine pixels.

[0067] The data driver DD may be connected to one or more data lines DL. The data driver DD may supply one or more data signals to the data lines DL. The data driver DD may receive digital video data and a data control signal from the timing controller 400. The data driver DD may convert the digital video data into an analog data voltage based on the data control signal from the timing controller 400, and may supply the analog data voltage to the data lines DL. In this case, the pixels PX located on one horizontal line may be selected by a write gate signal from the gate driver GD, and the data voltage may be supplied to the selected pixels PX located on one horizontal line. For example, the data driver DD may generate one or more data voltages based on the data control signal from the timing controller 400, and may supply the generated data voltages to the data lines DL. The data driver DD may generate a reference voltage, and may supply the generated reference voltage to the data lines DL.

[0068] The common circuit CMC may include one or more sub-common circuits SCC. The sub-common circuits SCC may be arranged in a column in the second direction DR2 in the non-display area NDA. Each of the sub-common circuits SCC may be commonly connected to the pixels PX located in one horizontal line. For example, referring to Figure 2 , the common circuit CMC may include five sub-common circuits SCC (for example, a first sub-common circuit SCC to a fifth sub-common circuit SCC sequentially arranged in the opposite direction of the second direction DR2), the first sub-common circuit SCC may be commonly connected to six pixels PX closely aligned with the first sub-common circuit SCC in the first direction DR1, the second sub-common circuit SCC may be commonly connected to six pixels PX closely aligned with the second sub-common circuit SCC in the first direction DR1, the third sub-common circuit SCC may be commonly connected to six pixels PX closely aligned with the third sub-common circuit SCC in the first direction DR1, the fourth sub-common circuit SCC may be commonly connected to six pixels PX closely aligned with the fourth sub-common circuit SCC in the first direction DR1, and the fifth sub-common circuit SCC may be commonly connected to six pixels PX closely aligned with the fifth sub-common circuit SCC in the first direction DR1.

[0069] Figure 3 It shows Figure 2 Schematic diagram of an equivalent circuit of an exemplary pixel PX and a sub-common circuit SCC connected to the exemplary pixel PX.

[0070] Reference Figure 3 , the pixel PX may include a driving transistor Td, a switching transistor Ts, a first capacitor C1, a second capacitor C2, and a light emitting element ED.

[0071] The driving transistor Td may include a gate electrode, a source electrode, a drain electrode, and a body electrode. The driving transistor Td may control a source-drain current (hereinafter referred to as a driving current) based on a data voltage applied to the gate electrode. The driving current flowing through the channel region of the driving transistor Td may be proportional to the square of the difference between the threshold voltage and the voltage between the source electrode and the gate electrode. The gate electrode of the driving transistor Td may be electrically connected to a first node N1, the source electrode of the driving transistor Td may be electrically connected to a second node N2, the drain electrode of the driving transistor Td may be electrically connected to a third node N3, and the body electrode of the driving transistor Td may be electrically connected to a driving voltage line VDL that transmits a driving voltage VDD.

[0072] The light emitting element ED may emit light when receiving a driving current. The brightness or lightness of the light emitting element ED may be proportional to the size of the driving current. The light emitting element ED may be an organic light emitting diode (OLED) including a first electrode (e.g., an anode), a second electrode (e.g., a cathode), and an organic light emitting layer between the first electrode and the second electrode. As another example, the light emitting element ED may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor between the first electrode and the second electrode. As another example, the light emitting element ED may be a quantum dot light emitting element including a first electrode, a second electrode, and a quantum dot light emitting layer between the first electrode and the second electrode. As another example, the light emitting element ED may be a micro light emitting diode (micro LED). The first electrode of the light emitting element ED may be electrically connected to the third node N3. The second electrode of the light emitting element ED may be electrically connected to a common voltage line VSL that transmits a common voltage VSS.

[0073] The switch transistor Ts can be turned on by the write gate signal GW from the write gate line GWL, so that the data line DL and the first node N1 are electrically connected. The gate electrode of the switch transistor Ts can be electrically connected to the write gate line GWL, the source electrode of the switch transistor Ts can be electrically connected to the data line DL, the drain electrode of the switch transistor Ts can be electrically connected to the first node N1, and the body electrode of the switch transistor Ts can be electrically connected to the driving voltage line VDL. The data line DL can transmit a data voltage ( Figure 4 "Data voltage Vdt") or reference voltage ( Figure 4 The “reference voltage Vref”).

[0074] The first capacitor C1 may be electrically connected between the first node N1 and the second node N2. For example, a first electrode of the first capacitor C1 may be electrically connected to the first node N1, and a second electrode of the first capacitor C1 may be electrically connected to the second node N2.

[0075] The second capacitor C2 may be electrically connected between the second node N2 and the driving voltage line VDL. For example, a first electrode of the second capacitor C2 may be electrically connected to the second node N2, and a second electrode of the second capacitor C2 may be electrically connected to the driving voltage line VDL.

[0076] The sub common circuit SCC may include an initialization transistor Ti.

[0077] The initialization transistor Ti may be turned on by an initialization gate signal GI from the initialization gate line GIL, thereby electrically connecting the third node N3 to the common voltage line VSL. The gate electrode of the initialization transistor Ti may be electrically connected to the initialization gate line GIL, the source electrode of the initialization transistor Ti may be electrically connected to the third node N3, the drain electrode of the initialization transistor Ti may be electrically connected to the common voltage line VSL, and the body electrode of the initialization transistor Ti may be electrically connected to the driving voltage line VDL.

[0078] The third node N3 may be connected to the common line CL. In other words, the pixels PX (including Figure 3 The third nodes N3 of the pixels PX) may be commonly connected to the common line CL.

[0079] In one embodiment, since pixels PX located on one horizontal line can share one sub-common circuit SCC, some transistors (eg, initialization transistor Ti) can be removed from each of the pixels PX. As a result, the size of each pixel PX can be reduced, enabling fine pixels to be realized.

[0080] Figure 4 It shows Figure 3 Schematic timing diagram of an emission signal EM, a write gate signal GW, an initialization gate signal GI, a reference voltage Vref and a data voltage Vdt.

[0081] Reference Figure 4 , also refer to Figure 1 and Figure 3 , the display device 10 may operate based on an initialization period P1, a threshold voltage detection period P2, a data writing period P3, and an emission period P4.

[0082] During each of the initialization period P1, the threshold voltage detection period P2, the data writing period P3, and the emission period P4, the emission signal EM, the write gate signal GW, and the initialization gate signal GI may have an effective level or an ineffective level. Here, the effective level may refer to a voltage or level that can turn on a transistor. In other words, a signal having an effective level may have a voltage greater than the threshold voltage of the corresponding transistor. For example, referring to Figure 3, when the driving transistor Td, the switching transistor Ts and the initialization transistor Ti are P-type transistors, the effective level of each signal for the driving transistor Td, the switching transistor Ts and the initialization transistor Ti may mean a low level (eg, a negative level or a low voltage level).

[0083] The non-active level may refer to a voltage or level (e.g., a cut-off voltage) that can turn off a transistor. For example, a signal having a non-active level may have a voltage less than a threshold voltage of a corresponding transistor. Figure 3 , when the driving transistor Td, the switching transistor Ts and the initialization transistor Ti are P-type transistors, the inactive level of each signal for the driving transistor Td, the switching transistor Ts and the initialization transistor Ti may mean a high level (eg, a positive level or a high voltage level).

[0084] As another example, in the case where the driving transistor Td, the switching transistor Ts, and the initialization transistor Ti are N-type transistors, the valid level of each signal may mean a high level (e.g., a positive level or a high voltage level), and the invalid level of each signal may mean a low level (e.g., a negative level or a low voltage level).

[0085] During the initialization period P1, each of the emission signal EM, the write gate signal GW, and the initialization gate signal GI may have an effective level. During the initialization period P1, the write gate signal GW may have an inactive level for a period of time before the end of the initialization period P1 (e.g., before the emission signal EM changes from an active level to an inactive level). During the initialization period P1, a reference voltage Vref may be applied to the data line DL.

[0086] During the threshold voltage detection period P2, the initialization gate signal GI may have an effective level, and each of the emission signal EM and the write gate signal GW may have an ineffective level. During the threshold voltage detection period P2, the reference voltage Vref may be applied to the data line DL. The data voltage Vdt may be applied to the data line DL for a period of time before the threshold voltage detection period P2 ends (e.g., before the write gate signal GW changes from an ineffective level to an effective level).

[0087] During the data write cycle P3, each of the write gate signal GW and the initialization gate signal GI may have an effective level, and the emission signal EM may have an ineffective level. The write gate signal GW may have an ineffective level for a period of time before the data write cycle P3 ends (for example, before the emission signal EM changes from an ineffective level to an effective level). During the data write cycle P3, a data voltage Vdt may be applied to the data line DL. Here, the data voltage Vdt may be a voltage having a grayscale (or brightness) for displaying an image. A reference voltage Vref may be applied to the data line DL for a period of time before the data write cycle P3 ends (for example, before the emission signal EM changes from an ineffective level to an effective level).

[0088] During the emission period P4, the emission signal EM may have an effective level, and each of the write gate signal GW and the initialization gate signal GI may have an inactive level. The initialization gate signal GI may have an active level for a period of time after the emission period P4 starts (e.g., after the emission signal EM changes from an inactive level to an active level). During the emission period P4, a reference voltage Vref may be applied to the data line DL.

[0089] The reference voltage Vref, the driving voltage VDD, and the common voltage VSS may be DC voltages. The reference voltage Vref may be lower than the driving voltage VDD and higher than the common voltage VSS.

[0090] In the following we will refer to Figures 5 to 8 The operation of the display device 10 is described below. Figures 5 to 8 , the transistors circled with a dotted circle are transistors in an on state, and the transistors not circled with a dotted circle are transistors in an off state.

[0091] In the following we will refer to Figure 4 and Figure 5 The operation of the display device 10 during the initialization period P1 will be described.

[0092] Figure 5 It shows that Figure 4 During the initialization period P1 Figure 3 A schematic diagram of an equivalent circuit showing the operation of the device 10.

[0093] Reference Figure 4 and Figure 5Each of the emission signal EM, the write gate signal GW, and the initialization gate signal GI may have an effective level. The write gate signal GW may have an inactive level for a period of time before the end of the initialization period P1 (e.g., before the emission signal EM changes from an effective level to an inactive level). During the initialization period P1, a reference voltage Vref may be applied to the data line DL.

[0094] An emission signal EM having an active level may be applied to a gate electrode of the emission control transistor Te through the emission line EML. As a result, the emission control transistor Te may be turned on.

[0095] A write gate signal GW having an active level may be applied to the gate electrode of the switching transistor Ts through the write gate line GWL. As a result, the switching transistor Ts may be turned on.

[0096] An initialization gate signal GI having an active level may be applied to a gate electrode of the initialization transistor Ti through the initialization gate line GIL. As a result, the initialization transistor Ti may be turned on.

[0097] During the initialization period P1, as the switch transistor Ts is turned on, the drive transistor Td may also be turned on. For example, the reference voltage Vref from the data line DL may be applied to the gate electrode of the drive transistor Td through the turned-on switch transistor Ts. Because the reference voltage Vref is less than the drive voltage VDD applied to the source electrode (i.e., the second node N2) of the drive transistor Td, the drive transistor Td may be turned on. In response to the drive transistor Td being turned on, the voltage of the drain electrode (i.e., the third node N3) of the drive transistor Td may have a value corresponding to the drive voltage VDD.

[0098] During the initialization period P1, when the switch transistor Ts, the initialization transistor Ti and the emission control transistor Te are turned on, the gate electrode (i.e., the first node N1), the source electrode (i.e., the second node N2) and the drain electrode (i.e., the third node N3) of the driving transistor Td can be initialized. For example, the reference voltage Vref from the data line DL can be applied to the first node N1 as the gate electrode of the driving transistor Td by the turned-on switch transistor Ts. The driving voltage VDD from the driving voltage line VDL can be applied to the second node N2 as the source electrode of the driving transistor Td by the turned-on emission control transistor Te. The common voltage VSS from the common voltage line VSL can be applied to the third node N3 as the drain electrode of the driving transistor Td by the turned-on initialization transistor Ti. Therefore, the voltages of the gate electrode, the source electrode and the drain electrode of the driving transistor Td can be initialized. Specifically, the gate electrode of the driving transistor Td can be initialized by the reference voltage Vref, the source electrode of the driving transistor Td can be initialized by the driving voltage VDD, and the drain electrode of the driving transistor Td can be initialized by the common voltage VSS. Furthermore, since the common voltage VSS is applied to both the first and second electrodes of the light emitting element ED, the voltage across the light emitting element ED during the initialization period P1 may be less than its threshold voltage. Therefore, the light emitting element ED may remain off during the initialization period P1.

[0099] In the following we will refer to Figure 4 and Figure 6 The operation of the display device 10 during the threshold voltage detection period P2 will be described.

[0100] Figure 6 It shows that Figure 4 The threshold voltage detection period P2 Figure 3 A schematic diagram of an equivalent circuit showing the operation of the device 10.

[0101] Reference Figure 4 and Figure 6 During the threshold voltage detection period P2, the initialization gate signal GI may have an effective level, and each of the emission signal EM and the write gate signal GW may have an ineffective level. During the threshold voltage detection period P2, the reference voltage Vref may be applied to the data line DL. During a period before the threshold voltage detection period P2 ends (e.g., before the write gate signal GW changes from an ineffective level to an effective level), the data voltage Vdt may be applied to the data line DL.

[0102] An initialization gate signal GI having an active level may be applied to a gate electrode of the initialization transistor Ti through the initialization gate line GIL. As a result, the initialization transistor Ti may be turned on.

[0103] An emission signal EM having a non-active level may be applied to the gate electrode of the emission control transistor Te through the emission line EML. As a result, the emission control transistor Te may be turned off.

[0104] A write gate signal GW having a non-active level may be applied to the gate electrode of the switching transistor Ts through the write gate line GWL. As a result, the switching transistor Ts may be turned off. As the switching transistor Ts is turned off, the first node N1 may be maintained in a floating state.

[0105] During the threshold voltage detection period P2 , the driving transistor Td may be maintained in a turned-on state due to the reference voltage Vref and the driving voltage VDD previously applied to the first and second nodes N1 and N2 , respectively (eg, during the initialization period P1 ).

[0106] In the case where the emission control transistor Te, the driving transistor Td and the initialization transistor Ti are turned on, the driving current can flow from the driving voltage line VDL to the common voltage line VSL. The driving current can cause the voltage of the second node N2 (i.e., the voltage of the source electrode of the driving transistor Td) to fluctuate in a decreasing manner. Due to the voltage fluctuation of the second node N2 and the coupling of the first capacitor C1, the voltage of the first node N1 (i.e., the voltage of the gate electrode of the driving transistor Td) can also fluctuate. Therefore, the gate-source voltage of the driving transistor Td can remain constant. However, when the voltage of the body electrode of the driving transistor Td (i.e., the driving voltage VDD) remains constant, the voltage of the second node N2 fluctuates, and as a result, the absolute value of the threshold voltage (Vth) of the driving transistor Td is offset in an increasing manner. For example, the threshold voltage (Vth) of the driving transistor Td can increase in the negative direction. In the case where the threshold voltage (Vth) of the driving transistor Td gradually increases to become substantially equal to the gate-source voltage, the driving transistor Td is turned off, and the voltage of the driving transistor Td at the corresponding moment can be stored by the first capacitor C1. In other words, the threshold voltage (Vth) of the driving transistor Td may be detected by the first capacitor C1. Therefore, in the case where the driving transistor Td is turned off during the threshold voltage detection period P2, the threshold voltage (Vth) of the driving transistor Td may be stored in the first capacitor C1.

[0107] Therefore, during the threshold voltage detection period P2, the first capacitor C1 may detect and maintain the threshold voltage (Vth) of the driving transistor Td.

[0108] During the threshold voltage detection period P2 , because the voltage across both ends of the light emitting element ED is maintained at the same voltage (eg, maintained at the common voltage VSS), the light emitting element ED may remain turned off.

[0109] In the following we will refer to Figure 4 and Figure 7 The operation of the display device 10 during the data writing period P3 will be described.

[0110] Figure 7 It shows that Figure 4 During the data write cycle P3 Figure 3 A schematic diagram of an equivalent circuit showing the operation of the device 10.

[0111] Reference Figure 4 and Figure 7 During the data writing period P3, each of the write gate signal GW and the initialization gate signal GI may have an effective level, and the emission signal EM may have an ineffective level. The write gate signal GW may have an ineffective level for a period of time before the end of the data writing period P3 (for example, before the emission signal EM changes from an ineffective level to an effective level). During the data writing period P3, a data voltage Vdt may be applied to the data line DL. Here, the data voltage Vdt may be a voltage with a specific gray level (or brightness) for displaying an image. The reference voltage Vref may be applied to the data line DL for a period of time before the end of the data writing period P3 (for example, before the emission signal EM changes from an ineffective level to an effective level).

[0112] A write gate signal GW having an active level may be applied to the gate electrode of the switching transistor Ts through the write gate line GWL. As a result, the switching transistor Ts may be turned on.

[0113] An initialization gate signal GI having an active level may be applied to a gate electrode of the initialization transistor Ti through the initialization gate line GIL. As a result, the initialization transistor Ti may be turned on.

[0114] An emission signal EM having a non-active level may be applied to the gate electrode of the emission control transistor Te through the emission line EML. As a result, the emission control transistor Te may be turned off.

[0115] like Figure 7 As shown in , the data voltage Vdt may be applied to the first node N1 through the data line DL and the turned-on switching transistor Ts. Here, in the case where the driving transistor Td turned off during the previous data writing cycle P3 remains turned off during the current data writing cycle P3, the second node N2 may remain in a floating state. In an embodiment, during the data writing cycle P3, the driving transistor Td may have a weakly turned-on state, but may remain almost in a floating state.

[0116] Since the second node N2 is maintained in a floating state, the voltage of the second node N2 can increase as much voltage as the voltage coupled by the first capacitor C1 (e.g., the data voltage Vdt). Specifically, the voltage of the second node N2 may correspond to the sum of the data voltage Vdt and the threshold voltage (Vth) of the driving transistor Td (e.g., the absolute value of the threshold voltage (Vth) of the driving transistor Td). Because the data voltage Vdt can be divided by the first capacitor C1 and the second capacitor C2, the range of the data voltage Vdt (e.g., the range of grayscale) can be expanded. Therefore, fine grayscale expression becomes possible, which potentially improves the display quality of the display device 10. In one embodiment, the capacitance of the first capacitor C1 and the second capacitor C2 may be the same, but the present invention is not limited thereto. As another example, the capacitance of the second capacitor C2 may be greater than the capacitance of the first capacitor C1. For example, the ratio of the capacitance of the second capacitor C2 to the capacitance of the first capacitor C1 may be about 2:1.

[0117] During the data writing period P3, the first capacitor C1 can maintain a differential voltage (e.g., a gate-source voltage) between the first node N1 as the gate electrode of the driving transistor Td and the source electrode of the driving transistor Td. The gate-source voltage may include not only the data voltage Vdt but also the threshold voltage (Vth) of the driving transistor Td.

[0118] During the data writing period P3 , since the voltage across both ends of the light emitting element ED is maintained at the same voltage (eg, the common voltage VSS), the light emitting element ED may remain turned off during the data writing period P3 .

[0119] In the following we will refer to Figure 4 and Figure 8 The operation of the display device 10 during the emission period P4 is described.

[0120] Figure 8 It shows that Figure 4 During the transmission cycle P4 Figure 3 A schematic diagram of an equivalent circuit showing the operation of the device 10.

[0121] Reference Figure 4 and Figure 8 During the emission period P4, the emission signal EM may have an effective level, and each of the write gate signal GW and the initialization gate signal GI may have an inactive level. The initialization gate signal GI may have an active level for a period of time after the emission period P4 starts (e.g., after the emission signal EM changes from an inactive level to an active level). In addition, during the emission period P4, a reference voltage Vref may be applied to the data line DL.

[0122] An emission signal EM having an active level may be applied to a gate electrode of the emission control transistor Te through the emission line EML. As a result, the emission control transistor Te may be turned on.

[0123] A write gate signal GW having a non-active level may be applied to the gate electrode of the switching transistor Ts through the write gate line GWL. As a result, the switching transistor Ts may be turned off.

[0124] An initialization gate signal GI having a non-active level may be applied to a gate electrode of the initialization transistor Ti through the initialization gate line GIL. As a result, the initialization transistor Ti may be turned off.

[0125] During the emission period P4 , the driving transistor Td may be maintained in a turned-on state due to the gate-source voltage maintained by the first capacitor C1 .

[0126] During the emission period P4, as the emission control transistor Te and the driving transistor Td are turned on, the driving voltage VDD can be applied to the first electrode (i.e., the third node N3) of the light emitting element ED through the turned-on emission control transistor Te and the turned-on driving transistor Td. Because the gate-source voltage maintained by the first capacitor C1 may include the threshold voltage (Vth) of the driving transistor Td, the magnitude of the driving current flowing through the light emitting element ED can be determined based on the data voltage Vdt and the threshold voltage (Vth) of the driving transistor Td. Therefore, the driving current applied to the light emitting element ED can accurately reflect the magnitude of the data voltage VDD. In other words, the supplied driving current can have an accurate value compensated for the threshold voltage (Vth) of the driving transistor Td. Therefore, the driving current can be determined by compensating for different threshold voltages (Vth) of the driving transistor Td for different pixels PX, and therefore, the brightness deviation between the pixels PX caused by such different threshold voltages (Vth) can be minimized. Therefore, the display quality of the display device 10 can be improved.

[0127] During the emission period P4, the voltage of the first node N1 (eg, the voltage of the gate electrode of the driving transistor Td) may have a value corresponding to “VDD−(Vref+|Vth|+Vdt′)”, where Vdt′ may be the voltage of the second node N2.

[0128] Fig. 9 It shows Figure 2 Schematic diagram of another exemplary pixel PX and an equivalent circuit of a sub-common circuit SCC connected to the exemplary pixel PX.

[0129] Fig. 9 The examples in Figure 3The embodiments of the present invention differ at least in the configuration of the initialization transistor Ti of the sub-common circuit SCC and will therefore be described below, focusing mainly on the embodiment of the present invention. Figure 3 Differences between the embodiments.

[0130] Reference Fig. 9 , the initialization transistor Ti may be turned on by the initialization gate signal GI from the initialization gate line GIL, so that the third node N3 and the common voltage line VSL are electrically connected. The gate electrode of the initialization transistor Ti may be electrically connected to the initialization gate line GIL, the source electrode of the initialization transistor Ti may be electrically connected to the third node N3, the drain electrode of the initialization transistor Ti may be electrically connected to the common voltage line VSL, and the body electrode of the initialization transistor Ti may be electrically connected to the common voltage line VSL transmitting the common voltage VSS.

[0131] The initialization transistor Ti may be of a type opposite to other transistors of the pixel PX (e.g., the switch transistor Ts, the emission control transistor Te, and the drive transistor Td). For example, when the switch transistor Ts, the emission control transistor Te, and the drive transistor Td are P-type transistors (e.g., P-type metal oxide semiconductor field effect transistors (MOSFETs)), the initialization transistor Ti may be an N-type transistor (e.g., an N-type MOSFET).

[0132] N-type transistors can be more conducive to transmitting the common voltage VSS than P-type transistors. In other words, when the initialization transistor Ti connected to the common voltage line VSL through the source electrode is formed as an N-type transistor with high electron mobility, the common voltage VSS can be effectively transmitted through the turned-on initialization transistor Ti.

[0133] Fig.10 It shows Figure 2 Schematic diagram of another exemplary pixel PX and an equivalent circuit of a sub-common circuit SCC connected to the exemplary pixel PX.

[0134] Fig.10 The examples in Figure 3 The embodiments of the present invention differ at least in the configuration of the initialization transistor Ti of the sub-common circuit SCC and will therefore be described below, focusing mainly on the embodiment of the present invention. Figure 3 Differences between the embodiments.

[0135] Reference Fig.10 , the sub-common circuit SCC may include a plurality of initialization transistors Ti1 and Ti2 connected in series. For example, the sub-common circuit SCC may include a first initialization transistor Ti1 and a second initialization transistor Ti2.

[0136] The first and second initialization transistors Ti1 and Ti2 may be connected in series between the third node N3 and the common voltage line VSL.

[0137] The first initialization transistor Ti1 and the second initialization transistor Ti2 may be of a type opposite to other transistors (e.g., the switch transistor Ts, the emission control transistor Te, and the drive transistor Td) of the pixel PX. For example, in the case where the switch transistor Ts, the emission control transistor Te, and the drive transistor Td are P-type transistors (e.g., P-type MOSFETs), the first initialization transistor Ti1 and the second initialization transistor Ti2 may be N-type transistors (e.g., N-type MOSFETs).

[0138] The first initialization transistor Ti1 may be turned on by the initialization gate signal GI from the initialization gate line GIL, so that the third node N3 is electrically connected to the drain electrode of the second initialization transistor Ti2. The gate electrode of the first initialization transistor Ti1 may be electrically connected to the initialization gate line GIL, the drain electrode of the first initialization transistor Ti1 may be electrically connected to the third node N3, the source electrode of the first initialization transistor Ti1 may be electrically connected to the drain electrode of the second initialization transistor Ti2, and the body electrode of the first initialization transistor Ti1 may be electrically connected to the common voltage line VSL.

[0139] The second initialization transistor Ti2 may be turned on by an initialization gate signal GI from the initialization gate line GIL, so that the source electrode of the first initialization transistor Ti1 is electrically connected to the common voltage line VSL. The gate electrode of the second initialization transistor Ti2 may be electrically connected to the initialization gate line GIL, the drain electrode of the second initialization transistor Ti2 may be electrically connected to the source electrode of the first initialization transistor Ti1, and the source electrode and the body electrode of the second initialization transistor Ti2 may be electrically connected to the common voltage line VSL.

[0140] In the case where the sub-common circuit SCC includes a plurality of initialization transistors connected in series between the third node N3 and the common voltage line VSL, leakage currents of the plurality of initialization transistors may be minimized.

[0141] Fig.11 yes Figure 1 FIG. 1 is a schematic layout diagram of another exemplary display panel 100 .

[0142] Fig.11 The display panel 100 and Figure 2 The display panel of FIG. 1 differs at least in that it includes a plurality of common circuits CMC1 and CMC2 and will therefore be described below, focusing primarily on the common circuits CMC1 and CMC2. Figure 2 The display panel 100 is different.

[0143] Reference Fig.11 , the display panel 100 may include a first common circuit CMC1 disposed on one side of the non-display area NDA and a second common circuit CMC2 disposed on the other side of the non-display area NDA.

[0144] One side of the common line CL may be connected to the first common circuit CMC1 , and the other side of the common line CL may be connected to the second common circuit CMC2 .

[0145] The first common circuit CMC1 may include a plurality of first sub-common circuits SCC1. Figure 2 The sub-common circuits SCC are substantially the same or similar, and therefore, a detailed description thereof will be omitted.

[0146] Each of the first sub-common circuits SCC1 may include Figure 3 or Fig. 9 Initialization transistor Ti or Fig.10 The first initialization transistor Ti1 and the second initialization transistor Ti2.

[0147] The second common circuit CMC2 may include a plurality of second sub-common circuits SCC2. Figure 2 The sub-common circuits SCC are substantially the same or similar, and therefore, a detailed description thereof will be omitted.

[0148] Each of the second sub-common circuits SCC2 may include Figure 3 or Fig. 9 Initialization transistor Ti or Fig.10 The first initialization transistor Ti1 and the second initialization transistor Ti2.

[0149] The first and second sub-common circuits SCC1 and SCC2 connected to the same common line CL may operate simultaneously. For example, initialization transistors of the first and second sub-common circuits SCC1 and SCC2 connected to either side of the single common line CL may be turned on substantially simultaneously by the same initialization gate signal GI.

[0150] according to Fig.11 In the embodiment, since the common voltage VSS can be applied to both sides of each common line CL, the deviation of the common voltage VSS supplied to the pixels PX located at either end of each horizontal line (for example, the pixels PX located near the first common circuit CMC1 and the second common circuit CMC2 of each horizontal line) can be minimized.

[0151] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure belongs will be able to make various modifications and changes.Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0152] The embodiments disclosed in this disclosure are not intended to limit the technical spirit of the disclosure, but are intended to describe the technical spirit of the disclosure, and the scope of the technical spirit of the disclosure is not limited by these embodiments. The protection scope of the disclosure should be interpreted by the attached claims, and should be interpreted as all technical spirits within the equivalent scope are included in the scope of the disclosure.

Claims

1. A display device, wherein: The display device comprises: A display panel having a display area and a non-display area; A plurality of pixels are arranged in the display area; a light emitting element disposed in each of the plurality of pixels; a driving transistor provided in each of the plurality of pixels and electrically connected to the light emitting element; and A common circuit is provided in the non-display area and is electrically connected to a node between the light emitting element and the driving transistor.

2. The display device according to claim 1, wherein: The common circuit is electrically connected to the nodes through a common line.

3. The display device according to claim 1, wherein: The common circuit includes an initialization transistor electrically connected to the node and receiving a common voltage and an initialization gate signal.

4. The display device according to claim 3, wherein: The initialization transistor is electrically connected between the node and a common voltage line transmitting the common voltage, and The initialization gate signal is applied to a gate electrode of the initialization transistor.

5. The display device according to claim 1, wherein: Each of the plurality of pixels further comprises: a switching transistor electrically connected between the data line and the gate electrode of the driving transistor; and The emission control transistor is electrically connected between the source electrode of the driving transistor and a driving voltage line for transmitting a driving voltage.

6. The display device according to claim 5, wherein: A write gate signal is input to the gate electrode of the switching transistor, and An emission signal is input to a gate electrode of the emission control transistor.

7. The display device according to claim 6, wherein: The display device further includes: A gate driver transmits an initialization gate signal to the common circuit and transmits the write gate signal and the emission signal to each of the plurality of pixels.

8. The display device according to claim 7, wherein: During the initialization cycle, Each of the emission signal, the write gate signal, and the initialization gate signal has a valid level, and A reference voltage is applied to the data line.

9. The display device according to claim 8, wherein: The write gate signal has a non-active level during a portion of the initialization period before the initialization period ends.

10. The display device according to claim 8, wherein: During the threshold voltage detection period after the initialization period, The initialization gate signal has the effective level, Each of the emission signal and the write gate signal has a non-active level, and The reference voltage is applied to the data line, wherein the data voltage is applied to the data line during a portion of the threshold voltage detection period before the threshold voltage detection period ends, Wherein, during the data writing period after the threshold voltage detection period, Each of the write gate signal and the initialization gate signal has the effective level, The transmission signal has the non-active level, and A data voltage is applied to the data line, Before the end of the data writing cycle, during a portion of the data writing cycle, The write gate signal has the non-active level, and The reference voltage is applied to the data line, wherein, during the transmission period after the data writing period, The transmission signal has the effective level, The write gate signal has the non-active level, and the initialization gate signal has a non-active level, and The reference voltage is applied to the data line, Wherein, after the emission period starts, the initialization gate signal has the effective level during a portion of the emission period.

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