Display panel and compensation method thereof

Abstract

The invention provides a display panel and a compensation method thereof, the display panel comprises a data line, a plurality of first sub-pixels connected to the same data line, and at least one second sub-pixel, the second sub-pixel is arranged among the plurality of first sub-pixels, the compensation method comprises the following steps: in a first time period, controlling each first sub-pixel to load a corresponding first data voltage, the plurality of first data voltages are in a first voltage interval; and in a second time period, each second sub-pixel is controlled to load a corresponding second data voltage, the multiple second data voltages are located in a second voltage interval, the second time period and the first time period are not overlapped, and the second voltage interval and the first voltage interval are not overlapped, so that the effect of improving visual angle characteristic deterioration in the liquid crystal display panel is improved, and the display effect of the liquid crystal display panel is improved. And the picture display reliability of the display panel is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, in particular to the manufacture of display devices, and specifically to a display panel and a compensation method thereof. Background Art

[0002] In liquid crystal display panels, the four-domain pixel architecture can achieve both high resolution and high penetration compared to the eight-domain pixel architecture. However, the four-domain pixel architecture has the problem of high side brightness, which leads to deterioration of viewing angle characteristics. Generally, two adjacent sub-pixels of the same color are set to a higher grayscale and a lower grayscale relative to the original grayscale to reduce the side brightness, thereby improving the deterioration of viewing angle characteristics.

[0003] However, since sub-pixels of the same color are all connected to the same data line, the above operation will cause the data signal transmitted by the data line to include alternating higher data voltages and lower data voltages, that is, the jump between two adjacent data voltages is large, resulting in low charging efficiency of the sub-pixels, causing the voltages actually reached by the two adjacent sub-pixels after being charged to be less than the higher data voltage and greater than the lower data voltage, respectively, thereby reducing the difference between the data voltages of the two, which is not conducive to reducing the side-view brightness and reduces the improvement effect of the deterioration of the viewing angle characteristics.

[0004] Therefore, the effect of improving the deterioration of viewing angle characteristics of the existing four-domain pixel architecture is affected by the low charging efficiency and is not ideal. Summary of the invention

[0005] The object of the present invention is to provide a display panel and a compensation method thereof to solve the technical problem that the effect of improving the deterioration of the viewing angle characteristics of the existing four-domain pixel architecture is affected by the low charging efficiency.

[0006] The present invention provides a compensation method for a display panel, comprising:

[0007] The display panel includes a plurality of data lines, a plurality of first sub-pixels connected to the same data line, and at least one second sub-pixel, wherein the second sub-pixel is disposed between the plurality of first sub-pixels, and the method includes:

[0008] In a first time period, each of the first sub-pixels is controlled to load a corresponding first data voltage, and a plurality of the first data voltages are in a first voltage range;

[0009] In the second time period, each of the second sub-pixels is controlled to load a corresponding second data voltage, a plurality of the second data voltages are in a second voltage interval, the second time period does not overlap with the first time period, and the second voltage interval does not overlap with the first voltage interval.

[0010] In one embodiment, a plurality of first data voltages respectively loaded on a plurality of first sub-pixels are the same, and / or a plurality of second data voltages respectively loaded on a plurality of second sub-pixels are the same.

[0011] In one embodiment, the number of the second sub-pixels is greater than or equal to 2, the color of the first sub-pixels is the same as the color of the second sub-pixels, and the first sub-pixels and the second sub-pixels are arranged alternately.

[0012] In one embodiment, the first time period and the second time period are included in the same frame period.

[0013] In one embodiment, the step of controlling each of the first sub-pixels to load a corresponding first data voltage includes:

[0014] Acquire a plurality of the first data voltages corresponding to a plurality of the first sub-pixels, and continuously arrange the plurality of the first data voltages to form a first data voltage string;

[0015] The first data voltage string is transmitted through the data line, and a plurality of the first sub-pixels are turned on in sequence, so that each of the first sub-pixels is loaded with a corresponding first data voltage.

[0016] In one embodiment, before the step of controlling each of the first sub-pixels to load the corresponding first data voltage and the step of controlling each of the second sub-pixels to load the corresponding second data voltage, the steps include:

[0017] An original data voltage string is obtained, where the original data voltage string includes a plurality of the first data voltages and at least one second data voltage corresponding to at least one second sub-pixel, and the second data voltages are arranged between the plurality of the first data voltages.

[0018] In one embodiment, the data line is further connected to at least one third sub-pixel, the third sub-pixel is disposed between a plurality of the first sub-pixels, and one first sub-pixel is disposed between the second sub-pixel and the third sub-pixel, and the method further includes:

[0019] In a third time period, each of the third sub-pixels is controlled to load a corresponding third data voltage, a plurality of the third data voltages are in a third voltage range, the third time period, the second time period and the first time period do not overlap, the third voltage range, the second voltage range and the first voltage range do not overlap, and the second voltage range and the third voltage range are both greater than or less than the first voltage range.

[0020] In one embodiment, the number of the second sub-pixels and the number of the third sub-pixels are both greater than or equal to 2, the data line is connected to a plurality of pixel groups, and each of the pixel groups includes one of the second sub-pixels, one of the first sub-pixels, one of the third sub-pixels and another of the first sub-pixels arranged in sequence.

[0021] In one embodiment, the display panel includes a plurality of sub-pixels, and the plurality of sub-pixels include a plurality of the first sub-pixels and a plurality of the second sub-pixels;

[0022] The step of controlling each of the first sub-pixels to load a corresponding first data voltage during the first period includes:

[0023] In a first sub-frame period in a frame period, a plurality of rows of sub-pixels are sequentially scanned, and when a plurality of rows of the first sub-pixels are sequentially turned on, a plurality of corresponding first data voltages are sequentially loaded, and the first time period is included in the first sub-frame period;

[0024] Wherein, the step of controlling each of the second sub-pixels to load the corresponding second data voltage during the second period includes:

[0025] In the second sub-frame period of the frame period, multiple rows of the sub-pixels are scanned in sequence, and when the multiple rows of the second sub-pixels are turned on in sequence, the corresponding multiple second data voltages are loaded in sequence, the second time period is included in the second sub-frame period, and the length of the first sub-frame period is equal to the length of the second sub-frame period.

[0026] The present invention also provides a display panel for executing any of the display panel compensation methods described above.

[0027] The present invention provides a display panel and a compensation method thereof. The display panel comprises a plurality of data lines, a plurality of first sub-pixels connected to the same data line, and at least one second sub-pixel. The second sub-pixel is arranged between the plurality of first sub-pixels. The method controls each of the first sub-pixels to load a corresponding first data voltage and each of the second sub-pixels to load a corresponding second data voltage in a non-overlapping first time period and a second time period, respectively. The first voltage interval in which the plurality of first data voltages are located and the second voltage interval in which the plurality of second data voltages are located do not overlap, so that the data line can continuously transmit a plurality of first data voltages with a smaller bar value, and then continuously transmit a plurality of second data voltages with a smaller bar value, so as to reduce the frequency of voltage jumps, thereby effectively improving the charging efficiency of the first sub-pixels and the charging efficiency of the second sub-pixels, thereby improving the effect of improving the deterioration of the viewing angle characteristics in the liquid crystal display panel, and improving the reliability of the display of the display panel picture. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The present invention is further described below by means of the accompanying drawings. It should be noted that the accompanying drawings described below are only used to explain some embodiments of the present invention, and those skilled in the art can also obtain other accompanying drawings based on these accompanying drawings without creative work.

[0029] Figures 1 to 3 A schematic top view of a display panel provided by an embodiment of the present invention.

[0030] Figures 4 to 6 , Fig.11 Several flow charts of the display panel compensation method provided by the embodiments of the present invention.

[0031] Figures 7 to 10 A schematic diagram of dividing data signals provided in an embodiment of the present invention.

[0032] Fig.12 It is the waveform diagram of some signals in the gate drive circuit. DETAILED DESCRIPTION

[0033] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0034] In the description of the present invention, the terms "first", "second", etc. are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include one or more of the said features. In addition, it should be noted that the drawings only provide structures that are closely related to the present invention, and some details that are not closely related to the invention are omitted. The purpose is to simplify the drawings and make the invention clear at a glance, rather than to indicate that the actual device is the same as the attached structure. Figure 1 The same is not a limitation of the actual device.

[0035] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase at various times in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0036] The present invention provides a compensation method for a display panel, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0037] In one embodiment, if Figures 1 to 3 As shown, the display panel 100 includes a plurality of data lines 10, a plurality of first sub-pixels 201 connected to the same data line 10, and at least one second sub-pixel 202, wherein the second sub-pixels 202 are disposed between the plurality of first sub-pixels 201; Figure 4 As shown, the compensation method of the display panel 100 includes but is not limited to the following steps.

[0038] S1, in a first time period, controlling each of the first sub-pixels to load a corresponding first data voltage, and a plurality of the first data voltages are in a first voltage interval.

[0039] In this embodiment, the type of the display panel 100 is not limited, and it can be, but not limited to, a liquid crystal panel or a self-luminous panel. The number of data lines 10 can be multiple, and each data line 10 can be connected to multiple sub-pixels. It can be considered that there is at least one data line 10 that is sequentially connected to a first part of first sub-pixels 201, at least one second sub-pixel 202, and a second part of second sub-pixels 202201. Further, the data signal transmitted by the data line 10 can be used to drive the corresponding multiple first sub-pixels 201 and the corresponding at least one second sub-pixel 202 to emit light.

[0040] S2, in a second time period, controlling each of the second sub-pixels to load a corresponding second data voltage, a plurality of the second data voltages are in a second voltage interval, the second time period does not overlap with the first time period, and the second voltage interval does not overlap with the first voltage interval.

[0041] Specifically, the plurality of first data voltages V1 and the plurality of second data voltages V2 in the present embodiment are respectively in the first voltage interval and the second voltage interval without intersection, that is, the first data voltage V1 and the second data voltage V2 have a large difference, and the second sub-pixel 202 is provided between the plurality of first sub-pixels 201. If the data signal includes the first part of the first data voltage V1, the at least one second data voltage V2 and the second part of the second sub-pixel 202201 which are arranged in sequence and correspond to the first part 201, the at least one second sub-pixel 202 and the second part of the second sub-pixel 202, respectively, it can be considered that when the data signal transmitted by the data line 10 switches from the first data voltage V1 to the second data voltage V2, When switching from the second data voltage V2 to the first data voltage V1, due to the large voltage jump, based on the parasitic capacitance between the data line 10 and the transistor in the pixel circuit, the voltage on the first sub-pixel 201 and the voltage on the second sub-pixel 202 slowly rise or fall during the charging process, causing the one of the first sub-pixel 201 and the second sub-pixel 202 that is later acted upon by the corresponding first data voltage V1 or second data voltage V2 to be insufficiently charged, that is, the absolute value of the difference between the voltage actually transmitted to the first sub-pixel 201 and the voltage transmitted to the second sub-pixel 202 will be smaller than the absolute value of the difference between the first data voltage V1 and the second data voltage V2.

[0042] It should be noted that, for the liquid crystal display panel 100, generally, the same data line 10 connects multiple sub-pixels of the same color. When improving the deterioration of the viewing angle characteristics, two adjacent sub-pixels of the same color are specially loaded with two voltages with a large voltage difference. Compared with loading a voltage between the two "voltages with a large voltage difference", the overall side-view brightness of the two can be reduced. Of course, when the liquid crystal display panel 100 and the self-luminous display panel 100 display the picture normally, there will also be a situation where two adjacent sub-pixels connected to the same data line 10 are loaded with two voltages with a large voltage difference.

[0043] It can be understood that the second time period in this embodiment does not overlap with the first time period, that is, the data line 10 in this embodiment transmits multiple first data voltages V1 with similar voltages (all in the first voltage interval, that is, multiple first data voltages V1 may not be completely the same) and multiple second data voltages V2 with similar voltages (all in the second voltage interval, that is, multiple second data voltages V2 may not be completely the same) in the first time period and the second time period, respectively. In the first time period and the second time period, there is almost no voltage jump, which effectively improves the charging efficiency of the first sub-pixel 201 and the charging efficiency of the second sub-pixel 202. That is, the effect of improving the deterioration of the viewing angle characteristics in the liquid crystal display panel 100 can be improved, and the reliability of the screen display of the display panel 100 can be improved.

[0044] In one embodiment, the first data voltages V1 loaded by the first sub-pixels 201 are the same, and / or the second data voltages V2 loaded by the second sub-pixels 202 are the same. That is, in the first period, the data line 10 is used to transmit a constant voltage (equal to the first data voltage V1), and / or, in the second period, the data line 10 is used to transmit a constant voltage (equal to the second data voltage V2), which can further reduce the voltage jump amplitude in at least one of the first period and the second period of the data line 10, that is, the voltage jump amplitude in at least one of the first period and the second period is 0, which can further improve the problem of insufficient charging of the first sub-pixel 201 and the second sub-pixel 202, thereby improving the effect of improving the deterioration of the viewing angle characteristics and the reliability of the display of the display panel 100.

[0045] In one embodiment, if Figures 1 to 3 As shown, each of the data lines 10 is connected to a corresponding plurality of the first sub-pixels 201 and a corresponding at least one second sub-pixel 202; Figure 5 As shown, the step S1 includes but is not limited to the following steps: S101, controlling each of the first sub-pixels 201 on each of the data lines 10 to load the corresponding first data voltage V1; the step S2 includes but is not limited to the following steps: S201, controlling each of the second sub-pixels 202 on each of the data lines 10 to load the corresponding second data voltage V2.

[0046] Specifically, the present embodiment further specifies that the arrangements of the first sub-pixels 201 and the second sub-pixels 202 connected to each data line 10 are the same. Combining step S101 and step S201, it can be seen that the multiple first sub-pixels 201 connected to each data line 10 in the present embodiment can be loaded with the first data voltage V1 in the first time period, and the multiple second sub-pixels 202 connected to each data line 10 can be loaded with the second data voltage V2 in the second time period, that is, in the first time period, the multiple data lines 10 can be controlled to transmit the multiple first data voltages V1 in sequence to be loaded to the corresponding multiple first sub-pixels 201 respectively, and in the second time period, the multiple data lines 10 can be controlled to transmit at least one second data voltage V2 in sequence to be loaded to the corresponding at least one second sub-pixel 202 respectively.

[0047] Among them, Figures 1 to 3As shown, the display panel 100 may further include a plurality of gate lines 30, and a sub-pixel corresponding to each data line 10 may be electrically connected to the same gate line 30, for example, a first sub-pixel 201 corresponding to each data line 10 may be electrically connected to the same gate line 30, a second first sub-pixel 201 corresponding to each data line 10 may be electrically connected to another gate line 30, and a first second sub-pixel 202 corresponding to each data line 10 may be electrically connected to yet another gate line 30. Each gate line may be used to transmit a corresponding gate signal to control the electrically connected plurality of sub-pixels (all being the first sub-pixel 201, the second sub-pixel 202 or other sub-pixels) to be turned on in the same time period, and the time period of the turn-on should satisfy that the plurality of voltages in the plurality of data signals transmitted by the plurality of data lines 10 in this time period are exactly equal to the plurality of voltages that should be loaded on the plurality of sub-pixels, so as to complete the correct transmission of the voltage.

[0048] For ease of description, the present invention takes a plurality of sub-pixels arranged in row and column directions to form a matrix as an example. It can be considered that in the first period, a plurality of gate lines (eg, Figure 1 At least the first and third gate lines, Figure 2 At least the 2nd, 4th, and 6th gate lines, Figure 3 The plurality of gate signals transmitted by the plurality of gate lines (for example, the second and sixth gate lines) respectively may include a plurality of gate effective pulses, and the plurality of gate effective pulses are arranged in sequence at the starting points on the time axis (the pulse widths may be the same), so that the corresponding plurality of rows of first sub-pixels 201 may be turned on in sequence to be loaded with the corresponding plurality of first data voltages V1 in sequence; similarly, in the first period, the plurality of gate lines (for example, the gate lines corresponding to the plurality of rows of second sub-pixels 202) may be turned on in sequence. Figure 1 At least the 2nd and 4th gate lines, Figure 2 At least the 1st and 5th gate lines, Figure 3 The multiple gate signals transmitted by at least the 1st and 5th gate lines (in the gate lines) may respectively include multiple gate effective pulses, and the starting points of the multiple gate effective pulses are arranged in sequence on the time axis (the pulse widths may be the same), so that the corresponding multiple rows of second sub-pixels 202 can be turned on in sequence to be loaded with the corresponding multiple second data voltages V2 in sequence.

[0049] In one embodiment, if Figure 1As shown, the number of the second sub-pixels 202 is greater than or equal to 2, the color of the first sub-pixel 201 is the same as the color of the second sub-pixel 202, and the first sub-pixel 201 and the second sub-pixel 202 are arranged alternately. Based on the above discussion, all the first data voltages V1 and all the second data voltages V2 are in the first voltage interval and the second voltage interval, respectively. Further, in this embodiment, the first sub-pixels 201 and the second sub-pixels 202 are arranged alternately, that is, two sub-pixels (the first sub-pixel 201 and the second sub-pixel 202) with the same color and arranged adjacently can be loaded with the first data voltage V1 and the second data voltage V2 with relatively large differences. Combined with the above discussion, it can be known that the problem of deterioration of the viewing angle characteristics of the multi-domain architecture in the liquid crystal display panel 100 can be improved.

[0050] Specifically, Figure 1 As shown, the colors of multiple sub-pixels connected to the same data line 10 can be the same. For example, from left to right, the first data line 10 can be provided with multiple blue sub-pixels B, the second data line 10 can be provided with multiple green sub-pixels G, and the third data line 10 can be provided with multiple red sub-pixels R. The multiple blue sub-pixels B, the multiple green sub-pixels G, and the multiple red sub-pixels R can all include multiple first sub-pixels 201 located in odd rows and multiple second sub-pixels 202 located in even rows. That is, for sub-pixels of each color, the first sub-pixels 201 and the second sub-pixels 202 loaded with the first data voltage V1 and the second data voltage V2, respectively, can be arranged alternately, so that the side-view brightness corresponding to each color sub-pixel can be reduced to improve the problem of deterioration of the overall viewing angle characteristics.

[0051] In one embodiment, if Figures 2 to 3 As shown, the data line 10 is further provided with at least one third sub-pixel 203, the third sub-pixel 203 is provided between a plurality of the first sub-pixels 201, and one first sub-pixel 201 is provided between the second sub-pixel 202 and the third sub-pixel 203. Figure 6 As shown, the method also includes but is not limited to the following steps.

[0052] S3, in the third time period, control each of the third sub-pixels to load the corresponding third data voltage, a plurality of the third data voltages are in a third voltage range, the third time period, the second time period and the first time period do not overlap, the third voltage range, the second voltage range and the first voltage range do not overlap, and the second voltage range and the third voltage range are both greater than or less than the first voltage range.

[0053] Among them, the order of steps S1 to S3 is not limited. According to the different voltages loaded on the sub-pixels, on the basis of being divided into the first sub-pixel 201 and the second sub-pixel 202, it can also be divided into at least one third sub-pixel 203 loaded with at least one third data voltage V3. Similarly, in order to improve the problem of deterioration of the viewing angle characteristics of the multi-domain architecture in the liquid crystal display panel 100, in this embodiment, a third sub-pixel 203 is provided between multiple first sub-pixels 201, and further, a first sub-pixel 201 is also provided between the second sub-pixel 202 and the third sub-pixel 203. Combined with the discussion in step S3 that "the second voltage interval and the third voltage interval are both greater than or less than the first voltage interval", it can be seen that in this embodiment, multiple first sub-pixels 201, at least one second data voltage V2, which are respectively loaded with larger or smaller first data voltages V1, and at least one third sub-pixel 203 are respectively loaded with larger or smaller first data voltages V1. The two sub-pixels 202 are respectively connected to the two ends of the first sub-pixel 201 loaded with a smaller or larger first data voltage V1. Similarly, the color of the first sub-pixel 201, the color of the second sub-pixel 202 and the color of the third sub-pixel 203 can be the same. In this way, it can still be achieved that two sub-pixels with the same color and arranged adjacently (one of the second sub-pixel 202 and the third sub-pixel 203, and the first sub-pixel 201) can be loaded with two voltages with large differences (one of the smaller or larger second voltage interval and the third interval, and the first voltage interval, respectively).

[0054] In combination with the above discussion, it can be seen that in this embodiment, multiple larger or smaller voltages are further divided into a second voltage interval or a third voltage interval, and at both ends of the first sub-pixel 201 corresponding to the first voltage interval, there are respectively provided a second sub-pixel 202 and a third sub-pixel 203 corresponding to the second voltage interval and the third voltage interval which are greater than or less than the first voltage interval but have differences, which further performs differentiated settings, which is more conducive to improving the deterioration of viewing angle characteristics.

[0055] It can be understood that, based on the multiple sub-pixels of the same color connected to the same data line 10, compared with only dividing them into the first sub-pixel 201 and the second sub-pixel 202, this embodiment can be understood as dividing the multiple voltages corresponding to the "multiple sub-pixels" into more voltage intervals (to obtain including but not limited to the above three voltage intervals) according to the upper limit and the lower limit, so as to further reduce the difference between every two voltage intervals; of course, this embodiment can also be understood as dividing the above-mentioned (corresponding to Figure 1) The first voltage interval or the second voltage interval is further divided. Here, taking the further division of the first voltage interval as an example, a new first voltage interval and a new third voltage interval can be obtained, and the difference between the two is also very small. Similarly, in this embodiment, in the third period different from the first period and the second period, the third data voltage V3 is applied to all the third sub-pixels 203 to control their light emission.

[0056] In one embodiment, if Figure 2 As shown, the number of the second sub-pixels 202 and the number of the third sub-pixels 203 are both greater than or equal to 2, and the data line 10 is connected to a plurality of pixel groups 40, each of which includes one second sub-pixel 202, one first sub-pixel 201, one third sub-pixel 203 and another first sub-pixel 201 arranged in sequence. Specifically, as discussed above, since the second voltage interval and the third voltage interval are both greater than or less than the first voltage interval, the second voltage interval and the third voltage interval here can be understood as Figure 1 Therefore, for a plurality of first sub-pixels 201 arranged continuously, three of the first sub-pixels 201 arranged continuously are taken as an example. Figure 2 As shown, it can be considered that a third sub-pixel 203 loaded with the third data voltage V3 can be provided between the two relatively front first sub-pixels 201, and a first sub-pixel 201 loaded with the first data voltage V1 can be provided between the two relatively rear first sub-pixels 201. Therefore, on the whole, the multiple sub-pixels (multiple blue sub-pixels B, multiple green sub-pixels G, and each of the multiple green sub-pixels G) connected to the same data line 10 can be divided into multiple pixel groups according to the above-mentioned division method.

[0057] Further, such as Figure 3 As shown, the multiple sub-pixels connected to the same data line 10 may also include multiple fourth sub-pixels 204. Similarly, in a fourth time period different from the first time period, the second time period and the third time period, each fourth sub-pixel may be controlled to load a corresponding fourth data voltage V4, and the multiple fourth data voltages V4 are in a fourth voltage interval. Similarly, it can be understood here that the multiple voltages corresponding to the "multiple sub-pixels" are evenly divided into more voltage intervals (to obtain including but not limited to the above four voltage intervals) according to the upper and lower limits, so as to further reduce the difference between every two voltage intervals; of course, it can also be understood here that the above-mentioned (corresponding to Figure 1 ) One of the first voltage interval and the second voltage interval is further divided to obtain a new first voltage interval and a new fourth voltage interval, and the other is further divided to obtain a new second voltage interval and a new third interval.

[0058] Specifically, Figure 3 As shown, here, taking the example that the first voltage interval and the fourth voltage interval are both greater than or less than the second voltage interval and the third voltage interval, taking the multiple sub-pixels connected to the same data line 10 as an example, the second sub-pixel 202 and the third sub-pixel 203 can be arranged alternately. Similarly, the multiple first sub-pixels 201 and the multiple fourth sub-pixels can be arranged alternately, and a first sub-pixel 201 or a fourth sub-pixel can be provided between adjacent second sub-pixels 202 and third sub-pixels 203. Correspondingly, it can also be met that a second sub-pixel 202 or a third sub-pixel 203 can be provided between adjacent first sub-pixels 201 and fourth sub-pixels. At this time, it can be considered that each pixel group includes the second sub-pixel 202, the first sub-pixel 201, the third sub-pixel 203 and the fourth sub-pixel connected in sequence.

[0059] In one embodiment, if Figures 1 to 3 As shown, the first time period and the second time period are included in the same frame period. Among them, the frame period of the present invention can be calculated according to the refresh rate of the display panel, and can be the inverse of the refresh rate. That is, within a frame period, it can be divided into at least a first time period and a second time period, and the multiple gate signals transmitted by multiple gate lines are respectively configured as discussed above. In the first time period, (all) data lines 10 are used to (all) first sub-pixels 201 (respectively) load corresponding (multiple) first data voltages V1, and in the second time period, (all) data lines 10 are used to (all) second sub-pixels 202 (respectively) load corresponding (multiple) second data voltages V2, that is, by controlling all first sub-pixels 201 to emit light and all second sub-pixels 202 to emit light in the same frame period through time-sharing control, so as to realize that the data line 10 can transmit the first data voltage V1 and the second data voltage V2 without alternating, so as to reduce the risk of large voltage jumps in the data signal, so as to improve the effect of improving the deterioration of the viewing angle characteristics in the liquid crystal display panel 100 and the reliability of the display of the display panel 100. In one frame period, a plurality of first sub-pixels 201 start to emit light and a plurality of second sub-pixels 202 start to emit light by time-sharing control, thereby forming a complete frame of picture.

[0060] Specifically, the following example is taken as an example where the frame period is equal to T:

[0061] Combined with the above Figure 1As discussed above, since the same data line 10 is only provided with the first sub-pixel 201 and the second sub-pixel 202, that is, the data line 10 is only used to transmit the first data voltage V1 and the second data voltage V2, a frame can be divided into a first time period and a second time period with time lengths equal to T1 and T2 respectively, and the first sub-pixel 201 and the second sub-pixel 202 are arranged alternately. When the row refresh rate of the sub-pixels is consistent, without considering the time interval between or before and after the first time period and the second time period, as shown in FIG. Figure 7 As shown, it can be set to T1=T2=T / 2. For example, the first sub-pixel 201 and the second sub-pixel 202 are located in odd rows and even rows respectively. For each data line 10, it can be considered that a plurality of first data voltages V1 and a plurality of second data voltages V2 are transmitted in the first period and the second period respectively. The order of the first period and the second period is not limited here.

[0062] Combined with the above Figure 2 As discussed above, since the same data line 10 is connected with the first sub-pixel 201, the second sub-pixel 202 and the third sub-pixel 203, that is, the data line 10 will be used to transmit the first data voltage V1, the second data voltage V2 and the third data voltage V3, a frame can be divided into a first time period, a second time period and a third time period with time lengths equal to T1, T2 and T3 respectively. Combined with the above discussion, it can be seen that each pixel group includes two first sub-pixels 201, one second sub-pixel 202 and one third sub-pixel 203. If the same data line 10 is connected with an integer number of pixel groups, it can be considered that the number of the second sub-pixel 202 and the third sub-pixel 203 are both half of the number of the first sub-pixel 201, then it can be set to T1=2*T2=2*T3=T / 2. Figure 2 It can be seen that, for example, the first sub-pixel 201, the second sub-pixel 202 and the third sub-pixel 203 are located in the 2k row, the (4k-3) row and the (4k-1) row respectively, k is a positive integer, and the order of the three time periods is not limited here. In particular, since the second voltage interval and the third voltage interval are relatively close, the second time period and the first time period can be arranged continuously to further realize the transition of voltage jump between two adjacent time periods;

[0063] Different from the above Figure 2 , if the voltage intervals are evenly divided into more voltage intervals (that is, the lengths of the three voltage intervals are equal) according to the upper and lower limits connected to the multiple first data voltages V1, the multiple second data voltages V2, and the multiple third data voltages V3, then the number of the first sub-pixels 201, the second sub-pixels 202, and the third sub-pixels 203 is equal, that is, it can be considered that each pixel group can (in sequence) include a first sub-pixel 201, a second sub-pixel 202, and a third sub-pixel 203, such as Figure 8As shown, at this time, it can be set to T1=T2=T3=T / 3, for example, the first sub-pixel 201, the second sub-pixel 202 and the third sub-pixel 203 are respectively located in the (3k-2) row, the (3k-1) row and the 3k row, k is a positive integer, and the order of the three time periods is not limited here. In particular, if the second voltage interval is between the first voltage interval and the third voltage interval, the second time period can be set between the other two time periods to further realize the transition of voltage jump between two adjacent time periods;

[0064] Combined with the above Figure 3 As discussed above, since the same data line 10 is provided with a first sub-pixel 201, a second sub-pixel 202, a third sub-pixel 203 and a fourth sub-pixel, that is, the data line 10 is used to transmit a first data voltage V1, a second data voltage V2, a third data voltage V3 and a fourth data voltage V4, a frame can be divided into a first time period, a second time period, a third time period and a fourth time period with time lengths equal to T1, T2, T3 and T4 respectively. Combined with the above discussion, it can be known that each pixel group includes a first sub-pixel 201, a second sub-pixel 202, a third sub-pixel 203 and a fourth sub-pixel. If the same data line 10 is connected to an integer number of pixel groups, such as Fig. 9 As shown, it can be set to T1 = T2 = T3 = T4 = T / 4, and observe Figure 3 It can be seen that, for example, the first sub-pixel 201, the second sub-pixel 202, the third sub-pixel 203 and the fourth sub-pixel are located in the (4k-2) row, the (4k-3) row, the (4k-1) row and the 4k row respectively, k is a positive integer, and the order of the four time periods is not limited here. In particular, if the second voltage interval, the third voltage interval, the first voltage interval and the fourth voltage interval increase or decrease successively, the four time periods can also be arranged in the order of the second time period, the third time period, the first time period and the fourth time period to further realize the transition of voltage jump between two adjacent time periods.

[0065] In summary, if Fig.10As shown, a suitable voltage interval can be set according to the relative sizes of the multiple data voltages corresponding to the multiple sub-pixels connected to the same data line 10. Assuming that the number of voltage intervals is N (N is greater than or equal to 2), the multiple sub-pixels can also be correspondingly divided into at least one first sub-pixel 201 to at least one N-th sub-pixel. Correspondingly, each frame period T needs to be divided into N time periods (the first time period to the N-th time period). Further, it can be considered that the time periods are equally divided, that is, the length of each time period is equal, which is equal to T / N. Based on the consistent refresh rate of each row, the number of corresponding data voltages transmitted in each time period is taken as the number of times the data voltage is transmitted. Taking the number i as an example, it can be considered that each pixel group includes the first sub-pixel 201 to the Nth sub-pixel arranged in sequence. In the first time period, all the first sub-pixels 201 of the (k*N+1)th row corresponding to multiple first data voltages V1 (in the first voltage interval) can be controlled to emit light, and in the second time period, all the second sub-pixels 202 of the (k*N+2)th row corresponding to multiple second data voltages V2 (in the second voltage interval) can be controlled to emit light. And so on, in the Nth time period, all the Nth sub-pixels of the k*Nth row corresponding to multiple Nth data voltages VN (in the Nth voltage interval) can be controlled to emit light.

[0066] Specifically, based on the fact that the first time period and the second time period are included in the same frame period, step S1 may include:

[0067] S11, in a first sub-frame period in a frame period, sequentially scanning a plurality of rows of sub-pixels, and sequentially loading a plurality of corresponding first data voltages when a plurality of rows of the first sub-pixels are sequentially turned on, wherein the first time period is included in the first sub-frame period;

[0068] Step S2 may include:

[0069] S12, in the second sub-frame period of the frame period, scan multiple rows of the sub-pixels in sequence, and when the multiple rows of the second sub-pixels are turned on in sequence, load the corresponding multiple second data voltages in sequence, the second time period is included in the second sub-frame period, and the length of the first sub-frame period is equal to the length of the second sub-frame period.

[0070] exist Figures 7 to 10 On this basis, it can be further set to divide the frame period into multiple sub-frame periods of equal duration (including at least the first sub-frame period and the second sub-frame period), that is, within a frame period equal to T, all row sub-pixels can be scanned at least N times (N is greater than or equal to 2), and the duration of each scan of all row sub-pixels can be equal to T / N.

[0071] In step S11, the time period for scanning multiple rows of first sub-pixels in the first sub-frame period can be referred to as the corresponding first time period, and in step S12, the time period for scanning multiple rows of second sub-pixels in the second sub-frame period can be referred to as the corresponding second time period. Similarly, for each data line 10, it can be considered that multiple first data voltages V1 and multiple second data voltages V2 are transmitted in the first time period of the first sub-frame period and in the second time period of the corresponding second sub-frame period, respectively, and the order of the first sub-frame period and the second sub-frame period is not limited here.

[0072] Of course, the present invention does not limit whether the first time period and the second time period are included in the same frame period. Based on the premise that the frame period is certain, when the first time period and the second time period are included in different frame periods, for example, in the first time period in the previous frame period, the corresponding multiple first data voltages can be transmitted in sequence through multiple data lines to control each first sub-pixel in the display panel to load the corresponding first data voltage, and in the second time period in the next frame period, the corresponding multiple second data voltages can be transmitted in sequence through multiple data lines to control each first sub-pixel in the display panel to load the corresponding second data voltage. Here, the position and proportion of the first time period in the previous frame and the position and proportion of the second time period in the next frame are not limited. There may be a gap or no gap between the first time period and the second time period.

[0073] In one embodiment, if Fig.11 As shown, the above step S1 may include but is not limited to the following steps.

[0074] S102 , acquiring a plurality of first data voltages corresponding to a plurality of first sub-pixels, and continuously arranging the plurality of first data voltages to form a first data voltage string.

[0075] In combination with the above discussion, it can be known that multiple first sub-pixels 201 need to be controlled to emit light within the first time period. Furthermore, in order to ensure the frame refresh rate of the display panel 100, in this embodiment, multiple first data voltages V1 are arranged continuously to form a first data voltage V1 string, so that multiple first data voltages V1 can be arranged continuously to avoid interspersing the second data voltage V2 that is not used in the first time period, including but not limited to, to improve the overall transmission rate of the first data voltage V1.

[0076] S103 , transmitting the first data voltage string through the data line, and sequentially turning on a plurality of the first sub-pixels, so that each of the first sub-pixels is loaded with a corresponding first data voltage.

[0077] Continuing from the above discussion, since the first data voltage V1 string only includes multiple first data voltages V1, the data line 10 transmits the first data voltage V1 string, and in conjunction with the multiple gate signals transmitted by the multiple gate lines as discussed above, it can be possible to sequentially turn on and load the first data voltage V1 to the multiple first sub-pixels 201 connected to the same data line 10 in the first time period, thereby only controlling the multiple first sub-pixels 201 to emit light.

[0078] Similarly, the above-mentioned step S2 may also include but not limited to the following steps.

[0079] S202 , obtaining a plurality of second data voltages corresponding to a plurality of second sub-pixels, and continuously arranging the plurality of second data voltages to form a second data voltage string.

[0080] Please refer to the above description about step S102.

[0081] S203 , transmitting the second data voltage string through the data line, and sequentially turning on a plurality of the second sub-pixels, so that each of the second sub-pixels is loaded with a corresponding second data voltage.

[0082] Please refer to the above description about step S103.

[0083] In one embodiment, if Fig.11 As shown, the above steps S1 and S2 may include but are not limited to the following steps.

[0084] S4, obtaining an original data voltage string, wherein the original data voltage string includes a plurality of the first data voltages and at least one second data voltage corresponding to at least one second sub-pixel, and the second data voltage is arranged between the plurality of the first data voltages.

[0085] Specifically, combined with the above Figures 1 to 3 As can be seen from the discussion of , it can be considered that the arrangement order of the data voltages in the original data voltage string received by the timing control module corresponds to the arrangement order of multiple sub-pixels connected to the same data line 10, for example Figure 1 The original data voltage string in the embodiment includes a first data voltage V1 and a second data voltage V2 which are alternately arranged. Figure 2 The original data voltage string in the embodiment includes the second data voltage V2, the first data voltage V1, the third data voltage V3 and the first data voltage V1 arranged in sequence, and arranged as a cycle unit. Figure 3 The original data voltage string in the embodiment includes a second data voltage V2, a first data voltage V1, a third data voltage V3 and a fourth data voltage V4 which are sequentially arranged and arranged as a cycle unit.

[0086] Therefore, the above steps S102 to S103 and S202 to S203 are executed by, but not limited to, the timing control module and the source driving module to convert the original data voltage string into a data signal including a first data voltage V1 string and a second data voltage V2 string, so as to cooperate with the multiple gate signals transmitted by the multiple gate lines to control all the first sub-pixels 201 and all the second sub-pixels 202 to emit light in the first time period and the second time period respectively.

[0087] The present invention also provides a display panel, wherein the display panel is used to execute any of the display panel compensation methods described above.

[0088] In one embodiment, in combination Figures 1 to 3 As shown, the display panel 100 includes: the above-mentioned multiple gate lines, each of which is connected to the corresponding (row) multiple first sub-pixels 201 or the corresponding (row) multiple second sub-pixels 202; the above-mentioned multiple data lines 10, each of which is connected to the corresponding (column) multiple first sub-pixels 201 and the corresponding (same column) multiple second sub-pixels 202; multiple first gate driving circuits 401 arranged in cascade, each of which is electrically connected to the corresponding (row) multiple first sub-pixels 201 through the corresponding gate line; multiple second gate driving circuits 402 arranged in cascade, each of which is electrically connected to the corresponding (row) multiple second sub-pixels 202 through the corresponding gate line; wherein the multiple first gate driving circuits 401 and the multiple second gate driving circuits 402 are respectively used to control the corresponding multiple first sub-pixels 201 and the corresponding multiple second sub-pixels 202 to turn on in the first time period and the second time period, so as to be electrically connected to the corresponding data lines 10 respectively.

[0089] Specific, for example Figure 2 As shown, the display panel 100 may further include a plurality of third gate driving circuits 403 arranged in cascade and corresponding to the plurality of third sub-pixels 203, for example Figure 3 As shown, the display panel 100 may further include a plurality of fourth gate driving circuits 404 that are cascaded and correspond to a plurality of fourth sub-pixels. A start signal is applied to the first-stage gate driving circuit in each gate driving circuit to cooperate with the plurality of gate driving circuits to achieve signal transmission and output. Figures 1 to 3 As shown, the first-level first gate driving circuit 401, the first-level second gate driving circuit 402, the first-level third gate driving circuit 403 and the first-level fourth gate driving circuit 404 can be loaded with the first start signal STV1, the second start signal STV2, the third start signal STV3 and the fourth start signal STV4 respectively.

[0090] like Fig.12 As shown here, Figure 1 Taking the gate drive architecture in as an example, the starting point of the start effective pulse of the second start signal can be located after the end point of the gate effective pulse in the gate signal output by the last level first gate drive circuit 401. Furthermore, each level of gate drive circuit needs to load a clock signal. Here, the clock signals CK1, CK3, CK5, and CK7 are loaded to the first to fourth level first gate drive circuits 401, respectively, and the clock signals CK2, CK4, CK6, and CK8 are loaded to the first to fourth level second gate drive circuits 402, respectively. For example:

[0091] In the first time period equal to T1, the start pulse in the first start signal enables the first-stage first gate driving circuit 401 to start working, and CK1, CK3, CK5, and CK7 sequentially have clock pulses (the time interval between the starting points of the clock pulses of two adjacent clock signals may be 1H) to sequentially control the first to fourth-stage first gate driving circuits 401 to work, so as to sequentially generate four gate effective pulses for turning on the first sub-pixels 201 of the first to fourth rows;

[0092] In the second time period equal to T2, the start pulse in the second start signal enables the first-stage first gate driving circuit 401 to start working, and CK2, CK4, CK6, and CK8 have clock pulses in sequence (the time interval between the starting points of the clock pulses of two adjacent clock signals may be 1H) to control the first to fourth-stage second gate driving circuits 402 to work in sequence, so as to generate four gate effective pulses for turning on the first to fourth rows of second sub-pixels 202 in sequence;

[0093] Furthermore, there may be a time interval t between the first time period and the second time period to distinguish the two time periods.

[0094] The present invention provides a display panel and a compensation method thereof. The display panel comprises a plurality of data lines, a plurality of first sub-pixels connected to the same data line, and at least one second sub-pixel. The second sub-pixel is arranged between the plurality of first sub-pixels. The method controls each of the first sub-pixels to load a corresponding first data voltage and each of the second sub-pixels to load a corresponding second data voltage in a non-overlapping first time period and a second time period, respectively. The first voltage interval in which the plurality of first data voltages are located and the second voltage interval in which the plurality of second data voltages are located do not overlap, so that the data line can continuously transmit a plurality of first data voltages with a smaller bar value, and then continuously transmit a plurality of second data voltages with a smaller bar value, so as to reduce the frequency of voltage jumps, thereby effectively improving the charging efficiency of the first sub-pixels and the charging efficiency of the second sub-pixels, thereby improving the effect of improving the deterioration of the viewing angle characteristics in the liquid crystal display panel, and improving the reliability of the display of the display panel picture.

[0095] The display panel and compensation method thereof provided in the embodiments of the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A compensation method for a display panel, characterized in that: The display panel includes a plurality of data lines, a plurality of first sub-pixels connected to the same data line, and at least one second sub-pixel, wherein the second sub-pixel is disposed between the plurality of first sub-pixels, and the method includes: In a first time period, each of the first sub-pixels is controlled to load a corresponding first data voltage, and a plurality of the first data voltages are in a first voltage range; In the second time period, each of the second sub-pixels is controlled to load a corresponding second data voltage, a plurality of the second data voltages are in a second voltage interval, the second time period does not overlap with the first time period, and the second voltage interval does not overlap with the first voltage interval.

2. The display panel compensation method according to claim 1, wherein: The first data voltages loaded onto the plurality of first sub-pixels are the same, and / or the second data voltages loaded onto the plurality of second sub-pixels are the same.

3. The display panel compensation method according to claim 1, wherein: The number of the second sub-pixels is greater than or equal to 2, the color of the first sub-pixels is the same as the color of the second sub-pixels, and the first sub-pixels and the second sub-pixels are arranged alternately.

4. The display panel compensation method according to claim 1, wherein: The first time period and the second time period are included in the same frame period.

5. The display panel compensation method according to claim 4, characterized in that: The step of controlling each of the first sub-pixels to load a corresponding first data voltage comprises: Acquire a plurality of the first data voltages corresponding to a plurality of the first sub-pixels, and continuously arrange the plurality of the first data voltages to form a first data voltage string; The first data voltage string is transmitted through the data line, and a plurality of the first sub-pixels are turned on in sequence, so that each of the first sub-pixels is loaded with a corresponding first data voltage.

6. The display panel compensation method according to claim 5, characterized in that: Before the step of controlling each of the first sub-pixels to load the corresponding first data voltage and the step of controlling each of the second sub-pixels to load the corresponding second data voltage, the steps include: An original data voltage string is obtained, where the original data voltage string includes a plurality of the first data voltages and at least one second data voltage corresponding to at least one second sub-pixel, and the second data voltages are arranged between the plurality of the first data voltages.

7. The display panel compensation method according to claim 1, wherein: The data line is further connected to at least one third sub-pixel, the third sub-pixel is arranged between a plurality of the first sub-pixels, and one first sub-pixel is arranged between the second sub-pixel and the third sub-pixel, and the method further includes: In a third time period, each of the third sub-pixels is controlled to load a corresponding third data voltage, a plurality of the third data voltages are in a third voltage range, the third time period, the second time period and the first time period do not overlap, the third voltage range, the second voltage range and the first voltage range do not overlap, and the second voltage range and the third voltage range are both greater than or less than the first voltage range.

8. The display panel compensation method according to claim 7, wherein: The number of the second sub-pixels and the number of the third sub-pixels are both greater than or equal to 2, the data line is connected to a plurality of pixel groups, and each of the pixel groups includes one of the second sub-pixels, one of the first sub-pixels, one of the third sub-pixels and another of the first sub-pixels arranged in sequence.

9. The display panel compensation method according to any one of claims 1 to 8, characterized in that: The display panel includes a plurality of sub-pixels, and the plurality of sub-pixels include a plurality of the first sub-pixels and a plurality of the second sub-pixels; The step of controlling each of the first sub-pixels to load a corresponding first data voltage during the first period includes: In a first sub-frame period in a frame period, a plurality of rows of sub-pixels are sequentially scanned, and when a plurality of rows of the first sub-pixels are sequentially turned on, a plurality of corresponding first data voltages are sequentially loaded, and the first time period is included in the first sub-frame period; Wherein, the step of controlling each of the second sub-pixels to load the corresponding second data voltage during the second period includes: In the second sub-frame period of the frame period, multiple rows of the sub-pixels are scanned in sequence, and when the multiple rows of the second sub-pixels are turned on in sequence, the corresponding multiple second data voltages are loaded in sequence, the second time period is included in the second sub-frame period, and the length of the first sub-frame period is equal to the length of the second sub-frame period.

10. A display panel, characterized in that: Used to execute the compensation method for the display panel as claimed in any one of claims 1 to 9.

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