Memory device and method for operating memory

Abstract

A memory device and a method of operating a memory are provided, the method of operating a memory includes providing a plurality of MRAM cells, and dividing the plurality of MRAM cells into a plurality of groups, the plurality of groups including a first group and a second group. A first MRAM cell of the first group is written from a first state to a second state, and a second MRAM cell of the second group is written from the first state to the second state. The writing of the first MRAM cell is verified, including comparing a first read current of the first MRAM cell with a first reference value. The writing of the second MRAM cell is verified, including comparing a second read current of the second MRAM cell with a second reference value.

Description

Technical Field

[0001] An embodiment of the present disclosure relates to a memory device and a method for operating the memory, and more particularly to a magnetoresistive random access memory device and a method for operating the magnetoresistive random access memory. Background Art

[0002] Non-volatile memory is memory that retains data in the absence of power. Magnetoresistive random-access memory (MRAM) is a non-volatile random access memory (RAM) technology that uses magnetic storage elements to store data. An MRAM device includes an array of MRAM cells, each of which is implemented as a single bit cell for storing binary data values. Each MRAM cell includes a magnetic tunneling junction ("MTJ" or "MTJ element") formed by a pair of ferromagnetic layers separated by a thin insulating layer. The two layers include a magnetic layer that is permanently magnetized in a fixed magnetic field alignment direction (this layer is also called a pinned layer), and a magnetic layer that can be changeably magnetized (this layer is called a free layer).

[0003] The changeably magnetized magnetic layer can be magnetized in one of two orientations relative to the permanent magnetized layer. The two orientations are characterized by distinct series resistances through the stacked layers of the MTJ. The magnetic field orientation of the changeable layer can be aligned identically to the orientation of the permanent magnet layer (parallel), or the magnetic field of the changeable layer can be aligned directly opposite to the orientation of the permanent magnet layer (anti-parallel). The parallel alignment state has a relatively low resistance, i.e., a low logic state "0". The anti-parallel alignment state has a high resistance, i.e., a high logic state "1". These two states, as sensed from their relatively high or low resistances, represent different binary logic values ​​for a bit in the memory. Summary of the invention

[0004] In some embodiments, a method for operating a memory is provided, comprising the following steps: providing a plurality of magnetoresistive random access memory cells; dividing these magnetoresistive random access memory cells into a plurality of groups including a first group and a second group; writing a first magnetoresistive random access memory cell of the first group from a first state to a second state; writing a second magnetoresistive random access memory cell of the second group from a first state to a second state; verifying the writing of the first magnetoresistive random access memory cell, comprising the step of comparing a first read current of the first magnetoresistive random access memory cell with a first reference value; and verifying the writing of the second magnetoresistive random access memory cell, comprising the step of comparing a second read current of the second magnetoresistive random access memory cell with a second reference value.

[0005] In some embodiments, a memory device is provided, comprising: a first group of magnetoresistive random access memory cells, the first group including a first magnetoresistive random access memory cell; a second group of magnetoresistive random access memory cells, the second group including a second magnetoresistive random access memory cell; and a sense amplifier for comparing a first read current of the first magnetoresistive random access memory cell with a first reference value and comparing a second read current of the second magnetoresistive random access memory cell with a second reference value different from the first reference value.

[0006] In some embodiments, a method for operating a memory is provided, comprising the following steps: providing a plurality of magnetoresistive random access memory cells; dividing the magnetoresistive random access memory cells into a plurality of groups, the groups comprising a first group having the first magnetoresistive random access memory cells and a second group having the second magnetoresistive random access memory cells; comparing a basic read current of each of the first magnetoresistive random access memory cells and each of the second magnetoresistive random access memory cells with a basic reference value; based on the comparison, A plurality of selected magnetoresistive random access memory cells among the random access memory cells are written from a first state to a second state; based on comparison, a plurality of selected magnetoresistive random access memory cells among these second magnetoresistive random access memory cells are written from the first state to the second state; a first read current of each of these first magnetoresistive random access memory cells is compared with a first reference value different from a basic reference value; and a second read current of each of these second magnetoresistive random access memory cells is compared with a second reference value different from the basic reference value and the first reference value. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the disclosed embodiments are described in the accompanying Figure 1 The following detailed description is best understood when read together. Please note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion. In addition, the drawings are illustrative as examples of embodiments of the presently disclosed embodiments and are not intended to be limiting.

[0008] Figure 1 is a block diagram illustrating an example of an MRAM memory device according to some embodiments;

[0009] Figure 2 FIG. 1 is a diagram according to some embodiments Figure 1 Block diagrams of other aspects of example MRAM memory devices;

[0010] Figure 3 is a graph illustrating an example of read current distribution in an example MTJ state of an MRAM cell according to some embodiments;

[0011] Figure 4 is a graph illustrating other aspects of an example of distribution of a read current in an example MTJ state of an MRAM cell according to some embodiments;

[0012] Figure 5 is a graph illustrating other aspects of an example of distribution of a read current in an example MTJ state of an MRAM cell according to some embodiments;

[0013] Figure 6 Including diagrams according to some embodiments are shown in Figure 5 Graphs of examples of different reference states of the distribution of the read current in;

[0014] Figure 7 An example of a method for determining an intermediate (IM) state of an MRAM cell according to some embodiments is illustrated;

[0015] Figures 8 to 12 For illustration according to some embodiments Figure 7 A diagram of an aspect of the method illustrated in FIG.

[0016] Figures 13 to 16 For an illustration of some embodiments, Figures 8 to 12 A diagram of an alternative method to the method illustrated in FIG.

[0017] Fig.17 and Fig.18 For illustration according to some embodiments Figures 8 to 16 A diagram of another alternative method to those methods illustrated in FIG.

[0018] Figures 19 to 22 is a graph illustrating the application of the disclosed method to different temperatures, according to some embodiments.

[0019]

Explanation of symbols

[0020] 100: Magnetoresistive random access memory (MRAM) memory device

[0021] 102:Memory Controller

[0022] 110: Array

[0023] 112: Magnetoresistive Random Access Memory (MRAM) bit cell

[0024] 112A: First magnetoresistive random access memory (MRAM) cell

[0025] 112B: Second magnetoresistive random access memory (MRAM) unit

[0026] 116: memory cell selection transistor

[0027] 120:MTJ element

[0028] 140: Bit Line Multiplexer

[0029] 142: Bit line driver

[0030] 144:Sense Amplifier

[0031] 200: "Original Reference" status

[0032] 201: First reference state

[0033] 202: Second reference state

[0034] 210: Curve

[0035] 212:AP status curve

[0036] 212A: Group 1

[0037] 212B: Second Group

[0038] 212C: Group

[0039] 214: Current curve

[0040] 220: Frame / Overlap Area

[0041] 221: Part

[0042] 222: Arrow

[0043] 224: Arrow / Second Quantity

[0044] 226: Arrow

[0045] 228: Arrow

[0046] 230: Arrow

[0047] 240:Iread current level

[0048] 242:Iread current level

[0049] 244:Iread current level

[0050] 246:Iread current level

[0051] 250: quantity

[0052] 262: Arrow

[0053] 264: Arrow

[0054] 300: Methods

[0055] 310: Operation

[0056] 312: Operation

[0057] 314: Operation

[0058] 316: Operation

[0059] 318: Operation

[0060] 320: Operation

[0061] AP: Status

[0062] BL[0]: bit line

[0063] BL0: bit line

[0064] BL: Bit Line

[0065] IM: Status

[0066] Iread: read current

[0067] P: Status

[0068] REF_AP: Split reference value

[0069] REF_AP1: Split reference value

[0070] REF_AP2: Split reference value

[0071] REF_Cell2: Cell reference

[0072] REF: Reference current

[0073] REF': Reference

[0074] REF1: Reference value

[0075] REF2: Reference value

[0076] REF3: Reference value

[0077] SL[0]: Source line

[0078] SL0: Source line

[0079] SL: Source Line

[0080] WL[0]~WL[n]: memory word line

[0081] WL: Word Line

[0082] SA: Sense Amplifier

[0083] BL: Bit Line

[0084] MTJ: Magnetic Tunneling Junction DETAILED DESCRIPTION

[0085] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosed embodiments. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0086] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein for ease of description to describe the relationship of one or more elements or features to another or further elements or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0087] Magnetoresistive random-access memory (MRAM) is a non-volatile random-access memory technology that uses magnetic storage elements to store data. An MRAM device includes an array of MRAM cells, each of which is implemented as a single bit cell for storing binary data values. Each MRAM cell includes a magnetic tunneling junction ("MTJ" or "MTJ element") formed by a pair of ferromagnetic layers separated by a thin insulating layer. The two layers include a magnetic layer that is permanently magnetized in a fixed magnetic field alignment direction (this layer is also called a pinned layer), and a magnetic layer that can be changeably magnetized (this layer is called a free layer).

[0088] The changeably magnetized magnetic layer can be magnetized in one of two orientations relative to the permanent magnetized layer. The two orientations are characterized by distinct series resistances through the stacked layers of the MTJ. The magnetic field orientation of the changeable layer can be aligned identically to the orientation of the permanent magnet layer (parallel), or the magnetic field of the changeable layer can be aligned directly opposite to the orientation of the permanent magnet layer (anti-parallel). The parallel alignment state has a relatively low resistance, and the anti-parallel alignment state has a higher resistance. These two states, as sensed from their relatively high or low resistances, represent different binary logic values ​​for a bit in the memory.

[0089] The two states of an MRAM cell are sensed from its relatively high or low resistance (RH and RL), and the two states represent different binary logic values ​​of the bit stored in the memory. For example, RL (or high cell current) can be assigned a logic "0" ("data-0"); RH (or low cell current) can be assigned a logic "1" ("data-1"). The bit of data stored in an MRAM memory cell, i.e., the logic "0" or "1" value, can be determined by comparing the current flowing through the memory cell with another current flowing through another memory cell.

[0090] More specifically, MRAM stores data at a memory cell having an MTJ element formed of a pinned layer and a free layer separated by a thin insulating layer. The free layer is magnetized in one of two orientations relative to the permanent magnetized layer. The two orientations are characterized by distinct series resistances through the stacked layers of the MTJ. The magnetic field orientation of the changeable layer can be aligned the same as the orientation of the permanent magnet layer (parallel, or "P"), or aligned opposite to the orientation of the permanent magnet layer (anti-parallel, or "AP"). The parallel alignment state P has a relatively low resistance, and the anti-parallel alignment state AP has a higher resistance.

[0091] A problem associated with MRAM is the "intermediate state" (IM), which occurs when the MTJ of the MRAM is subjected to a magnetic field that is not strong enough to fully switch its magnetic orientation. As mentioned above, in order to write data to an MRAM cell, a magnetic field is applied to change the orientation of one of the magnetic layers of the MRAM cell. If the field is strong enough, the field fully switches the orientation, and the MTJ is in a stable state representing either 0 or 1.

[0092] However, if the magnetic field applied during a write operation is not strong enough to adequately switch the magnetic orientation of the storage layer, the MTJ may end up in an intermediate state. In the intermediate state, the magnetic orientation is partially altered, but not enough to reliably represent a 0 or 1. This intermediate state results in a resistance level that falls between a high resistance state and a low resistance state. Through a read operation on the MRAM cell, the resistance state of the MTJ needs to be accurately detected. The presence of the intermediate state can complicate the read process because the final state of the MRAM cell is unknown or difficult to access.

[0093] This IM phenomenon can cause data errors or disturb neighboring cells when reading or writing data. Some attempts to address the IM phenomenon include using higher write voltages or currents, longer write times, multiple "shots" of applied magnetic fields, and the like. However, such attempted solutions can adversely affect MRAM cell duration and write throughput.

[0094] Generally speaking, an MRAM read operation involves applying a sense current through the MTJ element of the MRAM cell. The sense current generates a voltage drop across the MTJ, and this voltage is amplified by the sense amplifier to detect the resistance change. When the MTJ is in the P state (parallel low resistance state), the current across the MTJ is different from the current when the MTJ is in the AP state (anti-parallel high resistance state). This resistance difference results in a current and voltage difference at the output of the sense amplifier.

[0095] The current or voltage difference is compared to a reference value or threshold value. If the measured current is lower than the reference value, the measured current indicates that the MTJ is in a high resistance state (AP), which usually represents a binary value (e.g., 1). If the current is higher than the reference value, the current indicates a low resistance state (parallel alignment), thereby representing other binary values ​​(e.g., 0).

[0096] Various embodiments of the present application are directed to methods for addressing IM phenomena with MRAM memory cells, including using different reference values ​​for MRAM cells that suffer from IM problems. Figure 1 An example of an MRAM memory device 100 according to aspects of the disclosed embodiments is shown. The memory device 100 includes an array 110 of a plurality of MRAM cells. The memory device 100 further includes a memory controller 102 that receives memory addresses and controls various components of the device 100 to read data or write data to the array 110. The memory controller 102 may include various circuits as further discussed below.

[0097] Figure 2 Other aspects of an example of a memory device 100 are shown. The MRAM array 110 includes an array of MRAM bit cells 112 arranged in rows and columns. For simplicity of discussion, Figure 2 Only a single column of MRAM bit cells 112 is shown in detail. In the illustrated example, the MRAM bit cells 112 each include an MTJ element 120. Each row of the array 110 has a corresponding bit line BL and a corresponding source line SL. Figure 2 , only the first bit line BL[0] and the first source line SL[0] of the first row of MTJ elements 120 are shown. Each row of the array has a corresponding word line WL. In the illustrated example, multiple rows of MRAM bit cells each have a corresponding memory word line WL[0-n], and the MRAM bit cell 112 is connected to the bit line BL[0].

[0098] Each of the MRAM bit cells 112 has a corresponding memory cell select transistor 116 coupled between the MTJ element 120 and the source line SL[0] of the MRAM bit cell 112. Each of the memory cell select transistors 116 has a gate terminal coupled to the word line WL[0-n] of the corresponding column. In the illustrated example, the memory cell select transistors 116 are NMOS transistors, although other switching devices are within the scope of the disclosed embodiments.

[0099] The memory controller 102 of the memory device 100 includes a sense amplifier 144 connected to the bit line BL to read the current flowing through the memory bit cell 112 and compare the multiple currents with the reference current to read data from the memory array 110. The output of the sense amplifier 144 is then latched and used to determine the data read from the MRAM cell 112. The data can be sent to the memory controller 102 for further processing or storage. The bit line multiplexer 140 is used to select the bit line BL based on the received memory address, and the bit line driver 142 is used to change the potential on the bit line BL.

[0100] In an exemplary write operation for writing data to the MRAM bit cell 112, a write voltage is applied to the bit line BL0, the source line SL0, and the appropriate word line WL[0-n]. For example, the voltage applied to the word line WL[0] activates the memory cell selection transistor 116 connected thereto, and a write current flows through the connected MRAM bit cell 112. The write current flows through the MTJ 120 of the MRAM bit cell 112, thereby causing the MTJ 120 to switch from a parallel state to an anti-parallel state or vice versa, whereby a bit of data is written and stored in the MRAM bit cell 112. When it is necessary to switch the MTJ 120 from the anti-parallel state to the parallel state to store a "0" value, the switching current passes through the MTJ 120 from the free layer to the reference layer. Conversely, when it is necessary to switch the MTJ 120 from the parallel state to the anti-parallel state to store a "1" value, the switching current passes through the MTJ 120 from the reference layer to the free layer.

[0101] When the free layer of the MTJ 120 is in the parallel state, the MTJ 120 exhibits a low resistance representing a logical "0" value, and the MTJ 120 is said to be in the parallel state or the low resistance state P. Conversely, when the free layer is in the anti-parallel state, the MTJ 120 exhibits a high resistance representing a logical "1" value, and the MTJ 120 is said to be in the anti-parallel state or the high resistance state AP. In some embodiments, the logic represented by the MTJ 120 in the high or low resistance state is arbitrary, for example, a logical "1" may be represented by the MTJ 120 in the low resistance state, and a logical "0" may be represented by the MTJ 120 in the high resistance, and is determined by the desired convention for the memory device. Regardless of which convention is selected, the MTJ 120 can store binary data via two writable and readable states, such as the high resistance state and the low resistance state. For consistency purposes, the embodiments described herein will use the convention that an MTJ 120 in a low resistance parallel state P represents a "0" value and an MTJ 120 in a high resistance anti-parallel state AP represents a "1" unless stated otherwise.

[0102] In an exemplary read operation, a read voltage is applied to the bit line BL[0] and source line SL[0] associated with the row of the selected bit cell 112 to be read and the word lines WL[0-n] associated with the word lines of the selected MRAM bit cell 112 to be read. For example, a read voltage may be applied to the bit line BL[0], source line SL[0], and word line WL[0] to read the data bit stored in the connected MRAM bit cell 112. To select other cells, different combinations of bit lines, source lines, and word lines are activated to generate read currents indicative of the data stored at the respective cells.

[0103] Figure 3 An example of the distribution of read current in an example MTJ state of the MRAM cell 112 is shown. In the illustrated example, when the MRAM bit cell 112 is read, the read current Iread flows through the MTJ 120. The magnitude of the read current Iread corresponds to the resistance state of the MTJ 120. For example, when the MTJ 120 is in the low resistance state, i.e., the parallel state P, the read current Iread will be greater than that of the parallel state P. Figure 3 In contrast, when the MTJ 120 is in a high resistance state, that is, in the anti-parallel state AP, the read current Iread will be less than that of the reference current REF as shown by the curve 210 in FIG. Figure 3212 in FIG. 2 shows a reference current Iref, indicating that the MRAM bit cell 112 stores a bit logic "1" value of data therein. The T sense amplifier 144 can compare the read current Iread with the reference current REF to sense the bit logic "0" or "1" value of the data stored in the MRAM bit cell 112. The sense amplifier 144 amplifies the level of the sensed data bit and outputs the amplified bit of data so that the bit of data stored in the MRAM bit cell 112 can be read from the MRAM bit cell 112. In some examples, the reference current value is determined based on the peak read current Iread of the AP and P states, such as

[0104] (Ip+Iap) / 2

[0105] Where Ip is the peak read current Iread of the P state curve 210, and Iap is the peak read current Iread of the AP state curve 212. In some examples, the sense amplifier 144 is used to compare the read current Iread with a reference value REF.

[0106] As mentioned above, the IM state can occur when the MTJ of an MRAM is subjected to a magnetic field that is not strong enough to switch its magnetic orientation. Thus, if the magnetic field applied during a write operation is not strong enough to switch the magnetic orientation of the storage layer, the MTJ can end up in an intermediate state, which results in a resistance level that falls between the high resistance state and the low resistance state.

[0107] Figure 4 The current curve 214 is shown indicating the IM state, where the MTJ is in an intermediate state (i.e., between the AP state and the P state), which results in a resistance level that falls between the high resistance state and the low resistance state. The value of the reference current (or voltage) REF can be used to verify the success or failure of the MRAM cell write. Consider an example where the MRAM cell is being written from the AP state to the P state. As discussed above, curve 210 illustrates a read current Iread that is greater than the reference REF, thereby clearly indicating the P state of the MRAM cell 112. The right portion of the curve 214 illustrating the IM state is greater than the reference value REF, while the left portion of the curve 214 is less than the reference value REF. As Figure 4 As further shown in FIG. 2 , the IM state curve 214 and the P state curve 210 overlap in the region indicated by box 220. Since a portion of the IM curve 214 is greater than the reference REF and coincides with the P state curve 210, it may be considered as written to the P state. However, this situation may result in an ambiguous read value, and the IM current may return to the AP value, resulting in a write failure. The same situation exists as follows: a portion 221 of the IM state curve 214 overlaps with the AP curve 212, which may result in an ambiguous read value for reading a cell written to the AP state.

[0108] Figure 5 The following situation is shown: the reference REF' is shifted to the right and used as the reference value for all "AP cells" (i.e., cells with read current Iread falling on the AP curve 212), and the multiple AP cells are written to the P state. If only those read current Iread values ​​of the curve 210 that are greater than the reference value REF' (i.e., to the right of the reference value REF') are regarded as indicating that the MRAM cell 112 has been written to the P state, some MRAM cells may be regarded as writing failures and end up, even though the MRAM cells show read current Iread higher than the original reference value REF. This situation may lead to unnecessary rewriting of MRAM cells.

[0109] According to aspects of the disclosed embodiments, the reference value REF varies for different MRAM cells or groups of MRAM cells so that the IM curve 214 does not overlap with the P curve 210 and / or the AP curve 212. This facilitates more accurate detection of the IM state, which in turn may require a cell rewrite. For example, Figure 6 The following diagrams illustrate read current curves 210, 214, and 212 for the P state, IM state, and AP state, respectively. Figure 3 In the "original reference" state 200, the reference value REF is determined according to (Ip+Iap) / 2 (i.e., at the midpoint between the AP curve 212 and the P curve 210). In addition to the basic reference state 200, the basic reference REF is used. Figure 6 A first reference state 201 and a second reference state 202 are depicted, each of which uses respective reference values ​​REF1 and REF2 instead of the original or base reference REF. In this way, at the overlap region 220, the IM curve 214 and the P curve 210 are effectively eliminated.

[0110] The first reference state 201 uses the first reference value REF1 for determining the write state of the first group 212A of AP cells. The first group of AP cells 212A corresponds to those MRAM cells 112 having lower AP read currents Iread. In other words, the read currents Iread of the first group of AP cells 212A are on the left portion of the curve 212, indicating a portion of the AP read current Iread distribution having lower read currents Iread. For these cells, the reference value REF1 is greater than the original or base reference value REF by a first amount, thereby shifting the reference value REF1 to the right of the graph by an amount indicated by arrow 222 closer to the left portion of the P curve 210. In some embodiments, a sense amplifier 144 is used to compare the read currents Iread of the first group of AP cells 212A to the first reference REF1.

[0111] This effectively eliminates a portion of the IM curve 214 in the overlap region 220, and the MRAM cells 112 of the first group corresponding to the AP cells 212A are therefore considered to be written to the P-state if the Iread value is greater than the REF1 value (i.e., the right side). If the Iread value is less than the REF1 value (i.e., the left side), the AP cell is considered to have not been successfully written to the P-state (i.e., the write failed) and the cell is overwritten.

[0112] The second reference state 202 uses the second reference value REF2 for determining the write state of the second group 212B of AP cells. The second group 212B of AP cells corresponds to those MRAM cells 112 having higher AP read currents Iread. In other words, the read currents Iread of these AP cells 212B are on the right portion of the curve 212, indicating a portion of the AP read current Iread distribution having higher read currents Iread. For these cells, the reference value REF2 is greater than the original or base reference value REF by a second amount greater than the first amount, thereby moving the reference value REF2 further to the right of the right portion of the graph closer to the P curve 210 by an amount indicated by arrow 224. In some embodiments, the sense amplifier 144 is used to compare the read currents Iread of the second group of AP cells with the second reference REF2.

[0113] This effectively eliminates a portion of the P-curve 210 in the overlap region 220, and the MRAM cells 112 corresponding to the second group 212B of AP cells are therefore considered to be written to the P-state if the Iread value is greater than the REF2 value (i.e., the right side). If the Iread value is less than the REF2 value (i.e., the left side), the AP cell is considered to have not been successfully written to the P-state (i.e., write failed) and the cell is overwritten.

[0114] Figure 7 A method 300 is shown for determining the IM state of MRAM cells 112 and rewriting the cells when necessary, in accordance with disclosed embodiments. Figure 7 An example is further described in Figure 6 , and corresponds to the case where the MRAM cell 112 is being written from a first state (eg, AP state) to a second state (eg, P state). However, the illustrated method also applies to writing from a P state to an AP state, for example.

[0115] More specifically, in the example where the MRAM cells 112 are written from the AP state discussed above to the P state, at operation 310, the MRAM cells 112 are pre-verified to determine which cells are written from AP to P. In other words, at operation 310, the cells use a "base" or "learned" reference value, such as that shown in FIG. Figure 3The reference value in operation 310 is read to identify the MRAM cell 112 in the AP state (i.e., the cell having the Iread current corresponding to the curve 212). In some examples, the base reference value REF of operation 310 is determined according to (Ip+Iap) / 2, where Ip is the read current Iread of the P state, and Iap is the read current Iread of the AP state. Figure 8 This AP curve 212 is illustrated, where an MRAM cell 112 demonstrating a read current Iread that falls on this curve will be verified as requiring a write to the P state. In other words, the MRAM cell is pre-verified by comparing the base read current of the MRAM cell 112 to a base reference value REF. In some embodiments, a sense amplifier 144 is used to compare the read current Iread of the AP cell to the reference REF to pre-verify the MRAM cell 112. Therefore, in operation 310, any MRAM cell 112 determined to be already in the second or P state (i.e., the Iread current corresponds to the P curve 210) does not need to be written to the P state. For example, the memory controller 102 may include a first or "target" register that stores a target value for each MRAM cell 112. The pre-verification operation 310 may include reading the MRAM cells 112 and storing the read results of each in a second or "read" register. A bit-by-bit comparison of the target register and the read register will identify (e.g., verify) those MRAM cells 112 that need to be written from the AP state to the P state.

[0116] At operation 312, the MRAM cells 112 in the AP state that are to be written to the P state are divided into a plurality of groups based on the orientation of the corresponding Iap current on the AP curve 212. In some examples, the identified MRAM cells 112 are divided into two groups or three groups, or into more than three groups. In some examples, the MRAM cells are divided into a plurality of groups prior to the pre-verification operation 310. As mentioned above, the MRAM cells 112 having a read current Iread according to the AP curve 212 (i.e., AP cells) are pre-verified in operation 310 as requiring a write from the AP state to the P state. Fig. 9The AP cells identified at operation 310 are shown partitioned into a first group 212A (lower AP Iread current on the left) and a second group 212B (higher AP Iread current on the right) using the peak value of the AP read current distribution Iap as the partition reference value REF_AP. In some implementations, an identifier specifying the partition group (e.g., first group 212A or second group 212B) of each MRAM cell may be stored in a memory, such as a third or "partition" register. Thus, each bit of the partition register may store a logic 0 to specify the corresponding MRAM memory cell 112 as a first group 212A MRAM cell, and the partition register may store a logic 1 to specify the corresponding MRAM cell 112 as a second group 212B MRAM cell.

[0117] exist Figure 7 In operation 314, the identified AP units 212A, 212B are written from a first state (eg, AP state) to a second state (eg, P state), as shown in FIG. Fig.10 , as indicated by arrow 230. After the writing process of operation 314, the written cell is verified.

[0118] More specifically, at operation 316, a first reference value is used to verify the first group 212A. In some examples, the reference value is increased by a first amount. In some examples, the first reference value REF1 (i.e., the reference for the left AP group 212A) is determined according to (Ip+Iap) / 2+m, where m is a predetermined reference increment. In other examples, the reference value is increased above the base reference REF by a predetermined current amount, a predetermined percentage, a percentage or portion of the original or base reference value REF, a percentage or portion of the Ip or Iap current, etc.

[0119] Therefore, if Fig.11, the first reference value REF1 is shifted to the right of the base reference REF by a first amount, such that for a successful write verification from the AP state to the P state, the Iread current needs to be greater than the base reference value REF (e.g., Ip+Iap) / 2) by at least the amount indicated by arrow 222 (i.e., REF1). AP cells 212A having a read current less than the first reference value REF1 are considered recorded write failures. In some examples, the sense amplifier 144 therefore compares the read current Iread of the MRAM cells 112 of the first AP group 212A with the first reference value REF1. In other words, verification of the first AP cell group 212A includes reading the MRAM cells 112 of the first AP cell group 212A using the first reference value REF1. The read result based on comparing the read current Iread with the first reference value REF1 can be recorded to a memory, such as the read register discussed above. The contents of the read register can then be compared with the corresponding bits of the target register, and matching values ​​are considered successful writes, while values ​​that do not match are considered write failures.

[0120] The process then repeats for the next (e.g., second) AP group of cells 212B. As mentioned above, these cells 212B have higher AP read currents Iread, and therefore the read currents Iread indicating successful writes to the P state are also higher. As shown in operation 318, the second reference value REF2 is used to verify the second group 212B. The reference value for the second AP group 212B is increased by a second amount 224, thereby moving the reference value further to the right, as shown in FIG. Fig.12 As shown in Fig. 9, the second AP group 212B has a greater Iread current than the first group 212A. Therefore, the Iread current of the second group 212B increases more to be considered successfully written to the P state (rather than being considered the IM state). In some instances, the second reference value REF2 (i.e., the reference for the right AP group 212B) is determined based on Ip-n, where n is a predetermined reference decrement. In other instances, the reference value is reduced from the Ip current level by a predetermined current amount, a predetermined percentage, a percentage or portion of the original or base reference value REF, a percentage or portion of the Ip or Iap current, etc. Furthermore, in some instances, m=n. In addition, in yet other instances, the second reference value REF2 is determined based on (Ip+Iap) / 2+n, where n>m. Therefore, the second reference value REF2 is further moved to the right, and the Iread current needs to be greater than the base reference REF by at least an amount 224 (i.e., greater than REF2) to be considered written to the P state rather than the IM state. The write failure bits of the second AP group 212B - the cells with Iread current less than the reference value REF2 - are recorded. In some examples, the sense amplifier 144 therefore compares the read current Iread of the MRAM cells 112 of the second AP group 212B with the second reference value REF2. In other words, the verification of the second AP cell group 212B includes reading the MRAM cells 112 of the second cell group 212B using the second reference value REF2. The read result based on comparing the read current Iread with the second reference value REF2 can be recorded to a memory, such as the read register discussed above. The contents of the read register can then be compared with the corresponding bits of the target register, and matching values ​​are considered to be successfully written, while non-matching values ​​are considered to be write failures.

[0121] In addition, in some embodiments, the controller 102 is used to provide reference values ​​REF1 and REF2 to the sense amplifier 144 for the corresponding cell groups 212A and 212B. Furthermore, the controller 102 can be used to calculate the reference values ​​REF1 and REF2 as mentioned above. In other examples, the sense amplifier 144 may include multiple sense amplifiers, each of which receives a different reference value (e.g., one sensor amplifier receives REF1 and another sensor receives REF2). The controller 102 in this embodiment further includes logic circuitry to select the relevant sense amplifier output based on whether the cell group 212A or the cell group 212B memory cell is being verified.

[0122] exist Figure 7 At operation 320, any write fail bits recorded at operations 316 and 318 are overwritten.

[0123] As mentioned above, the disclosed process is not limited to partitioning the MRAM cells 112 to be written into two groups. In other examples, more than two groups are used in the partitioning process. Figures 13 to 16 An example of the AP cell 212 being divided into three groups is shown, including group 212A (left portion of the AP current curve—lower AP Iread current), 212B (right portion of the AP current curve—higher AP Iread current), and 212C (middle portion of the AP current curve—AP Iread current between the first group 212A and the second group 212B). For dividing the AP cell group 212 into three groups 212A, 212B, and 212C, the peak values ​​of the AP read current ± a predetermined number may be used to determine two divided reference values ​​REF_AP1 and REF_AP2. In some examples, REF_AP1 and REF_AP2 are determined according to Iap±m.

[0124] The AP cells 212 to be written to the P state (ie, groups 212A, 212B, 212C) are therefore written, and as shown in FIG. Fig.14 As shown in FIG. , the first reference value is used to verify the first group 212A. Fig.14 In the example of , the first reference REF1 is the same as the basic reference REF, i.e. (Ip+Iap) / 2. Fig.14 As shown in FIG. 1 , the Iread current of the first group 212A needs to be greater than the first reference REF1 (ie, the basic reference value REF) to be considered as a successful write from the AP state to the P state. The AP cells 212A having a read current less than the first reference value REF1 are considered as write failures.

[0125] In some examples, the second reference value REF2 increases above the first reference value REF1 (i.e., REF) by a first amount. In some examples using three AP groups, the second reference value REF2 (i.e., the reference value for the middle AP group 212C) is determined according to (Ip+Iap) / 2+m. As mentioned above, m is a predetermined reference increment, such as a predetermined current amount, a predetermined percentage, a percentage or portion of the original or base reference value REF, a percentage or portion of the Ip or Iap current, etc.

[0126] Therefore, if Fig.15 , the second reference value REF2 is shifted to the right of the first reference REF1 by the amount indicated by arrow 226, so that for a successful write verification of the middle group of AP cells 212C from the AP state to the P state, the Iread current needs to be greater than the first reference value REF1 by at least the amount 226 (i.e., REF2). The AP cells 212C having a read current less than the second reference value REF2 are considered to have failed writes.

[0127] The process is then repeated for the next (e.g., second) AP group of cells 212B. These cells 212B have still higher AP read currents Iread than the cells of the first and third groups 212A and 212C, and thus the read current Iread indicating a successful write to the P state is also higher for group 212B. As a result, the third reference value REF3 for AP group 212B is further increased, thereby moving the reference value further to the right, as shown by Fig.16 As indicated by arrow 228 in FIG.

[0128] like Fig.13 , the second AP group 212B has an Iread current greater than both the first group 212A (i.e., on the left) and the third group 212C (i.e., in the middle). Therefore, the Iread current of the second group 212B increases still further to be considered successfully written to the P state (rather than being considered the IM state). In some examples, the third reference value REF3 is the Ip current. In other examples, REF3 is determined in other ways, such as a predetermined increase above the Iap or (Ip+Iap) / 2 value or a predetermined decrease below the Ip value. Therefore, the third reference value REF3 is moved still further to the right, and the Iread current needs to be greater than the first reference REF1 (i.e., the base reference REF) by at least an amount 228 (i.e., greater than REF3) to be considered written to the P state.

[0129] As mentioned above Figure 7 As mentioned in the discussion of , write failures are recorded and then rewritten according to operation 320 .

[0130] The disclosed embodiments are not limited to dividing the cells to be written into two or three groups. The MRAM cells to be written from the first state to the second state may be divided into more than three groups, where the writing from the first state to the second state will be verified using a corresponding number of reference values. In yet other embodiments, each cell to be written from the first state to the second state is verified using an individual reference value. In other words, in some examples, each "group" may be considered to have a single MRAM cell.

[0131] Fig.17 and Fig.18 An example of determining a reference value for each cell is shown. In other words, each of the memory cells has a corresponding reference value for verifying the write process. The magnetic tunnel junction (TMR) of the MTJ of each MRAM cell 112 is generally predictable and repeatable. Therefore, the Iread current indicating the first state (e.g., AP state) of the individual MRAM cell 112 can be determined and recorded. Fig.17The first MRAM cell 112A is shown having a first Iread current level 240, indicating a first state, such as shown in FIG. Fig.17 Assuming that the first cell 112A demonstrates a second Iread current level 242 of the P state at a relatively similar position of the P curve, the individual cell reference REF_Cell1 is adjusted based on the current ratio or current delta between the AP Iread level 240 and the P Iread level 242. The base reference value REF (e.g., (Ip+Iap) / 2) can therefore be adjusted accordingly by an amount 250.

[0132] Fig.18 An example is shown in which the second MRAM cell 112B has a first Iread current level 244 indicating an AP state at another location on the AP curve 212 and a second Iread current level 246 indicating a P state at a relatively similar location on the P curve. Thus, the individual cell reference REF_Cell2 is adjusted based on the current ratio or current delta between the AP Iread level 244 and the P Iread level 246, as indicated at 252.

[0133] The process for solving the IM problem is applied to MRAM operation under varying temperatures. The resistance level of the MRAM cell 112 in the AP state and / or the P state may vary according to temperature. Fig.19 and Fig. 20 An example of a high temperature level (eg, 150° C.) is shown, and Fig.21 and Fig. 22 An example of a low temperature level (eg, -40° C.) is shown, whereby read current curves 210 , 214 , and 212 are depicted in the P state, IM state, and AP state under high temperature and low temperature conditions, respectively.

[0134] Fig.19 and Fig.21 A first reference state 201 is shown, and Fig. 20 and Fig. 22 A second reference state 202 of the high temperature MRAM cell and the low temperature MRAM cell is shown. Figure 6 In general, the first reference state 201 and the second reference state 202 use respective reference values ​​REF1 and REF2 instead of the original or base reference REF.

[0135] Draw on Fig.19 and Fig.21The first reference state 201 in FIG. 1 uses the first reference value REF1 for determining the write state of the first group 212A of AP cells corresponding to those MRAM cells 112 having lower AP read currents Iread. For these cells, the reference value REF1 is greater than the original or base reference value REF by a first amount, thereby moving the reference value REF1 to the right of the graph by an amount indicated by arrow 262 closer to the left portion of the P curve 210.

[0136] Draw on Fig. 20 and Fig. 22 The second reference state 202 in FIG. 1 uses the second reference value REF2 for determining the write state of the second group 212B of AP cells corresponding to those MRAM cells 112 having higher AP read currents Iread. For these cells, the reference value REF2 is greater than the original or base reference value REF by a second amount that is greater than the first amount, thereby moving the reference value REF2 further to the right of the graph closer to the right portion of the P curve 210 by the amount indicated by arrow 264.

[0137] Compare Fig.21 and Fig. 22 The read current curves 210, 214 and 212 are Fig.19 and Fig. 20 The corresponding read current curves 210, 214 and 212 of FIG. 1 are shown to have different shapes in the low temperature implementation compared to the high temperature case. This is due to the change in TMR due to the temperature difference.

[0138] exist Fig.19 and Fig.21 In the example of , the first reference value REF1 is determined according to (Ip+Iap) / 2+m%, where m% is a predetermined reference increment percentage. Fig. 20 and Fig. 22 In the example of , the second reference value REF2 is determined according to Ip-n%, where n% is a predetermined reference reduction percentage. Since the first reference value REF1 and the second reference value REF2 are based on percentage differences, the illustrated IM solution is effective for both high temperature implementation and low temperature implementation.

[0139] Thus, aspects of the disclosed embodiments address problems associated with the IM phenomenon. For example, MRAM cell writes may be difficult to verify in situations where a portion of the IM read current curve of the MRAM overlaps with the Iread curve for the AP state or P state, which may make the MRAM write process difficult. Previous attempts to address the problem may affect soft error rate (SER) as well as endurance and write yield. According to the disclosed examples, the MRAM write cells are partitioned into multiple MRAM cell groups, and reference values ​​are implemented for the respective MRAM cell groups, effectively eliminating the IM overlap with the P / AP state.

[0140] In some examples, a method for identifying an IM state of MRAM cell writing includes: providing a plurality of MRAM cells, and dividing the plurality of MRAM cells into a plurality of groups, the plurality of groups including a first group and a second group. Writing a first MRAM cell of the first group from a first state to a second state, and writing a second MRAM cell of the second group from the first state to the second state. Verifying the writing of the first MRAM cell includes comparing a first read current of the first MRAM cell with a first reference value. The writing of the second MRAM cell is verified, including comparing a second read current of the second MRAM cell with a second reference value.

[0141] In some embodiments, each of the MRAM cells includes a magnetic tunneling junction element.

[0142] In some embodiments, the first state is an anti-parallel state.

[0143] In some embodiments, the second state is a parallel state.

[0144] In some embodiments, the method further comprises the following step: if the first read current of the first MRAM cell is less than the first reference value, identifying a write failure of the first MRAM cell.

[0145] In some embodiments, the method further comprises the following step: if the second read current of the second MRAM cell is less than a second reference value, identifying a write failure of the second MRAM cell.

[0146] In some embodiments, the second reference value is greater than the first reference value.

[0147] In some embodiments, the method further comprises the steps of: determining a base reference value; determining a first reference value by increasing the base reference value by a first amount; and determining a second reference value by increasing the base reference value by a second amount greater than the first amount.

[0148] In some embodiments, the basic reference value is determined according to (Ip+Iap) / 2, where Ip is a peak read current of the parallel state curve, and Iap is a peak read current of the anti-parallel state curve.

[0149] In some embodiments, the first reference value is determined according to (Ip+Iap) / 2+m, where m is a predetermined reference increment.

[0150] In some embodiments, the second reference value is determined according to Ip-n, where n is a predetermined reference decrement.

[0151] In some embodiments, these groups further include a third group, and the method further includes the following steps: writing a third magnetoresistive random access memory cell of the third group from the first state to the second state; and verifying the writing of the third magnetoresistive random access memory cell, including the step of comparing a third read current of the third magnetoresistive random access memory cell with a third reference value.

[0152] In some embodiments, the method further includes the following steps: pre-verifying the first state of the first magnetoresistive random access memory cell, including the step of comparing the first state read current of the first magnetoresistive random access memory cell with a basic reference value; and pre-verifying the first state of the second magnetoresistive random access memory cell, including the step of comparing the first state read current of the second magnetoresistive random access memory cell with a basic reference value.

[0153] In some embodiments, the first group includes only the first MRAM cell, and wherein the second group includes only the second MRAM cell.

[0154] According to other disclosed examples, a memory device includes a first group of MRAM cells including a first MRAM cell and a second group of MRAM cells including a second MRAM cell. A sense amplifier is used to compare a first read current of the first MRAM cell with a first reference value and to compare a second read current of the second MRAM cell with a second reference value different from the first reference value.

[0155] In some embodiments, the second reference value is greater than the first reference value.

[0156] In some embodiments, a first magnetoresistive random access memory cell and a second magnetoresistive random access memory cell are used to selectively write from a first state to a second state; and wherein the sensing amplifier is used to: verify the writing of the first magnetoresistive random access memory cell from the first state to the second state by comparing a first read current of the first magnetoresistive random access memory cell with a first reference value; and verify the writing of the second magnetoresistive random access memory cell from the first state to the second state by comparing a second read current of the second magnetoresistive random access memory cell with a second reference value.

[0157] According to yet other examples, a method for identifying an IM state of an MRAM cell includes: providing a plurality of MRAM cells, and dividing the plurality of MRAM cells into a plurality of groups, the plurality of groups including a first group having the plurality of first MRAM cells and a second group having the plurality of second MRAM cells. Comparing a basic read current of each of the plurality of first MRAM cells and each of the plurality of second MRAM cells with a basic reference value. Writing a selected MRAM cell of the plurality of first MRAM cells from a first state to a second state based on the comparison. Writing a selected MRAM cell of the plurality of second MRAM cells from a first state to a second state based on the comparison. Comparing a first read current of each of the plurality of first MRAM cells with a first reference value different from the basic reference value, and comparing a second read current of each of the plurality of second MRAM cells with a second reference value different from the basic reference value and the first reference value.

[0158] In some embodiments, the method further comprises the following steps: identifying multiple write failures of these first MRAM cells based on comparing the first read current; and identifying multiple write failures of these second MRAM cells based on comparing the second read current.

[0159] In some embodiments, the first state is an anti-parallel state and the second state is a parallel state.

[0160] The present disclosure summarizes various embodiments so that those skilled in the art can better understand the aspects of the present disclosure embodiments. Those skilled in the art should understand that they can readily use the present disclosure embodiments as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure embodiments, and such equivalent constructions may be variously changed, substituted, and replaced herein without departing from the spirit and scope of the present disclosure embodiments.

Claims

1. A method for operating a memory, characterized in that: The following steps are involved: Providing a plurality of magnetoresistive random access memory cells; Dividing the plurality of magnetoresistive random access memory cells into a plurality of groups including a first group and a second group; Writing a first magnetoresistive random access memory cell of the first group from a first state to a second state; Writing a second MRAM cell of the second group from the first state to the second state; Verifying the writing of the first MRAM cell comprises the steps of comparing a first read current of the first MRAM cell with a first reference value; and Verifying the writing of the second MRAM cell includes the step of comparing a second read current of the second MRAM cell with a second reference value.

2. The method according to claim 1, characterized in that The first state is an anti-parallel state and the second state is a parallel state.

3. The method according to claim 2, characterized in that Further comprising the following steps: Determine a basic reference value; determining the first reference value by increasing the base reference value by a first amount; and The second reference value is determined by increasing the basic reference value by a second amount that is greater than the first amount.

4. The method according to claim 3, characterized in that The basic reference value is determined according to (Ip+Iap) / 2, wherein Ip is a peak read current of a parallel state curve, and Iap is a peak read current of an anti-parallel state curve.

5. The method according to claim 3, characterized in that The first reference value is determined according to (Ip+Iap) / 2+m, where m is a predetermined reference increment.

6. The method according to claim 3, characterized in that The second reference value is determined according to Ip-n, where n is a predetermined reference decrement.

7. The method according to claim 3, characterized in that Further comprising the following steps: Pre-verifying the first state of the first MRAM cell, comprising the steps of comparing a first state read current of the first MRAM cell with the basic reference value; and Pre-verifying the first state of the second MRAM cell includes comparing a first state read current of the second MRAM cell with the basic reference value.

8. A memory device, characterized in that: Include: a first group of MRAM cells, the first group including a first MRAM cell; a second group of MRAM cells, the second group including a second MRAM cell; and A sense amplifier is used to compare a first read current of the first MRAM cell with a first reference value and to compare a second read current of the second MRAM cell with a second reference value different from the first reference value.

9. A method for operating a memory, characterized in that: The following steps are involved: Providing a plurality of magnetoresistive random access memory cells; Dividing the plurality of MRAM cells into a plurality of groups, the plurality of groups comprising a first group having a plurality of first MRAM cells and a second group having a plurality of second MRAM cells; comparing a basic read current of each of the plurality of first MRAM cells and each of the plurality of second MRAM cells with a basic reference value; Based on the comparison, writing a plurality of selected MRAM cells from the plurality of first MRAM cells from a first state to a second state; Based on the comparison, writing a plurality of selected MRAM cells from the plurality of second MRAM cells from the first state to the second state; comparing a first read current of each of the plurality of first MRAM cells with a first reference value different from the basic reference value; and A second read current of each of the plurality of second MRAM cells is compared with a second reference value different from the basic reference value and the first reference value.

10. The method according to claim 9, characterized in that Further comprising the following steps: identifying a plurality of write failures of the plurality of first MRAM cells based on the comparing the first read current; and identifying a plurality of write failures of the plurality of second MRAM cells based on the comparing the second read currents, The first state is an anti-parallel state, and the second state is a parallel state.

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