Memory device and programming method thereof

Abstract

The invention relates to a memory device and a programming method thereof. The memory device has a memory cell array including a plurality of word lines and dummy word line groups. The programming method comprises the following steps: selecting a selected word line from a plurality of word lines, applying a programming voltage to the selected word line for programming, and applying an unselected voltage to the word lines except the selected word line in the plurality of word lines and a virtual word line group; performing programming verification on the programmed selection word line; when the selected word line passes the programming verification, performing at least one of upper threshold detection and lower threshold detection on the threshold voltage distribution of at least one of the virtual word line groups; and when at least one of the virtual word line groups does not pass the detection, displaying the state of the selected word line as a programming failure or setting error mark.

Description

Technical Field

[0001] The present invention relates to an operating method of a memory device, and more particularly to a memory device and a programming method thereof. Background Art

[0002] Program disturb is a key challenge in overcoming NAND memory cell scaling issues. Junction leakage and channel boosting ratio (CBR) are considered to be the two main components that limit program disturb. There are many ways to improve program disturb. Source / drain junction engineering is used to improve junction leakage. However, program disturb caused by poor boosting is still a consideration in memory cell scaling issues.

[0003] Program disturb window is also highly needed in the development of 3D NAND flash memory. High reliability triple-level cell (TLC) or quad-level cell (QLC) requires a high memory cell opening window between the high threshold voltage state and the erased state. Therefore, the unselected programming voltage (VPASSP) applied to the virtual word line is an issue to control the gradient channel potential, thereby avoiding hot electron interference. However, the threshold voltage VT of the virtual word line is not always distributed as expected. Program / mold erase cycles or process variability including vertical channel size and profile will also affect the threshold voltage VT of the virtual word line. In this way, the original gradient channel potential condition will be changed and the optimized unselected programming voltage setting will be destroyed.

[0004] Figure 1 A schematic diagram of voltage application during programming is shown. When programming each word line of the memory cell array, a programming bias VPGM is applied to the selected word line, and a pass bias VPASSP is applied to the unselected word line. In addition, the memory cell array also includes bottom dummy word lines DWLB0-DWLB2, and when programming, the bottom dummy word lines DWLB0-DWLB2 are also applied with unselected programming voltage biases VPASSP1-VPASSP3. Figure 1 As shown, taking the bottom dummy word line DWLB1 as an example, if the threshold voltage is too low or too high, the expected gradient channel potential I will be affected to become a distribution of II or III, which will cause programming interference.

[0005] Figure 2AA graph showing the relationship between the threshold voltage of a virtual word line and the number of programming times of each word line is drawn, wherein the horizontal axis is the threshold voltage VT of the virtual word line DWLB0, and the vertical axis is the number of programming times. The value of the threshold voltage VT is recorded once each time a word line is programmed. Figure 2A It can be seen that when programming from the top word line WL95 to the bottom word line WL0 of the 3D NAND flash memory in sequence, as the number of programming times increases, the threshold voltage VT of the virtual word line DWLB0 also gradually increases.

[0006] Figure 2B A schematic diagram showing the disturbance of the threshold voltage of a virtual word line is shown. Figure 2B As shown, the horizontal axis is the word line number, from word line WL95 to word line WL0 in sequence, and the vertical axis is the threshold voltage VT (upper threshold (high bound, HB)) of the virtual word line DWLB0. Figure 2B It can be seen that after the word lines WL95 to WL0 are programmed in sequence, the threshold voltage VT of the virtual word line DWLB0 is disturbed and increases from about 0.5V to about 3V.

[0007] Therefore, a programming method for 3D NAND flash memory is needed to reduce the influence of the threshold voltage VT of the virtual word line, thereby improving the quality and reliability of memory devices such as 3D NAND. Summary of the invention

[0008] The invention provides a memory device and a programming method thereof, so as to further ensure the programming validity and data retention, and improve the programming reliability.

[0009] According to one embodiment of the present invention, a programming method for a memory device is provided. The memory device has a memory cell array, and the memory cell array includes a plurality of word lines and a virtual word line group. The programming method includes the following steps. A selected word line is selected from the plurality of word lines, a programming voltage is applied to the selected word line for programming, and an unselected voltage is applied to the plurality of word lines other than the selected word line and the virtual word line group. Programming verification is performed on the programmed selected word line. When the selected word line passes the programming verification, at least one of an upper threshold detection and a lower threshold detection is performed on the threshold voltage distribution of at least one virtual word line of the virtual word line group. When the at least one virtual word line of the virtual word line group fails to pass at least one of the upper threshold detection and the lower threshold detection, the state of the selected word line is displayed as a programming failure or a setting error flag.

[0010] According to another embodiment of the present invention, a memory device is provided. The memory device includes a memory cell array and a controller. The memory cell array includes a plurality of word lines and a virtual word line group. The controller is used to control the memory cell array. The controller programs each of the plurality of word lines, which includes the following steps. A selected word line is selected from the plurality of word lines, a programming voltage is applied to the selected word line for programming, and an unselected voltage is applied to the plurality of word lines other than the selected word line and the virtual word line group. Programming verification is performed on the programmed selected word line. When the selected word line passes the programming verification, at least one of an upper threshold detection and a lower threshold detection is performed on the threshold voltage distribution of at least one virtual word line of the virtual word line group. When the at least one virtual word line of the virtual word line group fails to pass at least one of the upper threshold detection and the lower threshold detection, the state of the selected word line is displayed as a programming failure or a setting error flag.

[0011] According to an embodiment of the present invention, in the above-mentioned programming method and memory device, the above-mentioned upper threshold detection further includes the following steps: reading a first threshold voltage of at least one of the virtual word lines of the virtual word line group. When the first threshold voltage is higher than a preset upper threshold value, determining whether the number of upper threshold failure bits is greater than a first specified value. When the number of upper threshold failure bits is greater than the first specified value, displaying the state of the selected word line as the programming failure or setting the error flag.

[0012] According to an embodiment of the present invention, in the above-mentioned programming method and memory device, the lower threshold detection further includes the following steps: reading a second threshold voltage of at least one of the virtual word lines of the virtual word line group. When the second threshold voltage is lower than a preset lower threshold value, determining whether the number of lower threshold failure bits is greater than a second specified value. When the number of lower threshold failure bits is greater than the second specified value, displaying the state of the selected word line as the programming failure or setting the error flag.

[0013] According to an embodiment of the present invention, in the above-mentioned programming method and memory device, the first prescribed value and the second prescribed value may be the same.

[0014] According to an embodiment of the present invention, in the above-mentioned programming method and memory device, the programming failure may include marking the selected word line as a dummy word line, or marking the selected block as a bad block. According to an embodiment of the present invention, in the above-mentioned programming method and memory device, the error identification may include setting a flag for the selected word line to modify the operation setting.

[0015] According to an embodiment of the present invention, in the above-mentioned programming method and memory device, the programming method or controller further executes: when at least one of the virtual word lines in the virtual word line group passes at least one of the upper threshold detection and the lower threshold detection, the display status is passed programming and the programming of the memory device is ended.

[0016] According to an embodiment of the present invention, in the above-mentioned programming method and memory device, the memory device may be a 3D NAND flash memory or a 2D NAND flash memory. According to an embodiment of the present invention, in the above-mentioned programming method and memory device, the memory cells of the memory cell array may be single-layer cells, triple-layer cells, quad-layer cells or multi-layer cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of voltage application during programming in the prior art is shown.

[0018] Figure 2A A diagram showing the relationship between the threshold voltage of a dummy word line and the programming times of each word line is shown.

[0019] Figure 2B FIG. 4 is a schematic diagram showing that the threshold voltage of a dummy word line is disturbed.

[0020] Figure 3 A schematic diagram of a memory structure associated with each word line is shown.

[0021] Figure 4 A schematic diagram of the structure of each word line is shown.

[0022] Figure 5 4 is a schematic diagram of a memory programming process according to an embodiment of the present invention.

[0023] Figure 6 4 is a schematic diagram of voltage waveforms for memory programming according to an embodiment of the present invention.

[0024] Figure 7 A conceptual diagram of an upper threshold value / lower threshold value for detecting a threshold voltage distribution of a dummy word line according to an embodiment of the present invention.

[0025] Figure 8 It is a schematic diagram of a flow chart of detecting whether the threshold voltage distribution of a virtual word line passes the upper threshold value / lower threshold value detection according to an embodiment of the present invention.

[0026] Fig. 9 4 is a threshold voltage distribution diagram of a virtual word line for upper threshold / lower threshold detection according to an embodiment of the present invention.

[0027] Fig. 10A FIG. 4 is a schematic diagram illustrating an example of modifying operation settings according to an embodiment of the present invention.

[0028] Fig. 10B FIG. 2 is a schematic diagram illustrating another example of modifying operation settings according to an embodiment of the present invention.

[0029] Fig.11 is a schematic diagram of a memory device according to an embodiment of the present invention.

[0030]

Explanation of symbols

[0031] 10: Dielectric core

[0032] 20: Channel layer

[0033] 30: Charge capture layer

[0034] 100: Memory control circuit

[0035] 110: Memory cell array

[0036] WL0~WL95:Word line

[0037] DWLB0~DWLB2: Bottom dummy word line

[0038] DWLB: bottom dummy word line group

[0039] DWLT0~DWLT2: Top virtual word line

[0040] CSL: Common Source Line

[0041] SSL, SSL0, SSL1, SSL2: Select line

[0042] GSL: Global Source Line

[0043] GBL: Global Bit Line

[0044] VC: Vertical Channel

[0045] 100: Controller

[0046] 110: Memory cell array DETAILED DESCRIPTION

[0047] The present invention is directed to a method for programming a memory device. In the following, a 3D NAND flash memory is used as an example for explanation, but the present invention is not limited thereto, and any 3D structured memory can be applied. In addition, the present invention can also be applied to a 2D memory.

[0048] Figure 3 FIG. 1 shows a memory architecture as an application example of an embodiment of the present invention, which illustrates a partial structure of a 3D NAND flash memory. Figure 3The schematic structure of the 3D NAND flash memory shown in the figure has multiple word lines WL0~WL95 (96 as an example) formed in the vertical direction z, and the vertical channel VC is also formed along the vertical direction z. Each word line extends on the xy plane. In addition, the bottom virtual word lines DWLB2~DWLB0 are also configured below the word line WL0, and the top virtual word lines DWLT2~DWLT0 are also configured above the word line WL95. Here, although 3 bottom virtual word lines and 3 top virtual word lines are illustrated, their number is not particularly limited and can be appropriately adjusted according to needs.

[0049] In addition, the 3D NAND flash memory may further include a common source line (CSL) configured on the substrate SB. The substrate SB may be a silicon substrate. The common source line CSL may be in the form of a conductive layer or a plurality of conductive lines configured on the substrate SB. The common source line CSL connects the source lines together. In one embodiment, the common source line CSL further extends in the normal direction z of the substrate SB. The 3D NAND flash memory may further include selection lines SSL0, SSL1, SSL2, etc., which may be arranged above the top virtual word line DWLT2. The 3D NAND flash memory may also form a global source line (GSL) on the lower side of the bottom virtual word line, and a global bit line (GBL) may be formed on the upper side of the top virtual word line to connect each bit line. Figure 3 The 3D NAND flash memory structure shown is only for the convenience of understanding the relationship between the word lines (data word lines) WL0-WL95 and the virtual word lines, and is not intended to limit the implementation objects of the present invention.

[0050] Figure 4 The structure diagram of each word line is shown in FIG. Figure 3 A magnified view of the word line section. Figure 4 As described above, the 3D NAND flash memory includes a plurality of word lines WL0-WL95, which are penetrated by a vertical channel VC. The vertical channel VC has a dielectric layer core 10, a channel layer 20 surrounding the dielectric layer core 10, and a charge trapping layer 30 between each word line WL0-WL95 and the channel layer 20. The channel layer 20 is formed of, for example, polysilicon. The charge trapping layer is, for example, composed of an oxide-nitride-oxide (ONO) layer. The structure illustrated here is only an example of a 3D NAND memory to which the programming method of the present invention can be applied, and the method of the present invention is not limited to any memory structure.

[0051] Figure 5 1 is a schematic diagram of a programming flow of a memory device according to an embodiment of the present invention. The programming method of the memory device of this embodiment can be applied to Figure 3 The 3D NAND flash memory device shown in FIG. has a memory cell array. The memory cell array may include a plurality of word lines WL and a dummy word line group DWL. As an example, the dummy word line group DWL may include a plurality of bottom dummy word lines DWLB0 to DWLB2 and top dummy word lines DWLT0 to DWLT2 (see FIG. 1 ). Figure 3 In the following description, the bottom dummy word lines DWLB0-DWLB2 are taken as examples to illustrate the programming method of the present invention, but it can also be applied to the top dummy word lines DWLT0-DWLT2.

[0052] like Figure 5 As shown, in step S100, a word line in the memory cell array is programmed. For example, one of the word lines in the memory cell array is selected, i.e., the selected word line. Afterwards, a programming voltage (bias) VPGM is applied to the selected word line to program the selected word line. Here, programming the selected word line refers to programming all memory cells coupled to the selected word line. In addition, an unselected voltage VPASSP is applied to other word lines other than the selected word line among the above-mentioned multiple word lines and the bottom virtual word lines DWLB0~DWLB2 (virtual word line group). In addition, when programming, the selected word line can be programmed by using the so-called Increment Step Programming Pulse (ISPP).

[0053] In step S102, program verification is performed on the programmed selected word line. This program verification can be performed in any feasible manner, and the present invention is not particularly limited. Program verification can determine whether the memory cells on the selected word line have been correctly programmed. If the programmed selected word line does not pass the program verification, it means that the selected word line has not been correctly programmed, so the process returns to step S100, and the selected word line is programmed again by increasing the programming voltage until it passes the program verification.

[0054] Figure 6 The waveform of the programming voltage VPGM for the selected word line in the programming phase and the waveform of the unselected voltage VPASSP applied to the unselected word line are illustrated. In addition, the voltage VPASSR in the programming verification phase is applied to the unselected word line, and the state verification voltages AV, BV, ..., GV, etc. are applied to the selected word line. The voltage waveforms here are only illustrative examples and are not intended to limit the waveforms of the programming voltage and the verification voltage of the present invention.

[0055] In step S104, after the selected word line passes the programming verification in step S102, at least one of the upper threshold detection (high bound check, HB check) and the lower threshold detection (low bound check, LB check) is then performed on the distribution of the threshold voltage VT of at least one of the virtual word lines in the virtual word line group (i.e., to determine whether there is interference). The upper threshold and the lower threshold can be preset as needed. In addition, this example will take the bottom virtual word line group DWLB (such as DWLB0~DWLB2) as an example, but the top virtual word line group DWLT can also be tested. In the following example, the bottom virtual word line DWLB0 is used as an illustrative example, but this test can be performed on all the bottom virtual word lines of the bottom virtual word line group DWLB.

[0056] As mentioned above Figure 2A and Figure 2B As shown in FIG. 1 , after all word lines are programmed, the threshold voltage of the bottom virtual word line DWLB0 will be disturbed to a high voltage, thus affecting the accuracy of programming. Therefore, even if the programming verification is passed after programming the selected word line (step S102, yes), if the threshold voltage of the bottom virtual word line DWLB0 is disturbed, the correctness of its programming and the retention of data will be affected to a certain extent. Therefore, in this example, the bottom virtual word line DWLB0 will be further read to determine whether the distribution of the threshold voltage VT of the bottom virtual word line DWLB0 passes the upper threshold detection and / or the lower threshold detection.

[0057] like Figure 7 As shown, the vertical axis is the bit count (BC) and the horizontal axis is the threshold voltage VT. First, for the detection of the distribution of the threshold voltage VT of the bottom virtual word line (such as DWLB0), the upper threshold HB and the lower threshold LB can be preset. Therefore, by reading the threshold voltage value VT of the storage cell on the bottom virtual word line DWLB0, the upper threshold detection and the lower threshold detection are performed, which can further determine whether the programming of the selected word line is invalid. This will be further explained below. In addition, as Figure 6 As shown, when detecting a dummy word line, for example, a read voltage is applied to the bottom word line DWLB0 to perform upper threshold detection and lower threshold detection. When detecting a dummy word line, an unselected bias VPASSR is applied to all word lines (such as WL0 to WL95). In one example, the unselected bias VPASSR when detecting a dummy word line can be the same as the unselected bias VPASSR applied to the unselected word line in the programming verification stage. In another example, the unselected bias VPASSR when detecting a dummy word line can be different from the unselected bias VPASSR applied to the unselected word line in the programming verification stage.

[0058] Figure 8FIG. 1 is a flow chart of detecting whether the threshold voltage distribution of a virtual word line passes the upper threshold value / lower threshold value detection according to the example. Figure 8 As shown, Figure 5 The step S104 further includes step S104A and step S104B, which are respectively performing an upper threshold detection and a lower threshold detection on the bottom dummy word line DWLB0.

[0059] also, Fig. 9 According to the detection conditions of the upper threshold detection and the lower threshold detection of the bottom dummy word line DWLB0 exemplified by the present invention. Fig. 9 As shown, an example of the upper threshold detection condition is to detect the upper threshold of the bottom virtual word line DWLB0, such as setting the upper threshold HB_check, and using 200 bits as the judgment value of the failure bit count (FBC). In addition, the threshold voltage interval is set to 0 to 2V. In addition, an example of the lower threshold detection condition is to detect the lower threshold of the bottom virtual word line DWLB0, such as setting the lower threshold LB_check, and using 200 bits as the judgment value of the failure bit count (FBC). In addition, the threshold voltage interval is set to 0 to -2V.

[0060] like Figure 8 and Fig. 9 As shown, in step S104A, the bottom virtual word line DWLB0 is read to determine whether it passes the upper threshold test. That is, when the threshold voltage VT (first threshold voltage) of the virtual word line DWLB0 is higher than the preset upper threshold HB_check, the number of failure bit counts FBC will be counted, and it will be determined whether the upper threshold failure bit count FBC_HB is greater than the first specified value N. When the upper threshold failure bit count FBC_HB is greater than the first specified value N, it indicates that the above-mentioned programming of the selected word line is failed. At this time, step S108 is executed to display the state of the selected word line as program fail, or set an error flag. On the contrary, when the upper threshold failure bit count FBC_HB is less than the first specified value N, step S104B is then executed.

[0061] In step S104B, the bottom virtual word line DWLB0 is read to determine whether it passes the lower threshold detection. That is, when the threshold voltage VT (second threshold voltage) of the virtual word line DWLB0 is lower than the preset lower threshold LB_check, the number of failure bit counts FBC is counted, and it is determined whether the lower threshold failure bit count FBC_LB is greater than the second specified value M. When the lower threshold failure bit count FBC_LB is greater than the second specified value M, it indicates that the above-mentioned programming of the selected word line is failed. At this time, step S108 is executed to display the state of the selected word line as programming failure, or set an error flag. On the contrary, when the lower threshold failure bit count FBC_LB is less than the second specified value M, step S106 is then executed to display the state of the selected word line as passed programming. After that, the programming operation is completed.

[0062] It should be noted that the above-mentioned step S104A (upper threshold detection) and step S104B (lower threshold detection) do not need to be performed at the same time. In other words, the upper threshold detection and the lower threshold detection can be performed either or both. Figure 8 For example, assuming that only the upper threshold detection of step S104A is performed, whether to perform step S106 or step S108 can be determined according to whether the upper threshold failure bit number FBC_HB is greater than the first specified value N.

[0063] Furthermore, when both the upper threshold detection of step S104A and the lower threshold detection of step S104B are performed, the order thereof can be arbitrary and there is no particular limitation in the implementation of the present invention.

[0064] Therefore, in step S104, when at least one of the bottom dummy word lines in the bottom dummy word line group DWLB fails to pass at least one of the upper threshold detection and the lower threshold detection, step S108 is executed. In step S108, the state of the selected word line is displayed as program fail, or an error flag is set. Thus, the user can know which word line has a problem and needs attention, thereby avoiding use or modifying the operation setting.

[0065] Regarding programming failure, when the bottom dummy word line DWLB0 does not pass the detection of the upper threshold or the lower threshold (especially, in step S108, it is determined that the word line is difficult to program), the controller can set some of the disturbed word lines as bad blocks or as dummy word lines (different from the bottom or top dummy word lines mentioned above), thereby avoiding the use of these disturbed word lines when operating the memory device.

[0066] Regarding setting the error flag, the controller may perform some corresponding operations, such as revising the operation setting. That is, in step S108, if it is determined that the condition that the word lines cannot be correctly programmed is relatively less serious, that is, these word lines are still usable despite the problem, the operation setting is revised. As an example, a new read level may be set to determine the programming risk. Fig. 10A The threshold voltage distribution diagram after programming is illustrated. When there is no threshold voltage distribution disturbance, the erased state ER and the programmed state A can be distinguished and read out by the read level RDA. However, if at least one of the upper threshold detection and the lower threshold detection is used to detect that there is a threshold voltage distribution disturbance (such as the erased state ER is disturbed to shift to the right (as shown by the bold erased state ER')), the programmed state A will be mistakenly read as the erased state ER' by the read level RDA. At this time, if the word line is still in a usable state, the read level RDA can be set to a new read level RDA' (shifted to the right (upward)) to change the operation setting.

[0067] Fig. 10B FIG. 1 is a schematic diagram illustrating another example of modifying the operation setting of an embodiment of the present invention. As described above, the erase state ER is disturbed to Fig. 10A or Fig. 10B At this time, even if the read level RDA is set to the new read level RDA', the programming state A is too close to the disturbed erased state ER', which will cause more failed bits to be counted. Therefore, as another modification of the operation setting, each programming state A~G (together with the corresponding read state A~G) can also be shifted (upward), that is, from Fig. 10B The solid line programming states A to G in FIG. 1 are shifted to the dotted line programming states A to G. In this way, since all states are shifted, the shifted programming state A and the disturbed erased state ER' can be further separated, so the number of failed bits can be reduced during the read operation.

[0068] On the other hand, in step S104, when at least one of the bottom dummy word lines (one of DWLB0-DWLB2) in the bottom dummy word line group DWLB passes at least one of the upper threshold detection and the lower threshold detection, step S106 is executed to make the state of the selected word line of the memory device display as passed programming. After that, the programming operation of the selected word line is completed, and the programming of the next word line is performed.

[0069] Fig.11 FIG. 4 is a block diagram of a control circuit of a memory device according to an embodiment of the present invention. Fig.11The diagram is a simplified schematic diagram. Those skilled in the art can design the actual circuit architecture and various functional blocks such as row decoders, column decoders, voltage generating circuits, various buffers, control logic, I / O circuits, etc. appropriately according to their needs based on the concept of the present invention.

[0070] like Fig.11 As shown, the memory device includes at least but not limited to a controller 100 and a memory cell array 110. The memory cell array 110 is composed of a plurality of memory cells arranged in an array. The memory cell array 100 also includes a dummy word line group, a plurality of word lines WL (such as WL0 to WL95), a common source line CSL and a bit line BL (such as reference Figure 3 ) etc. In addition, although Fig.11 Only the bottom dummy word line group DWLB is illustrated, but it may also include Figure 3 The top virtual word lines (such as DWLT0-DWLT2, etc.) are shown. In addition, by applying bias voltages to the plurality of word lines WL, the common source line CSL, and the bit line BL, operations such as reading, programming, or erasing are performed on each word line WL of the memory device. Here, the memory cell array 110 is not particularly limited. As an example, the memory cell array 110 can be configured as a 3D or 2D NAND flash memory cell array.

[0071] The controller 100 is basically used to control all operations of the memory cell array 110, including reading, programming and erasing, etc. Here, only the programming operation is described, and the remaining reading and erasing operations can be any current operation mode, and the description is omitted here.

[0072] In addition, the controller 100 may be configured to perform the above-mentioned operations on the word lines WL and the bottom dummy word line group DWLB (which may also further include the top dummy word line group DWLT) of the memory cell array 110. Figure 5 , Figure 8 The programming control process shown is such as transmitting a control signal to the memory cell array 110. In addition, the controller 100 can be configured to perform the setting process of step S108 (as described above, displaying a programming failure or setting an error flag) on ​​each word line WL of the memory cell array 110 according to the upper threshold detection and / or lower threshold detection results of the virtual word line, and can also perform the setting process of step S106 (as described above, displaying a programming pass).

[0073] The above embodiments are based on 3D NAND flash memory as an example, but the present invention is not limited to NAND flash memory, and other types of memory can also be applied. In addition, in addition to 3D NAND flash memory, the programming method of the present invention can also be applied to 2D flash memory.

[0074] In addition, the programming method of the present invention is not only applicable to memories with 2D or 3D structures, but can also be applied to structures in which the storage cells are single-level cells (SLC) storing 1 bit, double-level cells storing 2 bits, triple-level cells (TLC) storing 3 bits, or quad-level cells (QLC) storing 4 bits, or multiple-level cells (MLC).

[0075] In summary, after programming the word line and passing the programming verification, the present invention further performs an upper threshold detection and / or a lower threshold detection of the threshold voltage distribution on at least one of the bottom virtual word lines, and determines whether it is disturbed. When the threshold voltage distribution of the bottom (or top) virtual word line passes the upper threshold detection and / or the lower threshold detection, the programming result of the word line is displayed as passed. In this way, the effectiveness of programming and data retention can be further ensured to improve the reliability of programming.

Claims

1. A method for programming a memory device, wherein the memory device has a memory cell array, the memory cell array includes a plurality of word lines and a dummy word line group, the programming method comprising: Selecting a selected word line from the plurality of word lines, applying a programming voltage to the selected word line for programming, and applying an unselected voltage to the plurality of word lines other than the selected word line and the dummy word line group; performing program verification on the programmed selected word line; When the selected word line passes programming verification, performing at least one of an upper threshold detection and a lower threshold detection on a threshold voltage distribution of at least one virtual word line of the virtual word line group; as well as When the at least one dummy word line of the dummy word line group fails to pass at least one of the upper threshold detection and the lower threshold detection, the state of the selected word line is displayed as a programming failure or a setting error flag.

2. The programming method of the memory device according to claim 1, wherein the upper threshold detection further comprises: Reading a first threshold voltage of at least one of the virtual word lines of the virtual word line group; When the first threshold voltage is higher than a preset upper threshold value, determining whether the upper threshold failure bit number is greater than a first specified value; When the upper threshold failure bit number is greater than a first specified value, the state of the selected word line is displayed as the programming failure or the error flag is set.

3. The programming method of the memory device according to claim 1, wherein the lower threshold detection further comprises: Reading a second threshold voltage of at least one of the virtual word lines of the virtual word line group; When the second threshold voltage is lower than a preset lower threshold value, determining whether the number of lower threshold failure bits is greater than a second specified value; When the number of lower threshold failure bits is greater than the second specified value, the state of the selected word line is displayed as the programming failure or the error flag is set.

4. The programming method of the memory device according to claim 2, wherein the lower threshold detection further comprises: Reading a second threshold voltage of at least one of the virtual word lines of the virtual word line group; When the second threshold voltage is lower than a preset lower threshold value, determining whether the number of lower threshold failure bits is greater than a second specified value; When the number of lower threshold failure bits is greater than the second specified value, the state of the selected word line is displayed as the programming failure or the error flag is set. 5 . The programming method of the memory device according to claim 4 , wherein the first prescribed value is the same as the second prescribed value. 6 . The programming method of the memory device according to claim 1 , wherein the programming failure comprises marking the selected word line as a dummy word line, or marking a selected block as a bad block. 7 . The programming method of the memory device according to claim 1 , wherein the error identification comprises setting a flag for the selected word line to modify an operation setting.

8. The method for programming a memory device according to claim 1 , further comprising: When the at least one dummy word line of the dummy word line group passes at least one of the upper threshold detection and the lower threshold detection, a state is displayed as programming passed and programming of the memory device is completed. 9 . The programming method of the memory device according to claim 1 , wherein the memory device is a 3D NAND flash memory or a 2D NAND flash memory. 10 . The programming method of the memory device according to claim 1 , wherein the memory cells of the memory cell array are single-level cells, triple-level cells, quad-level cells or multi-level cells.

11. A memory device comprising A memory cell array includes a plurality of word lines and a dummy word line group; as well as A controller for controlling the storage cell array, wherein the controller programs each of the plurality of word lines, including: Selecting a selected word line from the plurality of word lines, applying a programming voltage to the selected word line to perform the programming, and applying an unselected voltage to the plurality of word lines other than the selected word line and the dummy word line group; performing program verification on the programmed selected word line; When the selected word line passes programming verification, performing at least one of an upper threshold detection and a lower threshold detection on a threshold voltage distribution of at least one dummy word line of the dummy word line group; and When the at least one dummy word line of the dummy word line group fails to pass at least one of the upper threshold detection and the lower threshold detection, the state of the selected word line is displayed as a programming failure or a setting error flag.

12. The memory device of claim 11, wherein the upper threshold detection further comprises: Reading a first threshold voltage of at least one of the virtual word lines of the virtual word line group; When the first threshold voltage is higher than a preset upper threshold value, determining whether the upper threshold failure bit number is greater than a first specified value; When the upper threshold failure bit number is greater than a first specified value, the state of the selected word line is displayed as the programming failure or the error flag is set.

13. The memory device of claim 11 , wherein the lower threshold detection further comprises: Reading a second threshold voltage of at least one of the virtual word lines of the virtual word line group; When the second threshold voltage is lower than a preset lower threshold value, determining whether the number of lower threshold failure bits is greater than a second specified value; When the number of lower threshold failure bits is greater than the second specified value, the state of the selected word line is displayed as the programming failure or the error flag is set.

14. The memory device of claim 12, wherein the lower threshold detection further comprises: Reading a second threshold voltage of at least one of the virtual word lines of the virtual word line group; When the second threshold voltage is lower than a preset lower threshold value, determining whether the number of lower threshold failure bits is greater than a second specified value; When the number of lower threshold failure bits is greater than the second specified value, the state of the selected word line is displayed as the programming failure or the error flag is set.

15. The memory device of claim 14, wherein the first prescribed value is the same as the second prescribed value.

16. The memory device of claim 11, wherein the programming failure comprises marking the selected word line as a dummy word line, or marking a selected block as a bad block.

17. The memory device of claim 11, wherein the error identification comprises setting a flag for the selected word line to modify an operation setting.

18. The memory device of claim 11, wherein the controller further performs: When the at least one dummy word line of the dummy word line group passes at least one of the upper threshold detection and the lower threshold detection, a state is displayed as programming passed and programming of the memory device is completed.

19. The memory device of claim 11, wherein the memory device is a 3D NAND flash memory or a 2D NAND flash memory.

20. The memory device of claim 11, wherein memory cells of the memory cell array are single-level cells, triple-level cells, quad-level cells, or multi-level cells.

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