Error checking and cleaning operation method and semiconductor device and system performing same

Abstract

The invention relates to an error check cleaning operation method and a semiconductor device and a semiconductor system performing the same. The semiconductor system includes: a controller outputting a chip selection signal and a command address for performing a read operation, and then outputting a chip selection signal and a command address for performing an ECS operation; and a semiconductor device including a plurality of memory cells, generating a latch row address and a latch column address by latching the command address when an error occurs in internal data output from a memory cell selected from among the plurality of memory cells after a read operation based on the chip selection signal and the command address is started, and determining priorities of ECS operations of the plurality of memory cells based on the latch row address and the latch column address, and re-storing the internal data in the same memory cell by correcting errors of the internal data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0139065 filed in the Korean Intellectual Property Office on October 17, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to a semiconductor system, and more particularly to a semiconductor system that latches a command address when an error occurs in internal data after a read operation starts, preferentially performs an error check and scrubbing (ECS) operation on a memory cell corresponding to the latched command address after an ECS operation starts, and then sequentially performs the ECS operation on a plurality of memory cells. Background Art

[0004] Recently, in order to increase the operating speed of semiconductor devices, a method of inputting and outputting multi-bit data per clock cycle is used, such as DDR2, DDR3, DDR4, and DDR5. Since the probability of an error occurring during data transmission increases as the input / output speed of data becomes faster, a separate device and method for ensuring the reliability of data transmission is additionally required.

[0005] A method for ensuring the reliability of data transmission by generating an error check code capable of checking whether an error occurs whenever data is transmitted and transmitting the error check code together with the data is used. The error check code includes an error detection code (EDC) capable of detecting an error that occurs and an error correction code (ECC) capable of autonomously correcting an error when an error occurs.

[0006] In addition, the semiconductor device prevents errors of internal data by performing an error check scrubbing (ECS) operation, which corrects errors of internal data stored in the semiconductor device by using ECC and stores the internal data again. The ECS operation is an operation of correcting errors of internal data stored therein by sequentially activating all storage cells already included in the semiconductor device and storing the internal data again. Summary of the invention

[0007] In an embodiment, a semiconductor system may include: a controller configured to output a chip select signal and a command address including a first logic level combination for performing a read operation, and configured to then output a chip select signal and a command address including a second logic level combination for performing an error check and scrubbing (ECS) operation, the second logic level combination being different from the first logic level combination; and a semiconductor device including a plurality of memory cells, the semiconductor device: configured to receive a command address to generate an internal command address after a read operation based on the chip select signal and the command address is started, the internal command address being used to generate a latch row address and a latch column address by latching the internal command address when an error occurs in internal data output from a memory cell selected from among the plurality of memory cells; configured to determine priorities of ECS operations of a plurality of memory cells corresponding to the latch row address and the latch column address; and configured to store the internal data again in the same selected memory cell after correcting the error of the internal data.

[0008] In an embodiment, a semiconductor device may include: an operation control circuit configured to: receive a command address to generate an internal command address after a read operation starts, the internal command address being used to generate a latched row address and a latched column address by latching a command address for selecting a memory cell included in a memory circuit when an error flag signal is enabled; and configured to generate a row address and a column address from the latched row address and the latched column address by detecting a logic level of an error flag signal after an error check and scrubbing (ECS) operation starts, or configured to generate a row address and a column address that are counted sequentially; and an ECS control circuit configured to correct an error included in internal data output from a memory cell selected by the row address and the column address after the ECS operation starts, and configured to output the error-corrected internal data and then store the internal data in the memory cell again.

[0009] In an embodiment, an error check and scrubbing (ECS) method may include: a read operation step: after the read operation starts, when an error occurs in internal data that has been stored in a storage cell selected by a row address and a column address generated based on a command address among a plurality of storage cells, a latch row address and a latch column address are generated by latching an internal command address generated from the command address; and after correcting the error of the internal data, the internal data is output as data; and an ECS operation step: after the ECS operation starts, after correcting the error of the internal data that has been stored in the selected storage cell based on a logic level of an error flag signal, the internal data is stored again based on the latch row address and the latch column address; and then, after correcting the error of the internal data that has been stored in a plurality of storage cells, the internal data is stored again. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram showing a configuration of a semiconductor system according to an embodiment of the present disclosure.

[0011] Figure 2 It shows that according to Figure 1 FIG. 1 is a block diagram showing a configuration of an embodiment of a semiconductor device included in a semiconductor system.

[0012] Figure 3 It shows that according to Figure 2 A block diagram showing a configuration of an embodiment of an operation control circuit included in a semiconductor device shown.

[0013] Figure 4 It shows that according to Figure 3 A block diagram of the construction of an embodiment of an error address generation circuit included in the address generation circuit shown.

[0014] Figure 5 It shows that according to Figure 4 FIG. 1 is a block diagram showing a configuration of an embodiment of a selection transfer circuit included in an error address generation circuit.

[0015] Figure 6 It shows that according to Figure 3 FIG. 2 is a block diagram showing the configuration of an embodiment of an address selection circuit included in an address generation circuit.

[0016] Figure 7 It shows that according to Figure 2 A block diagram showing a configuration of an embodiment of a memory circuit included in a semiconductor device shown.

[0017] Figure 8 It shows that according to Figure 7 A block diagram showing the configuration of an embodiment of a core circuit included in a memory circuit is shown.

[0018] Fig. 9 It shows that according to Figure 8 A diagram of the construction of an embodiment of a first memory matrix included in the core circuit is shown.

[0019] Fig.10 It shows that according to Figure 2 FIG. 1 is a block diagram showing a configuration of an embodiment in which an ECS control circuit included in a semiconductor device performs a read operation of a normal operation and an ECS operation.

[0020] Fig.11 is a diagram for describing a read operation of a semiconductor device according to an embodiment of the present disclosure.

[0021] Fig.12 is a diagram for describing an ECS operation of a semiconductor device according to an embodiment of the present disclosure.

[0022] Fig.13 is a timing diagram for describing a read operation of a semiconductor device according to an embodiment of the present disclosure.

[0023] Fig.14 is a timing diagram for describing an ECS operation of a semiconductor device according to an embodiment of the present disclosure.

[0024] Fig.15 is a flowchart for describing an ECS method of a semiconductor system according to an embodiment of the present disclosure.

[0025] Fig.16 It shows that according to the application Figure 1 and Fig.15 A diagram of the configuration of an embodiment of an electronic system of a semiconductor system is shown. DETAILED DESCRIPTION

[0026] In the description of the following embodiments, the term "preset" means that the value of the parameter is predetermined when the parameter is used in a process or algorithm. According to the embodiment, the value of the parameter can be set at the beginning of the process or algorithm, or when the process or algorithm is executed.

[0027] Terms such as "first" and "second" are used to distinguish a plurality of components, but are not limited to the components. For example, a first component may be referred to as a second component, and vice versa.

[0028] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that the components may be directly coupled or connected to each other, or coupled or connected to each other with another component interposed therebetween. Conversely, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that the components are directly coupled or connected to each other without interposing another component therebetween.

[0029] "Logical high level" and "logical low level" are used to describe the logic level of a signal. A signal with a "logical high level" is different from a signal with a "logical low level". For example, when a signal with a first voltage corresponds to a signal with a "logical high level", a signal with a second voltage may correspond to a signal with a "logical low level". According to an embodiment, the "logical high level" may be set to a voltage higher than the "logical low level". According to an embodiment, the logic level of a signal may be set to a different logic level or an opposite logic level. For example, in some embodiments, a signal with a logical high level may be set to have a logical low level, and in some embodiments, a signal with a logical low level may be set to have a logical high level.

[0030] The present disclosure is described in more detail below through examples. The above examples are only used to illustrate the present disclosure, and the scope of the present disclosure is not limited by the examples.

[0031] An embodiment of the present disclosure provides a semiconductor system that latches a command address when an error occurs in internal data after a read operation starts, preferentially performs an error check and scrubbing (ECS) operation on a storage cell corresponding to the latched command address after an ECS operation starts, and then sequentially performs the ECS operation on a plurality of storage cells.

[0032] According to an embodiment of the present disclosure, the priority of the ECS operation can be set by latching a command address when an error occurs in the internal data after the start of the read operation, preferentially performing the ECS operation on the memory cell corresponding to the latched command address after the start of the ECS operation, and then sequentially performing the ECS operation on the plurality of memory cells. In an embodiment, the semiconductor device 20 can determine the priority of the ECS operation of the plurality of memory cells MC based on the latched row address RLA<1:M> and the latched column address CLA<1:N>.

[0033] In addition, according to an embodiment of the present disclosure, errors in internal data can be quickly corrected by latching a command address when an error occurs in internal data after a read operation starts, preferentially performing an ECS operation on a storage unit corresponding to the latched command address after an ECS operation starts, and then sequentially performing an ECS operation on multiple storage units.

[0034] like Figure 1 As shown, the semiconductor system 1 according to the embodiment of the present disclosure may include a controller 10 and a semiconductor device 20. The semiconductor device 20 may include an operation control circuit (OP CTR) 210 and an error check and scrub (ECS) control circuit (ECSCTR) 230.

[0035] The controller 10 may include a first control pin 11_1, a second control pin 11_2, a third control pin 11_3, and a fourth control pin 11_4. The semiconductor device 20 may include a first device pin 21_1, a second device pin 21_2, a third device pin 21_3, and a fourth device pin 21_4. The first transmission line L11 may be connected between the first control pin 11_1 and the first device pin 21_1. The second transmission line L12 may be connected between the second control pin 11_2 and the second device pin 21_2. The third transmission line L13 may be connected between the third control pin 11_3 and the third device pin 21_3. The fourth transmission line L14 may be connected between the fourth control pin 11_4 and the fourth device pin 21_4.

[0036] The controller 10 may transmit a chip selection signal CS for controlling the semiconductor device 20 to the semiconductor device 20 through the first transmission line L11. The controller 10 may transmit a command address CA for controlling the semiconductor device 20 to the semiconductor device 20 through the second transmission line L12. The controller 10 may transmit a clock CLK to the semiconductor device 20 through the third transmission line L13. The controller 10 may transmit data DATA to the semiconductor device 20 through the fourth transmission line L14. The controller 10 may receive data DATA from the semiconductor device 20 through the fourth transmission line L14. The chip selection signal CS may be set as a signal that is enabled to perform normal operation, ECS operation, and internal operation of the semiconductor device 20. The command address CA may include a plurality of bits, and may be set as a command including a command for controlling the operation of the semiconductor device 20 and a command for selecting a plurality of memory cells ( Figure 8 MC in) and multiple error units ( Figure 8 The clock CLK may be set as a signal that periodically switches to synchronize the operations of the controller 10 and the semiconductor device 20. The data DATA may include a plurality of bits and may be set as common data that is input to and output from the semiconductor device 20.

[0037] When the read operation starts from the storage circuit ( Figure 2 220) includes a plurality of storage units ( Figure 8 Internal data output by MC in Figure 2 When an error occurs in ID<1:128> in the memory cell, the operation control circuit 210 may latch the command address CA for selecting the memory cell. The operation control circuit 210 may generate a latch row address ( Figure 4 RLA<1:M> in the Figure 4 After the ECS operation starts, the operation control circuit 210 can respectively latch the row address ( Figure 4 RLA<1:M> in the Figure 4 CLA<1:N> in the byte array generates the row address ( Figure 2 RAD<1:M>) and column address ( Figure 2 CAD<1:N> in ), and then generates row addresses that are counted sequentially ( Figure 2 RAD<1:M>) and column address ( Figure 2 CAD<1:N> in the table.

[0038] After the ECS operation starts, the ECS control circuit 230 can correct the Figure 2RAD<1:M>) and column address ( Figure 2 CAD<1:N> in the selected memory cell ( Figure 8 Internal data output by MC in Figure 2 The error in ID<1:128>) can be output, and the corrected internal data ( Figure 2 ID<1:128> in order to store the internal data again in the memory cell ( Figure 8 MC in ).

[0039] After the read operation of the normal operation based on the chip selection signal CS and the command address CA starts, when the memory cell ( Figure 8 Internal data output by MC in Figure 2 When an error occurs in ID<1:128> in the address field, the semiconductor device 20 can generate a latch row address ( Figure 4 RLA<1:M> in the Figure 4 The semiconductor device 20 can latch the row address ( Figure 4 RLA<1:M> in the Figure 4 CLA<1:N> in the READ_SRC) to determine the priority of ECS operations for multiple memory cells, which can correct internal data ( Figure 2 After the read operation based on the chip selection signal CS and the command address CA is started, the semiconductor device 20 can correct the error of the row address ( Figure 2 RAD<1:M>) and column address ( Figure 2 CAD<1:N> in the selected memory cell ( Figure 8 Internal data output by MC in Figure 2 After the write operation based on the chip selection signal CS and the command address CA is started, the semiconductor device 20 can output the internal data ( Figure 2 ID<1:128>) is stored in multiple memory cells by row address ( Figure 2 RAD<1:M>) and column address ( Figure 2 CAD<1:N> in the selected memory cell ( Figure 8 MC in ).

[0040] Figure 22 is a block diagram showing a configuration according to an embodiment of a semiconductor device 20 included in a semiconductor system 1. The semiconductor device 20 may include an operation control circuit (OP CTR) 210, a memory circuit (MEM CT) 220, an ECS control circuit (ECSCTR) 230, and a data input-output circuit (Data I / O) 240.

[0041] The operation control circuit 210 may generate an activation command ACT, a read command RD, a write command WT, and a precharge command PCG based on the chip selection signal CS and the first to fourth command addresses CA<1:4> in synchronization with the clock CLK. The operation control circuit 210 may generate an activation command ACT in synchronization with the clock CLK, and the activation command is enabled when the chip selection signal CS and the first to fourth command addresses CA<1:4> both have a logic level combination for an activation operation. The operation control circuit 210 may generate a read command RD in synchronization with the clock CLK, and the read command RD is enabled when the chip selection signal CS and the first to fourth command addresses CA<1:4> both have a logic level combination for a read operation of a normal operation and a read operation of an ECS operation. The operation control circuit 210 may generate a write command WT in synchronization with the clock CLK, and the write command WT is enabled when the chip selection signal CS and the first to fourth command addresses CA<1:4> both have a logic level combination for a write operation of a normal operation and a write operation of an ECS operation. The operation control circuit 210 may generate a precharge command PCG in synchronization with the clock CLK, and the precharge command PCG is enabled when the chip selection signal CS and the first to fourth command addresses CA<1:4> all have a logic level combination for a precharge operation. The first to fourth command addresses CA<1:4> may be set as a first group of command addresses. In an embodiment, the first to Nth command addresses CAD<1:N> may include a first group of command addresses including the first to fourth command addresses CA<1:4>.

[0042] The activation operation may be set to an operation of activating a plurality of word lines included in the storage circuit 220 before performing the read operation and the write operation. The read operation of the normal operation may be set to an operation for outputting the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8> that have been stored in the storage circuit 220. The write operation of the normal operation may be set to an operation for storing the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8> in the storage circuit 220. The read operation of the ECS operation may be set to an operation for outputting the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8> that have been stored in the storage circuit 220. The write operation of the ECS operation may be set to an operation for storing the first to 128th internal data ID<1:128> after error correction in the same storage unit of the storage circuit 220 based on the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8>, from which the first to 128th internal data ID<1:128> have been output after the start of the read operation of the ECS operation. The read operation of the ECS operation and the write operation of the ECS operation may be performed continuously. The precharge operation may be set to a common precharge operation.

[0043] After the read operation and write operation of the normal operation start, the operation control circuit 210 may generate the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> based on the fifth to Lth command addresses CA<5:L>. When the error flag signal EF is enabled to a logic high level after the read operation of the normal operation starts, the operation control circuit 210 may latch the fifth to Lth command addresses CA<5:L>. Depending on the logic level of the error flag signal EF after the ECS operation starts, the operation control circuit 210 may generate the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> based on the fifth to Lth command addresses CA<5:L>. The operation control circuit 210 may generate the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> based on the fifth to Lth command addresses CA<5:L> that have been latched during the interval in which the error flag signal EF is enabled to a logic high level after the ECS operation starts. The operation control circuit 210 may generate the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> sequentially counted during an interval in which the error flag signal EF is disabled as a logic low level after the ECS operation starts. The fifth to Lth command addresses CA<5:L> may be set as the second group command addresses.

[0044] The storage circuit 220 may include a first storage matrix to a sixteenth storage matrix (mat) ( Figure 8 223_1 to 223_16) and the error storage area ( Figure 8 223_17 in). The first to sixteenth storage matrices ( Figure 8 Each of 223_1 to 223_16) may include a plurality of word lines ( Fig. 9 WL <1> To WL <m>) and multiple bit lines ( Fig. 9 Yi<1> to Yi<N) in, and may include connected to multiple word lines ( Fig. 9 WL<1> to WL in <m>) and multiple column lines ( Fig. 9 Yi <1> To Yi <n>) of multiple storage units ( Figure 8 MC in).

[0045] When the active command ACT is enabled, the storage circuit 220 may perform operations for activating a plurality of word lines ( Fig. 9 WL <1> To WL <m>) activation operation. When the read command RD is enabled after the read operation of the normal operation starts, the storage circuit 220 can output the data stored in the plurality of storage cells ( Figure 8 The storage circuit 220 stores the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8> in the storage cells selected by the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> in the MC of the storage circuit 220. When the write command WT is enabled after the write operation of the normal operation starts, the storage circuit 220 can store the first to 128th internal data ID<1:128> in the plurality of storage cells ( Figure 8 The storage circuit 220 can output the data stored in the plurality of storage cells (MC in ) selected by the first to M-th row addresses RAD<1:M> and the first to N-th column addresses CAD<1:N>. When the read command RD is enabled after the read operation of the ECS operation starts, the storage circuit 220 can output the data stored in the plurality of storage cells ( Figure 8 The storage circuit 220 stores the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8> in the storage cells selected by the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> in the MC of the ECS operation. When the write command WT is enabled after the write operation of the ECS operation starts, the storage circuit 220 can store the first to 128th internal data ID<1:128> that have been corrected in the plurality of storage cells ( Fig. 9 The memory circuit 220 may store memory cells selected by the first to M-th row addresses RAD<1:M> and the first to N-th column addresses CAD<1:N> in the MC of FIG. 2. When the precharge command PCG is enabled, the memory circuit 220 may perform a precharge operation.

[0046] After the read operation of the normal operation starts, the ECS control circuit 230 may correct the error of the first to 128th internal data ID<1:128> based on the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8>. After the read operation of the normal operation starts, the ECS control circuit 230 may output the first to 128th internal data ID<1:128> that have been corrected to the data input-output circuit 240. After the write operation of the normal operation starts, the ECS control circuit 230 may output the first to 128th internal data ID<1:128> generated from the first to 128th data DATA<1:128> to the storage circuit 220. After the write operation of the normal operation starts, the ECS control circuit 230 may output the first to eighth internal parity IP<1:8> generated by performing the ECC encoding operation on the first to 128th internal data ID<1:128>, which are generated from the first to 128th data DATA<1:128>, to the storage circuit 220. After the read operation of the ECS operation starts, the ECS control circuit 230 may correct errors of the first to 128th internal data ID<1:128> based on the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8>. After the write operation of the ECS operation starts, the ECS control circuit 230 may output the first to 128th internal data ID<1:128> that have been corrected to the storage circuit 220 so that the first to 128th internal data ID<1:128> that have been corrected are stored again in the storage unit ( Figure 8 MC in ).

[0047] The ECS control circuit 230 may generate an error flag signal EF which is enabled to a logic high level when an error occurs in the first to 128th internal data ID<1:128> after the start of a read operation of a normal operation. After the start of a write operation of an ECS operation, the ECS control circuit 230 may correct the error of the first to 128th internal data ID<1:128>, store the corrected first to 128th internal data ID<1:128> again in the storage circuit 220, and generate the error flag signal EF which is disabled to a logic low level.

[0048] After the read operation of the normal operation starts, the data input-output circuit 240 can output the first to 128th internal data ID<1:128> that have been corrected as the first to 128th data DATA<1:128>. After the write operation of the normal operation starts, the data input-output circuit 240 can output the first to 128th data DATA<1:128> as the first to 128th internal data ID<1:128>.

[0049] After a read operation in a normal operation based on the chip selection signal CS and the first to Lth command addresses CA<1:L> is started, a memory cell ( Figure 8 When an error occurs in the first to 128th internal data ID<1:128> output by the MC in the semiconductor device 20, the semiconductor device 20 can generate the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> by latching the fifth to Lth command addresses CA<5:L>. The semiconductor device 20 can determine the priority of ECS operations of multiple storage cells based on the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N>, can correct the errors of the first to 128th internal data ID<1:128>, and can store the corrected first to 128th internal data ID<1:128> in the same storage cell. The priority of the ECS operation can mean that the correction of the errors already stored in multiple storage cells ( Figure 8 The semiconductor device 20 may correct the error of the first to 128th internal data ID<1:128> in the memory cells selected by the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> (the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> are generated from the fifth to Lth command addresses CA<5:L> that have been latched) from among the plurality of memory cells, and store the first to 128th internal data ID<1:128> again after the error of the first to 128th internal data ID<1:128> that have been stored by sequentially activating the plurality of memory cells and store the first to 128th internal data ID<1:128> again after the read operation of the normal operation based on the chip select signal CS and the first to Lth command addresses CA<1:L> is started. Figure 8 The semiconductor device 20 may correct the error of the first to 128th internal data ID<1:128> outputted from the chip select signal MC in ... Figure 8 MC in ).

[0050] Figure 3 is a block diagram showing a configuration according to an embodiment of an operation control circuit 210 included in a semiconductor device 20. The operation control circuit 210 may include a reference voltage generation circuit (VREF GEN) 211, an input circuit 212, a command decoder (CMD DEC) 213, and an address generation circuit 214.

[0051] The reference voltage generating circuit 211 may generate a reference voltage VREF having a constant voltage level. The reference voltage generating circuit 211 may generate a reference voltage VREF having a voltage level that is half of each of a logic high level and a logic low level in order to detect the logic levels of the chip selection signal CS and the first to Lth command addresses CA<1:L>. The reference voltage generating circuit 211 may be implemented as a voltage generating circuit having a constant voltage level even if precession, voltage, and temperature change.

[0052] The input circuit 212 may include a first receiver (first RX) 212_1 and a second receiver (second RX) 212_2. The first receiver 212_1 may generate an internal chip select signal ICS by comparing a chip select signal CS and a reference voltage VREF in synchronization with a rising edge of a clock CLK. The first receiver 212_1 may be implemented as a differential amplifier circuit and may generate an internal chip select signal ICS by detecting and amplifying a difference between a voltage level of the chip select signal CS and a reference voltage VREF.

[0053] The second receiver 212_2 may generate the first to Lth internal command addresses ICA<1:L> by comparing the first to Lth command addresses CA<1:L> and the reference voltage VREF in synchronization with the rising edge of the clock CLK. The second receiver 212_2 may generate the first group internal command addresses ICA<1:4> by comparing the first group command addresses CA<1:4> and the reference voltage VREF in synchronization with the rising edge of the clock CLK. The second receiver 212_2 may generate the second group internal command addresses ICA<5:L> by comparing the second group command addresses CA<5:L> and the reference voltage VREF in synchronization with the rising edge of the clock CLK. The second receiver 212_2 may be implemented as a differential amplifier circuit and may generate the first to Lth internal command addresses ICA<1:L> by detecting and amplifying the difference between the voltage levels of the first to Lth command addresses CA<1:L> and the reference voltage VREF. The second receiver 212_2 has been shown as only one circuit, but may be implemented as “L” differential amplification circuits corresponding to the number of bits of the first to Lth command addresses CA<1:L>.

[0054] The command decoder 213 may generate an activation command ACT for performing an activation operation by decoding the internal chip selection signal ICS and the first group of internal command addresses ICA<1:4>. The command decoder 213 may generate a read command RD for performing a read operation of a normal operation and a read operation of an ECS operation by decoding the internal chip selection signal ICS and the first group of internal command addresses ICA<1:4>. The command decoder 213 may generate a write command WT for performing a write operation of a normal operation and a write operation of an ECS operation by decoding the internal chip selection signal ICS and the first group of internal command addresses ICA<1:4>. The command decoder 213 may generate a precharge command PCG for performing a precharge operation by decoding the internal chip selection signal ICS and the first group of internal command addresses ICA<1:4>. The command decoder 213 may generate an ECS command ECS for performing an ECS operation by decoding the internal chip selection signal ICS and the first group of internal command addresses ICA<1:4>.

[0055] The address generation circuit 214 may include an error address generation circuit (EAD GEN) 214_1 and an address selection circuit (ADD SEL) 214_2 .

[0056] The error address generation circuit 214_1 may latch the second group internal command address ICA<5:L> during an interval in which the error flag signal EF is enabled to a logic high level. The error address generation circuit 214_1 may generate first to M-th error row addresses ERAD<1:M> and first to N-th error column addresses ECAD<1:N> from the latched second group internal command address ICA<5:L>. The first to M-th error row addresses ERAD<1:M> may be generated by some bits of the second group internal command address ICA<5:L>. The first to N-th error column addresses ECAD<1:N> may be generated by some bits of the second group internal command address ICA<5:L>. The error address generation circuit 214_1 may generate first to M-th error row addresses ERAD<1:M> and first to N-th error column addresses ECAD<1:N> that are sequentially counted during an interval in which the ECS command ECS is enabled to a logic high level and the error flag signal EF is disabled to a logic low level. The sum of the bit numbers of the first to Mth error row addresses ERAD<1:M> and the bit numbers of the first to Nth error column addresses ECAD<1:N> may be set to be the same as the bit number of the second group internal command address ICA<5:L>.

[0057] When the ECS command ECS is disabled to a logic low level, the address selection circuit 214_2 may generate the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> based on the second group internal command address ICA<5:L>. When the ECS command ECS is enabled to a logic high level, the address selection circuit 214_2 may generate the first to Mth row addresses RAD<1:M> based on the first to Mth error row addresses ERAD<1:M>. When the ECS command ECS is enabled to a logic high level, the address selection circuit 214_2 may generate the first to Nth column addresses CAD<1:N> based on the first to Nth error column addresses ECAD<1:N>. The sum of the number of bits of the first to Mth row addresses RAD<1:M> and the number of bits of the first to Nth column addresses CAD<1:N> may be set to be the same as the number of bits of the second group internal command address ICA<5:L>.

[0058] When the ECS command ECS is disabled to a logic low level, the address generation circuit 214 may generate first to M-th row addresses RAD<1:M> and first to N-th column addresses CAD<1:N> based on the second group internal command address ICA<5:L>. When the error flag signal EF is enabled to a logic high level, the address generation circuit 214 may latch the second group internal command address ICA<5:L>. During an interval in which the ECS command ECS is enabled to a logic high level and the error flag signal EF is enabled to a logic high level, the address generation circuit 214 may generate first to M-th row addresses RAD<1:M> and first to N-th column addresses CAD<1:N> based on the latched second group internal command address ICA<5:L>. During an interval in which the ECS command ECS is enabled to a logic high level and the error flag signal EF is enabled to a logic low level, the address generation circuit 214 may generate first to Mth row addresses RAD<1:M> and first to Nth column addresses CAD<1:N> that are counted sequentially.

[0059] Figure 4 is a block diagram showing a configuration according to an embodiment of an error address generation circuit 214_1 included in the address generation circuit 214. The error address generation circuit 214_1 may include a counting circuit (CNT) 311, a latch circuit (LAT) 312, and a selection transfer circuit (SEL TR) 313.

[0060] When the ECS command ECS is enabled to a logic high level, the counting circuit 311 may generate the first to Mth row counting signals RCNT<1:M> and the first to Nth column counting signals CCNT<1:N> that are sequentially counted. For example, when the ECS command ECS is enabled to a logic high level, the counting circuit 311 may generate the first to Mth row counting signals RCNT<1:M> and the first to Nth column counting signals CCNT<1:N> that are sequentially counted. <1> The counting circuit 311 generates the first to Nth column counting signals CCNT<1:N> which are counted sequentially during the activated interval. When the ECS command ECS is enabled to a logic high level, the counting circuit 311 can generate the first to Nth column counting signals CCNT<1:N> which are counted sequentially. <n>After being activated and until the Nth column count signal CCNT <n>The second row counting signal RCNT is activated only when it is activated <2> To generate the second row count signal RCNT <2> When the ECS command ECS is enabled to a logic high level, the counting circuit 311 can count the signal RCNT in the Mth row. <m>After being activated and until the Mth row count signal RCNT <m>is activated and until the Nth column count signal CCNT <n>When activated, the first to M-th row counting signals RCNT<1:M> and the first to N-th column counting signals CCNT<1:N>, each having a logic low level, are generated.

[0061] During the interval in which the error flag signal EF is enabled to a logic high level, the latch circuit 312 may generate the first to Mth latch row addresses RLA<1:M> and the first to Nth latch column addresses CLA<1:N> by latching the second group internal command address ICA<5:L>. The first to Mth latch row addresses RLA<1:M> may be generated by some bits of the second group internal command address ICA<5:L>. The first to Nth latch column addresses CLA<1:N> may be generated by some bits of the second group internal command address ICA<5:L>. The sum of the number of bits of the first to Mth latch row addresses RLA<1:M> and the number of bits of the first to Nth latch column addresses CLA<1:N> may be set to be the same as the number of bits of the second group internal command address ICA<5:L>.

[0062] During the interval when the error flag signal EF is enabled to a logic high level, the selection transfer circuit 313 may output the first to M-th latch row addresses RLA<1:M> as the first to M-th error row addresses ERAD<1:M>. During the interval when the error flag signal EF is enabled to a logic high level, the selection transfer circuit 313 may output the first to N-th latch column addresses CLA<1:N> as the first to N-th error column addresses ECAD<1:N>. During the interval when the error flag signal EF is disabled to a logic low level, the selection transfer circuit 313 may output the first to M-th row count signals RCNT<1:M> as the first to M-th error row addresses ERAD<1:M>. During the interval when the error flag signal EF is disabled to a logic low level, the selection transfer circuit 313 may output the first to N-th column count signals CCNT<1:N> as the first to N-th error column addresses ECAD<1:N>.

[0063] Figure 5 2 is a block diagram showing a configuration according to an embodiment of a selection transfer circuit 313 included in an error address generation circuit 214_1. The selection transfer circuit 313 may include a first multiplexer 313_1 and a second multiplexer 313_2.

[0064] During an interval in which the error flag signal EF is enabled to a logic high level, the first multiplexer 313_1 may output the first to Mth latch row addresses RLA<1:M> as the first to Mth error row addresses ERAD<1:M>. During an interval in which the error flag signal EF is disabled to a logic low level, the first multiplexer 313_1 may output the first to Mth row counting signals RCNT<1:M> as the first to Mth error row addresses ERAD<1:M>.

[0065] During the interval when the error flag signal EF is enabled to a logic high level, the second multiplexer 313_2 may output the first to Nth latch column addresses CLA<1:N> as the first to Nth error column addresses ECAD<1:N>. During the interval when the error flag signal EF is disabled to a logic low level, the second multiplexer 313_2 may output the first to Nth column counting signals CCNT<1:N> as the first to Nth error column addresses ECAD<1:N>.

[0066] Figure 6 2 is a block diagram showing a configuration according to an embodiment of an address selection circuit 214_2 included in the address generation circuit 214. The address selection circuit 214_2 may include a third multiplexer 321 and a fourth multiplexer 322.

[0067] During the interval in which the ECS command ECS is enabled to a logic high level, the third multiplexer 321 may output the first to M-th error row addresses ERAD<1:M> as the first to M-th row addresses RAD<1:M>. During the interval in which the ECS command ECS is disabled to a logic low level, the third multiplexer 321 may output some bits of the second group internal command address ICA<5:L> as the first to M-th row addresses RAD<1:M>. Some bits of the second group internal command address ICA<5:L> for generating the first to M-th row addresses RAD<1:M> may be set to "M" bits.

[0068] During the interval in which the ECS command ECS is enabled to a logic high level, the fourth multiplexer 322 may output the first to Nth error column addresses ECAD<1:N> as the first to Nth column addresses CAD<1:N>. During the interval in which the ECS command ECS is disabled to a logic low level, the fourth multiplexer 322 may output the remaining bits of the second group of internal command addresses ICA<5:L> as the first to Nth column addresses CAD<1:N>. The remaining bits of the second group of internal command addresses ICA<5:L> used to generate the first to Nth column addresses CAD<1:N> may be set to "N" bits. The remaining bits of the second group of internal command addresses ICA<5:L> used to generate the first to Nth column addresses CAD<1:N> may be set to be different from some bits of the second group of internal command addresses ICA<5:L> used to generate the first to Mth row addresses RAD<1:M>.

[0069] Figure 7 2 is a block diagram showing a configuration according to an embodiment of a memory circuit 220 included in a semiconductor device 20. The memory circuit 220 may include a row control circuit (ROW CTR) 221, a column control circuit (COL CTR) 222, and a core circuit (CORECT) 223.

[0070] When the active command ACT is enabled, the row control circuit 221 may activate the first word line WL based on the first to Mth row addresses RAD<1:M>. <1> To the Mth word line WL <m>When the read command RD is enabled after the read operation of the normal operation and the read operation of the ECS operation start, the row control circuit 221 may activate the first word line WL based on the first to Mth row addresses RAD<1:M>. <1> To the Mth word line WL <m>When the write command WT is enabled after the write operation of the normal operation and the write operation of the ECS operation start, the row control circuit 221 may activate the first word line WL based on the first to Mth row addresses RAD<1:M>. <1> To the Mth word line WL <m>Any one of .

[0071] When the read command RD is enabled after the read operation of the normal operation and the read operation of the ECS operation start, the column control circuit 222 may activate the first column line Yi based on the first to Nth column addresses CAD<1:N>. <1> To the Nth column line Yi <n>When the write command WT is enabled after the write operation of the normal operation and the write operation of the ECS operation start, the column control circuit 222 may activate the first column line Yi based on the first to Nth column addresses CAD<1:N>. <1> To the Nth column line Yi <n>When the precharge command PCG is enabled after the precharge operation starts, the column control circuit 222 may perform the precharge operation.

[0072] The core circuit 223 may include first to sixteenth storage matrices ( Figure 8 223_1 to 223_16) and the error storage area ( Figure 8 223_17 in the figure). After the read operation of the normal operation and the read operation of the ECS operation start, the core circuit 223 can output the data stored in the first word line WL <1> To the Mth word line WL <m>The activated word line and the first column line Yi <1> To the Nth column line Yi <n>The memory cell connected to the activated bit line ( Figure 8 After the read operation of the normal operation and the read operation of the ECS operation start, the core circuit 223 can output the first to 128th internal data ID<1:128> stored in the first word line WL <1> To the Mth word line WL <m>The activated word line and the first column line Yi <1> To the Nth column line Yi <n>The faulty cell connected to the activated bit line ( Figure 8 After the write operation of the normal operation and the write operation of the ECS operation start, the core circuit 223 can store the first to 128th internal data ID<1:128> in the first word line WL <1> To the Mth word line WL <m>The activated word line and the first column line Yi <1> To the Nth column line Yi <n>The memory cell connected to the activated bit line ( Figure 8 The first to eighth internal parities IP<1:8> may be set as signals generated by performing an ECC encoding operation on the first to 128th internal data ID<1:128> input after the write operation of the normal operation starts.

[0073] Figure 8 2 is a block diagram showing a configuration according to an embodiment of a core circuit 223 included in a memory circuit 220. The core circuit 223 may include first to sixteenth memory matrices 223_1 to 223_16 and an error storage area 233_17.

[0074] Each of the first to sixteenth storage matrices 223_1 to 223_16 may include first to M-th word lines ( Fig. 9 WL <1> To WL <m>) and the first column line to the Nth column line ( Fig. 9 Yi <1> To Yi <n>), and may include first to M-th word lines ( Fig. 9 WL <1> To WL <m>) and the first column line to the Nth column line ( Fig. 9 Yi <1> To Yi <n>) are connected to multiple storage cells MC.

[0075] After the read operation of the normal operation and the read operation of the ECS operation start, the first storage matrix 223_1 may output the data stored in the first word line WL <1> To the Mth word line WL <m>The activated word line and the first column line Yi <1> To the Nth column line Yi <n>The first to eighth internal data ID<1:8> in the memory cells MC connected to the activated bit lines among them. After the read operation of the normal operation and the read operation of the ECS operation start, the second memory matrix 223_2 can output the data stored in the first word line WL <1> To the Mth word line WL <m>The activated word line and the first column line Yi <1> To the Nth column line Yi <n>The 9th to 16th internal data ID<9:16> in the memory cells MC connected to the activated bit lines.

[0076] After the write operation of the normal operation and the write operation of the ECS operation start, the first memory matrix 223_1 may store the first to eighth internal data ID<1:8> in the memory corresponding to the first word line WL <1> To the Mth word line WL <m>The activated word line and the first column line Yi <1> To the Nth column line Yi <n>After the write operation of the normal operation and the write operation of the ECS operation start, the second memory matrix 223_2 may store the 9th to 16th internal data ID<9:16> in the memory cells MC connected to the first word line WL <1> To the Mth word line WL <m>The activated word line and the first column line Yi <1> To the Nth column line Yi <n>Among them, the memory cell MC is connected to the activated bit line.

[0077] The third storage matrix 223_3 to the sixteenth storage matrix 223_16 can be implemented to have the same construction as each of the first storage matrix 223_1 and the second storage matrix 223_2, and can perform the same operation as each of the first storage matrix 223_1 and the second storage matrix 223_2, except that only the bits of the internal data are input and output, so the detailed description thereof is omitted. The first storage matrix 223_1 to the sixteenth storage matrix 223_16 can input and output 8 bits of internal data.

[0078] The error storage area 223_17 may include the first word line to the Mth word line ( Fig. 9 WL <1> To WL <m>) and the first column line to the Nth column line ( Fig. 9 Yi<1> to Yi<N) in, and may include connected to the first to the Mth word line ( Fig. 9 WL<1> to WL in <m>) and the first to Nth column lines ( Fig. 9 Yi <1> To Yi <n>) of multiple error units EC.

[0079] After the read operation of the normal operation and the read operation of the ECS operation start, the error storage area 223_17 may output the data stored in the first word line WL <1> To the Mth word line WL <m>The activated word line and the first column line Yi <1> To the Nth column line Yi <n>The first to eighth internal parities IP<1:8> in the error cells EC to which the activated bit lines are connected.

[0080] After a write operation of a normal operation starts, the error storage area 223_17 may store the first to eighth internal parities IP<1:8> on the first word line WL <1> To the Mth word line WL <m>The activated word line and the first column line Yi <1> To the Nth column line Yi <n>The activated bit line is connected to the error cell EC.

[0081] The error storage area 223_17 can be implemented to have the same construction as each of the first storage matrix 223_1 to the sixteenth storage matrix 223_16 and can perform the same operation as each of the first storage matrix 223_1 to the sixteenth storage matrix 223_16, except that, unlike each of the first storage matrix 223_1 to the sixteenth storage matrix 223_16, the error storage area 223_17 only inputs and outputs internal parity instead of internal data, so its detailed description is omitted.

[0082] Fig. 9 is a diagram showing a configuration according to an embodiment of a first memory matrix 223_1 included in the core circuit 223 .

[0083] The first memory matrix 223_1 may include first word lines WL <1> To the Mth word line WL <m>And the first line Yi <1> To the Nth column line Yi <n>The first memory matrix 223_1 may include a plurality of memory cells MC, at which the first word line WL <1> To the Mth word line WL <m>And the first line Yi <1> To the Nth column line Yi <n>intersects and the memory cell MC is connected to the first word line WL <1> To the Mth word line WL <m>and the first line Yi <1> To the Nth column line Yi <n>.

[0084] The first word line WL of the first storage matrix 223_1 <1> To the Mth word line WL <m>Any one of the first to M-th row addresses RAD<1:M> can be activated. The first column line Yi of the first memory matrix 223_1 <1> To the Nth column line Yi <n>Any one of the first to N-th column addresses CAD<1:N> may be activated.

[0085] After a read operation of a normal operation starts, the first memory matrix 223_1 may output the first to eighth internal data ID<1:8> that have been stored in the memory cells MC connected to the activated word lines and the activated column lines. After a write operation of a normal operation starts, the first memory matrix 223_1 may store the first to eighth internal data ID<1:8> in the memory cells MC connected to the activated word lines and the activated column lines.

[0086] After the read operation of the ECS operation starts, the first memory matrix 223_1 may output the 1st to 8th internal data ID<1:8> stored in the memory cells MC connected to the activated word lines and the activated column lines. After the write operation of the ECS operation starts, the first memory matrix 223_1 may store the 1st to 8th internal data ID<1:8> in the memory cells MC connected to the activated word lines and the activated column lines.

[0087] After the precharge operation starts, the first memory matrix 223_1 may perform a precharge operation.

[0088] The second to sixteenth storage matrices 223_2 to 223_16 may be implemented to have the same construction as the first storage matrix 223_1 and may perform the same operation as the first storage matrix 223_1, except that only the bits of the internal data are input and output, and thus their detailed descriptions are omitted. The error storage area 223_17 may be implemented to have the same construction as the first storage matrix 223_1 and may perform the same operation as the first storage matrix 223_1, except that, unlike the first storage matrix 223_1, the error storage area 223_17 only inputs and outputs the internal parity instead of the internal data, and thus their detailed descriptions are omitted.

[0089] Fig.10 2 is a block diagram showing a configuration according to an embodiment in which an ECS control circuit 230 included in a semiconductor device 20 performs a normal operation and a read operation of an ECS operation. The ECS control circuit 230 may include a delay circuit (DLY) 231, a transmission data generation circuit (TD GEN) 232, an error correction circuit 233, and an error flag signal generation circuit (EFGEN) 234.

[0090] The delay circuit 231 may generate the read delay signal DRD by delaying the read command RD by as much time as it takes to output all the first to 128th internal data ID<1:128> from the memory circuit 220 .

[0091] The transmission data generation circuit 232 may generate the first to 128th transmission data TD<1:128> by buffering the first to 128th internal data ID<1:128> output from the storage circuit 220 after the start of the read operation of the normal operation. The transmission data generation circuit 232 may generate the first to 128th transmission data TD<1:128> by buffering the first to 128th internal data ID<1:128> output from the storage circuit 220 after the start of the read operation of the ECS operation. The transmission data generation circuit 232 may be implemented to output the first to 128th internal data ID<1:128> to the storage circuit 220, the first to 128th internal data ID<1:128> being generated from the first to 128th data DATA<1:128> input after the start of the write operation of the normal operation.

[0092] The error correction circuit 233 may include an operation parity generation circuit (CP GEN) 233_1 , a syndrome generation circuit (SYN GEN) 233_2 , an error correction signal generation circuit (CR GEN) 233_3 , and an error processing circuit (ER PRC) 233_4 .

[0093] When the read delay signal DRD is enabled to a logic high level, the operation parity generation circuit 233_1 may generate the first to eighth operation parities CP<1:8> including information about errors of the first to 128th transmission data TD<1:128>. When the read delay signal DRD is enabled to a logic high level, the operation parity generation circuit 233_1 may generate the first to eighth operation parities CP<1:8> based on the first to 128th transmission data TD<1:128>. After the read operation of the normal operation starts, the operation parity generation circuit 233_1 may generate the first to eighth operation parities CP<1:8> by performing an ECC encoding operation based on the first to 128th transmission data TD<1:128>. After the read operation of the ECS operation starts, the operation parity generation circuit 233_1 may generate the first to eighth operation parities CP<1:8> by performing an ECC encoding operation on the first to 128th transmission data TD<1:128>. The operation parity generation circuit 233_1 may be implemented to generate first to eighth internal parity IP<1:8> by performing an ECC encoding operation on the first to 128th internal data ID<1:128>, which are generated from the 1st to 128th data DATA<1:128> input after the start of the write operation of the normal operation. The operation parity generation circuit 233_1 may be implemented to output the first to eighth internal parity IP<1:8> to the storage circuit 220 after the start of the write operation of the normal operation.

[0094] The ECC encoding operation may be set as an operation in which a common error correction circuit compares bits of data by using an error correction code (ECC) and generates parity bits based on the comparison result.

[0095] After the read operation of the normal operation starts, the syndrome generation circuit 233_2 can generate the first to eighth syndromes SYN<1:8> by comparing the first to eighth operation parities CP<1:8> and the first to eighth internal parities IP<1:8>. After the read operation of the ECS operation starts, the syndrome generation circuit 233_2 can generate the first to eighth syndromes SYN<1:8> by comparing the first to eighth operation parities CP<1:8> and the first to eighth internal parities IP<1:8>.

[0096] The error correction signal generation circuit 233_3 may generate first to 128th error correction signals CR<1:128> by performing an ECC decoding operation on the first to eighth syndromes SYN<1:8>.

[0097] The ECC decoding operation may be set as an operation in which a common error correction circuit generates syndrome bits by comparing parity bits of data generated in the ECC encoding operation with parity bits generated by using ECC at a previous timing and corrects errors contained in data by decoding the syndrome bits.

[0098] The error processing circuit 233_4 may correct the error of the first to 128th transmission data TD<1:128> based on the first to 128th error correction signals CR<1:128>, and may output the error-corrected first to 128th transmission data TD<1:128> as the first to 128th internal data ID<1:128>. After the read operation of the normal operation starts, the error processing circuit 233_4 may output the error-corrected first to 128th internal data ID<1:128> to the data input-output circuit 240. After the write operation of the ECS operation starts, the error processing circuit 233_4 may output the error-corrected first to 128th internal data ID<1:128> to the storage circuit 220.

[0099] When the read delay signal DRD is enabled, the error correction circuit 233 may detect an error of the first to 128th transmission data TD<1:128>, may correct the error of the first to 128th transmission data TD<1:128>, and may output the error-corrected first to 128th transmission data TD<1:128> as the first to 128th internal data ID<1:128>. When the read delay signal DRD is enabled, the error correction circuit 233 may correct the error of the first to 128th transmission data TD<1:128> by performing an ECC encoding operation and an ECC decoding operation on the first to 128th transmission data TD<1:128>, and may output the error-corrected first to 128th transmission data TD<1:128> as the first to 128th internal data ID<1:128>. After the read operation of the normal operation starts, the error correction circuit 233 may output the error-corrected first to 128th internal data ID<1:128> to the data input-output circuit 240. After the write operation of the ECS operation starts, the error correction circuit 233 may output the error-corrected first to 128th internal data ID<1:128> to the memory circuit 220 .

[0100] The error flag signal generating circuit 234 may generate an enabled error flag signal EF based on the first to 128th error correction signals CR<1:128>. When at least any one of the first to 128th error correction signals CR<1:128> is generated to have a logic high level, the error flag signal generating circuit 234 may generate the error flag signal EF enabled to a logic high level. The error flag signal generating circuit 234 may correct the error of the first to 128th internal data ID<1:128>, may store the corrected first to 128th internal data ID<1:128> again, and then may generate the error flag signal EF disabled to a logic low level.

[0101] Fig.11 is a diagram for describing a read operation of a semiconductor device according to an embodiment of the present disclosure. Fig.11 The read operation of the semiconductor device 20 according to the embodiment of the present disclosure is described. In this case, a case where an error occurs in the first to 128th internal data ID<1:128> can be described as an example as follows.

[0102] When the chip selection signal CS and the first group command address CA<1:4> both have a logic level combination for an activation operation, the operation control circuit 210 may generate an activation command ACT enabled to a logic high level in synchronization with the clock CLK. After a read operation of a normal operation starts, the operation control circuit 210 may generate first to M-th row addresses RAD<1:M> and first to N-th column addresses CAD<1:N> based on the first group command address CA<1:L>.

[0103] When the active command ACT is enabled, the storage circuit 220 may perform operations for activating a plurality of word lines ( Fig. 9 WL <1> To WL <m>) to activate any of them.

[0104] When the chip selection signal CS and the first group command address CA<1:4> both have a logic level combination for a read operation of a normal operation, the operation control circuit 210 may generate a read command RD enabled to a logic high level in synchronization with the clock CLK.

[0105] When the read command RD is enabled after the read operation of the normal operation starts, the storage circuit 220 may output the data stored in the plurality of storage cells ( Figure 8 In the MC in FIG. 1 , the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8> in the memory cells selected by the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> may cause an error ERROR in the first to 128th internal data ID<1:128>.

[0106] After the read operation of the normal operation starts, the ECS control circuit 230 may correct (error-correct) an error of the first to 128th internal data ID<1:128> based on the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8>. After the read operation of the normal operation starts, the ECS control circuit 230 may output the corrected first to 128th internal data ID<1:128> to the data input-output circuit 240. When an error occurs in the first to 128th internal data ID<1:128> after the read operation of the normal operation starts, the ECS control circuit 230 may generate an error flag signal EF enabled to a logic high level.

[0107] When the error flag signal EF is enabled to a logic high level after the read operation of the normal operation starts, the operation control circuit 210 can generate the first to Mth latch row addresses ( Figure 4 RLA<1:M> in ) and the first to Nth latch column addresses ( Figure 4 CLA<1:N> in the .

[0108] After the read operation of the normal operation starts, the data input-output circuit 240 may output the error-corrected first to 128th internal data ID<1:128> as the first to 128th data DATA<1:128>.

[0109] Fig.12 is a diagram for describing an ECS operation of a semiconductor device according to an embodiment of the present disclosure. Fig.12 The ECS operation of the semiconductor device 20 according to the embodiment of the present disclosure is described. In this case, a case where an error occurs in the first to 128th internal data ID<1:128> after the read operation of the normal operation starts may be described as an example as follows.

[0110] When the chip selection signal CS and the first group command address CA<1:4> both have a logic level combination for the activation operation, the operation control circuit 210 can generate an activation command ACT enabled to a logic high level in synchronization with the clock CLK. After the read operation of the ECS operation starts, the operation control circuit 210 can latch the first to M-th latch row addresses ( Figure 4 RLA<1:M> in ) and the first to Nth latch column addresses ( Figure 4 CLA<1:N> in the READ_WRITE_STORAGE_ENGINE(1) is used to generate the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N>.

[0111] When the active command ACT is enabled, the storage circuit 220 may perform operations for activating a plurality of word lines ( Fig. 9 WL <1> To WL <m>) to activate any of them.

[0112] When the chip selection signal CS and the first group command address CA<1:4> both have a logic level combination for a read operation of an ECS operation, the operation control circuit 210 may generate a read command RD enabled to a logic high level in synchronization with the clock CLK. When the chip selection signal CS and the first group command address CA<1:4> both have a logic level combination for a read operation of an ECS operation, the operation control circuit 210 may generate a write command WT disabled to a logic low level in synchronization with the clock CLK.

[0113] When the read command RD is enabled after the read operation of the ECS operation starts, the storage circuit 220 may output the data that have been stored in the plurality of storage cells ( Figure 8 In the MC in FIG. 1 , the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8> in the memory cells selected by the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> are displayed. At this time, an error may occur in the first to 128th internal data ID<1:128>.

[0114] After the read operation of the ECS operation starts, the ECS control circuit 230 may correct (error-correct) errors of the first to 128th internal data ID<1:128> based on the first to 128th internal data ID<1:128> and the first to eighth internal parities IP<1:8>.

[0115] When the chip selection signal CS and the first group command address CA<1:4> both have a logic level combination for a write operation of an ECS operation, the operation control circuit 210 may generate a write command WT enabled to a logic high level in synchronization with the clock CLK. When the chip selection signal CS and the first group command address CA<1:4> both have a logic level combination for a write operation of an ECS operation, the operation control circuit 210 may generate a read command RD disabled to a logic low level in synchronization with the clock CLK.

[0116] After the write operation of the ECS operation starts, the ECS control circuit 230 may output the error-corrected first to 128th internal data ID<1:128> to the storage circuit 220. After the write operation of the ECS operation starts, the ECS control circuit 230 may correct the error of the first to 128th internal data ID<1:128>, store the error-corrected first to 128th internal data ID<1:128> again in the storage circuit 220, and then generate the error flag signal EF disabled to a logic low level.

[0117] The operation control circuit 210 may generate a read command RD and a write command WT that are sequentially enabled so as to repeatedly perform a read operation and a write operation of the ECS operation. When the error flag signal EF is disabled as a logic low level, the operation control circuit 210 may generate first to Mth row addresses RAD<1:M> and first to Nth column addresses CAD<1:N> that are sequentially counted so as to repeatedly perform a read operation and a write operation of the ECS operation.

[0118] After the read operation of the ECS operation starts, the storage circuit 220 can output the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8> based on the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N>. After the write operation of the ECS operation starts, the storage circuit 220 can store the first to 128th internal data ID<1:128> that has been corrected based on the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N>.

[0119] After the read operation of the ECS operation starts, the ECS control circuit 230 can correct (error-correct) errors of the first to 128th internal data ID<1:128> based on the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8>. After the write operation of the ECS operation starts, the ECS control circuit 230 can output the corrected first to 128th internal data ID<1:128> to the storage circuit 220.

[0120] The semiconductor system 1 according to an embodiment of the present disclosure may set the priority of the ECS operation by latching the command address CA<5:L> when an error occurs in the first to 128th internal data ID<1:128> after the start of a read operation of a normal operation, preferentially performing the ECS operation on the memory cell corresponding to the latched command address CA<5:L> after the start of the ECS operation, and then sequentially performing the ECS operation on a plurality of memory cells. In an embodiment, the semiconductor system 1 may quickly correct the error of the first to 128th internal data ID<1:128> by latching the command address CA<5:L> when an error occurs in the first to 128th internal data ID<1:128> after the start of a read operation of a normal operation, preferentially performing the ECS operation on the memory cell corresponding to the latched command address CA<5:L> after the start of the ECS operation, and then sequentially performing the ECS operation on a plurality of memory cells.

[0121] Fig.13 is a timing diagram for describing a read operation of a semiconductor device according to an embodiment of the present disclosure. Fig.13 The read operation of the semiconductor device 20 according to the embodiment of the present disclosure will be described. In this case, a case where an error occurs in the first to 128th internal data ID<1:128> may be described as an example as follows.

[0122] At timing T1, the operation control circuit 210 may generate an activation command ACT with a logic high level for an activation operation by decoding the chip selection signal CS and the first group command address CA<1:4> in synchronization with the clock CLK. After the activation operation of the normal operation starts, the operation control circuit 210 may generate first to M-th row addresses RAD<1:M> and first to N-th column addresses CAD<1:N> based on the second group command address CA<5:L>.

[0123] When the active command ACT is enabled, the storage circuit 220 may perform operations for activating a plurality of word lines ( Fig. 9 WL <1> To WL <m>) to activate any of them.

[0124] At timing T2 , the operation control circuit 210 may generate a read command RD having a logic high level for a read operation of a normal operation by decoding the chip selection signal CS and the first group command address CA<1:4> in synchronization with the clock CLK.

[0125] At timing T3 , the delay circuit 231 of the ECS control circuit 230 may generate a read delay signal DRD having a logic high level by delaying the read command RD by as much time as it takes to output all of the first to 128th internal data ID<1:128> from the memory circuit 220 .

[0126] When the read command RD is enabled after the read operation of the normal operation starts, the storage circuit 220 may output the data that have been stored in the plurality of storage cells ( Figure 8 In the MC in FIG. 1 , the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8> in the memory cells selected by the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> are displayed. At this time, an error may occur in the first to 128th internal data ID<1:128>.

[0127] The transmission data generation circuit 232 of the ECS control circuit 230 may generate the first to 128th transmission data TD<1:128> by buffering the first to 128th internal data ID<1:128> output from the storage circuit 220 after the start of the read operation of the normal operation.

[0128] When the read delay signal DRD is enabled to a logic high level, the error correction circuit 233 of the ECS control circuit 230 may perform an ECC encoding operation and an ECC decoding operation on the first to 128th transfer data TD<1:128>.

[0129] At timing T4, the error correction circuit 233 of the ECS control circuit 230 may generate the first to 128th error correction signals CR<1:128> according to the ECC encoding operation and the ECC decoding operation on the first to 128th transmission data TD<1:128>. The error correction circuit 233 of the ECS control circuit 230 may generate the first to 128th internal data ID<1:128> by correcting the error of the first to 128th transmission data TD<1:128> based on the first to 128th error correction signals CR<1:128>. The error correction circuit 233 of the ECS control circuit 230 may output the first to 128th internal data ID<1:128> that have been corrected to the data input-output circuit 240.

[0130] When at least any one of the first to 128th error correction signals CR<1:128> is generated to have a logic high level, the error flag signal generation circuit 234 may generate the error flag signal EF enabled to a logic high level.

[0131] When the error flag signal EF is enabled to a logic high level after the read operation of the normal operation starts, the operation control circuit 210 can generate the first to Mth latch row addresses ( Figure 4 RLA<1:M> in ) and the first to Nth latch column addresses ( Figure 4 CLA<1:N> in the .

[0132] After the read operation of the normal operation starts, the data input-output circuit 240 may output the error-corrected first to 128th internal data ID<1:128> as the first to 128th data DATA<1:128>.

[0133] At timing T5 , the operation control circuit 210 may generate a precharge command PCG having a logic high level for a precharge operation by decoding the chip selection signal CS and the first group command address CA<1:4> in synchronization with the clock CLK.

[0134] When the precharge command PCG is enabled to a logic high level, the memory circuit 220 may perform a precharge operation.

[0135] Fig.14 is a timing diagram for describing the ECS operation of the semiconductor device according to an embodiment of the present disclosure. Fig.14 The ECS operation of the semiconductor device 20 according to the embodiment of the present disclosure is described. In this case, a case where an error occurs in the first to 128th internal data ID<1:128> after the read operation of the normal operation starts may be described as an example as follows.

[0136] At timing T11, the operation control circuit 210 may generate an activation command ACT with a logic high level for an activation operation by decoding the chip selection signal CS and the first group command address CA<1:4> in synchronization with the clock CLK. After the activation operation of the ECS operation starts, the operation control circuit 210 may generate first to M-th row addresses RAD<1:M> and first to N-th column addresses CAD<1:N> based on the second group command address CA<5:L>.

[0137] When the active command ACT is enabled, the storage circuit 220 may perform operations for activating a plurality of word lines ( Fig. 9 WL <1> To WL <m>) to activate any of them.

[0138] At timing T12 , the operation control circuit 210 may generate a read command RD having a logic high level for a read operation by decoding the chip selection signal CS and the first group of command addresses CA<1:4> in synchronization with the clock CLK.

[0139] At timing T13 , the delay circuit 231 of the ECS control circuit 230 may generate a read delay signal DRD having a logic high level by delaying the read command RD by as much time as it takes to output all of the first to 128th internal data ID<1:128> from the memory circuit 220 .

[0140] When the read command RD is enabled after the read operation of the ECS operation starts, the storage circuit 220 may output the data that have been stored in the plurality of storage cells ( Figure 8 In the MC in FIG. 1 , the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8> in the memory cells selected by the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> are displayed. At this time, an error may occur in the first to 128th internal data ID<1:128>.

[0141] The transmission data generation circuit 232 of the ECS control circuit 230 may generate the first to 128th transmission data TD<1:128> by buffering the first to 128th internal data ID<1:128> output from the storage circuit 220 after the read operation of the ECS operation starts.

[0142] When the read delay signal DRD is enabled to a logic high level, the error correction circuit 233 of the ECS control circuit 230 may perform an ECC encoding operation and an ECC decoding operation on the first to 128th transfer data TD<1:128>.

[0143] At timing T14, the error correction circuit 233 of the ECS control circuit 230 may generate the first to 128th error correction signals CR<1:128> according to the ECC encoding operation and the ECC decoding operation of the first to 128th transmission data TD<1:128>. The error correction circuit 233 of the ECS control circuit 230 may generate the first to 128th internal data ID<1:128> by correcting the error of the first to 128th transmission data TD<1:128> based on the first to 128th error correction signals CR<1:128>. The error correction circuit 233 of the ECS control circuit 230 may output the first to 128th internal data ID<1:128> that have been corrected to the storage circuit 220.

[0144] At timing T15 , the operation control circuit 210 may generate a write command WT having a logic high level for a write operation by decoding the chip selection signal CS and the first group command address CA<1:4> in synchronization with the clock CLK.

[0145] When the write command WT is enabled after the write operation of the ECS operation starts, the storage circuit 220 may store the first to 128th internal data ID<1:128> that have been corrected in the plurality of storage cells ( Figure 8 In this case, the memory cells (MC in ) in which the first to 128th internal data ID<1:128> having been corrected are stored are selected by the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N>. Figure 8 The MC in ( MC ) may be the same memory cell as the memory cell from which the first to 128th internal data ID<1:128> in which an error has occurred have been output after the read operation of the ECS operation starts.

[0146] The error flag signal generating circuit 234 may correct errors of the first to 128th internal data ID<1:128>, may store the corrected first to 128th internal data ID<1:128> again, and may generate an error flag signal EF disabled to a logic low level.

[0147] At timing T16 , the operation control circuit 210 may generate a precharge command PCG having a logic high level for a precharge operation by decoding the chip selection signal CS and the first group command address CA<1:4> in synchronization with the clock CLK.

[0148] When the precharge command PCG is enabled to a logic high level, the memory circuit 220 may perform a precharge operation.

[0149] Thereafter, the operation control circuit 210 may generate first to M-th row addresses RAD<1:M> and first to N-th column addresses CAD<1:N> that are sequentially counted after the ECS operation starts.

[0150] When the read command RD is enabled after the read operation of the ECS operation starts, the storage circuit 220 may output the data that have been stored in the plurality of storage cells ( Figure 8 The first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8> in the memory cells selected by the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> in MC).

[0151] After the read operation of the ECS operation starts, the ECS control circuit 230 may correct errors of the first to 128th internal data ID<1:128> based on the first to 128th internal data ID<1:128> and the first to eighth internal parities IP<1:8>.

[0152] After the write operation of the ECS operation starts, the ECS control circuit 230 may output the first to 128th internal data ID<1:128> that have been corrected to the storage circuit 220 so as to store the first to 128th internal data ID<1:128> that have been corrected to the storage unit ( Figure 8 MC in ).

[0153] When the write command WT is enabled after the write operation of the ECS operation starts, the storage circuit 220 may store the first to 128th internal data ID<1:128> that have been corrected in the plurality of storage cells ( Fig. 9 In the memory cells selected by the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> in MC).

[0154] The read and write operations of the ECS operation may be performed repeatedly until the correction has been stored in all storage cells ( Figure 8 until the operation of detecting the error in the internal data in the MC) and storing the corrected internal data again is completed.

[0155] The semiconductor system 1 according to an embodiment of the present disclosure may set the priority of the ECS operation by latching the command address CA<5:L> when an error occurs in the first to 128th internal data ID<1:128> after the start of a read operation of a normal operation, preferentially performing the ECS operation on the memory cell corresponding to the latched command address CA<5:L> after the start of the ECS operation, and then sequentially performing the ECS operation on a plurality of memory cells. In an embodiment, the semiconductor system 1 may quickly correct the error of the first to 128th internal data ID<1:128> by latching the command address CA<5:L> when an error occurs in the first to 128th internal data ID<1:128> after the start of a read operation of a normal operation, preferentially performing the ECS operation on the memory cell corresponding to the latched command address CA<5:L> after the start of the ECS operation, and then sequentially performing the ECS operation on a plurality of memory cells.

[0156] Fig.15 is a flowchart for describing an ECS method of a semiconductor system according to an embodiment of the present disclosure.

[0157] The ECS method may include a standby operation step S11 , a read operation detection step S12 , a read operation step S13 , an ECS operation step S14 , and an internal operation step S15 .

[0158] The standby operation step S11 may be set as a step performed before performing a read operation and a write operation of a normal operation. In the standby operation step S11, in an embodiment, the semiconductor system 1 may maintain a standby state without performing an operation of inputting and outputting data in order to reduce current consumption.

[0159] The read operation detection step S12 may be set as a step for detecting that a read operation of a normal operation is performed. When the chip selection signal CS and the first to fourth command addresses CA<1:4> of the first group all have a logic level combination for performing a read operation in the read operation detection step S12 (Yes), the read operation step S13 may be entered. When the chip selection signal CS and the first to fourth command addresses CA<1:4> of the first group do not have a logic level combination for performing a read operation in the read operation detection step S12 (No), the ECS operation step S14 may be entered.

[0160] The reading operation step S13 may be configured to output the data stored in a storage unit ( Figure 8 The step of the first to 128th internal data ID<1:128> in MC) belongs to a plurality of storage units ( Figure 8 The first to M-th row addresses RAD<1:M> and the first to N-th column addresses CAD<1:N> are generated based on the second group command address CA<5:L> after the read operation step is started. The read operation step S13 may be configured to generate the first to M-th latch row addresses (by latching the second group command address CA<5:L>) when an error occurs in the first to 128th internal data ID<1:128> that have been output. Figure 4 RLA<1:M> in ) and the first to Nth latch column addresses ( Figure 4 The read operation step S13 may be set as a step of outputting the first to 128th data DATA<1:128> by correcting errors of the first to 128th internal data ID<1:128>.

[0161] The reading operation step S13 may include an internal data error detecting step S131 , an error flag signal generating step S132 , an internal data error correcting step S133 , and a data outputting step S134 .

[0162] The internal data error detection step S131 may be set as a step of detecting an error of the first to 128th internal data ID<1:128> after the start of the read operation of the normal operation. When an error occurs in the first to 128th internal data ID<1:128> in the internal data error detection step S131 (Yes), the error flag signal generation step S132 may be entered. When an error does not occur in the first to 128th internal data ID<1:128> in the internal data error detection step S131 (No), the data output step S134 may be entered.

[0163] In the internal data error detection step S131, the operation control circuit 210 may generate a read command RD having a logic high level for a read operation by decoding the chip selection signal CS and the first group command address CA<1:4> in synchronization with the clock CLK. When the read command RD is enabled after the read operation of the normal operation starts, the storage circuit 220 may output the data stored in the plurality of storage cells ( Fig. 9 The ECS control circuit 230 may detect errors of the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8> in the memory cells selected by the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> among the MC in FIG. 1. The ECS control circuit 230 may detect errors of the first to 128th internal data ID<1:128> based on the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8>.

[0164] The error flag signal generating step S132 may be set as a step of generating an error flag signal EF that is enabled when an error occurs in the first to 128th internal data ID<1:128>.

[0165] In the error flag signal generating step S132, when an error occurs in the first to 128th internal data ID<1:128> after the ECS control circuit 230 performs the ECC encoding operation and the ECC decoding operation based on the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8>, the ECS control circuit 230 may generate the error flag signal EF having a logic high level. When no error occurs in the first to 128th internal data ID<1:128> after the ECS control circuit 230 performs the ECC encoding operation and the ECC decoding operation based on the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8>, the ECS control circuit 230 may generate the error flag signal EF having a logic low level.

[0166] The internal data error correction step S133 may be set as a step of correcting errors of the first to 128th internal data ID<1:128> based on the first to 128th internal data ID<1:128> and the first to eighth internal parities IP<1:8>.

[0167] In the internal data error correction step S133 , the ECS control circuit 230 may correct errors of the first to 128th internal data ID<1:128> by performing ECC encoding operations and ECC decoding operations based on the first to 128th internal data ID<1:128> and the first to eighth internal parities IP<1:8>.

[0168] The data output step S134 may be set as a step of outputting the first to 128th internal data ID<1:128> as the first to 128th data DATA<1:128> when no error occurs in the first to 128th internal data ID<1:128> in the internal data error detection step S131 (No). The data output step S134 may be set as a step of outputting the first to 128th internal data ID<1:128> corrected for error as the first to 128th data DATA<1:128> when an error occurs in the first to 128th internal data ID<1:128> in the internal data error detection step S131 (Yes).

[0169] In the data output step S134, the ECS control circuit 230 may perform an ECC encoding operation and an ECC decoding operation based on the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8>, and when no error occurs in the first to 128th internal data ID<1:128>, the first to 128th internal data ID<1:128> may be output to the data input-output circuit 240. The ECS control circuit 230 may perform an ECC encoding operation and an ECC decoding operation based on the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8>, and when an error occurs in the first to 128th internal data ID<1:128>, the error-corrected first to 128th internal data ID<1:128> may be output to the data input-output circuit 240.

[0170] When the data output step S134 is completed, the standby operation step S11 may be entered again.

[0171] The ECS operation step S14 may be set as a step of correcting the data stored in the first to M-th latch row addresses ( Figure 4 RLA<1:M> in ) and the first to Nth latch column addresses ( Figure 4 CLA<1:N>) selects the memory cell ( Figure 8 The first to 128th internal data ID<1:128> in the MC) are corrected, and the first to 128th internal data ID<1:128> whose errors have been corrected are stored in the same storage unit ( Figure 8 The ECS operation step S14 may be set as the following steps: the first to 128th internal data ID<1:128> that have been corrected are stored again in the first to M latch row addresses ( Figure 4 RLA<1:M> in ) and the first to Nth latch column addresses ( Figure 4 CLA<1:N>) selects the memory cell ( Figure 8 MC in ), and then by correcting the MC stored in multiple storage units ( Figure 8 The first to 128th internal data ID<1:128> are stored again to avoid errors in the first to 128th internal data ID<1:128> in MC).

[0172] The ECS operation step S14 may include an ECS operation detection step S141 , an error flag signal detection step S142 , an ECS operation execution step S143 , an error flag signal resetting step S144 , and a normal ECS operation step S145 .

[0173] The ECS operation detection step S141 may be provided as a step of detecting an ECS operation.

[0174] When the chip selection signal CS and the first to fourth command addresses CA<1:4> of the first group all have a logic level combination for performing the ECS operation in the ECS operation detection step S141 (Yes), the error flag signal detection step S142 may be entered. When the chip selection signal CS and the first to fourth command addresses CA<1:4> of the first group do not have a logic level combination for performing the ECS operation in the ECS operation detection step S141 (No), the internal operation step S15 may be entered.

[0175] The error flag signal detection step S142 may be set as a step of detecting the logic level of the error flag signal EF. When the error flag signal EF is enabled to a logic high level in the error flag signal detection step S142 (Yes), the ECS operation execution step S143 may be entered. When the error flag signal EF is disabled to a logic low level in the error flag signal detection step S142 (No), the normal ECS operation step S145 may be entered.

[0176] The ECS operation execution step S143 may be configured as follows: when the error flag signal EF is enabled to a logic high level (Yes), by correcting the error flag signal EF stored in the first to M-th latch row addresses ( Figure 4 RLA<1:M> in ) and the first to Nth latch column addresses ( Figure 4 CLA<1:N>) selects the memory cell ( Figure 8 The first to 128th internal data ID<1:128> in the MC) are stored again in the same storage unit ( Figure 8 MC in ).

[0177] In the ECS operation execution step S143, the operation control circuit 210 may generate a read command RD having a logic high level for a read operation by decoding the chip selection signal CS and the first group command address CA<1:4> in synchronization with the clock CLK. When the error flag signal EF is enabled to a logic high level after the read operation of the ECS operation starts, the operation control circuit 210 may latch the first to M-th latch row addresses ( Figure 4 RLA<1:M> in ) and the first to Nth latch column addresses ( Figure 4 CLA<1:N> in the READ_WRITE_STORAGE_ENGINE<1:M>) to generate the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N>, the first to Mth latch row addresses ( Figure 4 RLA<1:M> in ) and the first to Nth latch column addresses ( Figure 4 The CLA<1:N> in the ECS operation is generated by latching the second group command address CA<5:L>. In the ECS operation execution step S143, when the read command RD is enabled after the read operation of the ECS operation starts, the storage circuit 220 can output the data stored in the plurality of storage cells ( Fig. 9 The first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8> in the memory cells selected by the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> among the MC in the ECS operation execution step S143, the ECS control circuit 230 may correct the errors of the first to 128th internal data ID<1:128> based on the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8>. The ECS control circuit 230 may output the corrected first to 128th internal data ID<1:128> to the memory circuit 220. In the ECS operation execution step S143, the operation control circuit 210 may generate a write command WT with a logic high level for a write operation by decoding the chip selection signal CS and the first group command address CA<1:4> in synchronization with the clock CLK. When the write command WT is enabled after the write operation of the ECS operation starts, the storage circuit 220 may store the first to 128th internal data ID<1:128> that have been corrected in the plurality of storage cells ( Fig. 9 In the memory cells selected by the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> in MC).

[0178] The error flag signal resetting step S144 may be set as a step of disabling the error flag signal EF after the first to 128th internal data ID<1:128> are stored again by correcting errors of the first to 128th internal data ID<1:128>.

[0179] In the error flag signal resetting step S144 , the error flag signal generating circuit 234 may store the first to 128th internal data ID<1:128> again by correcting errors of the first to 128th internal data ID<1:128> and then may generate the error flag signal EF disabled to a logic low level.

[0180] When the error flag signal resetting step S144 is completed, the standby operation step S11 may be entered again.

[0181] The normal ECS operation step S145 may be set as a step of disabling the error flag signal EF by correcting the error of the first to 128th internal data ID<1:128>, storing again the data stored in the plurality of storage cells ( Figure 8 The first to 128th internal data IDs <1:128> in MC).

[0182] In the normal ECS operation step S145, when the error flag signal EF is disabled to a logic low level after the read operation of the ECS operation starts, the operation control circuit 210 may generate the first to M-th row addresses RAD<1:M> and the first to N-th column addresses CAD<1:N> that are sequentially counted. In the normal ECS operation step S145, when the read command RD is enabled after the read operation of the ECS operation starts, the storage circuit 220 may output the data stored in the plurality of storage cells ( Fig. 9 1:128> and the first to eighth internal parity IP<1:8> in the memory cells selected by the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> among the MC in the ECS operation step S145. In the normal ECS operation step S145, the ECS control circuit 230 may correct the errors of the first to 128th internal data ID<1:128> based on the first to 128th internal data ID<1:128> and the first to eighth internal parity IP<1:8>. The ECS control circuit 230 may output the corrected first to 128th internal data ID<1:128> to the memory circuit 220. In the normal ECS operation step S145, the operation control circuit 210 may generate a write command WT with a logic high level for a write operation by decoding the chip selection signal CS and the first group command address CA<1:4> in synchronization with the clock CLK. When the write command WT is enabled after the write operation of the ECS operation starts, the storage circuit 220 may store the first to 128th internal data ID<1:128> corrected by errors again in the plurality of storage cells ( Fig. 9 In the memory cells selected by the first to Mth row addresses RAD<1:M> and the first to Nth column addresses CAD<1:N> counted sequentially, among the MC in FIG.

[0183] When the normal ECS operation step S145 is completed, the standby operation step S11 may be entered again.

[0184] The internal operation step S15 may be set as a step of performing a precharge operation.

[0185] In the internal operation step S15, the operation control circuit 210 can generate a precharge command PCG with a logic high level for the precharge operation by decoding the chip selection signal CS and the first group command address CA<1:4> in synchronization with the clock CLK. When the precharge command PCG is enabled to a logic high level, the storage circuit 220 can perform the precharge operation. The internal operation step S15 has been set to the precharge operation, but can also be set to various internal operations of the semiconductor device 20.

[0186] When the internal operation step S15 is completed, the standby operation step S11 may be entered again.

[0187] In an ECS method according to an embodiment of the present disclosure, the priority of the ECS operation can be set by latching the command address CA<5:L> when an error occurs in the first to 128th internal data ID<1:128> after the start of a read operation of a normal operation, preferentially performing the ECS operation on a storage cell corresponding to the latched command address CA<5:L> after the start of the ECS operation, and then sequentially performing the ECS operation on a plurality of storage cells. In the ECS method, in one embodiment, the error of the first to 128th internal data ID<1:128> can be quickly corrected by latching the command address CA<5:L> when an error occurs in the first to 128th internal data ID<1:128> after the start of a read operation of a normal operation, preferentially performing the ECS operation on a storage cell corresponding to the latched command address CA<5:L> after the start of the ECS operation, and then sequentially performing the ECS operation on a plurality of storage cells.

[0188] Fig.16 1 is a block diagram showing the configuration of an embodiment of an electronic system 1000 according to an embodiment of the present disclosure. Fig.16 As shown, the electronic system 1000 may include a host 1100 and a semiconductor system 1200 .

[0189] The host 1100 and the semiconductor system 1200 may transmit signals to each other by using an interface protocol. The interface protocol used between the host 1100 and the semiconductor system 1200 may include a multimedia card (MMC), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a peripheral component interconnect express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a serial attached SCSI (SAS), and a universal serial bus (USB).

[0190] The semiconductor system 1200 may include a controller 1300 and a semiconductor device 1400 (K: 1). The controller 1300 may control the semiconductor device 1400 (K: 1) so that the semiconductor device 1400 (K: 1) performs a normal operation and an ECS operation. When an error occurs in the first to 128th internal data ID<1: 128> after the start of a read operation of a normal operation, the semiconductor device 1400 (K: 1) may latch a command address CA<5: L> respectively. The semiconductor device 1400 (K: 1) may set the priority of the ECS operation by preferentially performing an ECS operation on a memory cell corresponding to the command address CA<5: L> that has been latched after the start of the ECS operation, and then sequentially performing the ECS operation on a plurality of memory cells. In an embodiment, the semiconductor device 1400 (K:1) can quickly correct errors of the first to 128th internal data ID<1:128> by preferentially performing an ECS operation on a memory cell corresponding to a command address CA<5:L> that has been latched after the ECS operation starts, and then sequentially performing an ECS operation on a plurality of memory cells.

[0191] In one embodiment, the controller 1300 may be implemented as Figure 1 In one embodiment, the semiconductor devices 1400 (K:1) can each be implemented as Figure 1 . According to an embodiment, the semiconductor devices 1400 (K:1) may each be implemented as one of a dynamic random access memory (DRAM), a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory (FRAM).< / m> < / m> < / m> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / n> < / m> < / m> < / m> < / n> < / m> < / m> < / n> < / n> < / m> < / n> < / m> < / m>

Claims

1. A semiconductor system comprising: A controller that: outputs a chip select signal and a command address including a first logic level combination for performing a read operation; and then outputs a chip select signal and a command address including a second logic level combination for performing an ECS operation, the second logic level combination being different from the first logic level combination, ECS referring to error check scrubbing; and A semiconductor device comprising a plurality of memory cells, wherein: after the read operation based on the chip selection signal and the command address is started, the semiconductor device receives the command address to generate an internal command address, wherein the internal command address is used to generate a latch row address and a latch column address by latching the internal command address when an error occurs in internal data output from a memory cell selected from among the plurality of memory cells; determines the priority of the ECS operation of the plurality of memory cells corresponding to the latch row address and the latch column address; and after correcting the error in the internal data, stores the internal data again in the same selected memory cell.

2. The semiconductor system according to claim 1, wherein: The semiconductor device: after the ECS operation starts, after the error of the internal data output from the selected memory cell among the plurality of memory cells is corrected based on the row address and the column address generated from the latched row address and the latched column address, the internal data is stored again in the same memory cell from which the internal data is output, and Then, the internal data is stored again in the same memory cell by correcting errors of the internal data stored in the plurality of memory cells sequentially selected based on the row address and the column address.

3. The semiconductor system according to claim 1, wherein: The priority of the ECS operation means that an operation of storing the internal data again after correcting the error of the internal data stored in the selected memory cell among the plurality of memory cells based on the latched row address and the latched column address is preferentially performed.

4. The semiconductor system according to claim 1, wherein: The semiconductor device comprises: an operation control circuit which: after the read operation starts, when the error occurs in the internal data output from the memory cell selected from among the plurality of memory cells included in the memory circuit, generates the latched row address and the latched column address by latching the command address for selecting the memory cell selected from among the plurality of memory cells; and after the ECS operation starts, generates the row address and the column address which are counted sequentially after the row address and the column address are generated from the latched row address and the latched column address; and An ECS control circuit, which: corrects the error of the internal data output from the storage cell selected by the row address and the column address among the multiple storage cells after the ECS operation starts; and outputs the corrected internal data so as to store the corrected internal data again in the storage cell selected among the multiple storage cells.

5. The semiconductor system according to claim 4, wherein: The operation control circuit: generating the row address and the column address from the latched row address and the latched column address based on an error flag signal enabled when the error occurs in the internal data; as well as When the error flag signal is disabled, the row address and the column address are generated by sequentially counting the row address and the column address.

6. The semiconductor system according to claim 5, wherein: The operation control circuit: generating the row address and the column address from the latched row address and the latched column address; After correcting the error in the internal data, storing the internal data again; as well as The error flag signal is then disabled.

7. The semiconductor system according to claim 4, wherein: The operation control circuit comprises: An input circuit, which: generates an internal chip selection signal and the internal command address by receiving the chip selection signal and the command address in synchronization with a clock, wherein the internal command address includes a first group of internal command addresses and a second group of internal command addresses; a command decoder that: generates a read command for performing the read operation by decoding the internal chip select signal and the first group of internal command addresses; and generates a write command after generating an ECS command and the read command for performing the ECS operation by decoding the internal chip select signal and the first group of internal command addresses; and an address generation circuit, which: generates the row address and the column address based on the second group of internal command addresses when the ECS command is disabled; generates the row address and the column address by latching the second group of internal command addresses during an interval in which an error flag signal is enabled when the ECS command is enabled; and generates the row address and the column address that are counted sequentially during an interval in which the error flag signal is disabled.

8. The semiconductor system according to claim 7, wherein: The address generation circuit comprises: an error address generating circuit, which: latches the second group of internal command addresses during an interval in which the error flag signal is enabled when the ECS command is enabled; generates an error row address and an error column address from the latched second group of internal command addresses; and generates the error row address and the error column address that are sequentially counted during an interval in which the error flag signal is disabled when the ECS command is enabled; and The address selection circuit generates the row address and the column address based on the second group of internal command addresses when the ECS command is disabled, and generates the row address and the column address based on the error row address and the error column address when the ECS command is enabled.

9. The semiconductor system according to claim 8, wherein: The error address generating circuit comprises: a counting circuit, which: generates a row count signal and a column count signal that are counted sequentially when the ECS command is enabled; a latch circuit that: generates the latched row address and the latched column address by latching the second group of internal command addresses during an interval in which the error flag signal is enabled; and A transmission circuit is selected, which: during the interval when the error flag signal is enabled, outputs the latched row address and the latched column address as the error row address and the error column address; and during the interval when the error flag signal is disabled, outputs the row count signal and the column count signal as the error row address and the error column address.

10. The semiconductor system according to claim 4, wherein: The ECS control circuit comprises: a transmission data generating circuit that generates transmission data by buffering the internal data output from the storage unit selected from among the plurality of storage units; an error correction circuit that: detects an error of the transmission data when a read delay signal is enabled; generates the internal data by correcting the error of the transmission data; and outputs the internal data to the storage unit selected from among the plurality of storage units; and An error flag signal generating circuit generates an enabled error flag signal based on an error correction signal generated by detecting the error of the transmission data, and generates a disabled error flag signal after the internal data is stored again after the error of the internal data is corrected.

11. The semiconductor system according to claim 10, wherein: The error correction circuit comprises: an operation parity generation circuit, which: generates an operation parity when the read delay signal is enabled, the operation parity including information of the error of the transmission data; a syndrome generation circuit that: generates a syndrome by comparing the operation parity with an internal parity output from an error cell included in the storage circuit; an error correction signal generating circuit, which generates the error correction signal by decoding the syndrome; and An error processing circuit that, after correcting the error of the transmission data based on the error correction signal, outputs the transmission data as the internal data.

12. A semiconductor device comprising: an operation control circuit, which: after a read operation starts, receives a command address to generate an internal command address, the internal command address is used to generate a latched row address and a latched column address by latching the command address for selecting a memory cell included in a memory circuit when an error flag signal is enabled; and after an ECS operation starts, generates a row address and a column address from the latched row address and the latched column address by detecting a logic level of the error flag signal, or generates the row address and the column address counted sequentially, ECS refers to error check scrubbing; and An ECS control circuit that: corrects an error included in internal data output from the storage unit selected by the row address and the column address after the ECS operation starts; and outputs the error-corrected internal data and then stores the internal data in the storage unit again.

13. The semiconductor device according to claim 12, wherein: The operation control circuit: generating the row address and the column address from the latched row address and the latched column address when the error flag signal is enabled; as well as When the error flag signal is disabled, the row address and the column address are generated by sequentially counting the row address and the column address.

14. The semiconductor device according to claim 12, wherein: The operation control circuit: generating the row address and the column address from the latched row address and the latched column address; After correcting the error in the internal data, storing the internal data again; as well as The error flag signal is disabled.

15. The semiconductor device according to claim 12, wherein: The operation control circuit comprises: An input circuit, which: generates an internal chip selection signal and the internal command address by receiving the chip selection signal and the command address in synchronization with a clock, the internal command address including a first group of internal command addresses and a second group of internal command addresses; a command decoder that: generates a read command for performing the read operation by decoding the internal chip select signal and the first group of internal command addresses; and generates a write command after generating an ECS command and the read command for performing the ECS operation by decoding the internal chip select signal and the first group of internal command addresses; and an address generation circuit, which: generates the row address and the column address based on the second group of internal command addresses when the ECS command is disabled; generates the row address and the column address by latching the second group of internal command addresses during an interval in which an error flag signal is enabled when the ECS command is enabled; and generates the row address and the column address that are counted sequentially during an interval in which the error flag signal is disabled.

16. The semiconductor device according to claim 15, wherein: The address generation circuit comprises: an error address generating circuit, which: latches the second group of internal command addresses during the interval in which the error flag signal is enabled when the ECS command is enabled; generates an error row address and an error column address from the latched second group of internal command addresses; and generates the error row address and the error column address that are sequentially counted during the interval in which the error flag signal is disabled when the ECS command is enabled; and The address selection circuit generates the row address and the column address based on the second group of internal command addresses when the ECS command is disabled, and generates the row address and the column address based on the error row address and the error column when the ECS command is enabled.

17. The semiconductor device according to claim 16, wherein: The error address generating circuit comprises: a counting circuit, which: generates a row count signal and a column count signal that are counted sequentially when the ECS command is enabled; a latch circuit that: generates the latched row address and the latched column address by latching the second group of internal command addresses during the interval in which the error flag signal is enabled; and A transmission circuit is selected, which: during the interval when the error flag signal is enabled, outputs the latched row address and the latched column address as the error row address and the error column address; and during the interval when the error flag signal is disabled, outputs the row count signal and the column count signal as the error row address and the error column address.

18. The semiconductor device according to claim 12, wherein: The ECS control circuit comprises: a transmission data generating circuit, which: generates transmission data by buffering the internal data output from the storage unit; an error correction circuit which: when a read delay signal is enabled, detects an error of the transmission data; generates the internal data by correcting the error of the transmission data; and outputs the internal data to the selected storage unit among the plurality of storage units; and An error flag signal generating circuit, which: generates the error flag signal to be enabled based on an error correction signal generated by detecting the error of the transmission data; and generates the error flag signal to be disabled after the internal data is stored again after the error of the internal data is corrected.

19. The semiconductor device according to claim 18, wherein: The error correction circuit comprises: an operation parity generation circuit, which: generates an operation parity when the read delay signal is enabled, the operation parity including information of the error of the transmission data; a syndrome generating circuit, which: generates a syndrome by comparing the operation parity with an internal parity output from an error cell included in the storage circuit; an error correction signal generating circuit, which generates the error correction signal by decoding the syndrome; and An error processing circuit that, after correcting the error of the transmission data based on the error correction signal, outputs the transmission data as the internal data.

20. An ECS method, ESC refers to error checking and cleaning, the method comprising: A read operation step: after the read operation starts, when an error occurs in internal data that has been stored in a memory cell selected by a row address and a column address among a plurality of memory cells, generating a latch row address and a latch column address by latching an internal command address generated from a command address, the row address and the column address being generated based on the command address; and after correcting said error in said internal data, outputting said internal data as data; as well as ECS operation steps: after the ECS operation starts, after the error of the internal data already stored in the selected storage unit is corrected based on the logic level of the error flag signal, the internal data is stored again based on the latch row address and the latch column address; then, after the error of the internal data already stored in the plurality of storage units is corrected, the internal data is stored again.

21. The ECS method of claim 20, wherein: The error flag signal is a signal that is enabled when the error occurs in the internal data and is disabled after the internal data is stored again after the error of the internal data is corrected.

22. The ECS method of claim 20, wherein: The reading operation steps include: Internal data error detection step: detecting the error in the internal data; An error flag signal generating step: generating an enabled error flag signal when the error occurs in the internal data; An internal data error correction step of correcting the error of the internal data based on the internal data and the internal parity check; and Data output step: when no error occurs in the internal data in the internal data error detection step, outputting the internal data as data; and when the error occurs in the internal data in the internal data error detection step, outputting the internal data that has been corrected as data.

23. The ECS method of claim 20, wherein: The ECS operation steps include: ECS operation detection step: detecting the ECS operation; An error flag signal detection step: detecting a logic level of the error flag signal after the ECS operation starts; An ECS operation execution step: when the error flag signal is enabled, storing the internal data again based on the latched row address and the latched column address by correcting the error of the internal data already stored in the selected storage unit; an error flag signal resetting step of disabling the error flag signal after storing the internal data again by correcting the error of the internal data; and Normal ECS operation step: when the error flag signal is disabled, storing the internal data again by correcting the error of the internal data stored in the plurality of storage cells based on the row address and the column address counted sequentially.

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