System and method for testing memory device

Abstract

A system for testing memory devices includes a plurality of memory devices and a tester. The test machine performs: generating a first multipurpose instruction to the memory devices, and generating a first data signal to a first data pin of each of a first set of the memory devices to store first identity data. Generating a second multipurpose instruction to the memory devices, and generating a first data signal to a second data pin of each of a second set of the memory devices to store second identity data; a third multi-purpose instruction and a fourth multi-purpose instruction are generated to the memory devices to select a first set and a second set from the memory devices, respectively, and write equalization pulses of the first set and the second set have a first time shift and a second time shift, respectively. The system provided by the invention is helpful for improving the test efficiency.

Description

Technical Field

[0001] The present invention relates to a system and method for testing a memory device, and more particularly to a system and method for testing a memory device using identity instructions. Background Art

[0002] As the process technology of memory devices develops rapidly, the circuits of memory devices are designed to have smaller size and higher density. Higher circuit density helps to improve the speed and performance of memory, but higher error rate and manufacturing difficulties arise. Generally speaking, in order to ensure the reliability and yield of the product, memory testing is indispensable. Summary of the invention

[0003] In some embodiments, a system for testing memory devices is provided. The system includes a plurality of memory devices and a tester. Each of the memory devices includes a memory unit. The tester is operatively coupled to the memory devices and performs: generating a first multi-purpose instruction to the memory devices, and generating a first data signal to a first data pin of each of a first set of the memory devices to store first identity data in a plurality of first mode registers of the first set of the memory devices. Generate a second multi-purpose instruction to these memory devices, and generate a first data signal to the second data pin of each of the second set of these memory devices to store second identity data in multiple second mode registers of the second set of these memory devices; generate a third multi-purpose instruction and a fourth multi-purpose instruction to these memory devices to respectively select the first set and the second set from these memory devices, and respectively make the write equalization pulses of the first set and the second set have a first time shift and a second time shift; transmit write data to multiple data pins of these memory devices to perform write operations on these memory devices, these data pins include first and second data pins; and receive read data from these data pins and compare the write data and the read data to obtain a test result.

[0004] In some embodiments, the test machine generates third and fourth multi-purpose instructions to select the first and second sets according to first and second identity data stored in the first and second sets of the memory devices, respectively.

[0005] In some embodiments, the tester generates a first mode register write command to the first and second sets of the memory devices to store setting values ​​in the third mode registers of the first set of the memory devices when the first set of the memory devices is selected.

[0006] In some embodiments, when the tester generates a first data signal to a first set of these memory devices to store first identity data, the tester generates a second data signal to a second data pin of each of a second set of these memory devices to prohibit the second set of these memory devices from storing the first identity data.

[0007] In some embodiments, the first data signal and the second data signal are inversely proportional to each other.

[0008] In some embodiments, the tester includes a storage device. The storage device stores a data array. Each column of the data array includes multiple values ​​and corresponding identity data. The tester outputs multiple signals corresponding to these values ​​to these data pins to select corresponding sets from these memory devices to store corresponding identity data.

[0009] In some embodiments, each of such values ​​is either a first logical value or a second logical value.

[0010] In some embodiments, the test machine maps the first and second identity data according to the data array to generate a first setting value and a second setting value respectively. The first and second setting values ​​are stored in the first and second sets of the memory devices respectively.

[0011] In some embodiments, a method for testing a memory device is provided. The method includes: performing a first write-leveling training operation on a first memory device to obtain a first setting value; generating a first multi-purpose instruction to the first memory device and the second memory device to perform an enumeration identity operation to store first identity data; generating a first data sequence having a first logic value to the first memory device, wherein in response to the first data sequence, the first memory device is prohibited from performing the enumeration identity operation; generating a second multi-purpose instruction to select the identity operation to the first and second memory devices to select the corresponding memory device storing the first identity data; generating a mode register write instruction to the corresponding memory device to store the first setting value in the mode register of the corresponding memory device; writing the first data to the first and second memory devices; and reading the first and second memory devices to obtain the second data and the third data respectively; and comparing the first data with the second and third data to generate a test result.

[0012] In some embodiments, the method further includes: generating a second data sequence having a second logic value to a second memory device, the second memory device performing an enumeration identity operation in response to the second data sequence to store the first identity data in a mode register of the second memory device.

[0013] In some embodiments, the method further includes: storing a data array, wherein a column of the data array includes a first value and a second value that is inverse to the first value, wherein the first value is a first logical value or a second logical value; generating a second data sequence having the first value to the first memory device and generating a third data sequence having the second value to the first memory device to select one of the first and second memory devices to store the second identity data.

[0014] In some embodiments, the first setting value is a value indicating a time shift of a write equalization pulse for starting a write operation.

[0015] In some embodiments, a method for testing a memory device is provided. The method includes: generating a plurality of identity commands and a plurality of data signals to store a plurality of identity data in a plurality of memory devices, wherein first identity data and second identity data in the plurality of identity data are different from each other; generating a plurality of mode register write commands to the plurality of memory devices to set the plurality of memory devices to have a plurality of time shifts corresponding to write-equalization pulses based on the plurality of identity data, wherein a first time shift and a second time shift in the plurality of time shifts correspond to a first identity data and a second identity data, respectively, and the first and second time shifts are different from each other; and generating a test result based on the write data to the plurality of memory devices and a plurality of read data obtained from the plurality of memory devices.

[0016] In some embodiments, generating the mode register write commands includes generating a first selection command to select a first set of memory devices storing the first identity data from the memory devices.

[0017] In some embodiments, generating the mode register write commands includes writing a first setting value to a plurality of mode registers of a first memory device set.

[0018] In some embodiments, generating the mode register write command further includes generating a first setting value according to the first identity data.

[0019] In some embodiments, the memory devices store the identity data in a plurality of mode registers of the memory devices.

[0020] In some embodiments, generating the identity commands and the data signals includes generating a first data signal to a first set of memory devices among the memory devices to store first identity data.

[0021] In some embodiments, generating the identity instructions and the data signals includes generating a second data signal to a second set of memory devices among the memory devices to prohibit the second set of memory devices among the memory devices from storing the first identity data.

[0022] In some embodiments, the first data signal has a low logic level and the second data signal has a high logic level. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The aspects of one embodiment of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0024] Figure 1 is a schematic diagram of a system for testing a memory according to some embodiments of the present invention;

[0025] Figure 2 is a schematic diagram of a system according to some embodiments of the present invention;

[0026] Figure 3A and Figure 3B is a waveform diagram of an example of an internal write-leveling procedure according to some embodiments of the present invention;

[0027] Figure 4 is a schematic diagram of a system according to some embodiments of the present invention;

[0028] Figure 5 is a waveform diagram of an example enumeration identity operation according to some embodiments of the present invention;

[0029] Figure 6 is a diagram of waveforms enumerating example identity operations according to some embodiments of the present invention;

[0030] Figure 7 is a waveform diagram of an example of an identity selection operation according to some embodiments of the present invention; and

[0031] Figure 8 is a flow chart of a method according to some embodiments of the invention. DETAILED DESCRIPTION

[0032] The following disclosure provides many different embodiments or examples of different features for achieving the provided objectives. The following describes specific examples of components and arrangements to simplify an embodiment of the present invention. Of course, the plurality of components are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first and second features are directly contacted to form, and may also include an embodiment in which additional features are formed between the first and second features so that the first and second features may not be directly contacted. In addition, the present invention may repeat component symbols or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments or configurations discussed.

[0033] The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which each term is used. The use of examples in this specification, including examples of any term discussed herein, is illustrative only and in no way limits the scope and meaning of an embodiment of the case or any exemplary term. Likewise, an embodiment of the case is not limited to the various embodiments given in this specification.

[0034] The words “include,” “including,” “have,” “contain,” etc. used in this document are open-ended terms, meaning including but not limited to.

[0035] The reference to "one embodiment" or "some embodiments" in the specification means that the specific features, structures, implementations or characteristics described in the embodiment are included in at least one embodiment of the present invention. Therefore, when "in one embodiment" or "in some embodiments" is mentioned in different places in the specification, it does not necessarily refer to the same embodiment. These features, structures, implementations or characteristics can be combined into one or more embodiments in any suitable manner.

[0036] Further, for ease of description, spatially relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] As used herein, "approximately", "about", "approximately" or "substantially" shall generally refer to any approximation of a given value or range, wherein it varies depending on the various fields involved, and its scope shall be consistent with the broadest interpretation understood by those skilled in the art to cover all of the multiple modifications and similar structures. In some embodiments, it shall generally refer to within 20 percent of a given value or range, preferably within 10 percent, and more preferably within 5 percent. The numerical values ​​given herein are approximate, meaning that if not explicitly stated, the term "approximately", "about", "approximately" or "substantially" can be inferred, or other approximate values ​​are meant.

[0038] refer to Figure 1 . Figure 1FIG. 1 is a schematic diagram of a system 100 for testing memory according to some embodiments of the present invention. To illustrate, the system 100 includes a memory device 110 and a tester 120. In some embodiments, the memory device 110 is operatively coupled to the tester 120.

[0039] In some embodiments, the memory device 110 is a memory device such as a single in-line memory module (SIMM), a dual in-line memory module (DIMM), a dynamic random access memory (DRAM) chip, a static random access memory (DRAM) chip, etc. In some embodiments, the memory device 110 is a fifth-generation double data rate synchronous dynamic random access memory (DDR5 SDRAM) chip.

[0040] like Figure 1 As shown, the memory device 110 includes a memory array 111, a control circuit 112, a mode register 113a, a mode register 113b and a mode register 113c. The control circuit 112 is coupled to the memory array 111 and the mode registers 113a-113c. The memory array 111 includes a plurality of memory cells 114, and the plurality of memory cells are arranged in a plurality of columns and a plurality of rows. According to different embodiments, the memory cell 114 includes a volatile memory cell, a non-volatile memory cell and a combination thereof. In some embodiments, the mode registers 113a, 113b and 113c are respectively the first mode register (MR1), the second mode register (MR2) and the third mode register (MR3) of the DDR5 SDRAM.

[0041] According to some embodiments, the memory array 111 further includes a plurality of word lines WL and a plurality of bit lines BL. The word lines WL and the bit lines BL include conductive structures, such as metal lines. Figure 1 As shown, in some embodiments, each row of memory cells 114 is coupled to a corresponding word line WL and each column of memory cells 114 is coupled to a corresponding bit line BL.

[0042] In practice, the control circuit 112 performs an operation (e.g., a write operation or a read operation) on the memory array 111 by controlling and / or sensing signals on the word lines WL and the bit lines BL. In some embodiments, the control circuit 112 performs an operation on the memory array 111 according to a command received by the memory device 110, such as a command from the tester 120. For example, the tester 120 generates a write command corresponding to a memory address to the memory device 110. The control circuit 112 stores the write data in the memory cell 114 corresponding to the memory address through the word lines WL and the bit lines BL. In some embodiments, the control circuit 112 includes a column address decoder, a row address decoder, and a sense amplifier.

[0043] In some embodiments, the control circuit 112 performs operations on the mode register 113a and the mode register 113b. In some embodiments, the control circuit 112 performs operations on the mode register 113a and the mode register 113b according to instructions received by the memory device 110 (e.g., instructions from the tester 120). For example, the tester 120 generates a mode register write (MRW) instruction for the mode register 113a to the memory device 110, and the control circuit 112 writes data to the mode register 113a according to the MRW instruction.

[0044] According to some embodiments, the tester 120 is a memory tester, such as a DRAM tester or an SRAM tester. In some embodiments, the tester 120 is a programmable tester. Figure 1 As shown, the test machine 120 includes a processor 121 and a storage device 122. In some embodiments, the processor 121 is coupled to the storage device 122.

[0045] According to different embodiments, the processor 121 is, for example, a central processing unit (CPU), or other programmable general-purpose or special-purpose micro control unit (MCU), microprocessor, digital signal processor (DSP), programmable controller, application specific integrated circuit (ASIC), graphics processing unit (GPU), arithmetic logic unit (ALU), complex programmable logic device (CPLD), field programmable gate array (FPGA) or other similar components or combinations of the above components.

[0046] According to some embodiments, the memory device 122 includes a universal buffer memory (UBM). In some embodiments, the UBM stores data output to the memory device 110.

[0047] Figure 1 The system 100 shown is provided for illustrative purposes. Various implementations of the system 100 are within the contemplated scope of an embodiment of the present disclosure. For example, in some embodiments, the memory array 111 is a three-dimensional memory array.

[0048] refer to Figure 2 . Figure 2 is a schematic diagram of a system 100 according to some embodiments of the present invention. Figure 1 For ease of understanding, Figure 2 Similar components in the present invention are marked with the same reference numerals. For the sake of brevity, the specific operations of similar components that have been discussed in detail in the above paragraphs are omitted herein.

[0049] For illustration, in some embodiments, the system 100 further includes a plurality of memory devices 110, a bus 201, and a plurality of data lines (pins) 202. Figure 1 As shown, the tester 120 is coupled to the memory device 110 via a bus 201. In addition, the tester 120 is coupled to each memory device 110 via a data line (pin) 202, respectively.

[0050] In practice, the tester 120 transmits a command / address signal to the memory device 110 via the bus 201, and transmits a data signal DQ to the memory device 110 via the data line (pin) 202. For example, in order to control the memory device 110 to perform a write operation, the tester 120 outputs a write command to the memory device via the bus 201, and outputs write data to the memory device 110 via the data line (pin) 202.

[0051] Figure 2 The system 100 shown in FIG. 1 is provided for illustrative purposes. Various implementations of the system 100 are within the contemplated scope of an embodiment of the present invention. For example, in some embodiments, a memory device 110 includes a plurality of data lines (pins) 202 coupled to a tester 120 .

[0052] In some embodiments, the tester 120 performs tests on the memory device 110 to detect functional defects. In some embodiments, the tester 120 performs tests on the memory device 110 under different settings of the memory device 110, such as different settings of write leveling internal cycle alignment (WICA). In some embodiments, during a write operation, the control circuit 112 starts writing data to the memory array 111 in response to an internal write leveling (internal WL) pulse (i.e., the level of the internal write leveling signal generated in the control circuit 112 is pulled high). In some embodiments, the setting value of WICA indicates a time shift of the internal WL pulse.

[0053] In some embodiments, the WICA setting is determined by an internal write leveling process to ensure correct timing of the data strobe (DQS) signal of the memory device 110, wherein the internal write leveling process is also referred to as data strobe training (DQS training). For details on the WICA setting and the internal write leveling process for the memory device 110, please refer to Figure 3A and Figure 3B Further description.

[0054] refer to Figure 3A and Figure 3B . Figure 3A and Figure 3B is a waveform diagram of an example of an internal write-leveling procedure according to some embodiments of the present invention. Figure 1 to Figure 2 For ease of understanding, FIG. 3A to FIG. 3BSimilar components in the present invention are marked with the same reference numerals. For the sake of brevity, the specific operations of similar components that have been discussed in detail in the above paragraphs are omitted herein.

[0055] In terms of description, Figure 3A As shown, at time point t1, the tester 120 outputs a mode register write command MRW1 to write a value (e.g., logic value 1) to the mode register 113b to enable the write leveling mode. After the write leveling mode is enabled, the tester 120 outputs a write command WRITE to the memory device 110 at time point t2 and at time point t 3-- Generate a DQS toggle signal pair, i.e., a signal DQS_t and a signal DQS_c that are staggered in each unit interval. In response to the write command, the control circuit 112 pulls up the level of the internal WL signal at time point t5 to generate an internal WL pulse. In some embodiments, the tester 120 generates a device deselect command (DES) between the mode write value command and the write command. In response to the device deselect command, the memory device 110 stops executing the operation.

[0056] According to some embodiments, the internal write leveling process is executed to align the internal write leveling pulse and the DQS switching signal pair. In practice, the control circuit 112 samples the internal write leveling signal using the signal DQS_t and the signal DQS_c to obtain a sampled value. Based on the sampled value, it can be determined whether the internal write leveling pulse is aligned with the DQS switching signal pair.

[0057] For example, in some Figure 3A In the illustrated embodiment, the internal write leveling process is executed to align the internal write leveling pulse with the third interleaving point (e.g., time point t4) in the DQS switching signal pair. The control circuit 112 samples the internal write leveling signal when the signal DQS_t and the signal DQS_c intersect with each other for the third time in the internal write leveling process and obtains the sampled value as logic zero. Then, at time point t6, the memory device 110 pulls down the data signal DQ on the data line (pin) 202 to a value having the sampled value (logic zero). In some embodiments, the tester 120 receives the data signal DQ and determines that the internal write leveling pulse and the DQS switching signal pair are not aligned with each other according to the value of the data signal DQ being logic zero. In some embodiments, at time point t7 after the sampled value is output, the tester 120 outputs the mode register write instruction MRW2 to write a value (e.g., logic zero) to the mode register 113b to end the write leveling mode.

[0058] According to some embodiments, the tester 120 controls the control circuit 112 to shift (generate early) the internal write equalization pulse and repeat the above reference Figure 3A The operation continues until the internal write equalization pulse is aligned with the DQS switching signal pair. Figure 3B An example of internal write equalization pulse alignment with DQS switching signal pair is shown. Figure 3B As shown, the sampled value of the internal write equalization pulse at time point t4 is logic one, and the memory device 110 pulls up the data signal DQ of the data line (pin) 202 to a value of logic one at time point t6.

[0059] Figure 3A and Figure 3B The waveform of the internal write equalization is provided for illustrative purposes. Various implementations of the waveform of the internal write equalization are within the contemplated scope of an embodiment of the present invention. For example, in some embodiments, the tester 120 outputs a mode register write instruction between the mode register write instruction MRW1 and the write instruction WRITE to set the WICA setting value in the mode register 113c.

[0060] In some embodiments, the setting values ​​(e.g., WICA setting values) of different memory devices 110 are different from each other. In some embodiments, the setting values ​​are adjusted according to the different operating voltages and / or system clock cycle times (tCK) of the memory devices 110. According to some embodiments, the tester 120 writes different setting values ​​to different memory devices 110 before performing a test on the memory devices 110.

[0061] refer to Figure 4 . Figure 4 is a schematic diagram of a system 100 according to some embodiments of the present invention. Figure 1 , Figure 2 , Figure 3A and Figure 3B For ease of understanding, Figure 4 Similar components in the present invention are marked with the same reference numerals. For the sake of brevity, the specific operations of similar components that have been discussed in detail in the above paragraphs are omitted herein.

[0062] For illustration, the tester 120 performs a test on a plurality of memory devices 110, the plurality of memory devices 110 including a set g1 to a set gn of the memory devices 110. Before performing the test, the tester 120 writes a setting value v1 (e.g., a value of 3, indicating that the internal WL pulse is shifted by three tCKs) to a mode register of each of the set g1, the tester 120 writes a setting value v2 (e.g., a value of 4, indicating that the internal WL pulse is shifted by four tCKs) to a mode register of each of the set g2, ... and writes a setting value vn (e.g., a value of 5, indicating that the internal WL pulse is shifted by five tCKs) to a mode register of each of the set gn.

[0063] In practice, the tester 120 performs a per DRAM addressability (PDA) operation to respectively set the plurality of memory devices 110. In other words, different setting values ​​are written to different sets of memory devices 110.

[0064] The PDA operation includes an enumerate identity (enumerate ID) operation and a select identity (select ID) operation. According to some embodiments, in order to write different setting values ​​(setting values ​​v1-vn) to different sets of memory devices 110 (sets g1-gn), the tester 120 writes different identity data (identity, ID) id1-idn to different sets of memory devices 110 (sets g1-gn) through the enumerate ID operation.

[0065] Next, the test machine 120 writes different set values ​​(set values ​​v1-vn) to the mode registers storing the identity data id1-idn in different sets of the memory devices 110 through the select ID operation. For example, during the select ID operation, the set g1 is selected according to the identity data id1 stored in the set g1, and the test machine 120 writes the set value v1 to the selected set g1. Further details about the enumerate ID operation and the select ID operation on the memory device 110 will be referred to below. Figures 5 to 7 describe.

[0066] Figure 4 The system 100 shown is provided for illustrative purposes. Various implementations of the system 100 are within the contemplated scope of an embodiment of the present invention. For example, in some embodiments, the memory devices 110 in the same set (e.g., set g1) are not all adjacent. For example, the memory devices 110 of set g2 are disposed between the memory devices 110 of two sets g1.

[0067] refer to Figure 5 . Figure 5 is a waveform diagram of an example enumerate ID operation according to some embodiments of the present invention. Figure 1 , Figure 2 , Figure 3A , Figure 3B and Figure 4 For ease of understanding, Figure 5 Similar components in the present invention are marked with the same reference numerals. For the sake of brevity, the specific operations of similar components that have been discussed in detail in the above paragraphs are omitted herein.

[0068] To illustrate, at time point t a , the tester 120 generates a multi-purpose command (MPC) MPC1 to the memory device 110 to perform a PDA enumerate programming entry operation, i.e., start a PDA enumerate programming mode. Specifically, the tester 120 generates an MPC with an operation code (opcode) indicating a PDA enumerate programming entry operation and transmits it to all memory devices 110 coupled to the bus 201 through the bus 201. According to some embodiments, in the PDA enumerate programming mode, the memory device 110 is allowed (enabled) to perform an enumerate ID operation to store an ID in response to an MPC with an operation code indicating an enumerate ID operation (also referred to as an ID instruction).

[0069] Next, at time point t after the transmission of the multi-purpose instruction MPC1 having an operation code instructing the PDA to enumerate the programming entry operation b To time point t c During the period, the tester 120 generates a DES instruction, and the memory device 110 stops executing the operation in response to the DES instruction.

[0070] At time point t c , the tester 120 generates a multi-purpose instruction with an operation code indicating the enumerate ID operation, namely, the identity instruction (ID instruction) IDC1 and transmits it to the memory device 110 via the bus 201. At time point t- c At the next time point t f, the tester 120 generates a DQS switching signal pair to the memory device 110. In some embodiments, the ID instruction IDC1 includes an ID, and the control circuit 112 performs an enumerate ID operation in response to the ID instruction IDC1 and the DQS switching signal pair to store the ID. During the enumerate ID operation, the control circuit 112 writes the ID to the mode register 113a. In some embodiments, the control circuit 112 performs an enumerate ID operation during the DQS switching signal pair (from time point t f To time point t g ) writes ID to the mode register 113a.

[0071] In some embodiments, the control circuit 112 performs the enumerateID operation in response to the ID command, the DQS switching signal pair, and the data signal DQ of the data line (pin) 202 having a first logic level (e.g., a sequence of data having a value of logic zero). According to some embodiments, during the DQS switching signal pair, when the data signal DQ has a second logic level opposite to the first logic level (e.g., having a value of logic one), the control circuit 112 stops writing the ID to the mode register. In other words, the logic level of the data signal DQ needs to be kept low (maintained at a value of logic zero) during the DQS switching signal pair in order to write the ID to the mode register.

[0072] In some embodiments, in order to enable (allow) the control circuit 112 to perform the enumerate ID operation, the tester 120 generates a data sequence of logic zero values ​​to the memory device 110, wherein the data sequence of logic zero values ​​starts before the period of the DQS switching signal pair and ends after the period of the DQS switching signal pair. Figure 5 As shown, the test machine 120 at time point t e To time point t g During this period, the logic level of the data signal DQ (marked as enabled) is pulled down. At time point t e At time point t f Before time point t h At time point t g In some embodiments, at time t e Compared to time point t f Three tCK earlier and time point t h Compared to time point t g Three tCKs late.

[0073] Conversely, in order to disable (prohibit) the control circuit 112 from performing the enumerate ID operation, the tester 120 generates a data sequence of logic one values ​​to the memory device 110, wherein the data sequence of logic one values ​​starts before the period of the DQS switching signal pair and ends after the period of the DQS switching signal pair. Figure 5 As shown, the test machine 120 at time point t e To time point t g During this period, the data signal DQ (marked as disabled) is maintained at a high logic level.

[0074] In application, the tester 120 generates different data signals to the memory devices 110 to select a set of memory devices 110 to perform the enumerate ID operation. For example, when generating an ID command IDC1 to the memory devices (including the memory devices 110 of the sets g1-gn), the tester 120 generates a data signal DQ (marked as enabled) to the set g1 and generates a data signal DQ (marked as disabled) to the other sets (sets g2-gn). In this example, the memory devices 110 in the set g1 are enabled to write the ID of the ID command IDC1 to the mode register, while the memory devices 110 in the other sets (sets g2-gn) are prohibited from writing the ID to the mode register.

[0075] In some embodiments, the tester 120 generates different data signals according to the values ​​of the data array stored in the storage device 122. Each column of the data array includes an ID and a value (one or zero) corresponding to each memory device 110. For example, in the column of ID id1, the value corresponding to the memory device 110 of the set g1 is zero and the value corresponding to the other memory devices 110 is one. When the value corresponding to the memory device 110 in the column is zero / one ... at the time point t e To time point t h A data sequence having logic values ​​of zero / one is generated to the memory device 110 .

[0076] At time t after the enumerate ID operation o The tester 120 generates a multi-purpose instruction MPC2 to the memory device 110 to execute a PDA enumerate programming exit operation to terminate (exit) the PDA enumerate programming mode. After terminating the PDA enumerate programming mode, the memory device 110 is prohibited from executing the enumerate ID operation.

[0077] Figure 5 The ones shown are given for illustrative purposes. Figure 5Various implementations are within the contemplated scope of an embodiment of the present invention. For example, in some embodiments, the tester 120 generates more ID instructions before the multi-purpose instruction MPC2.

[0078] refer to Figure 6 . Figure 6 is a diagram of waveforms of an example of enumerate ID operation according to some embodiments of the present invention. Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 4 and Figure 5 For ease of understanding, Figure 6 Similar components in the present invention are marked with the same reference numerals. For the sake of brevity, the specific operations of similar components that have been discussed in detail in the above paragraphs are omitted herein.

[0079] In some embodiments, the tester 120 repeatedly generates different ID commands to the memory device 110 to write different IDs to the memory devices 110 of different sets (eg, sets g1-gn). Figure 6 As shown, the test machine 120 at time point t c Generate an ID command IDC1 to write the ID to the memory device 110 of the set g1 and at time point t c At the next time point t i Another ID is generated to the memory device 110 of the set g2.

[0080] Specifically, at time point t c- , the tester 120 generates an ID instruction IDC1 to the memory device 110 and the tester 120 generates a sequence of data having a value of logic zero (time point t e To time point t h The data signal DQ labeled “g1”) is sent to the memory device 110 of the set g1 to enable (allow) the set g1 to store the ID of the ID instruction IDC1 and generate a sequence of data having a value of logic one (time point t e To time point t h The data signal DQ marked “g2” is sent to the memory devices 110 of other sets (sets g2-gn) so that other sets cannot (prohibit) store the ID of the ID instruction IDC1.

[0081] Similarly, at time t h At the next time point t i , the tester 120 generates an ID instruction IDC2 to the memory device 110 and the tester 120 generates a sequence of data having a value of logic zero (eg, at time point t k To time point t nThe data signal DQ labeled “g2”) is sent to the memory device 110 of the set g2 to enable (allow) the set g2 to store the ID of the ID instruction IDC2 and generate a sequence of data having a value of logic one (e.g., time point t k To time point t n The data signal DQ marked “g1” is sent to the memory devices 110 of other sets (sets g1, g3-gn) to prevent (prohibit) other sets from storing the ID of the ID instruction IDC2.

[0082] Figure 6 The waveform diagram of the enumerate ID operation is provided for illustrative purposes. Various implementations of the waveform of the enumerate ID operation are within the contemplated scope of an embodiment of the present case. For example, in some embodiments, before the multi-purpose instruction MPC2, the tester 120 generates different ID instructions to write different IDs to the sets g3-gn respectively.

[0083] After generating the multi-purpose instruction MPC2 to leave the PDA enumeration programming mode, the tester 120 repeatedly generates a multi-purpose instruction including an operation code indicating a select ID operation to the memory device 110 to store different setting values ​​in different sets of memory devices 110. The multi-purpose instruction indicating an operation code of the select ID operation is also called a select instruction. For further details about the select instruction, please refer to Figure 6 Described below.

[0084] refer to Figure 7 . Figure 7 is a waveform diagram of an example of a select ID operation according to some embodiments of the present invention. Figure 1 , Figure 2 , Figure 3A , Figure 3B ,and Figures 4 to 6 For ease of understanding, Figure 7 Similar components in the present invention are marked with the same reference numerals. For the sake of brevity, the specific operations of similar components that have been discussed in detail in the above paragraphs are omitted herein.

[0085] For illustration, at time t after the memory device 110 ends the PDA enumeration programming mode, p , the tester 120 generates a select instruction SEL1 indicating an ID to the memory device 110. q To time point t r , the test machine 120 generates a DES instruction to the memory device 110. Then, at time point t r, the tester 120 generates a mode register write instruction MRW3 to the memory device 110. According to some embodiments, after receiving the select instruction SEL1, only the memory device whose ID stored in the mode register 113a is the same as the ID of the select instruction SEL1 is enabled (allowed) to perform the mode register write operation. For example, when the ID of the select instruction SEL1 is "0001", the control circuit 112 compares "0001" with the ID stored in the mode register 113a through the enumerate ID instruction. When the ID stored in the mode register 113a is equal to "0001", the control circuit 112 performs the mode register write operation in response to the mode register write instruction MRW3.

[0086] In some embodiments, the tester 120 selects a set (e.g., set g1) from the memory device 110 through a select instruction SEL1 and writes a setting value to the selected set through a mode register write instruction MRW3. For example, the tester 120 generates a select instruction SEL1 including an ID, the ID being equal to the ID stored in the set g1, and the tester 120 generates a mode register write instruction MRW3 to write a setting value v1 to the mode register 113c of the set g1.

[0087] After the setting value is written into the mode register 113c of the memory device 110, the tester 120 generates a select instruction SEL2 to the memory device 110, wherein the select instruction SEL2 indicates to select all IDs. In other words, after the memory device 110 receives the select instruction SEL2, no matter what ID is stored in the memory device 110, each memory device 110 performs a mode register write operation in response to the mode register write instruction.

[0088] Figure 7 The waveform diagram of the select ID operation is provided for illustrative purposes. Various implementations of the waveform of the select ID operation are within the contemplated scope of an embodiment of the present invention. For example, in some embodiments, the tester 120 generates different select instructions to respectively select the sets g3-gn according to the IDs id3-idn stored in the sets g3-gn before the select instruction SEL2.

[0089] In some embodiments, after setting the memory device 110 (writing the setting values ​​v1-vn to the set g1-gn), the tester 120 performs a test on the memory device 110 to detect defects. In the test, the tester 120 generates a write command to the memory device 110. The tester 120 outputs data to the memory device 110 through the data line (pin) 202 to write the data into the memory device 110. Then, the tester 120 generates a read command to the memory device 110 to obtain the read data through the data line (pin) 202. In some embodiments, the write command and the read command include the same memory address. In some embodiments, the tester 120 compares the write data written to the memory device 110 and the read data obtained from the memory device 110 to determine whether the memory device 110 has a defect. In some embodiments, when the write data written to the memory device 110 and the read data obtained from the memory device 110 match each other, the tester 120 determines that the memory device 110 functions normally.

[0090] refer to Figure 8 . Figure 8 is a flow chart of a method 800 according to some embodiments of the present invention. Figure 8 More operations may be provided before, between, and after the operations shown. Also, for other embodiments of method 800, some of the operations described below may be replaced or removed. At least some of the operations in method 800 may be used to perform operations such as Figure 1 , Figure 2 and Figure 4 The system 100 in FIG. 800 includes operations 801-803, which will be discussed below.

[0091] In operation 801, the tester 120 generates an ID command and a data signal DQ to store an ID in the memory device 110. In some embodiments, the tester 120 generates at least two different IDs (eg, ID id1 and ID id2).

[0092] In some embodiments, the memory device 110 stores the memory device 110 in the mode register 113 c of the memory device 110 .

[0093] In some embodiments, the test machine 120 also generates a data signal (eg, Figure 5 Mid-time point t e To time point t h A data signal DQ indicating “enable” is sent to the memory device 110 of the set g1 to store the ID id1.

[0094] In some embodiments, the test machine 120 also generates another data signal (eg Figure 5 Mid-time point t eTo time point t h A data signal DQ indicating “disable” is sent to the memory device 110 of the set g2 to disable the set g2 from storing the ID id1.

[0095] In some embodiments, the data signal (eg Figure 5 Mid-time point t e To time point t h The data signal DQ indicating “enable”) has a low logic level, and the other data signal (eg Figure 5 Mid-time point t e To time point t h The data signal DQ indicating "disable" has a high logic level.

[0096] In operation 802 , the tester 120 generates a mode register write command (eg, mode register write command MRW3 ) to the memory device 110 to set a time shift of an internal WL pulse of the memory device 110 based on an ID, wherein at least two time shifts corresponding to at least two different IDs are different from each other.

[0097] In some embodiments, the tester 120 generates a mode register write command to write a setting value to the memory device 110. For example, the tester 120 generates a mode register write command MRW3 to write a setting value v1 to the mode register 113c of the memory device 110 of the set g1.

[0098] In some embodiments, the test machine 120 generates setting values ​​v1-vn of the pattern register write instruction according to ID id1-idn through a scramble function, wherein the scramble function maps ID id1-idn to setting values ​​v1-vn. For example, after the test machine 120 generates a select instruction of ID id1, the test machine 120 generates setting value v1 according to ID id1 through the scramble function. Then, the test machine 120 generates a pattern register write instruction of setting value v1 to the memory device 110. In some embodiments, the scramble function maps ID id1-idn to setting values ​​v1-vn according to a data array in the storage device 122. For example, ID id1 and setting value v1 are stored in the same column of the data array.

[0099] In operation 803 , the tester 120 generates a test result based on the write data written to the memory device 110 and the read data obtained from the memory device 110 .

[0100] As described above, the present invention provides a test system and method for testing memory devices with different set values. By outputting different data signals to different memory devices, the tester selects some of the multiple memory devices to perform the PDAenumerate ID operation, while the unselected memory devices in these memory devices do not perform the operation. In this way, different IDs can be effectively written to different memory devices. Therefore, the tester can write different set values ​​to these different memory devices according to the different IDs of different memory devices. Since each memory device can be set to have the most suitable set value, the system and method of the present invention help to improve the performance of the test.

[0101] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of an embodiment of the present invention. Those skilled in the art should understand that an embodiment of the present invention can be easily used as a basis for designing or modifying other processes and structures to implement the same purpose and / or achieve the same advantages of the embodiments introduced in the present invention. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of an embodiment of the present invention, and various changes, substitutions and modifications can be performed in an embodiment of the present invention without departing from the spirit and scope of an embodiment of the present invention.

[0102]

Explanation of symbols

[0103] 100: System

[0104] 110: Memory device

[0105] 111: Memory array

[0106] 112: Control circuit

[0107] 113a: Mode register

[0108] 113b: Mode register

[0109] 113c: Mode register

[0110] 114: memory unit

[0111] 120: Testing machine

[0112] 121: Processor

[0113] 122: Storage device

[0114] 201: Bus

[0115] 202: Data line (pin)

[0116] 800: Method

[0117] 801-803: Operation

[0118] BL: Bit Line

[0119] CMD: Command

[0120] DES: Device deselect command

[0121] DQ: data signal

[0122] DQS_c: signal

[0123] DQS_t: signal

[0124] IDC1: Identity Command

[0125] IDC2: Identity Command

[0126] MPC1: Multi-Purpose Instructions

[0127] MPC2: Multi-Purpose Instructions

[0128] MRW1: Mode register write instruction

[0129] MRW2: Mode register write instruction

[0130] MRW3: Mode register write instruction

[0131] SEL1: Select instruction

[0132] SEL2: Select instruction

[0133] t1-t7: time point

[0134] t a -t u : Time point

[0135] v1-vn: setting value

[0136] g1-gn: collection

[0137] WL: Character Line

[0138] WRITE: write instruction.

Claims

1. A system for testing a memory device, characterized in that: Include: a plurality of memory devices, wherein each of the plurality of memory devices comprises a memory cell; as well as A test machine operatively coupled to the plurality of memory devices and configured to: generating a first multi-purpose command to the plurality of memory devices, and generating a first data signal to a first data pin of each of a first set of the plurality of memory devices to store first identity data in a plurality of first mode registers of the first set of the plurality of memory devices; generating a second multi-purpose command to the plurality of memory devices, and generating the first data signal to a second data pin of each of a second set of the plurality of memory devices to store second identity data in a plurality of second mode registers of the second set of the plurality of memory devices; generating a third multi-purpose instruction and a fourth multi-purpose instruction to the plurality of memory devices to respectively select the first set and the second set from the plurality of memory devices, and respectively make the write equalization pulses of the first set and the second set have a first time shift and a second time shift; transmitting write data to a plurality of data pins of the plurality of memory devices to perform a write operation on the plurality of memory devices, the plurality of data pins including the first and second data pins; as well as The read data is received from the plurality of data pins and the write data is compared with the read data to obtain a test result.

2. The system of claim 1, wherein the test machine is further configured to generate the third and fourth multi-purpose instructions to respectively select the first and second sets according to the first and second identity data of the first and second sets stored in the plurality of memory devices.

3. The system according to claim 1, wherein the tester is further used to generate a first mode register write instruction to the first and second sets of the multiple memory devices to store setting values ​​in multiple third mode registers of the first set of the multiple memory devices when the first set of the multiple memory devices is selected.

4. The system according to claim 1, wherein when the tester generates the first data signal to the first set of the multiple memory devices to store the first identity data, the tester is also used to generate a second data signal to the second data pin of each of the second sets of the multiple memory devices to prohibit the second set of the multiple memory devices from storing the first identity data.

5. The system of claim 1, wherein the first data signal and the second data signal are inversely proportional to each other.

6. The system of claim 1, wherein the testing machine comprises: A storage device for storing a data array, wherein each column of the data array comprises a plurality of values ​​and corresponding identity data, The testing machine is also used for: A plurality of signals corresponding to the plurality of values ​​are output to the plurality of data pins to select corresponding sets from the plurality of memory devices to store the corresponding identity data. 7 . The system of claim 6 , wherein each value of the plurality of values ​​is a first logical value or a second logical value.

8. The system according to claim 6, wherein the test machine is further configured to map the first and second identity data according to the data array to generate a first setting value and a second setting value, respectively, wherein the first and second setting values ​​are stored in the first and second sets of the plurality of memory devices, respectively.

9. A method for testing a memory device, characterized in that: Include: performing a first write-leveling training operation on the first memory device to obtain a first setting value; generating a first multi-purpose instruction to the first memory device and the second memory device to perform an enumerate identity operation to store first identity data; generating a first data sequence having a first logic value to the first memory device, wherein in response to the first data sequence, the first memory device is prohibited from performing the enumerate identity operation; generating a second multi-purpose instruction for selecting an identity operation to the first and second memory devices to select a corresponding memory device storing the first identity data; generating a mode register write instruction to the corresponding memory device to store the first setting value in the mode register of the corresponding memory device; Writing first data to the first and second memory devices; as well as reading the first and second memory devices to obtain second data and third data respectively; and The first data is compared with the second and third data to generate a test result.

10. The method according to claim 9, wherein: Also includes: A second data sequence having a second logic value is generated to the second memory device. The second memory device performs the enumeration identity operation in response to the second data sequence to store the first identity data in a mode register of the second memory device.

11. The method according to claim 10, wherein: Also includes: storing a data array, wherein a column of the data array comprises a first value and a second value which is the inverse of the first value, wherein the first value is the first logic value or the second logic value; A second data sequence having the first value is generated to the first memory device and a third data sequence having the second value is generated to the first memory device to select one of the first and second memory devices to store second identity data.

12. The method according to claim 9, wherein the first setting value is a value indicating a time shift amount of a write equalization pulse for starting a write operation.

13. A method for testing a memory device, characterized in that: Include: generating a plurality of identity instructions and a plurality of data signals to store a plurality of identity data in a plurality of memory devices, wherein the first identity data and the second identity data in the plurality of identity data are different from each other; generating a plurality of mode register write commands to the plurality of memory devices to set the plurality of memory devices to have a plurality of time shifts corresponding to the write equalization pulses based on the plurality of identity data, wherein a first time shift and a second time shift of the plurality of time shifts correspond to the first and second identity data respectively, and the first and second time shifts are different from each other; as well as A test result is generated based on the write data to the plurality of memory devices and the plurality of read data obtained from the plurality of memory devices. 14 . The method of claim 13 , wherein generating the plurality of mode register write commands comprises generating a first selection command to select a first set of memory devices storing the first identity data from among the plurality of memory devices. 15 . The method of claim 14 , wherein generating the plurality of mode register write commands further comprises writing a first setting value to a plurality of mode registers of the first memory device set. 16 . The method of claim 15 , wherein generating the mode register write command further comprises generating the first setting value according to the first identity data. 17 . The method of claim 13 , wherein the plurality of memory devices store the plurality of identity data in a plurality of mode registers of the plurality of memory devices.

18. The method of claim 13, wherein generating the plurality of identity commands and the plurality of data signals comprises: A first data signal is generated to a first set of memory devices among the plurality of memory devices to store the first identity data.

19. The method of claim 18, wherein generating the plurality of identity commands and the plurality of data signals comprises: A second data signal is generated to a second set of memory devices among the plurality of memory devices to prohibit the second set of memory devices among the plurality of memory devices from storing the first identity data.

20. The method of claim 19, wherein the first data signal has a low logic level and the second data signal has a high logic level.

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