A method for manufacturing a semiconductor device and a semiconductor device manufactured based thereon

Abstract

The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the following steps carried out in sequence: (1) a transistor structure forming step, (2) a shallow trench forming step, and (3) an electrical isolation structure forming step; the transistor manufacturing step includes the following operations: providing a substrate, forming a dual well region on the substrate, and manufacturing a transistor structure in the dual well region; the dual well region includes an adjacent first well region and a second well region, and before the shallow trench forming step, the first well region and the second well region always remain continuously connected; the shallow trench forming step includes the following operations: forming a shallow trench at the boundary between the first well region and the second well region; the electrical isolation structure forming step includes the following operations: depositing an isolation oxide on the surface of the dual well region to form a shallow trench isolation structure and an electrical isolation layer. By keeping the first well region and the second well region continuously connected, the diffusion of well ions in other regions of the first well region / second well region to the boundary between the first well region and the second well region is suppressed, and the region where the well ions are uniformly doped in the first well region and the second well region is broadened. Based on this, the effect of suppressing the threshold voltage drop of the semiconductor device is achieved. At the same time, the above operations are also beneficial to simplifying the manufacturing process of the semiconductor device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and specifically, relates to a method for manufacturing a semiconductor device and a semiconductor device manufactured based thereon. Background Art

[0002] The shallow trench isolation (STI) process is a commonly used process in integrated circuit manufacturing. The STI process refers to filling a groove provided in an active region with an isolation oxide to embed a very thick oxide between the active regions of the device, thereby forming electrical isolation in the active region and dividing the active region into well regions with different electrical properties through the STI structure.

[0003] When the integrated circuit manufacturing process develops to the deep sub-micron process technology, the electrical characteristics of the region near the well region edge are affected by the distance from the groove region of the device to the well boundary. This phenomenon is called the well proximity effect (WPE). The reason for the WPE effect is that during the well ion implantation process, the ions accelerated by the electric field are scattered and emitted at the photoresist boundary and side. The scattered and reflected ions will enter the surface of the STI structure, affecting the doping concentration in the region near the well boundary and causing the well ion doping concentration near the well boundary to be non-uniform. The well ion doping concentration varies with the distance from the well boundary. The well ion doping concentration in the region near the well boundary is greater than that in the middle region of the well region. In particular, the diffusion of boron ions doped in the P-well region is more obvious because boron ions are lighter. In addition, with the development of the integrated circuit manufacturing process, the types of well ions implanted in the well region are increasing, resulting in more significant non-uniform diffusion of well ions. The existence of the WPE effect causes the threshold voltage of the device to decrease. When the integrated circuit manufacturing process further develops to the nano-process technology, the influence of the WPE effect becomes more and more serious and its impact on the device cannot be ignored. Summary of the Invention

[0004] In order to suppress the non-uniform diffusion of well ions, the present invention provides a method for manufacturing a semiconductor device and a semiconductor device manufactured based thereon.

[0005] According to a first aspect of the present invention, there is provided a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the following steps carried out in sequence: (1) a transistor structure forming step, (2) a shallow trench forming step, and (3) an electrical isolation structure forming step; the transistor manufacturing step includes the following operations: providing a substrate, forming a dual-well region by performing an ion implantation process on the substrate, and manufacturing a transistor structure in the dual-well region; the dual-well region includes an adjacent first well region and a second well region, the first well region is of a first conductivity type, the second well region is of a second conductivity type, and before the shallow trench forming step, the first well region and the second well region always remain uninterruptedly connected; the shallow trench forming step includes the following operations: forming a shallow trench at the boundary between the first well region and the second well region, and the shallow trench is a groove for manufacturing a shallow trench isolation structure; the electrical isolation structure forming step includes the following operations: depositing an isolation oxide on the surface of the dual-well region, at least a part of the isolation oxide fills the inside of the shallow trench to form a shallow trench isolation structure, and at least a part of the isolation oxide covers the transistor structure to form an electrical isolation layer on the surface of the transistor structure.

[0006] In the above method for manufacturing a semiconductor device provided by the present invention, when the first well region and the second well region are in an uninterruptedly connected state, the regions near the boundary between the first well region and the second well region are all doped with well ions (referred to as "boundary well ions"). The presence of the boundary well ions inhibits the diffusion of well ions in other regions of the first well region / second well region to the above-mentioned boundary, reducing the diffusion dose of well ions to the above-mentioned boundary, thereby broadening the regions where the well ions are uniformly doped in the first well region and the second well region. As described above, before the shallow trench forming step, the first well region and the second well region always remain uninterruptedly connected. Based on this, it is beneficial for the first well region and the second well region to still maintain good well ion doping uniformity after experiencing multiple annealing processes during the manufacturing of the transistor structure. Of course, to a certain extent, the well ion doping concentration in the region near the boundary between the first well region and the second well region may still be slightly higher than that in other regions of the first well region and the second well region. However, when entering the shallow trench forming step, by etching the boundary between the first well region and the second well region to form a shallow trench here, the region with a higher well ion doping concentration is removed through the above etching operation. Thus, after forming the shallow trench, for the first well region and the second well region that still remain in the device, the doped well ions can be uniformly distributed within their respective well regions, thereby suppressing the threshold voltage drop of the semiconductor device. In the prior art, generally, the shallow trench is formed before forming well regions of different electrical properties. Compared with the well regions, since the content of well ions in the region where the shallow trench is located is lower, this promotes the diffusion of well ions to the shallow trench, and during the subsequent process of forming the transistor structure, multiple annealing treatments are still required. The annealing treatment will further exacerbate the diffusion of well ions, resulting in a decrease in the concentration of well ions in the working region of the device, and ultimately leading to a significant drop in the threshold voltage of the semiconductor device.

[0007] On the other hand, in the above semiconductor device manufacturing method provided by the present invention, the shallow trench isolation structure and the electrical isolation layer can be formed in one step by depositing isolation oxides in the electrical isolation structure forming step, which is equivalent to integrating the STI process for manufacturing the shallow trench isolation structure and the ILD process for manufacturing the electrical isolation layer in the prior art into one process. This not only simplifies the process steps but also reduces the process cost and improves the economic benefits of the process.

[0008] Preferably, a stress buffer layer preparation step is further provided between the shallow trench forming step and the electrical isolation structure forming step; the stress buffer layer preparation step includes the following operations: S1. A stress buffer layer is formed on the surface of the dual well region so that the surface of the transistor structure and the inner wall surface of the shallow trench are both covered by the stress buffer layer; S2. The device provided with the stress buffer layer is annealed. Based on the stress memory effect, the above stress buffer layer transfers the stress to the regions it covers through annealing, and the stress will be directly memorized by these regions, so that the effective mass of the electron conductance and the scattering probability along the shallow trench direction will both decrease, thereby effectively improving the carrier mobility and the speed of the semiconductor device. In the above solution, since the stress buffer layer directly covers the inner wall surface of the shallow trench, the stress of the stress buffer layer can be more fully transferred to the shallow trench. On the other hand, the stress buffer layer can also act as an etching barrier layer, protecting the surface of the transistor and the shallow trench, and preventing the well ions in the region near the boundary of the shallow trench from diffusing into the shallow trench, which is beneficial to further improving the doping uniformity of the well ions in the first well region and the second well region and regulating the threshold voltage of the semiconductor device. In summary, the above setting of the stress buffer layer can play a role equivalent to the Stress Memorization Technique (SMT) for the device, so there is no need to perform additional SMT processing during the device manufacturing process, and the process flow is simplified, while the performance of the semiconductor device can be improved.

[0009] Preferably, the stress covering layer preparation step includes a tensile stress covering area preparation step and / or a compressive stress covering area preparation step; the stress covering layer obtained through the tensile stress covering area preparation step satisfies that after annealing treatment, the stress covering layer transfers tensile stress to the device structure it covers; the stress covering layer obtained through the compressive stress covering area preparation step satisfies that after annealing treatment, the stress covering layer transfers compressive stress to the device structure it covers. The type of stress that the stress covering layer can provide can be adjusted by adjusting the preparation process of the stress covering layer and the raw materials used. For example, in the tensile stress covering area preparation process, through the PECVD process, using SiH4 and NH3 as film-forming raw materials, a Si3N4 film is prepared as the above stress covering layer, and the stress covering layer obtained thereby can transfer tensile stress to the device structure through annealing treatment. Another example is that in the compressive stress covering area preparation process, through the PECVD process with a dual-frequency RF power supply, using SiH4, NH3, H2, and Ar (or N2) as film-forming raw materials, a Si3N4 film is prepared as the above stress covering layer, and the stress covering layer obtained thereby can transfer compressive stress to the device structure through annealing treatment.

[0010] Preferably, in the annealing treatment involved in the above stress covering layer transferring compressive stress to the device structure it covers after annealing treatment, the annealing treatment method is laser annealing, the annealing temperature is 1200°C to 1300°C, and the annealing duration is 300 μs to 500 μs. In actual situations, single-beam laser annealing or double-beam laser annealing can be selected based on the actual situation. Preferably, during the annealing treatment, an electrostatic microdisk (E-chuck 400C) is used to fix the wafer. More preferably, the annealing temperature is 1250°C and the annealing duration is 400 μs.

[0011] Preferably, in the shallow trench forming step, the forming of the shallow trench is completed through lithography technology combined with dry etching.

[0012] Preferably, a carbon-containing polymer is filled on the surface of the wafer to form a flat carbon coating (ODL layer), then a photoresist layer is provided on the surface of the ODL layer, and through lithography technology, a notch corresponding to the preset position of the shallow trench is formed in the photoresist layer. Then, dry etching is further performed along the formed notch to complete the forming of the shallow trench, and finally, the photoresist layer and the mask are removed.

[0013] Preferably, an anti-reflection layer is also provided between the ODL layer and the photoresist layer, and when the photoresist layer is removed, the above anti-reflection layer is removed together. Preferably, the anti-reflection layer is a bottom anti-reflection layer.

[0014] Preferably, in the shallow trench forming step, after the shallow trench is formed, an oxide protection layer is formed on the inner groove wall surface of the shallow trench. The setting of the above oxide protection layer can repair the damage to the inner groove wall surface of the shallow trench involved in the etching operation in the shallow trench forming step.

[0015] Preferably, in the transistor structure forming step, the preparation of the transistor structure sequentially includes the following operations: a gate dielectric layer process to form a gate dielectric layer on the surface of the double-well region; a gate process to form a gate on the surface of the gate dielectric layer; a lightly doped ion implantation process to form a diffusion region in the well region below the boundary of the gate by means of ion implantation; an outer spacer process to form a first spacer structure on the side of the gate, and the first spacer structure covers the side of the gate; a source / drain ion implantation process to form a source region and a drain region below the boundary of the gate by means of ion implantation; a Salicide process to form a metal silicide overlay on the surfaces of the gate, the source region, and the drain region.

[0016] Preferably, the gate dielectric layer covers the surface of the double-well region.

[0017] Preferably, the gate process includes the following operations: sequentially disposing a polysilicon gate material layer, a first oxide layer, a Si3N4 thin film layer, a second oxide layer, an amorphous carbon layer, and an anti-reflection layer on the surface of the gate dielectric layer; placing a mask on the surface of the anti-reflection layer, and the mask covers the position where the gate needs to be formed, and removing the polysilicon gate material layer, the first oxide layer, the Si3N4 thin film layer, the second oxide layer, the amorphous carbon layer, and the anti-reflection layer except for the part corresponding to the position of the gate through lithography; removing the mask and removing the remaining parts of the second oxide layer, the amorphous carbon layer, and the anti-reflection layer above the polysilicon gate material remaining on the surface of the gate dielectric layer, so as to retain the polysilicon gate material on the surface of the gate dielectric layer as the gate.

[0018] Preferably, the anti-reflection layer includes a first anti-reflection layer and a second anti-reflection layer arranged in a stack, wherein the second anti-reflection layer is closer to the mask and the second anti-reflection layer is the bottom anti-reflection layer.

[0019] Preferably, an inner spacer process is further included between the gate process and the lightly doped ion implantation process; the inner spacer process includes the following operations: forming a second spacer structure on the side of the gate, and the second spacer structure is disposed between the side of the gate and the first spacer structure.

[0020] Preferably, the inner spacer process includes the following operations: first forming a SiO2 thin film layer on the side of the gate, removing the Si3N4 thin film layer on the upper surface of the gate, then depositing a Si3N4 thin film layer on the surface of the double-well region that completely covers the outer surface of the gate, and removing the Si3N4 thin film layer except for the part covering the side region of the gate, thereby forming a SiO2 thin film layer and a Si3N4 thin film layer stacked in sequence on the side of the gate, and the two thin film layers together constitute the second spacer structure, and the second spacer structure covers the side of the gate.

[0021] Preferably, the first sidewall structure includes a SiO2 thin film layer and a Si3N4 thin film layer stacked in sequence on the surface of the second sidewall structure.

[0022] Preferably, in the stress covering layer preparation step, in the shallow trench forming step, after forming the oxide protection layer, an ion implantation process is performed on the region adjacent to the shallow trench in the double-well region at the location of the shallow trench to adjust the threshold voltage of the semiconductor device.

[0023] Preferably, after the electrical isolation structure forming step is completed, a contact hole forming step is further included; the contact hole forming step includes the following operations: forming a through hole perpendicular to the substrate in the electrical isolation layer, and filling tungsten in the through hole.

[0024] According to the second aspect of the present invention, a semiconductor device prepared by using the above semiconductor device preparation method is provided.

[0025] Based on the above semiconductor device preparation method, the semiconductor device provided by this solution has high controllability of the threshold voltage, so that the semiconductor device has good electrical performance.

[0026] According to the third aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a substrate, a double-well region, a transistor structure, and isolation oxide. The double-well region is provided on the surface of the substrate. The double-well region includes an adjacent first well region and a second well region. The first well region is of a first conduction type, and the second well region is of a second conduction type. A groove is provided at the junction of the first well region and the second well region, and the groove is a shallow trench; at least a part of the isolation oxide fills the inside of the shallow trench, and this part of the isolation oxide forms a shallow trench isolation structure; at least a part of the isolation oxide covers the surface of the transistor structure, and this part of the isolation oxide forms an electrical isolation layer; the shallow trench isolation structure and the electrical isolation layer are integrally formed. Based on the above semiconductor device preparation method provided by the present invention, since the shallow trench isolation structure and the electrical isolation layer are integrally formed by depositing the isolation oxide in one step, therefore, in the semiconductor device obtained therefrom, the shallow trench isolation structure and the electrical isolation layer are integrally formed.

[0027] Preferably, the semiconductor device further includes a stress covering layer. A stress covering layer is provided between the inner groove wall of the shallow trench and the shallow trench isolation structure filling the shallow trench, and a stress covering layer is provided between the transistor structure and the electrical isolation layer covering it. Since the stress covering layer extends to the inner groove wall of the shallow trench, the shallow trench can be subjected to more sufficient stress, and the stress covering layer is in the same direction as the movement direction of the carriers, thereby effectively improving the speed of the semiconductor device.

[0028] Preferably, an oxide protection layer is further provided between the inner groove wall of the shallow trench and the stress covering layer.

[0029] Preferably, the material of the stress overlay includes at least one of Si3N4 and SiCN.

[0030] Preferably, the stress overlay includes at least one of a tensile stress overlay region and a compressive stress overlay region. The tensile stress overlay region transfers tensile stress to the covered region after annealing, and the compressive stress overlay region transfers compressive stress to the covered region after annealing.

[0031] The tensile stress overlay region generates uniaxial tensile stress in the

[100] direction of the channel of the N-type transistor structure (NMOS), thereby reducing the effective mass and scattering probability of electron conductance in the channel direction and improving the speed of the NMOS. The compressive stress overlay region generates uniaxial compressive stress in the

[100] direction of the channel of the P-type transistor structure (PMOS). The compressive stress in this direction can split the valence band energy band, causing the heavy hole band to leave the valence band top and the light hole band to occupy the valence band top, thereby reducing the effective mass of hole conductance in the channel direction and increasing the speed of the PMOS.

[0032] Preferably, the stress overlay includes a tensile stress overlay region, the transistor structure includes an N-type transistor structure, and at least a part of the stress overlay covering the surface of the N-type transistor structure is a tensile stress overlay region.

[0033] Preferably, the above semiconductor device satisfies at least one of the following a, b, c, d, and e:

[0034] a. The transistor structure includes an N-type transistor structure, the N-type transistor structure includes an N-type transistor structure I, and the stress overlay covering the surface of the N-type transistor structure I is all a tensile stress overlay region;

[0035] b. The transistor structure includes a P-type transistor structure, the P-type transistor structure includes a P-type transistor structure I, and the stress overlay covering the surface of the P-type transistor structure I is all a compressive stress overlay region;

[0036] c. The transistor structure includes an N-type transistor structure, the N-type transistor structure includes an N-type transistor structure II, and the stress overlay covering the side surface of the N-type transistor structure II includes a tensile stress overlay region and a compressive stress overlay region;

[0037] d. The transistor structure includes a P-type transistor structure, the P-type transistor structure includes a P-type transistor structure II, and the stress overlay covering the side surface of the P-type transistor structure II includes a tensile stress overlay region and a compressive stress overlay region;

[0038] e. The transistor structure includes a P-type transistor structure, the P-type transistor structure includes a P-type transistor structure III, and the stress overlay covering the surface of the P-type transistor structure III is all a tensile stress overlay region.

[0039] Preferably, on a plane parallel to the substrate, the arrangement direction of the adjacent first well region and the second well region is defined as the L direction, and the direction perpendicular to the L direction is defined as the W direction; and the above semiconductor device satisfies at least one of the following f and g:

[0040] f. The semiconductor device satisfies c, and the stress covering layer covering the side surface of the N-type transistor structure II includes a longitudinal covering layer extending along the L direction and a transverse covering layer extending along the W direction. The longitudinal covering layer is a tensile stress covering region, and the transverse covering layer is a compressive stress covering region;

[0041] g. The semiconductor device satisfies d, and the stress covering layer covering the side surface of the P-type transistor structure II includes a longitudinal covering layer extending along the L direction and a transverse covering layer extending along the W direction. The longitudinal covering layer is a tensile stress covering region, and the transverse covering layer is a compressive stress covering region.

[0042] In summary, compared with the prior art, the present invention has the following unexpected beneficial technical effects:

[0043] 1. The semiconductor device is processed according to the process of first preparing the well region, then forming the shallow trench and forming the electrical isolation structure in the shallow trench. Based on this, the well ions in different well regions of the semiconductor device can be evenly distributed in their respective well regions, thereby avoiding the decrease of the semiconductor threshold voltage caused by the diffusion of well ions into the shallow trench.

[0044] 2. Since the preparation of the well region has been completed before the shallow trench is prepared, the shallow trench isolation structure and the electrical isolation layer can be prepared at one time during the process of forming the electrical isolation structure, which simplifies the semiconductor manufacturing process and reduces the cost of semiconductor manufacturing.

[0045] 3. In the preferred embodiment of the present invention, by covering the inner groove wall surface of the shallow trench with a stress covering layer, the stress of the stress covering layer can be more fully transmitted to the shallow trench, which can effectively improve the speed of the semiconductor device. At the same time, the stress covering layer can also prevent the well ions in the region near the boundary of the shallow trench from diffusing into the shallow trench, which is beneficial to further improving the doping uniformity of the well ions in the first well region and the second well region.

[0046] 4. In the preferred embodiment of the present invention, by comprehensively considering the conductivity type of the transistor and the equipment requirements, stress covering layers applying different stress types are provided on the surface of the transistor and the inner groove surface of the shallow trench arranged around the transistor, so as to effectively improve the speed of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a process flow chart of the semiconductor device manufacturing method adopted in Embodiment 1;

[0048] Figure 2 Process flow diagram of the transistor forming step involved in Example 1;

[0049] Figure 3 Schematic diagram of the wafer structure obtained after the gate dielectric process involved in Example 1 is completed;

[0050] Figure 4 Schematic diagram of the wafer structure obtained after S2 in the gate process involved in Example 1 is completed;

[0051] Figure 5 Schematic diagram of the wafer structure obtained after the gate process involved in Example 1 is completed;

[0052] Figure 6 Schematic diagram of the wafer structure obtained after the inner sidewall process involved in Example 1 is completed;

[0053] Figure 7 Schematic diagram of the wafer structure obtained after the outer sidewall process involved in Example 1 is completed;

[0054] Figure 8 Schematic diagram of the wafer structure obtained after the transistor forming step involved in Example 1 is completed;

[0055] Figure 9 Schematic diagram of forming a shallow trench in the shallow trench forming step involved in Example 1;

[0056] Figure 10 Schematic diagram of the wafer structure obtained after S2 in the shallow trench forming step involved in Example 1 is completed;

[0057] Figure 11 Schematic diagram of the wafer structure obtained after S3 in the shallow trench forming step involved in Example 1 is completed;

[0058] Figure 12 Schematic diagram of the wafer structure obtained after the stress buffer layer preparation step involved in Example 1 is completed;

[0059] Figure 13 Schematic diagram of the wafer structure obtained after the electrical isolation structure forming step involved in Example 1 is completed;

[0060] Figure 14 Schematic diagram of the wafer structure obtained after the contact hole forming step involved in Example 1 is completed;

[0061] Figure 15 Top view cross-sectional schematic diagram of the wafer structure obtained after the stress buffer layer preparation step involved in Example 1 is completed;

[0062] Figure 16It is a top - down cross - sectional schematic diagram of the wafer structure obtained after the stress - covering layer preparation step in Embodiment 2;

[0063] Figure 17 It is a top - down cross - sectional schematic diagram of the wafer structure obtained after the stress - covering layer preparation step in Embodiment 3;

[0064] Figure 18 It is a top - down cross - sectional schematic diagram of the wafer structure obtained after the stress - covering layer preparation step in Embodiment 4.

[0065] In the above - mentioned drawings, the corresponding relationships of each reference numeral are as follows:

[0066] 1 - 11, the first well region; 1 - 12, the second well region; 1 - 2, the gate dielectric layer; 1 - 3, the PLDD region; 1 - 4, the NLDD region; 1 - 5, the p + heavily doped region; 1 - 6, the n + heavily doped region; 1 - 7, the P - type transistor structure; 1 - 8, the N - type transistor structure;

[0067] 2, the gate; 2 - 1, the polysilicon gate material layer; 2 - 2, the first oxide layer; 2 - 3, the Si3N4 thin film layer; 2 - 4, the second oxide layer; 2 - 5, the amorphous carbon layer; 2 - 6, the ARC anti - reflection layer; 2 - 7, the BARC bottom anti - oxidation layer; 2 - 8, the mask;

[0068] 3 - 1, the first sidewall structure; 3 - 2, the second sidewall structure; 3 - 3, the metal silicide covering layer;

[0069] 4, the shallow trench; 4 - 1, the ODL layer; 4 - 2, the bottom anti - reflection layer; 4 - 3, the photoresist layer; 4 - 4, the oxide protection layer;

[0070] 5 - 1, the compressive stress - covering layer; 5 - 2, the tensile stress - covering layer;

[0071] 6 - 1, the shallow trench isolation structure; 6 - 2, the electrical isolation layer;

[0072] 7 - 1, the via; 7 - 2, tungsten. Detailed implementation manners

[0073] Next, in combination with the drawings and specific implementation manners, the present invention will be further described:

[0074] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0075] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0076] Embodiment 1

[0077] This embodiment provides a method for fabricating a semiconductor device. As Figure 1 shown, the method for fabricating the semiconductor device includes a transistor structure forming step, a shallow trench forming step, a stress buffer layer preparing step, an electrical isolation structure forming step, and a contact hole forming step, which are sequentially performed in order.

[0078] As Figure 2 shown, the transistor forming step includes the preparation of the transistor structure, which sequentially includes a gate dielectric layer process, a gate process, an inner spacer process, a lightly doped ion implantation process, an outer spacer process, a source / drain ion implantation process, and a salicide process.

[0079] In the gate dielectric layer process, an oxide layer is deposited on the surface of the substrate, and then ion implantation is performed on the wafer to form a dual well region in the substrate region below the oxide layer. The oxide layer on the upper surface of the dual well region is removed, and then an oxide layer with a thickness of about 55 Å is redeposited on the surface of the dual well region as the gate dielectric layer 1-2. The wafer structure obtained thereby is as Figure 3 shown. In Figure 3 , the dual well region includes adjacent first well region 1-11 and second well region 1-12. The first well region 1-11 is an N well, and the second well region 1-12 is a P well, as Figure 3 schematically shown.

[0080] In the gate process, a gate electrode is formed on the surface of the gate dielectric layer. In the gate process, the following operations are specifically included:

[0081] S1. A polysilicon gate electrode material layer 2-1, a first oxide layer 2-2, a Si3N4 thin film layer 2-3, a second oxide layer 2-4, an amorphous carbon layer 2-5, an ARC anti-reflection layer 2-6, and a BARC bottom anti-oxidation layer 2-7 covering the gate dielectric layer are sequentially disposed on the surface of the gate dielectric layer 1-2, asFigure 4 as shown

[0082] S2. On the surface of the bottom anti-oxidation layer 2-7 of the BARC, a photoresist and a mask are formed corresponding to the position of the gate 2, and the pattern of the mask matches the position where the photoresist is set.

[0083] S3. Through lithography technology, remove the parts of the polysilicon gate material layer 2-1, the first oxide layer 2-2, the Si3N4 thin film layer 2-3, the second oxide layer 2-4, the amorphous carbon layer 2-5, the ARC anti-reflection layer 2-6, and the BARC bottom anti-oxidation layer 2-7 except for the part corresponding to the position of the gate 2.

[0084] S4. Remove the mask 2-8, and remove the remaining parts of the second oxide layer 2-4, the amorphous carbon layer 2-5, the ARC anti-reflection layer 2-6, and the BARC bottom anti-oxidation layer 2-7 above the polysilicon gate material remaining on the surface of the gate dielectric layer 1-2, so as to retain the polysilicon gate material on the surface of the gate dielectric layer 1-2 as the gate 2. The obtained wafer structure is as Figure 5 shown

[0085] In the inner sidewall process, it specifically includes the following operations:

[0086] S1. First, generate a SiO2 thin film layer on the side of the gate 2;

[0087] S2. Then, remove the Si3N4 thin film structure originally belonging to the Si3N4 thin film layer 2-3 on the upper surface of the gate 2;

[0088] S3. Deposit a Si3N4 thin film layer on the surface of the double-well region that completely covers the outer surface of the gate 2;

[0089] S4. Remove the part of the Si3N4 thin film layer except for the area covering the side of the gate, thereby forming a SiO2 thin film layer and a Si3N4 thin film layer stacked in sequence on the side of the gate. These two thin film layers together constitute the second sidewall structure 3-2, as Figure 6 shown

[0090] As Figure 7 , in the light doping ion implantation process, use the ion implantation process to form a diffusion region in the well region below the boundary of the gate. Specifically, perform the ion implantation process on the first well region 1-11 to sequentially implant Ge, C, AS, and BF2 in the first well region 1-11 to form the PLDD region 1-3, and perform the ion implantation process on the second well region 1-12 to sequentially implant Ge, C, B, N, P, and AS in the second well region to form the NLDD region 1-4.

[0091] In the outer wall process, referring to the inner wall process, a SiO2 thin film layer and a Si3N4 thin film layer are sequentially formed on the side of the gate, stacked on the surface of the second side wall structure 3-2, and the two thin film layers together form the first side wall structure 3-1, as Figure 7 shown.

[0092] In the source / drain ion implantation process, the source region and the drain region are formed under the boundary of the gate by using the ion implantation process. The first well region 1-11 is subjected to the ion implantation process to sequentially implant Ge, B, and BF2 in the first well region 1-11 to form the source region and the drain region of the PMOS transistor, marked as the p+ heavily doped region 1-5. The second well region 1-12 is subjected to the ion implantation process to sequentially implant P, Ge, P, As, and F in the second well region to form the source region and the drain region of the NMOS transistor, marked as the n+ heavily doped region 1-6.

[0093] In the Salicide process, a metal silicide overlay 3-3 is formed on the surfaces of the gate 2, the p+ heavily doped region 1-5, and the n+ heavily doped region 1-6.

[0094] The wafer structure obtained after the transistor forming step is as Figure 8 shown. From Figures 3 to 8 it can be clearly seen that after the formation of the first well region 1-11 and the second well region 1-12, until the completion of the transistor forming step, the first well region 1-11 and the second well region 1-12 always remain continuously connected. In fact, before the formation of the shallow trench 4, the first well region 1-11 and the second well region 1-12 always remain continuously connected.

[0095] When the first well region 1-11 and the second well region 1-12 are in a continuously connected state, the regions near the boundary between the first well region 1-11 and the second well region 1-12 are doped with well ions (referred to as "boundary well ions"). The presence of the boundary well ions inhibits the diffusion of well ions in other regions of the first well region 1-11 / second well region 1-12 to the above-mentioned boundary, reducing the diffusion dose of well ions to the above-mentioned boundary, thereby broadening the region where the well ions are uniformly doped in the first well region 1-11 and the second well region 1-12. As described above, since the first well region and the second well region always remain continuously connected, based on this, it is beneficial for the first well region 1-11 and the second well region 1-12 to still maintain good well ion doping uniformity after experiencing multiple annealings during the preparation of the transistor structure.

[0096] In the shallow trench forming step, the forming of the shallow trench is completed by combining lithography technology with dry etching. In this embodiment, the shallow trench forming step specifically includes the following operations:

[0097] S1. Fill the surface of the wafer structure with a carbon-containing polymer to form a flat carbon coating (ODL layer 4-1), then sequentially set a bottom anti-reflection layer 4-2 and a photoresist layer 4-3 on the surface of the ODL layer 4-1, and form a notch corresponding to the preset position of the shallow trench 4 in the photoresist layer through lithography technology, as Figure 9 .

[0098] S2. Further perform dry etching along the formed notch to complete the formation of the shallow trench 4, and finally remove the ODL layer 4-1, the bottom anti-reflection layer 4-2, and the photoresist layer 4-3. The formed shallow trench 4 is as Figure 10 shown.

[0099] S3. Use the ISSG process (In-Situ Steam Generation) to perform in-situ oxidation treatment on the inner groove wall of the shallow trench 4, so as to form an oxide protection layer 4-4 on the surface of the inner groove wall of the shallow trench 4, as Figure 11 shown. The setting of the above-mentioned oxide protection layer 4-4 can repair the damage to the surface of the inner groove wall of the shallow trench 4 caused by the etching operation involved in the shallow trench formation step.

[0100] To a certain extent, after the transistor formation step is completed, the well ion doping concentration in the region near the boundary between the first well region 1-11 and the second well region 1-12 may still be slightly higher than that in other regions of the first well region 1-11 and the second well region 1-12 while maintaining an uninterrupted connection. However, when entering the shallow trench formation step, by etching the boundary between the first well region 1-11 and the second well region 1-12 to form the shallow trench 4 here, the region with a higher well ion doping concentration is removed by the above-mentioned etching operation. Thus, after the shallow trench 4 is formed, for the first well region 1-11 and the second well region 1-12 that still remain in the device, the doped well ions can be evenly distributed within their respective well regions, thereby suppressing the threshold voltage drop of the semiconductor device.

[0101] Next, a stress overlay preparation step is carried out. The stress overlay preparation step includes a tensile stress overlay region preparation process, a compressive stress overlay region preparation process, and an annealing treatment. The compressive stress overlay region preparation process includes the following operations: above the first well region 1-11, through the PECVD process of a dual-frequency radio frequency power supply, using SiH4, NH3, H2, and Ar as film-forming raw materials, a Si3N4 thin film is prepared on the surface of the first well region 1-11 as the compressive stress overlay layer 5-1. The compressive stress overlay layer 5-1 covers the transistor structure located in the first well region 1-11 and the inner wall surface region of the shallow trench 4 adjacent to the edge of the first well region 1-11. The tensile stress overlay region preparation process includes the following operations: above the second well region 1-12, through the PECVD process, using SiH4 and NH3 as film-forming raw materials, a Si3N4 thin film is prepared on the surface of the second well region 1-12 as the tensile stress overlay layer 5-2. The obtained tensile stress overlay layer 5-2 covers the transistor structure located in the second well region 1-12 and the inner wall surface region of the shallow trench 4 adjacent to the edge of the second well region 1-12. Finally, the wafer structure provided with the stress overlay is annealed. The compressive stress overlay layer 5-1 transfers compressive stress to the transistor structure in the first well region 1-11 and the inner wall surface region of the shallow trench 4 it covers (the direction of the compressive stress is as shown by the arrow direction marked below the compressive stress overlay layer 5-1 in Figure 12 ), and the tensile stress overlay layer 5-2 transfers tensile stress to the transistor structure in the second well region 1-12 and the inner wall surface region of the shallow trench 4 it covers (the direction of the tensile stress is as shown by the arrow direction marked below the tensile stress overlay layer 5-2 in Figure 12 ).

[0102] Based on the stress memory effect, the above stress overlay transfers stress to the regions it covers through annealing treatment, and the stress will be directly memorized by these regions. As a result, both the effective mass of electron conductance and the scattering probability along the direction of the shallow trench 4 can be reduced, thereby effectively improving the carrier mobility and the speed of the semiconductor device. In the above solution, since the stress overlay directly covers the inner wall surface of the shallow trench 4, the stress of the stress overlay can be more fully transferred to the shallow trench 4. On the other hand, the stress overlay can also act as an etching barrier, protecting the surface of the transistor and the shallow trench 4, and preventing the well ions in the region near the boundary of the shallow trench 4 from diffusing into the shallow trench 4, which is beneficial to further improving the doping uniformity of the well ions in the first well region 1-11 and the second well region 1-12 and regulating the threshold voltage of the semiconductor device. In summary, the setting of the above stress overlay can play a role equivalent to the Stress Memorization Technique (SMT) for the device. Therefore, there is no need to perform additional SMT processing during the device manufacturing process, and the process flow is simplified. However, the performance of the semiconductor device can be improved.

[0103] Next, the wafer structure obtained after completing the stress overlay preparation step is processed in an electrical isolation structure forming step. The electrical isolation structure forming step specifically includes the following operations: Deposit isolation oxide (tetraethyl orthosilicate, TEOS) on the surface of the dual-well region of the wafer structure. A part of the isolation oxide fills the inside of the shallow trench 4 to form a shallow trench isolation structure 6-1, and a part of the isolation oxide fills the gap between the transistor structures to gradually form an electrical isolation layer 6-2 (HarpTEOS). Then continue to deposit isolation oxide to thicken the electrical isolation layer 6-2 (PE TEOS). Then, the electrical isolation layer 6-2 obtained after the above operations is planarized by a CMP process, and its thickness is adjusted to about 2100 Å. Then continue to deposit isolation oxide to thicken the electrical isolation layer 6-2 (Recap TEOS) until the thickness of the electrical isolation layer 6-2 reaches about 2700 Å, thus completing the preparation of the electrical isolation layer 6-2. The wafer structure obtained after the electrical isolation structure forming step is as Figure 13 shown.

[0104] In the electrical isolation structure forming step, the shallow trench isolation structure 6-1 and the electrical isolation layer 6-2 are formed in one step by depositing isolation oxide, which is equivalent to integrating the STI process for preparing the shallow trench isolation structure and the ILD process for preparing the electrical isolation layer in the prior art into one step process. This not only simplifies the process steps, but also reduces the process cost and improves the economic efficiency of the process. Based on the above process characteristics, in the wafer structure thus obtained, the shallow trench isolation structure 6-1 and the electrical isolation layer 6-2 are integrally formed.

[0105] Next, a contact hole forming step is performed on the wafer structure, which specifically includes forming a through hole 7-1 perpendicular to the substrate in the electrical isolation layer 6-2 and filling tungsten 7-2 in the through hole to obtain a structure as Figure 14 shown. Finally, the back-end process is continued on this wafer structure to complete the preparation of the semiconductor device.

[0106] In actual situations, after a series of semiconductor device processing steps are completed, a semiconductor device sample can be obtained by preparing a sample. Then, the threshold voltage of the semiconductor device sample is measured. If there is a deviation between the measured threshold voltage of the sample and the preset value, it can be considered that in the process of manufacturing a semiconductor device with the same process, after the oxide protection layer 4-4 is prepared in the trench forming step, an ion implantation process is performed on the regions of the first well region 1-11 and the second well region 1-12 adjacent to the shallow trench 4 at the location of the shallow trench 4, and then the stress covering layer preparation step is performed, so as to reduce the deviation between the threshold voltage of the semiconductor device thus manufactured and the preset value. If through testing the sample, the measured threshold voltage of the sample is basically at the same level as the preset value, there is no need to perform the above-mentioned supplementary ion implantation operation.

[0107] In this embodiment, based on the stress covering layer preparation step adopted, in the manufactured semiconductor device, the transistor structure located in the first well region 1-11 (denoted as the P-type transistor structure 1-7) and the inner groove wall surface region of the shallow trench 4 adjacent to the edge of the first well region 1-11 are covered by a compressive stress covering layer 5-1, and the transistor structure located in the second well region 1-12 (denoted as the N-type transistor structure 1-8) and the inner groove wall surface region of the shallow trench 4 adjacent to the edge of the second well region 1-12 are covered by a tensile stress covering layer 5-2. For clear display, in the process of manufacturing a semiconductor device in Embodiment 1, a top-view cross-sectional visual schematic diagram of the wafer structure obtained after the stress covering layer preparation step is as Figure 15 shown.

[0108] In other specific embodiments, referring to the above method provided in this embodiment to manufacture a semiconductor device, the preparation of the stress covering layer can also be omitted according to the actual situation.

[0109] Embodiment 2

[0110] This embodiment manufactures a semiconductor device by referring to the semiconductor device manufacturing method adopted in Embodiment 1. In the operation of manufacturing a semiconductor device in this embodiment, the difference from Embodiment 1 is that: in the stress covering layer preparation step, in this embodiment, a tensile stress covering layer 5-2 covering the first well region 1-11 and covering the second well region 1-12 is prepared on the surfaces of the first well region 1-11 and the second well region 1-12, so that the surfaces of the P-type transistor structure 1-7 located in the first well region 1-11, the N-type transistor structure 1-8 located in the second well region 1-12, and the inner groove wall surface of the shallow trench 4 at the interface between the first well region 1-11 and the second well region 1-12 are all covered by the tensile stress covering layer 5-2, wherein the process of the tensile stress covering layer 5-2 prepared in this embodiment is consistent with the preparation process of the tensile stress covering region recorded in Embodiment 1. Except for the above differences, other operations of manufacturing a semiconductor device in this embodiment are all consistent with the corresponding operations in Embodiment 1.

[0111] For clear illustration, a top-down cross-sectional visual schematic diagram of the wafer structure obtained after completing the stress overlay layer preparation step in this embodiment is as Figure 16 shown.

[0112] Example 3

[0113] In this example, a semiconductor device is prepared with reference to the semiconductor device preparation method adopted in Example 1. In the operation of preparing the semiconductor device in this example, the difference from Example 1 is that: in the stress overlay layer preparation step, in this example, a compressive stress overlay layer 5-1 is formed on the side surface and top surface extending along the W direction of the P-type transistor structure 1-7 in the first well region 1-11, on the side surface and top surface extending along the W direction of the N-type transistor structure 1-8 in the second well region 1-12, and on the inner wall surface of the shallow trench 4 at the interface between the first well region 1-11 and the second well region 1-12; a tensile stress overlay layer 5-2 is formed on the side surface extending along the L direction of the P-type transistor structure 1-7 in the first well region 1-11 and on the side surface extending along the L direction of the N-type transistor structure 1-8 in the second well region 1-12. Among them, the process of the compressive stress overlay layer 5-1 prepared in this example is consistent with the preparation process of the compressive stress overlay region recorded in Example 1, and the process of the tensile stress overlay layer 5-2 prepared in this example is consistent with the preparation process of the tensile stress overlay region recorded in Example 1. Except for the above differences, other operations of preparing the semiconductor device in this example are consistent with the corresponding operations in Example 1.

[0114] For clear illustration, a top-down cross-sectional visual schematic diagram of the wafer structure obtained after completing the stress overlay layer preparation step in this example is as Figure 17 shown. In Figure 17 , in a plane parallel to the substrate, the arrangement direction of the adjacent first well region 1-11 and second well region 1-12 is defined as the L direction, and the direction perpendicular to the L direction is defined as the W direction.

[0115] Example 4

[0116] In this embodiment, a semiconductor device is fabricated with reference to the semiconductor device fabrication method employed in Embodiment 1. In the operation of fabricating the semiconductor device in this embodiment, the differences from Embodiment 1 are as follows: In the stress cover layer fabrication step, in this embodiment, a compressive stress cover layer 5-1 is formed on the side surface and top surface extending along the W direction of the P-type transistor structure 1-7 located in the first well region 1-11, and on the inner wall surface region of the shallow trench 4 adjacent to the edge of the first well region 1-11; a tensile stress cover layer 5-2 is formed on the side surface extending along the L direction of the P-type transistor structure 1-7 located in the first well region 1-11, on the surface of the N-type transistor structure 1-8 located in the second well region 1-12, and on the inner wall surface region of the shallow trench 4 adjacent to the edge of the second well region 1-12. Among them, the process of fabricating the compressive stress cover layer 5-1 in this embodiment is consistent with the process of fabricating the compressive stress cover region described in Embodiment 1, and the process of fabricating the tensile stress cover layer 5-2 in this embodiment is consistent with the process of fabricating the tensile stress cover region described in Embodiment 1. Except for the above differences, all other operations of fabricating the semiconductor device in this embodiment are consistent with the corresponding operations in Embodiment 1.

[0117] For a clear display, a top-view cross-sectional visual schematic diagram of the wafer structure obtained after completing the stress cover layer fabrication step in this embodiment is as shown in Figure 18 . In Figure 18 , in a plane parallel to the substrate, the arrangement direction of the adjacent first well region 1-11 and second well region 1-12 is defined as the L direction, and the direction perpendicular to the L direction is defined as the W direction.

[0118] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the protection scope of the present invention. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced, but these modifications or replacements are all within the protection scope of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that: The method for fabricating the semiconductor device includes the following steps carried out in sequence: (1) a transistor structure forming step, (2) a shallow trench forming step, and (3) an electrical isolation structure forming step; The transistor fabrication step includes the following operations: providing a substrate, forming a dual-well region by performing an ion implantation process on the substrate, and fabricating a transistor structure in the dual-well region; the dual-well region includes an adjacent first well region and a second well region, the first well region is of a first conduction type, the second well region is of a second conduction type, and before performing the shallow trench forming step, the first well region and the second well region always remain uninterruptedly connected; The shallow trench forming step includes the following operations: forming a shallow trench at the boundary between the first well region and the second well region, and the shallow trench is a groove for fabricating a shallow trench isolation structure; The electrical isolation structure forming step includes the following operations: depositing an isolation oxide on the surface of the dual-well region, at least a part of the isolation oxide filling the inside of the shallow trench to form a shallow trench isolation structure, and at least a part of the isolation oxide covering the transistor structure to form an electrical isolation layer on the surface of the transistor structure.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: A stress cover layer preparation step is further provided between the shallow trench forming step and the electrical isolation structure forming step; The stress cover layer preparation step includes the following operations: S1. forming a stress cover layer on the surface of the dual-well region, so that the surface of the transistor structure and the inner wall surface of the shallow trench are both covered by the stress cover layer; S2. annealing the device provided with the stress cover layer.

3. A semiconductor device fabricated by using the method for fabricating a semiconductor device according to any one of claims 1 or 2.

4. A semiconductor device, characterized in that: The semiconductor device includes a substrate, a dual-well region, a transistor structure, and an isolation oxide. The dual-well region is provided on the surface of the substrate. The dual-well region includes an adjacent first well region and a second well region. The first well region is of a first conduction type, and the second well region is of a second conduction type. A groove is provided at the junction of the first well region and the second well region, and the groove is a shallow trench; At least a part of the isolation oxide fills the inside of the shallow trench, and this part of the isolation oxide forms a shallow trench isolation structure; At least a part of the isolation oxide covers the surface of the transistor structure, and this part of the isolation oxide forms an electrical isolation layer; The shallow trench isolation structure and the electrical isolation layer are integrally formed.

5. The semiconductor device according to claim 4, wherein: The semiconductor device further includes a stress cover layer. The stress cover layer is provided between the inner wall of the shallow trench and the shallow trench isolation structure filling the shallow trench, and the stress cover layer is provided between the transistor structure and the electrical isolation layer covering it.

6. The semiconductor device according to claim 5, wherein: An oxide protection layer is further provided between the inner wall of the shallow trench and the stress cover layer.

7. The semiconductor device according to claim 5, wherein: The stress covering layer includes at least one of a tensile stress covering area and a compressive stress covering area. The tensile stress covering area transfers tensile stress to the area it covers after annealing treatment, and the compressive stress covering area transfers compressive stress to the area it covers after annealing treatment.

8. The semiconductor device according to claim 7, wherein: The stress covering layer includes the tensile stress covering area, and the transistor structure includes an N-type transistor structure. At least a part of the stress covering layer covering the surface of the N-type transistor structure is the tensile stress covering area.

9. The semiconductor device according to claim 7, wherein It satisfies at least one of the following a, b, c, d, and e: a. The transistor structure includes an N-type transistor structure, and the N-type transistor structure includes an N-type transistor structure I. The stress covering layer covering the surface of the N-type transistor structure I is all the tensile stress covering area; b. The transistor structure includes a P-type transistor structure, and the P-type transistor structure includes a P-type transistor structure I. The stress covering layer covering the surface of the P-type transistor structure I is all the compressive stress covering area; c. The transistor structure includes an N-type transistor structure, and the N-type transistor structure includes an N-type transistor structure II. The stress covering layer covering the side surface of the N-type transistor structure II includes the tensile stress covering area and the compressive stress covering area; d. The transistor structure includes a P-type transistor structure, and the P-type transistor structure includes a P-type transistor structure II. The stress covering layer covering the side surface of the P-type transistor structure II includes the tensile stress covering area and the compressive stress covering area; e. The transistor structure includes a P-type transistor structure, and the P-type transistor structure includes a P-type transistor structure III. The stress covering layer covering the surface of the P-type transistor structure III is all the tensile stress covering area.

10. The semiconductor device according to claim 9, wherein: On a plane parallel to the substrate, the arrangement direction of the adjacent first well region and the second well region is the L direction, and the direction perpendicular to the L direction is the W direction; And the semiconductor device satisfies at least one of the following f and g: f. The semiconductor device satisfies c. The stress covering layer covering the side surface of the N-type transistor structure II includes a longitudinal covering layer extending along the L direction and a transverse covering layer extending along the W direction. The longitudinal covering layer is the tensile stress covering area, and the transverse covering layer is the compressive stress covering area; g. The semiconductor device satisfies d. The stress covering layer covering the side surface of the P-type transistor structure II includes a longitudinal covering layer extending along the L direction and a transverse covering layer extending along the W direction. The longitudinal covering layer is the tensile stress covering area, and the transverse covering layer is the compressive stress covering area.

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