Preparation Method of Hybrid Bonding Structure and Semiconductor Device

Abstract

The present invention provides a method for preparing a hybrid bonding structure and a semiconductor device. The method includes: providing at least two bonding structures to be bonded, the top of the bonding structure to be bonded including a dielectric layer and a metal lead-out structure penetrating the dielectric layer along a first direction perpendicular to the top surface of the dielectric layer; performing a first chemical mechanical polishing process to make the top surface of the metal lead-out structure protrude from the top surface of the dielectric layer; performing a second chemical mechanical polishing process to make both ends of the metal lead-out structure flush with the top surface of the dielectric layer and form a dish-shaped depression on the top surface of the metal lead-out structure; performing plasma treatment on the top surface of the dielectric layer and the top surface of the metal lead-out structure to obtain an intermediate bonding structure; and hybrid bonding at least two of the intermediate bonding structures to form a hybrid bonding structure. This method avoids the formation of unbonded regions and bubbles during the bonding process and improves the yield of hybrid bonding.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technologies, and particularly to a method for preparing a hybrid bonding structure and a semiconductor device. Background Art

[0002] In the case where the development of very large scale integrated circuits is increasingly approaching the physical limit, three-dimensional integrated circuits, which have advantages in terms of physical size and cost, are an effective way to extend Moore's law and solve advanced packaging problems. Among them, hybrid bonding technology can achieve internal interconnection of thousands of chips while bonding two wafers, which can greatly improve chip performance and save costs.

[0003] The difficulty of hybrid bonding technology lies in achieving internal interconnection of metals and maintaining a high yield of this interconnection. Since hybrid bonding technology interconnects multiple chips on a wafer simultaneously, and there are height differences at the bonding interface. Among them, in some areas, the metal is higher than the bonding interface, resulting in bonding failure and forming un-bonded areas, and in other areas, the metal is lower than the bonding interface, and bubbles appear after bonding. Both of them lead to a reduction in the yield of hybrid bonding. Summary of the Invention

[0004] Based on this, in view of the problems in the above background art, it is necessary to provide a method for preparing a hybrid bonding structure and a semiconductor device, which can at least avoid forming un-bonded areas and bubbles during hybrid bonding and improve the yield of hybrid bonding.

[0005] To achieve the above object and other related objects, one aspect of the present application provides a method for preparing a hybrid bonding structure, including the following steps:

[0006] Provide at least two structures to be bonded, the top of the structure to be bonded includes a dielectric layer, and a metal lead-out structure penetrating the dielectric layer along a first direction perpendicular to the top surface of the dielectric layer;

[0007] Perform a first chemical mechanical polishing process to make the top surface of the metal lead-out structure protrude from the top surface of the dielectric layer;

[0008] Perform a second chemical mechanical polishing process to make both ends of the metal lead-out structure flush with the top surface of the dielectric layer, and form a dish-shaped depression on the top surface of the metal lead-out structure;

[0009] Perform plasma treatment on the top surface of the dielectric layer and the top surface of the metal lead-out structure to obtain an intermediate bonding structure;

[0010] Hybrid bond at least two of the intermediate bonding structures to form a hybrid bonding structure.

[0011] In one embodiment, during the execution of the first chemical mechanical polishing process, the removal rate of the dielectric layer is greater than the removal rate of the metal lead-out structure; during the execution of the second chemical mechanical polishing process, the removal rate of the metal lead-out structure is greater than the removal rate of the dielectric layer.

[0012] In one embodiment, the selectivity ratio range of the first polishing liquid of the first chemical mechanical polishing process for the dielectric layer and the metal lead-out structure includes 5:1 to 7:1, and the selectivity ratio range of the second polishing liquid of the second chemical mechanical polishing for the dielectric layer and the metal lead-out structure includes 2:1 to 4:1; the selectivity ratio of the first polishing liquid for the dielectric layer and the metal lead-out structure is higher than the selectivity ratio of the second polishing liquid for the dielectric layer and the metal lead-out structure.

[0013] In one embodiment, the content of H2O2 in the first polishing liquid of the first chemical mechanical polishing process is not higher than 0.8%, and the content of H2O2 in the second polishing liquid of the second chemical mechanical polishing is not lower than 1.2%; the content of H2O2 in the second polishing liquid is higher than the content of H2O2 in the first polishing liquid.

[0014] In one embodiment, the dielectric layer includes a first tetraethyl orthosilicate layer, a nitrogen-doped silicon carbide layer, and a second tetraethyl orthosilicate layer stacked in sequence along the first direction, and the first chemical mechanical polishing process is used to remove the second tetraethyl orthosilicate layer and part of the nitrogen-doped silicon carbide layer.

[0015] In one embodiment, performing plasma treatment on the top surface of the dielectric layer and the top surface of the metal lead-out structure to obtain an intermediate bonding structure includes: performing plasma treatment on the top surface of the dielectric layer to form open chemical bonds for bonding on the top surface of the dielectric layer; and performing plasma treatment on the top surface of the metal lead-out structure to adjust the depth of the dish-shaped depression.

[0016] In one embodiment, the height range of the top surface of the metal lead-out structure protruding above the top surface of the dielectric layer includes 300 Å to 400 Å, and the depth range of the dish-shaped depression includes 10 Å to 30 Å.

[0017] In one embodiment, after forming the hybrid bonding structure, the following steps are further included: annealing the hybrid bonding structure to cause the metal lead-out structure to expand and fill the dish-shaped depression.

[0018] In one embodiment, the polishing rotation speeds of the first chemical mechanical polishing process and the second chemical mechanical polishing process include 30 rpm to 80 rpm.

[0019] Another aspect of the present application further provides a hybrid bonding structure, which is prepared by using the preparation method of the hybrid bonding structure described in any one of the above.

[0020] According to the preparation method of the hybrid bonding structure and the semiconductor device provided by the present invention, the unexpected technical effect of the present application is as follows: for a bonding interface with height differences, first, the top surface of the metal lead-out structure protrudes from the top surface of the dielectric layer through the first chemical mechanical polishing process, and then the two ends of the metal lead-out structure are flush with the top surface of the dielectric layer through the second chemical mechanical polishing process, avoiding the formation of unbonded regions during the subsequent bonding process. At the same time, a dish-shaped depression is formed on the top surface of the metal lead-out structure through the second chemical mechanical polishing process and the depth of the dish-shaped depression is controlled to ensure that the dish-shaped depression is filled after the hybrid bonding structure is formed, avoiding the formation of bubble regions and improving the yield of hybrid bonding. Description of the Drawings

[0021] To better describe and illustrate the embodiments and / or examples of those applications disclosed herein, one or more drawings may be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the presently described embodiments and / or examples, and the presently understood best mode of these applications.

[0022] Figure 1 It is a schematic flow chart of a preparation method of a hybrid bonding structure provided in an embodiment;

[0023] Figure 2 It is a schematic cross-sectional structure diagram of the obtained structure after forming the metal lead-out structure in a preparation method of a hybrid bonding structure provided in an embodiment;

[0024] Figure 3 It is a schematic cross-sectional structure diagram of the obtained structure after performing the first chemical mechanical polishing process in a preparation method of a hybrid bonding structure provided in an embodiment;

[0025] Figure 4 It is a schematic cross-sectional structure diagram of the obtained structure after performing the second chemical mechanical polishing process in a preparation method of a hybrid bonding structure provided in an embodiment;

[0026] Figure 5 It is a schematic cross-sectional structure diagram of performing plasma treatment in a preparation method of a hybrid bonding structure provided in an embodiment;

[0027] Figure 6 It is a schematic cross-sectional structure diagram of the obtained structure after performing hybrid bonding in a preparation method of a hybrid bonding structure provided in an embodiment;

[0028] Figure 7Schematic cross-sectional view of the resulting structure after annealing in a method for preparing a hybrid bonding structure provided in an embodiment.

[0029] Description of reference numerals:

[0030] 100, wafer; 110, dielectric layer; 110a, first tetraethyl orthosilicate layer; 110b, nitrogen-doped silicon carbide layer; 110c, second tetraethyl orthosilicate layer; 120, barrier layer; 130, metal lead-out structure. Detailed implementation manners

[0031] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0033] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, without departing from the teachings of this application, the first element, component, region, layer or part discussed below can be denoted as the second element, component, region, layer or part.

[0034] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are also intended to encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under other elements" or "beneath them" or "under it" will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0035] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0036] Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application. As such, variations from the shapes as illustrated, for example due to manufacturing techniques and / or tolerances, are to be expected. Accordingly, embodiments of the present application should not be limited to the particular shapes of the regions shown herein but include shape deviations due to, for example, manufacturing. The regions shown in the figures are substantially schematic and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present application.

[0037] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present application. Although only the components related to the present application are shown in the illustrations and are not drawn according to the number, shape, and size of the components in actual implementation, the types, quantities, and proportions of the components in actual implementation may be arbitrarily changed, and the component layout type may also be more complex.

[0038] The difficulty of hybrid bonding technology lies in achieving internal interconnection of metals and maintaining a high yield of such interconnection. Since the hybrid bonding technology interconnects multiple chips on a wafer simultaneously, and there are height differences at the bonding interface. Among them, in some areas, the metal is higher than the bonding interface, resulting in bonding failure and the formation of un-bonded areas. In other areas, the metal is lower than the bonding interface, and bubbles appear after bonding. Both of them lead to a reduction in the yield of hybrid bonding.

[0039] To address the above problems, the present invention provides a method for preparing a hybrid bonding structure, as Figure 1 shown, including the following steps:

[0040] Step S101: Provide at least two structures to be bonded. The top of the structure to be bonded includes a dielectric layer and a metal lead-out structure that penetrates the dielectric layer along a first direction perpendicular to the top surface of the dielectric layer;

[0041] Step S102: Perform a first chemical mechanical polishing process to make the top surface of the metal lead-out structure protrude from the top surface of the dielectric layer;

[0042] Step S103: Perform a second chemical mechanical polishing process to make the two ends of the metal lead-out structure flush with the top surface of the dielectric layer and form a dish-shaped depression on the top surface of the metal lead-out structure;

[0043] Step S104: Perform plasma treatment on the top surface of the dielectric layer and the top surface of the metal lead-out structure to obtain an intermediate bonding structure;

[0044] Step S105: Hybrid bond at least two of the intermediate bonding structures to form a hybrid bonding structure.

[0045] In one embodiment, two wafers 100 are provided, and multiple chips are formed in each wafer 100. A dielectric layer 110 is formed on the top of each wafer 100, and a metal lead-out structure 130 that penetrates the dielectric layer along a first direction perpendicular to the top surface of the dielectric layer is formed in the dielectric layer 110 to form two structures to be bonded.

[0046] In one embodiment, the dielectric layer 110 includes a first tetraethyl orthosilicate layer 110a (TEOS), a nitrogen-doped silicon carbide layer 110b (NDC), and a second tetraethyl orthosilicate layer 110c (TEOS) that are sequentially stacked on the wafer 100. Specifically, the thickness range of the first tetraethyl orthosilicate layer 110a includes 4000 Å to 6000 Å, such as 4000 Å, 5000 Å, 6000 Å, preferably 5000 Å. The thickness range of the nitrogen-doped silicon carbide layer 110b includes 800 Å to 1200 Å, such as 800 Å, 1000 Å, 1200 Å, preferably 1000 Å. The thickness range of the second tetraethyl orthosilicate layer 110c includes 200 Å to 400 Å, such as 200 Å, 300 Å, 400 Å, preferably 300 Å. The method of forming the first tetraethyl orthosilicate layer 110a, the nitrogen-doped silicon carbide layer 110b, and the second tetraethyl orthosilicate layer 110c can use chemical vapor deposition (CVD), such as one of low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE).

[0047] In one embodiment, the metal lead-out structure 130 penetrates through the dielectric layer 110 along a first direction perpendicular to the top surface of the dielectric layer 110. To form the metal lead-out structure 130, a via hole that penetrates through the dielectric layer along the first direction perpendicular to the top surface of the dielectric layer is first formed by a photolithography process. Specifically, a patterned mask layer is formed on the dielectric layer 110, and the dielectric layer 110 is etched using the patterned mask layer as a mask until the surface of the wafer 100 is exposed, thereby forming a via hole that penetrates through the dielectric layer 110. The method for etching the dielectric layer 110 includes an anisotropic dry etching process, and the dry etching process includes, but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching, or laser ablation. A single etching method can be used, or more than one etching method can also be used. Next, a barrier layer 120 is formed on the bottom and sidewalls of the via hole. Specifically, a barrier layer 120 covering the top surface of the dielectric layer 110, the sidewalls of the via hole, and the bottom of the via hole can be formed by processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The material of the barrier layer 120 includes, but is not limited to, tantalum (Ta), tantalum nitride (TaN), etc. Next, a metal material layer is formed to fill the via hole, so as to form a metal lead-out structure 130 in the via hole, and the metal lead-out structure 130 is connected to the interconnect layer of the wafer chip. Specifically, a metal material layer covering the top surface of the dielectric layer 110 and filling the via hole can be formed by processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The metal material layer includes, but is not limited to, copper. Next, chemical mechanical polishing (CMP) is performed for bulk polishing to remove the metal material layer and the barrier layer 120 located on the top surface of the dielectric layer 110. Since a large amount of metal material needs to be removed during the bulk polishing stage, in order to accelerate the removal speed, the chemical mechanical polishing uses a high rotation speed, such as greater than 80 rpm, preferably 93 rpm, 97 rpm. However, high-speed polishing is likely to cause non-uniform polishing effects in different regions of the wafer. As shown in Figure 2 As shown, there is a problem of height difference at the bonding interfaces in different regions. The top surface of a part of the metal lead-out structure 130 is higher than the top surface of the dielectric layer 110. If directly bonded, an un-bonded area will be formed. The top surface of another part of the metal lead-out structure 130 is lower than the top surface of the dielectric layer 110. If directly bonded, bubbles will be formed.

[0048] Next, step S102 is executed. Referring to Figure 3 As shown, a first chemical mechanical polishing process is executed to make the top surface of the metal lead-out structure 130 protrude from the top surface of the dielectric layer 110.

[0049] In one embodiment, during the execution of the first chemical mechanical polishing process, in order to make the top surfaces of all the metal lead-out structures 130 protrude from the top surface of the dielectric layer 110, the removal rate of the dielectric layer 110 should be greater than that of the metal lead-out structures 130. To achieve a removal rate of the dielectric layer 110 greater than that of the metal lead-out structures 130, the selectivity ratio of the first polishing slurry for the first chemical mechanical polishing process with respect to the dielectric layer 110 and the metal lead-out structures 130 ranges from 5:1 to 7:1, such as 5:1, 6:1, or 7:1, preferably 6:1. To achieve the above selectivity ratio, the H2O2 content in the first polishing slurry for the first chemical mechanical polishing process is not higher than 0.8%, such as 0.6%, 0.7%, 0.8%, etc., preferably 0.8%.

[0050] In one embodiment, when the top surfaces of all the metal lead-out structures 130 protrude from the top surface of the dielectric layer 110, the height uniformity of the metal lead-out structures 130 can be achieved through the mechanical polishing effect of the first chemical mechanical polishing process on the top surfaces of the metal lead-out structures 130 with different heights. The range of the polishing rotation speed of the first chemical mechanical polishing process is from 30 rpm to 80 rpm, such as 30 rpm, 50 rpm, 80 rpm, preferably 50 rpm, 53 rpm. By using a low rotation speed in the first chemical mechanical polishing process, the polishing effect in different regions of the wafer can be made more uniform, not only making the top surfaces of the metal lead-out structures 130 protrude from the top surface of the dielectric layer 110, but also ensuring that the heights of the top surfaces of the metal lead-out structures 130 protruding from the top surface of the dielectric layer 110 are the same or similar.

[0051] Furthermore, for the dielectric layer 110 composed of the first tetraethyl orthosilicate layer 110a, the nitrogen-doped silicon carbide layer 110b, and the second tetraethyl orthosilicate layer 110c, the first chemical mechanical polishing process completely removes the first tetraethyl orthosilicate layer 110a and removes a part of the nitrogen-doped silicon carbide layer 110b, and the thickness range of the removed nitrogen-doped silicon carbide layer 110b is from 150 Å to 200 Å. In this way, after the execution of the first chemical mechanical polishing process, the height range of the top surfaces of the metal lead-out structures 130 protruding from the top surface of the dielectric layer 110 is from 300 Å to 400 Å.

[0052] By executing the first chemical mechanical polishing process, bonding interfaces with height differences in different regions of the wafer are all formed into bonding interfaces where the top surfaces of the metal lead-out structures 130 protrude from the top surface of the dielectric layer 110, and the height range of the metal lead-out structures 130 protruding from the dielectric layer 110 is controlled to be the same or similar. Although the bonding interfaces formed after the execution of the first chemical mechanical polishing process cannot be directly used for bonding, and direct bonding will cause un-bonded problems, the homogenization treatment of the bonding interfaces with height differences is achieved.

[0053] Next, step S103 is executed. Refer to Figure 4 As shown, a second chemical mechanical polishing process is performed to make both ends of the metal lead-out structure flush with the top surface of the dielectric layer, and a dish-shaped depression is formed on the top surface of the metal lead-out structure.

[0054] In one embodiment, during the execution of the second chemical mechanical polishing process, by making the removal rate of the metal lead-out structure 130 greater than that of the dielectric layer 110, it is possible to achieve that the top surface of the metal lead-out structure 130 changes from protruding above the top surface of the dielectric layer 110 to being flush with the top surface of the dielectric layer 110 at both ends. To achieve a removal rate of the metal lead-out structure 130 greater than that of the dielectric layer 110, the selectivity ratio of the second polishing liquid to the dielectric layer 110 and the metal lead-out structure 130 is lower than the selectivity ratio of the above-mentioned first polishing liquid to the dielectric layer 110 and the metal lead-out structure 130. Specifically, the selectivity ratio range of the second polishing liquid of the second chemical mechanical polishing process to the nitrogen-doped silicon carbide layer 110b in the dielectric layer 110 and the metal lead-out structure 130 includes 2:1 to 4:1, such as 2:1, 2.7:1, 3.8:1, or 4:1, preferably 2.7:1 or 3.8:1. To achieve the above selectivity ratio, the H2O2 content in the second polishing liquid is higher than the H2O2 content in the first polishing liquid, and the H2O2 content in the second polishing liquid of the second chemical mechanical polishing process is not less than 1.2%, such as 1.2%, 1.3%, 1.4%, etc., preferably 1.2%.

[0055] In one embodiment, the polishing rotation speed of the second chemical mechanical polishing process includes 30 rpm to 80 rpm, such as 30 rpm, 50 rpm, 80 rpm, preferably 50 rpm, 53 rpm. By using a low rotation speed in the second chemical mechanical polishing process, the polishing effect in different regions of the wafer can be made more uniform, not only making both ends of the metal lead-out structure 130 flush with the top surface of the dielectric layer 110, but also making the depths of the dish-shaped depressions formed on the top surface of the metal lead-out structure 130 the same or similar. Specifically, the depth range of the dish-shaped depressions includes 10 Å to 30 Å, such as 10 Å, 20 Å, 30 Å, etc.

[0056] By performing the second chemical mechanical polishing process, the situation where the top surface of the metal lead-out structure 130 protrudes from the top surface of the dielectric layer 110 in different regions of the wafer is eliminated, avoiding the problem of un-bonded in subsequent bonding. The second chemical mechanical polishing process makes the two ends of the metal lead-out structure 130 flush with the top surface of the dielectric layer 110. It is a further homogenization treatment of the bonding interface with height difference on the basis of the homogenization treatment of the bonding interface with height difference by the first chemical mechanical polishing process, and its control accuracy is higher than that of the first chemical mechanical polishing step. Therefore, not only can the two ends of the metal lead-out structure 130 be made flush with the top surface of the dielectric layer 110, but also the depth range of the dish-shaped depression of the metal lead-out structure 130 can be controlled.

[0057] Next, step S104 is performed. Referring to Figure 5 As shown, plasma treatment is performed on the top surface of the dielectric layer 110 and the top surface of the metal lead-out structure 130 to obtain an intermediate bonding structure. Among them, the plasma treatment is used for: (1) performing plasma treatment on the top surface of the dielectric layer 110 to form open chemical bonds for bonding on the top surface of the dielectric layer 110; (2) performing plasma treatment on the top surface of the metal lead-out structure 130 to adjust the depth of the dish-shaped depression.

[0058] In one embodiment, the gas used for plasma treatment includes nitrogen, oxygen, hydrogen, etc. Preferably, nitrogen plasma is used to treat the top surface of the dielectric layer 110, and then the surface treated by plasma is rinsed with deionized water (DIW) to form open chemical bonds (-O-H) for bonding. Since the bonding performance of the NDC layer after plasma treatment is better than that of the TEOS layer after plasma treatment, the dielectric layer 110 adopts a stacked structure of a first tetraethyl orthosilicate layer 110a, a nitrogen-doped silicon carbide layer 110b, and a second tetraethyl orthosilicate layer 110c. And in step S102, the second tetraethyl orthosilicate layer 110c and part of the nitrogen-doped silicon carbide layer 110b are removed to expose the nitrogen-doped silicon carbide layer 110b as the bonding surface, and plasma treatment is performed on it for subsequent bonding.

[0059] In one embodiment, plasma treatment is performed on the top surface of the metal lead-out structure 130 to adjust the depth of the dish-shaped depression. Before performing plasma treatment on the top surface of the metal lead-out structure 130, first measure the depth of the dish-shaped depression on the top surface of the metal lead-out structure 130. Specifically, an atomic force microscope (AFM) can be used to measure the depth of the dish-shaped depression on the top surface of the metal lead-out structure 130. Then, based on the depth of the dish-shaped depression on the top surface of the metal lead-out structure 130, determine the number of plasma treatment times or the plasma treatment time. Specifically, the duration of each plasma treatment is about 10 s, and each plasma treatment can increase the depth of the dish-shaped depression on the top surface of the metal lead-out structure 130 by about 5 Å. When the depth of the dish-shaped depression on the top surface of the metal lead-out structure 130 reaches the preset depth, for example, the measured depth of the dish-shaped depression is 20 Å, at this time, there is no need to adjust the depth of the dish-shaped depression on the top surface of the metal lead-out structure 130 through plasma treatment, and only one plasma treatment can be performed or the plasma treatment time can be set to 5 s to 15 s to form open chemical bonds for bonding on the top surface of the dielectric layer 110. When the depth of the dish-shaped depression on the top surface of the metal lead-out structure 130 does not reach the preset depth, for example, the measured depth of the dish-shaped depression is 5 Å, two plasma treatments can be performed or the plasma treatment time can be set to 15 s to 25 s to further deepen the depth of the dish-shaped depression to reach the depth range of 10 Å to 30 Å. After performing plasma treatment, it may further include the step of measuring again the depth of the dish-shaped depression on the top surface of the metal lead-out structure 130 to confirm that the depth of the dish-shaped depression on the top surface of the metal lead-out structure 130 reaches the preset depth.

[0060] By performing plasma treatment, not only can a bonding interface with good bonding performance be formed, but also the bonding interface can be homogenized again on the basis of the homogenization treatment of the bonding interface in the first chemical mechanical polishing and the second chemical mechanical polishing. Its control accuracy is higher than that of the first chemical mechanical polishing and the second chemical mechanical polishing steps, and the top surface of the metal lead-out structure 130 is controlled again to ensure that both ends of the metal lead-out structure 130 are flush with the top surface of the dielectric layer 110, and the depth of the dish-shaped depression of the metal lead-out structure 130 is within the preset range.

[0061] Next, perform step S105, referring to Figure 6 as shown, hybrid bond at least two of the intermediate bonding structures to form a hybrid bonding structure.

[0062] In one embodiment, the hybrid bonding of at least two of the intermediate bonding structures includes bonding the metal lead-out structures of two intermediate bonding structures to each other in a corresponding manner, and bonding the dielectric layer regions to the dielectric layer regions in a corresponding manner. Since the situation where the top surface of the metal lead-out structure 130 protrudes from the top surface of the dielectric layer 110 is eliminated by the second chemical mechanical polishing process in step S103, the formation of an un-bonded region is avoided. However, since a dish-shaped groove is formed on the top surface of the metal lead-out structure 130, microbubbles are formed in the hybrid bonding structure formed after the hybrid bonding, as shown in Figure 6 shown. Further, the bubbles can be eliminated by performing a heat treatment on the hybrid bonding structure to form a structure as shown in Figure 7 shown. Specifically, an annealing treatment is performed to expand the metal lead-out structure 130 to fill the dish-shaped depression. The temperature range of the annealing treatment includes 300°C to 400°C, such as 300°C, 350°C, 400°C, preferably 350°C. The time range of the annealing treatment includes 100 min to 150 min, such as 100 min, 120 min, 150 min, preferably 120 min. After the annealing treatment, the metal lead-out structure expands to fill the microbubbles formed by the dish-shaped depression, and the microbubbles are eliminated. In this embodiment, the depth of the dish-shaped depression is jointly controlled by steps S103 and S104, so that the microbubbles formed by the dish-shaped depression are small enough to ensure that the thermal expansion of the metal caused by the annealing treatment can fill the dish-shaped depression to eliminate the microbubbles.

[0063] So far, the introduction of the related steps of the preparation method of the hybrid bonding structure of the embodiment of the present invention has been completed. It can be understood that the preparation method of the hybrid bonding structure of this embodiment not only includes the above steps, but may also include other required steps before, during, or after the above steps, and all of them are included in the scope of this manufacturing method.

[0064] The present invention also provides a semiconductor device, including a hybrid bonding structure, and the hybrid bonding structure can be prepared by the above preparation method of the hybrid bonding structure.

[0065] As shown in Figure 7 shown, the hybrid bonding structure includes at least two intermediate bonding structures that are hybrid-bonded to each other. The top of the intermediate bonding structure includes a dielectric layer, and a metal lead-out structure that penetrates the dielectric layer along a first direction perpendicular to the top surface of the dielectric layer. Among them, both ends of the metal lead-out structure in the intermediate bonding structure are flush with the top surface of the dielectric layer.

[0066] In one embodiment, the hybrid bonding structure includes two wafers 100, and a plurality of chips are formed in each wafer 100. A dielectric layer 110 is formed on the top of each wafer 100, and a metal lead-out structure 130 penetrating the dielectric layer along a first direction perpendicular to the top surface of the dielectric layer is formed in the dielectric layer 110. Wherein, the dielectric layer 110 includes a first tetraethyl orthosilicate layer 110a and a plasma-treated nitrogen-doped silicon carbide layer 110b stacked in sequence along the first direction on the wafer 100, and the plasma-treated nitrogen-doped silicon carbide layer 110b serves as a bonding interface.

[0067] In one embodiment, the metal lead-out structure 130 is connected to the interconnection layer of the wafer chip. The metal lead-out structure 130 includes, but is not limited to, copper. A barrier layer 120 is further formed between the metal lead-out structure 130 and the dielectric layer 110. The material of the barrier layer 120 includes, but is not limited to, tantalum (Ta) or tantalum nitride (TaN).

[0068] In one embodiment, in the hybrid bonding structure, the metal lead-out structures of the two intermediate bonding structures are bonded to each other correspondingly, and the dielectric layer regions are bonded to each other correspondingly. The two ends of the metal lead-out structure in the intermediate bonding structure are flush with the top surface of the dielectric layer, avoiding the formation of un-bonded regions in the hybrid bonding structure.

[0069] The specific structure of the hybrid bonding structure can refer to the description of the corresponding part in the above text. For the sake of brevity, it will not be described in detail here.

[0070] According to the preparation method of the hybrid bonding structure and the semiconductor device provided by the present invention, for the bonding interface with high and low drops, first, the top surface of the metal lead-out structure is protruded from the top surface of the dielectric layer through a first chemical mechanical polishing process, and then the two ends of the metal lead-out structure are flush with the top surface of the dielectric layer through a second chemical mechanical polishing process, avoiding the formation of un-bonded regions during the subsequent bonding process. At the same time, a dish-shaped depression is formed on the top surface of the metal lead-out structure through the second chemical mechanical polishing process and the depth of the dish-shaped depression is controlled to ensure that the dish-shaped depression is filled after the hybrid bonding structure is formed, avoiding the formation of bubble regions and improving the yield of hybrid bonding.

[0071] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation to the present application.

[0072] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0073] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0074] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for preparing a hybrid bonding structure, characterized in that, Including the following steps: Providing at least two structures to be bonded, the top of the structure to be bonded includes a dielectric layer, and a metal lead-out structure penetrating the dielectric layer along a first direction perpendicular to the top surface of the dielectric layer. Wherein, forming the metal lead-out structure includes: forming a through-hole penetrating the dielectric layer along a first direction perpendicular to the top surface of the dielectric layer by a lithography process; forming a metal material layer to fill the through-hole; performing bulk grinding to remove the metal material layer located on the top surface of the dielectric layer; Performing a first chemical mechanical polishing process to make the top surface of the metal lead-out structure protrude from the top surface of the dielectric layer; Performing a second chemical mechanical polishing process to make the two ends of the metal lead-out structure flush with the top surface of the dielectric layer, and forming a dish-shaped depression on the top surface of the metal lead-out structure; Performing plasma treatment on the top surface of the dielectric layer and the top surface of the metal lead-out structure to obtain an intermediate bonding structure, including: performing plasma treatment on the top surface of the dielectric layer to form open chemical bonds for bonding on the top surface of the dielectric layer; and performing plasma treatment on the top surface of the metal lead-out structure to adjust the depth of the dish-shaped depression; Hybrid bonding at least two of the intermediate bonding structures to form a hybrid bonding structure.

2. The manufacturing method of the hybrid bonding structure according to claim 1, characterized in that, During the process of performing the first chemical mechanical polishing process, the removal rate of the dielectric layer is greater than the removal rate of the metal lead-out structure; During the process of performing the second chemical mechanical polishing process, the removal rate of the metal lead-out structure is greater than the removal rate of the dielectric layer.

3. The manufacturing method of the hybrid bonding structure according to claim 2, characterized in that, The selectivity ratio range of the first polishing liquid of the first chemical mechanical polishing process for the dielectric layer and the metal lead-out structure includes 5:1 to 7:1, and the selectivity ratio range of the second polishing liquid of the second chemical mechanical polishing for the dielectric layer and the metal lead-out structure includes 2:1 to 4:1; The selectivity ratio of the first polishing liquid for the dielectric layer and the metal lead-out structure is higher than the selectivity ratio of the second polishing liquid for the dielectric layer and the metal lead-out structure.

4. The manufacturing method of the hybrid bonding structure according to claim 3, characterized in that The content of H2O2 in the first polishing liquid of the first chemical mechanical polishing process is not higher than 0.8%, and the content of H2O2 in the second polishing liquid of the second chemical mechanical polishing is not lower than 1.2%; The content of H2O2 in the second polishing liquid is higher than the content of H2O2 in the first polishing liquid.

5. The manufacturing method of the hybrid bonding structure according to claim 4, characterized in that, The dielectric layer includes a first tetraethyl orthosilicate layer, a nitrogen-doped silicon carbide layer, and a second tetraethyl orthosilicate layer stacked in sequence along the first direction. The first chemical mechanical polishing process is used to remove the second tetraethyl orthosilicate layer and part of the nitrogen-doped silicon carbide layer.

6. The preparation method of the hybrid bonding structure according to claim 1, wherein The height range of the top surface of the metal lead-out structure protruding from the top surface of the dielectric layer includes 300 Å to 400 Å, and the depth range of the dish-shaped depression includes 10 Å to 30 Å.

7. The method for preparing the hybrid bonding structure according to claim 6, wherein After forming the hybrid bonding structure, the following steps are further included: Performing annealing treatment on the hybrid bonding structure to make the metal lead-out structure expand and fill the dish-shaped depression.

8. The manufacturing method of the hybrid bonding structure according to claim 1, characterized in that The polishing speeds of the first chemical mechanical polishing process and the second chemical mechanical polishing process include 30 rpm to 80 rpm.

9. A semiconductor device, characterized in that, Comprising: A hybrid bonding structure, prepared by using the preparation method of the hybrid bonding structure according to any one of claims 1 to 8.

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