Chip stacking structure and wafer level packaging method

Abstract

The invention discloses a chip stacking structure and a wafer level packaging method.The chip stacking structure comprises a first chip structure and a second chip structure which are connected in a bonding mode, the size of the first chip structure is larger than that of the second chip structure, the first chip structure is provided with a second face used for being connected with the second chip structure in a bonding mode, and the second face is provided with a second face used for being connected with the second chip structure in a bonding mode. The chip stacking structure comprises a supporting structure and a filling layer, the supporting structure is connected to the second surface in a bonding manner, the filling layer is arranged between the second chip structure and the supporting structure, and the supporting structure is arranged outside the second chip structure in a surrounding manner; the supporting structure can be used for improving the warping phenomenon of the chip stacking structure during plastic package filling.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging and testing, and in particular to a chip stacking structure and a wafer-level packaging method. Background Art

[0002] In chip application areas, such as large-area display or image acquisition, due to the size of a single chip, multiple chips need to be repeatedly arranged to form a matrix array to achieve the effect of a large-area array. At the same time, the display or image acquisition chip needs to match the computing module, such as the analog-to-digital conversion module, which needs to be placed on the back of the chip.

[0003] A common practice in the industry is to use wafer-level bonding to stack and interconnect the two wafers of sensor and computing to achieve this effect. However, this method requires that the two chips of sensor and computing have the same size and interface in order to be bonded at the wafer level. There is also another approach, which uses a substrate as a transfer board, and mounts the two chips of sensor and computing on the upper and lower sides, which will result in a long signal transmission path and thus affect performance. Another approach is to mount a small-size chip to a large wafer, then perform plastic encapsulation and filling, and then cut it. The support structure formed after plastic encapsulation is severely warped. Summary of the invention

[0004] One of the objectives of the present invention is to provide a chip stacking structure to at least solve the technical problem of warping during plastic packaging filling between chips and wafers in the prior art.

[0005] One of the objectives of the present invention is to provide a wafer-level packaging method.

[0006] To achieve one of the above-mentioned purposes of the invention, an embodiment of the present invention provides a chip stacking structure including a first chip structure and a second chip structure bonded to each other, wherein the size of the first chip structure is larger than the size of the second chip structure, and the first chip structure has a second surface for bonded to the second chip structure, and the chip stacking structure includes a supporting structure bonded to the second surface and a filling layer arranged between the second chip structure and the supporting structure, and the supporting structure is arranged outside the second chip structure.

[0007] As a further improvement of an embodiment of the present invention, the outer wall surface of the support structure and the outer wall surface of the first chip structure are located in the same plane.

[0008] As a further improvement of an embodiment of the present invention, the first chip structure includes a first welding area, the second chip structure includes a second welding area, and the first welding area is bonded to the second welding area.

[0009] As a further improvement of an embodiment of the present invention, the support structure includes a third welding area arranged on a surface facing the first chip structure, and the third welding area is connected to the first welding area.

[0010] As a further improvement of an embodiment of the present invention, the support structure includes a third through silicon via arranged on a surface away from the first chip structure and a third interconnect structure arranged in the third through silicon via, and the third interconnect structure is used to connect the third welding area and the external circuit.

[0011] As a further improvement of an embodiment of the present invention, the chip stacking structure includes a first metal bump disposed in the second welding area, and the first metal bump is connected to the first welding area.

[0012] As a further improvement of an embodiment of the present invention, the first metal bump corresponds to a middle area of ​​the first chip structure.

[0013] As a further improvement of one embodiment of the present invention, the second chip structure includes a third surface and a fourth surface relative to each other, the fourth surface faces away from the first chip structure, and the second welding area is located on the third surface; the second chip structure includes a second silicon via that penetrates the fourth surface along its thickness direction, and a second interconnection structure that is arranged in the second silicon via and further extends to the fourth surface, and the second interconnection structure is used to connect to an external circuit.

[0014] As a further improvement of an embodiment of the present invention, the second interconnect structure further extends to a surface of the support structure away from the first chip structure.

[0015] As a further improvement of an embodiment of the present invention, the first chip structure includes a first surface and a second surface relative to each other, the first surface is away from the second chip structure, and the first welding area is located on the first surface; the first chip structure includes a first silicon via that penetrates the second surface along its thickness direction, and a first interconnection structure that is arranged in the first silicon via and further extends to the second surface, and the first interconnection structure connects the first welding area and the second welding area.

[0016] To achieve one of the above-mentioned purposes of the invention, an embodiment of the present invention provides a wafer-level packaging method, comprising the following steps:

[0017] Providing a first wafer, wherein the first wafer includes a plurality of first chip structures that can be obtained by segmentation;

[0018] Providing a second wafer and cutting the second wafer to obtain a plurality of single second chip structures; the size of the first chip structure is larger than the size of the second chip structure;

[0019] Providing a wafer-level silicon wafer, wherein the silicon wafer has a plurality of meshes, and the size of the meshes matches the size of a single second chip structure;

[0020] The wafer-level silicon wafer and a plurality of second chip structures are bonded to the second surface of the first wafer to form a wafer-level packaging structure, and the plurality of second chip structures are located in the mesh.

[0021] As a further improvement of an embodiment of the present invention, the step of “providing a first wafer” includes:

[0022] A first through silicon via is formed on the second surface of the first wafer; a first welding area is provided on the first surface of the first wafer, and the first surface and the second surface are arranged opposite to each other;

[0023] A first interconnect structure is fabricated in the first through silicon via, wherein the first interconnect structure is connected to a first welding region.

[0024] As a further improvement of an embodiment of the present invention, before “cutting the second wafer”, the method includes: manufacturing a first metal bump on a second welding area of ​​the second wafer.

[0025] As a further improvement of an embodiment of the present invention, “bonding a plurality of second chip structures to the first wafer” includes: bonding the first metal bump and the first interconnect structure.

[0026] As a further improvement of an embodiment of the present invention, "providing a wafer-level silicon wafer" includes: making a third welding area on the surface of the silicon wafer.

[0027] As a further improvement of an embodiment of the present invention, "bonding the wafer-level silicon wafer to the first wafer" includes: bonding the first interconnect structure and the third welding area.

[0028] As a further improvement of one embodiment of the present invention, the steps are as follows:

[0029] A second through silicon via is formed on the fourth surface of the second chip structure, and a second welding area is provided on the third surface of the second chip structure;

[0030] A second interconnect structure is fabricated in the second through silicon via, and the second interconnect structure is used to connect the second welding area and an external circuit.

[0031] As a further improvement of one embodiment of the present invention, "providing a wafer-level silicon wafer" includes the steps of: making a third through silicon via on the surface of the silicon wafer, making a third interconnection structure in the third through silicon via, and the third interconnection structure is used to connect an external circuit.

[0032] As a further improvement of one embodiment of the present invention, the steps are as follows:

[0033] filling the wafer-level packaging structure;

[0034] The wafer-level packaging structure is cut to obtain a single chip stacking structure.

[0035] Compared with the prior art, the present invention provides a chip stacking structure, wherein the support structure is located outside the second chip structure and connected to the first chip structure, and the filling layer is further arranged between the support structure and the second chip structure to improve the warping phenomenon caused by plastic sealing between the first chip structure and the second chip structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Schematic diagram of the chip stacking structure in the first embodiment of the present invention.

[0037] Figure 2 Schematic diagram of a chip stacking structure in a second embodiment of the present invention.

[0038] Figure 3 Schematic diagram of a chip stacking structure in a third embodiment of the present invention.

[0039] Figure 4 is a schematic diagram of a first wafer in one embodiment of the present invention.

[0040] Figure 5 is a schematic diagram of a second chip structure in one embodiment of the present invention.

[0041] Figure 6 Schematic diagram of a wafer-level silicon wafer in one embodiment of the present invention.

[0042] Figure 7 Schematic diagram of a wafer-level packaging structure formed in the first embodiment of the present invention.

[0043] Figure 8 Schematic diagram of a wafer-level packaging structure formed in a second embodiment of the present invention.

[0044] Fig. 9 Schematic diagram of a wafer-level packaging structure formed in a third embodiment of the present invention. DETAILED DESCRIPTION

[0045] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0046] It should be noted that the term "comprises" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In addition, the terms "first", "second", "third", "fourth", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0047] The terms "connected", "connected to" or any other variants are intended to cover various relative positions in a connection relationship, so as to include direct connection or indirect connection. Among them, the direct connection can be formed by a gas pipeline, and the indirect connection can be a connection relationship established by a device such as a valve body, a sensor, etc., a connection relationship can be established by a gas circuit component such as a brake control unit, or a connection relationship can be established by any other medium such as air.

[0048] See also Figure 1 , is a schematic structural diagram of a chip stacking structure 1000 provided in one embodiment of the present invention.

[0049] The chip stacking structure 1000 includes a first chip structure 10 and a second chip structure 20 bonded to each other. The size of the first chip structure 10 is larger than that of the second chip structure 20. The first chip structure 10 has a second surface for bonding to the second chip structure 20. The chip stacking structure 1000 includes a supporting structure 30 bonded to the second surface and a filling layer 40 arranged between the second chip structure 20 and the supporting structure 30. The supporting structure 30 is arranged outside the second chip structure 20.

[0050] In the prior art, the size of the first chip structure 10 is larger than that of the second chip structure 20. After the second chip structure 20 is mounted on the first chip structure 10, the first chip structure 10 and the second chip structure 20 are completely plastic-sealed and filled. Since the thermal expansion coefficient of the filled organic material is large and the curing temperature is high, the warping area after curing is relatively large and wide.

[0051] A support structure 30 is arranged outside the second chip structure 20, and then the gap between the second chip structure 20 and the support structure 30 is filled. The filling layer is small and the warping area is small. The material of the support structure 30 is preferably silicon. When the support structure 30 is made of silicon, the material is consistent with the first chip structure 10 and the second chip structure 20, and the silicon material has less warping phenomenon. The support structure 30 can also be made of hard and non-deformable materials such as glass and ceramics as needed. The thermal expansion coefficient of the selected material should be as close as possible to the thermal expansion coefficient of silicon to improve the warping phenomenon.

[0052] The support structure 30 is annularly disposed outside the second chip structure 20 .

[0053] The outer wall surface of the support structure 30 and the outer wall surface of the first chip structure 10 are located in the same plane, ensuring that the first chip structure layer and the second chip structure layer have the same size.

[0054] The filling layer 40 is not only located between the second chip structure 20 and the supporting structure 30 , but also located in the gap between the first chip structure 10 and the second chip structure 20 .

[0055] The first chip structure 10 includes a first welding area 11 , and the second chip structure 20 includes a second welding area 21 . The first welding area 11 is bonded to the second welding area 21 to achieve electrical connection between the first chip structure 10 and the second chip structure 20 .

[0056] In a preferred embodiment, the first chip structure 10 includes a first surface and a second surface opposite to each other, wherein the first surface faces away from the second chip structure 20 , and the second surface faces the second chip structure 10 .

[0057] The first welding region 11 may be selectively located at a first surface away from the second chip structure 10 or at a second surface close to the second chip structure 10 , as long as electrical connection with the second welding region 21 can be achieved.

[0058] In a specific embodiment, combined with Figure 1 As shown, the first welding area 11 is located on the first surface, and the first chip structure 10 also includes a functional area 12 arranged on the first surface; the first chip structure 10 includes a first silicon via that penetrates the second surface along its thickness direction, and a first interconnection structure 13 that is arranged in the first silicon via and further extends to the second surface, and the first interconnection structure 13 connects the first welding area 11 and the second welding area 21.

[0059] It can be understood that, in order to facilitate the formation of the first interconnect structure 13 , the first chip structure 10 includes an insulating layer and a soldering layer disposed between the second surface and the first interconnect structure 13 .

[0060] In a preferred embodiment, the first chip structure 10 includes a solder resist layer 14 arranged on the first interconnect structure 13, and the solder resist layer 14 has a window to expose a portion of the first interconnect structure 13, and the exposed first interconnect structure 13 is used to connect to the second welding area 21. The solder resist layer 14 can prevent the second welding area 21 from extending excessively, resulting in a short circuit connection between the first welding area 11 and the second welding area 21.

[0061] In a preferred embodiment, the second chip structure 20 includes a third surface and a fourth surface relative to each other, the third surface faces the first chip structure 10, and the fourth surface faces away from the first chip structure 10, and the second welding area 21 is located on the third surface; the second chip structure 20 includes a second silicon via that penetrates the fourth surface along its thickness direction, and a second interconnect structure 22 that is arranged in the second silicon via and further extends to the fourth surface, and the second interconnect structure 22 is used to connect to an external circuit.

[0062] The third surface and the fourth surface of the second chip structure 20 need to be formed with a second welding area 21 and a second interconnection structure 22, respectively, for connecting the first chip structure 10 and the external circuit. Specifically, the surface of the second interconnection structure 22 forms a solder ball 24, which is connected to the external circuit through the solder ball 24.

[0063] In a preferred embodiment, the chip stacking structure 1000 includes a first metal bump 23 disposed on the second welding area 21 , and the first metal bump 23 is connected to the first welding area 11 .

[0064] Specifically, combined Figure 1 As shown, the first metal bump 23 is connected to the exposed first interconnect structure 13. In practical applications, the first metal bump 23 is mostly formed by solder. The solder resist layer 14 can prevent the solder from spreading to other effective circuit areas of the first chip structure 10 in a molten state, causing a circuit short circuit or failure. In other embodiments, the first metal bump 23 can also be made of other solders. When other solders are used, the first chip structure 10 can also be provided with a solder resist layer 14.

[0065] In a preferred embodiment, the first metal bump 23 corresponds to the middle area of ​​the first chip structure 10. More specifically, the central axes of the first chip structure 10 and the second chip structure 20 are aligned. When the first chip structure 10 and the second chip structure 20 are mounted, it is equivalent to mounting them with the central axes aligned to ensure that the chip stacking structure 1000 has balanced stress.

[0066] Combination Figure 1 As described above, in the first embodiment of the present case, the support structure 30 is disposed outside the second chip structure 20 and connected to the second surface of the first chip structure 10, and the support structure 30 can only be used to achieve support and reduce warping. In more embodiments, the support structure 30 can also be provided with an interconnection structure to achieve the function of an adapter plate, taking into account the transmission density of signals between the first chip structure 10 and the second chip structure 20.

[0067] Combination Figure 2As shown, in the second embodiment of the present case, the second interconnect structure 22 of the second chip structure 20 further extends to the surface of the support structure 30 away from the first chip structure 10, and is further used to connect to an external circuit to expand the number of solder balls 24 of the second chip structure 20 to facilitate electrical connection with different external circuits.

[0068] Combination Figure 3 As shown, in the third embodiment of the present case, the support structure 30 includes a third welding area 31 disposed on the surface facing the first chip structure 10, and the third welding area 31 is connected to the first welding area 11. A third metal bump 32 is disposed on the surface of the third welding area 31, and the third metal bump 32 is connected to the first chip structure 10, specifically to the exposed first interconnect structure 13.

[0069] Therefore, the first chip structure 10 can independently lead out the first welding area 11 through the support structure 30 to connect with an external circuit.

[0070] Specifically, the support structure 30 includes a third through silicon via disposed on a surface away from the first chip structure 10 and a third interconnect structure 33 disposed on the third through silicon via, and the third interconnect structure 33 is used to connect the third welding area 31 and an external circuit.

[0071] Similarly, in the third embodiment, the second interconnect structure 22 can also be arranged to further extend to the surface of the support structure 30 away from the first chip structure 10. In this way, through the support structure 30, the electrical signal of the first chip structure 10 can be independently led out, and the first chip structure 20 and the second chip structure 20 can be electrically coupled before leading out the electrical signal.

[0072] Combination Figure 4-9 As shown, the present invention also protects a wafer-level packaging method, through which the chip stacking structure 1000 in the above technical solution can be obtained, and the wafer-level packaging method includes the following steps:

[0073] S1: Provide a first wafer 100, wherein the first wafer 100 includes a plurality of first chip structures 10 that can be obtained by segmentation. Figure 4 As shown in FIG. a, the first chip structure 10 includes a first welding area 11 and a functional area 12 .

[0074] Combination Figure 4 As shown in b, the step of “providing a first wafer 11” includes:

[0075] S11: a first through silicon via is fabricated on the second surface of the first wafer 100 ; a first welding area 11 is disposed on the first surface of the first wafer 100 , and the first surface and the second surface are disposed opposite to each other.

[0076] A first interconnection structure 13 is fabricated in the first through silicon via, and the first interconnection structure 13 is connected to the first welding region 11. This is equivalent to performing a through silicon via process and a rewiring process on the second surface of the first wafer 100 to achieve vertical interconnection.

[0077] It is understandable that before making the first interconnect structure 13, an insulating layer and a solder layer need to be made first, and then the first interconnect structure 13 is made on the surface of the solder layer; it is understandable that after the first interconnect structure 13 is made, a solder resist layer 14 can be made on the surface of the first interconnect structure 13, and the solder resist layer 14 exposes part of the first interconnect structure 13 for electrical connection.

[0078] S2: providing a second wafer 200 and cutting the second wafer 200 to obtain a plurality of single second chip structures 20; combining Figure 5 As shown, the second chip structure 20 includes a second welding region 21 .

[0079] The size of the first chip structure 10 is larger than that of the second chip structure 20 ; if the first chip structure 10 and the second chip structure 20 are the same size, wafer-level bonding and singulation can be performed directly without the need for plastic encapsulation and singulation after mounting.

[0080] Before “cutting the second wafer 200 ”, the process includes: manufacturing a first metal bump 23 on the second welding area 21 of the second wafer 200 . Manufacturing the first metal bump 23 before cutting is simple in process, time-saving and efficient.

[0081] S3: Provide wafer-level silicon wafer 300, combined with Figure 6 As shown in FIG. 1 , the silicon wafer 300 has a plurality of meshes 310 , the size of which matches the size of a single second chip structure 20 ; the specific size is slightly larger than the size of the second chip structure 20 to facilitate installation and prevent interference.

[0082] S4: Bonding the wafer-level silicon wafer 300 and the plurality of second chip structures 20 to the second surface of the first wafer 100 to form a wafer-level packaging structure 2000. Figure 7 As shown, a plurality of the second chip structures 20 are located in the mesh 310 .

[0083] Specifically, "bonding a plurality of second chip structures 20 to the first wafer 100" includes: bonding the first metal bump 23 and the first interconnect structure 13, including dielectric bonding and dielectric-free bonding, and dielectric bonding further includes conductive adhesive bonding and metal bonding.

[0084] Combination Figure 7 , 8As shown, in the first and second embodiments, “bonding the wafer-level silicon wafer 300 to the first wafer 100” includes: bonding one side surface of the wafer-level silicon wafer 300 to the solder resist layer 14 of the first wafer 100. No electrical connection is required between the wafer-level silicon wafer 300 and the first wafer 100.

[0085] Combination Figure 6 As shown in b, in the third embodiment, "providing a wafer-level silicon wafer 300" includes: making a third welding area 31 on the surface of the silicon wafer 300.

[0086] Combination Fig. 9 As shown, in the third embodiment, "bonding the wafer-level silicon wafer 300 to the first wafer 100" includes: bonding the first interconnect structure 13 and the third welding area 31. Specifically, the third welding area 31 is provided with a second metal bump 32, and the second metal bump 32 is bonded to the exposed first interconnect structure 13, and an electrical connection needs to be formed between the wafer-level silicon wafer 300 and the first wafer 100.

[0087] It should be noted that there is no strict distinction between the bonding of the first wafer 100 and the second chip structure 20 , and the bonding of the first wafer 100 and the wafer-level silicon wafer 300 .

[0088] S5: Filling the wafer-level packaging structure 1000; combining Figure 7 As shown, after the first wafer 100, the plurality of second chip structures 20 and the wafer-level silicon wafer 300 are bonded, the grooves and gaps after bonding can be filled to form a filling layer 40 to form a plastic-sealed overall wafer-level structure, which is convenient for subsequent through-silicon via processes and rewiring processes. The specific filling process can use vacuum printing or vacuum laminating equipment.

[0089] After filling, grinding of the second chip structure 20 and the surface of the wafer-level silicon wafer 300 facing away from the first wafer 100 may be performed optionally.

[0090] S6: a second through silicon via is fabricated on the fourth surface of the second chip structure 20, and a second welding area 21 is provided on the third surface of the second chip structure 20; a second interconnection structure 22 is fabricated in the second through silicon via, and the second interconnection structure 22 is used to connect the second welding area 21 and an external circuit.

[0091] Combination Figure 7 As shown, in the first embodiment, the second interconnect structure 22 and the solder balls 23 are only manufactured on the third surface of the second chip structure 20, and the wafer-level silicon wafer 300 is only used for support.

[0092] Combination Figure 8As shown, in the second embodiment, the second interconnect structure 22 and the solder balls 24 may continue to be manufactured on the surface of the wafer-level silicon chip 300 .

[0093] Combination Fig. 9 As shown, in the third embodiment, the wafer-level packaging method includes the steps of: making a third through silicon via on the surface of the silicon wafer 300, and making a third interconnect structure 33 in the third through silicon via, wherein the third interconnect structure 33 is used to connect to an external circuit.

[0094] S6: cutting the wafer-level packaging structure 2000 to obtain a single chip stacking structure 1000. The first chip structure 10 is obtained by cutting the first wafer 100, and the support structure 30 is obtained by cutting the wafer-level silicon wafer 300.

[0095] The beneficial effects of the present invention are as follows: the support structure 30 is located outside the second chip structure 20, and the filling layer 40 is then filled between the support structure 30 and the second chip structure 20, thereby improving the warping phenomenon of direct plastic packaging filling; the support structure 30 is provided with an interconnection structure, taking into account the signal transmission density; after the second chip structure 20 is cut, it is bonded to the first wafer 100 together with the wafer-level silicon wafer 300, and then filled, the interconnection structure is made, and cut, which is equivalent to wafer-level packaging production, simplifying the process.

[0096] It can be formed by referring to any of the technical solutions provided above, and will not be described in detail here.

[0097] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0098] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A chip stacking structure, characterized in that: The invention comprises a first chip structure and a second chip structure bonded to each other, wherein the size of the first chip structure is larger than that of the second chip structure, the first chip structure has a second surface for bonding to the second chip structure, the chip stacking structure comprises a supporting structure bonded to the second surface and a filling layer arranged between the second chip structure and the supporting structure, and the supporting structure is arranged outside the second chip structure.

2. The chip stacking structure according to claim 1, characterized in that: The outer wall surface of the support structure and the outer wall surface of the first chip structure are located in the same plane.

3. The chip stacking structure according to claim 1, characterized in that: The first chip structure includes a first welding area, the second chip structure includes a second welding area, and the first welding area is bonded to the second welding area.

4. The chip stacking structure according to claim 3, characterized in that: The support structure includes a third welding area arranged on a surface facing the first chip structure, and the third welding area is connected to the first welding area.

5. The chip stacking structure according to claim 4, characterized in that: The support structure includes a third through silicon via disposed on a surface away from the first chip structure and a third interconnect structure disposed on the third through silicon via, wherein the third interconnect structure is used to connect a third welding area and an external circuit.

6. The chip stacking structure according to claim 3, characterized in that: The chip stacking structure includes a first metal bump disposed on the second welding area, and the first metal bump is connected to the first welding area.

7. The chip stacking structure according to claim 6, characterized in that: The first metal bump corresponds to a middle area of ​​the first chip structure.

8. The chip stacking structure according to claim 3, characterized in that: The second chip structure includes a third surface and a fourth surface relative to each other, the fourth surface is away from the first chip structure, and the second welding area is located on the third surface; the second chip structure includes a second silicon via that penetrates the fourth surface along its thickness direction, and a second interconnection structure that is arranged in the second silicon via and further extends to the fourth surface, and the second interconnection structure is used to connect to an external circuit.

9. The chip stacking structure according to claim 8, characterized in that: The second interconnect structure further extends to a surface of the support structure facing away from the first chip structure.

10. The chip stacking structure according to claim 3, characterized in that: The first chip structure includes a first surface and a second surface relative to each other, the first surface is away from the second chip structure, and the first welding area is located on the first surface; the first chip structure includes a first silicon via that penetrates the second surface along its thickness direction, and a first interconnection structure that is arranged in the first silicon via and further extends to the second surface, and the first interconnection structure connects the first welding area and the second welding area.

11. A wafer-level packaging method, characterized in that: The following steps are involved: Providing a first wafer, wherein the first wafer includes a plurality of first chip structures that can be obtained by segmentation; Providing a second wafer and cutting the second wafer to obtain a plurality of single second chip structures; the size of the first chip structure is larger than the size of the second chip structure; Providing a wafer-level silicon wafer, wherein the silicon wafer has a plurality of meshes, and the size of the meshes matches the size of a single second chip structure; The wafer-level silicon wafer and a plurality of second chip structures are bonded to the second surface of the first wafer to form a wafer-level packaging structure, and the plurality of second chip structures are located in the mesh.

12. The wafer-level packaging method according to claim 11, characterized in that: "Provide the first wafer" includes: A first through silicon via is formed on the second surface of the first wafer; a first welding area is provided on the first surface of the first wafer, and the first surface and the second surface are arranged opposite to each other; A first interconnect structure is fabricated in the first through silicon via, wherein the first interconnect structure is connected to a first welding region.

13. The wafer level packaging method according to claim 12, characterized in that: Before "cutting the second wafer", the method includes: making a first metal bump in the second welding area of ​​the second wafer.

14. The wafer-level packaging method according to claim 13, characterized in that: "Bonding a plurality of second chip structures to the first wafer" includes: bonding the first metal bumps and the first interconnect structure.

15. The wafer level packaging method according to claim 12, characterized in that: "Providing a wafer-level silicon wafer" includes: making a third welding area on the surface of the silicon wafer.

16. The wafer level packaging method according to claim 15, characterized in that: "Bonding the wafer-level silicon wafer to the first wafer" includes: bonding the first interconnect structure and the third welding area.

17. The wafer-level packaging method according to claim 11, characterized in that: Includes steps: A second through silicon via is formed on the fourth surface of the second chip structure, and a second welding area is provided on the third surface of the second chip structure; A second interconnect structure is fabricated in the second through silicon via, and the second interconnect structure is used to connect the second welding area and an external circuit.

18. The wafer level packaging method according to claim 11, characterized in that: "Providing a wafer-level silicon wafer" includes the steps of: making a third through silicon via on the surface of the silicon wafer, making a third interconnect structure in the third through silicon via, and the third interconnect structure is used to connect to an external circuit.

19. The wafer-level packaging method according to claim 11, characterized in that: Includes steps: filling the wafer-level packaging structure; The wafer-level packaging structure is cut to obtain a single chip stacking structure.

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