Substrate warping suppression structure and chip packaging structure

Abstract

The invention relates to the field of chip packaging, in particular to a substrate warping suppression structure and a chip packaging structure. Comprising a warping suppression part and at least one first containing concave part which is formed in the second connecting end face and extends in the direction of the first connecting end face. The depth of the first containing groove is smaller than the distance between the first connecting end face and the second connecting end face. A corresponding first containing groove is further formed in the side, close to the substrate, of the warping restraining ring. And a capacitor arranged on the substrate can be buckled and covered in the first accommodating groove. Therefore, through the structural arrangement, when the warping suppression ring is connected with the substrate, the coverage width of the warping suppression ring does not need to be reduced in order to avoid the capacitor. On the contrary, the coverage width of the chip is increased as much as possible without being limited by capacitance, so that the coverage area is increased, the inhibition capability on the deformation amplitude of the substrate is finally improved, the warping amplitude of the substrate can be reduced, and the stability of the chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging, and in particular to a substrate warping suppression structure and a chip packaging structure. Background Art

[0002] In the emerging demands such as the Internet of Things, artificial intelligence, high-computing computing, big data, and Industry 4.0, a large amount of data transmission and transfer is required, which also places higher and higher requirements on processor performance. However, the traditional single chip design can no longer meet the growing demand. In order to meet this challenge, the emerging technology - advanced packaging (Chiplet) technology for high-performance system chips came into being. Advanced packaging refers to cutting-edge flip chip packaging (FC, Flip chip), wafer level packaging (WLP, Wafer level packaging), system-level packaging (SiP, System In a Package) and 2.5D, 3D packaging, etc. As an important method to increase connection density, improve system integration and miniaturization, it takes on the responsibility of continuing Moore's Law when the difficulty of advancing single chips to higher-end processes increases greatly.

[0003] Existing GPU (Graphics Processing Unit), NPU (Neural network Processing Unit) and other chips are also developing in the direction of multi-connection, multi-chip, modularization and three-dimensionalization, and the corresponding large-size 2.5D system-level packaging has become the mainstream trend of advanced packaging of such chips. At the same time, since system-level packaging involves a variety of heterogeneous materials, each material will shrink or expand according to its own characteristics under the influence of external pressure and temperature changes. However, due to the different deformation characteristics of each material, the materials will be squeezed and pulled against each other, which will bring a series of stress and warping problems. Among them, the material of the chip core is silicon, and its CTE (Customer Terminal Equipment) is 3 to 4ppm; while the material of the substrate is organic matter, and its CTE is 13 to 20ppm. Since the CTE between the two differs by 3 to 5 times, the degree of deformation between the two is also quite different. As a result, the substrate will sink downward to form a smiley face shape or bulge upward to form a crying face shape under the influence of temperature, such as Figure 3 Under the influence of this deformation, the connection between the chip core and the substrate is easily broken, thereby affecting the operational stability of the chip.

[0004] To solve the above problems, the mainstream 2.5D system-level packaging mostly adopts the TSMC CoWoS structure, which controls the warping of the chip during package reflow, mounting, and use by arranging a circle of harder stainless steel or copper rings around the substrate. However, since large chips have stronger and more complex power requirements, more capacitors will be arranged in the area around the core of the substrate chip to meet the design requirements. Therefore, the setting of the capacitors greatly limits the coverage area of ​​the ring, which greatly reduces the ability of the ring to limit the warping of the substrate, increasing the operation risk of the chip. Summary of the invention

[0005] In view of this, the present invention provides a substrate warping suppression structure and a chip packaging structure, which at least partially solve the problems existing in the prior art.

[0006] According to one aspect of the present invention, there is provided a substrate warpage suppression structure, comprising:

[0007] The warping suppression ring has a first connection end surface and a second connection end surface that are arranged opposite to each other, and the second connection end surface is used for fixed connection with the edge area of ​​the substrate.

[0008] At least one first accommodating groove is provided on the second connecting end surface and extends toward the first connecting end surface, and the depth of the first accommodating groove is less than the distance between the first connecting end surface and the second connecting end surface. A plurality of first accommodating grooves are arranged at intervals.

[0009] Furthermore, the setting position of each first accommodating groove corresponds to the installation position of the first target capacitor, the volume of the first accommodating groove is larger than the volume of the first target capacitor, and the first target capacitor is a capacitor whose installation area on the substrate overlaps with the connection area between the warping suppression ring and the substrate.

[0010] Furthermore, the cross section of the warping suppression ring is rectangular, and the first accommodating groove is a rectangular parallelepiped groove.

[0011] Furthermore, it also includes:

[0012] At least one second accommodating through groove is formed on the second connecting end surface and vertically penetrates to the first connecting end surface, and the second accommodating through groove horizontally penetrates to the inner side surface of the warping suppression ring. A plurality of second accommodating through grooves are arranged at intervals.

[0013] Furthermore, the setting position of each second accommodating groove corresponds to the installation position of the second target capacitor, the volume of the second accommodating groove is larger than the volume of the second target capacitor, and the second target capacitor is a capacitor in which there is partial overlap between the installation area on the substrate and the connection area between the warping suppression ring and the substrate.

[0014] Furthermore, the first accommodating grooves and the second accommodating through grooves are alternately arranged in the circumferential direction of the warping suppression ring.

[0015] According to a second aspect of the present invention, there is also provided a chip packaging structure, comprising:

[0016] The cover plate is used for being fixedly arranged just above the chip core, and the cover plate has a first heat dissipation end surface arranged close to the chip core.

[0017] A flexible heat dissipation layer is fixedly arranged on the first heat dissipation end surface, the thickness of the flexible heat dissipation layer is greater than the distance between the first heat dissipation end surface and the upper surface of the chip core, and the material of the flexible heat dissipation layer is a flexible metal with adaptive deformation ability under the action of external force. And

[0018] In the above-mentioned substrate warping suppression structure, the first connection end surface of the warping suppression ring is fixedly connected to the portion of the first heat dissipation end surface close to the outer edge. The distance between the first connection end surface and the second connection end surface is greater than the thickness of the flexible heat dissipation layer.

[0019] Furthermore, the cover plate is a vacuum chamber heat spreader, and the end surface of the vacuum chamber heat spreader on one side of the evaporation end is a first heat dissipation end surface.

[0020] Furthermore, the flexible heat dissipation layer is fixedly connected to the first heat dissipation end surface by electroplating, chemical plating or welding. The flexible metal includes nickel, copper, gold and silver.

[0021] Furthermore, the area of ​​the first heat dissipation end surface is larger than the upper surface area of ​​the chip core.

[0022] The technical solution of the present invention has at least the following beneficial effects:

[0023] The warping suppression ring in the present invention is fixed to the edge area of ​​the substrate to limit the degree of warping deformation at the edge of the substrate, thereby reducing the overall deformation warping degree of the substrate. In addition, a corresponding first accommodating groove is provided on the side of the warping suppression ring close to the substrate. The capacitor cover arranged on the substrate can be placed in the first accommodating groove. Thus, through the above-mentioned structural arrangement, when the warping suppression ring is connected to the substrate, it is not necessary to reduce its own coverage width in order to avoid the capacitor. On the contrary, without being restricted by the capacitor, the coverage width of the ring can be increased as much as possible to increase the coverage area, thereby ultimately improving the ability to suppress the deformation amplitude of the substrate, reducing the amplitude of the substrate warping, and increasing the stability of the chip.

[0024] In addition, since the first accommodating groove in the present invention is not a through groove from the first connection end face to the second connection end face, the continuity of the overall structure of the entire warping suppression ring is ensured. At the same time, when there are multiple first accommodating grooves, the multiple first accommodating grooves need to be arranged at intervals, thereby avoiding the situation where a large volume groove is opened on the warping suppression ring, further ensuring the continuity of the overall structure of the entire warping suppression ring. Therefore, it can be ensured that the warping suppression ring can still have a high overall rigidity even after the first accommodating groove is opened, and thus can have a better suppression performance on the amplitude of substrate warping. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 This is a schematic diagram of the connection structure between the warping suppression ring and the first accommodating groove in one embodiment of the present application;

[0027] Figure 2 This is a schematic diagram of the connection structure between the warping suppression ring, the first accommodating groove and the second accommodating through groove in another embodiment of the present application;

[0028] Figure 3 This is a schematic structural diagram of another embodiment of the present application in which a substrate forms a smiling face (right side) or a crying face (left side) shape under the influence of temperature;

[0029] Figure 4 This is a schematic structural diagram of a first warpage suppression group in another embodiment of the present application;

[0030] Figure 5 This is a schematic structural diagram of the first warpage suppression group in another second embodiment of the present application;

[0031] Figure 6 Schematic diagram of the structure of the first warpage suppression group in another three embodiments of the present application;

[0032] Figure 7 It is a curve change diagram of the warping degree of the diagonal line of the substrate in three groups of experimental objects in another embodiment of the present application in a high temperature environment (240° C.);

[0033] Figure 8 It is a curve change diagram of the warping degree of the diagonal line of the substrate in three groups of experimental objects in another embodiment of the present application in a room temperature environment (30° C.);

[0034] Fig. 9This is a schematic diagram of a chip packaging structure in an embodiment of the present application;

[0035] Fig.10 This is a schematic diagram of the upper surface of the chip core being deformed upward and concave due to temperature in one embodiment of the present application;

[0036] Fig.11 Schematic diagram of temperature performance of four heat dissipation experiment groups in one embodiment of the present application.

[0037] Reference numerals

[0038] 1. Warping suppression ring; 10. First accommodating groove; 11. Second accommodating through groove; 12. Annular channel; 2. Substrate; 21. First target capacitor; 22. Second target capacitor; 3. Chip core; 4. Cover plate; 41. Evaporation end; 42. Steam chamber; 43. Condensation end; 5. Thermal interface material; 6. Solder ball; 7. Flexible heat dissipation layer; 8. PCB board; 9. Cavity. DETAILED DESCRIPTION

[0039] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0040] It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. Moreover, all other embodiments obtained by ordinary technicians in the field without creative work based on the embodiments in the present disclosure are within the scope of protection of the present disclosure.

[0041] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein may be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein may be implemented independently of any other aspect, and two or more of these aspects may be combined in various ways. For example, any number of aspects described herein may be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein may be used to implement this device and / or practice this method.

[0042] As an embodiment of the present invention, Figure 1 As shown, a substrate 2 warping suppression structure is provided, the suppression structure comprising: a warping suppression ring 1 and a first accommodating groove 10 .

[0043] The cross section of the warping suppression ring 1 is rectangular, and the warping suppression ring 1 has a first connection end face and a second connection end face that are arranged opposite to each other, and the second connection end face is used to be fixedly connected to the edge area of ​​the substrate 2. Specifically, the warping suppression ring 1 can be a ring in an existing chip packaging structure, which is arranged in an annular shape, fixedly covered on the edge area of ​​the substrate 2 by welding or gluing, and extends a certain length toward the center area of ​​the substrate 2. Usually, the warping suppression ring 1 can be made of stainless steel or copper, and its function is equivalent to a reinforcing rib, which suppresses the deformation of the substrate 2 to a certain extent, thereby reducing the amplitude of the warping deformation of the substrate 2 after the temperature changes, and thereby reducing the risk of the solder ball 6 fixed between the substrate 2 and the PCB (Printed Circuit Board) board being crushed or torn, so as to further improve the operating stability of the chip.

[0044] The first accommodating groove 10 is a rectangular groove. The first accommodating groove 10 is opened on the second connecting end surface and extends toward the first connecting end surface, and the depth of the first accommodating groove 10 is less than the distance between the first connecting end surface and the second connecting end surface. A plurality of first accommodating grooves 10 are arranged at intervals.

[0045] In the prior art, in order to avoid the capacitor on the substrate 2, the coverage width of the ring is generally relatively small, which leads to a reduction in the coverage area of ​​the entire ring, a decrease in its own rigidity, and thus a significant reduction in the ability of the ring to limit the warping of the substrate 2.

[0046] In this embodiment, a corresponding first accommodating groove 10 is also provided on the side of the warpage suppression ring 1 close to the substrate 2. The capacitor cover provided on the substrate 2 can be placed in the first accommodating groove 10. Therefore, through the above-mentioned structural setting, when the warpage suppression ring 1 is connected to the substrate 2, it is not necessary to reduce its own coverage width W in order to avoid the capacitor. Instead, without being restricted by the capacitor, the coverage width can be increased as much as possible to increase the coverage area, and finally the ability to suppress the deformation amplitude of the substrate 2 is improved, which can reduce the amplitude of the warpage of the substrate 2 and increase the stability of the chip.

[0047] In addition, the cross section of the warpage suppression ring 1 in this embodiment is rectangular, and the first accommodating groove 10 is a rectangular parallelepiped groove. Therefore, at the position where the first accommodating groove 10 is provided, the cross section of the warpage suppression ring 1 is similar to an n-shaped hollow rectangular frame, such as Figure 1As shown in the enlarged view on the right side of the figure. This cross-sectional shape can further increase the volume of the solid part of the warpage suppression ring 1, while also ensuring the flatness of the upper surface of the warpage suppression ring 1. When encountering external physical impact (such as falling), on the one hand, a larger impact surface can be provided, thereby reducing the impact pressure at each location. On the other hand, since the warpage suppression ring 1 itself has more solid parts, the absorption of impact energy can be increased, thereby reducing the degree of damage to the substrate 2 and the capacitor caused by external physical impact.

[0048] In the present invention, an experimental comparison is made between the warping suppression capability of the existing ring structure and the ring structure in this embodiment on the substrate 2 at different temperatures. The experimental results are as follows: Figure 7 and Figure 8 As shown. Specifically, three groups of rings of different forms are set to package substrates 2 of the same specifications. The core material of the packaged substrate 2 is E705GX, the thickness of the substrate 2 is 2.19mm, the size of the substrate 2 is L1=70mm, L4=58mm, and the diagonal length is 90.9mm. The material of the chip core 3 on the substrate 2 is silicon wafer, and the size of the chip core 3 is L2=44mm, L3=30mm.

[0049] The three sets of rings are made of stainless steel and are fixedly connected to the substrate 2 by conventional glue. However, the structures and widths of the three sets of rings are different, as follows:

[0050] The first warpage suppression group Figure 4 As shown, the ring is a completely solid annular structure, on which there is no first accommodating groove 10 and annular channel 12, and due to the limitation of the capacitor arranged on the substrate 2, the width L5 of the ring is 8 mm.

[0051] The second warpage suppression group Figure 5 As shown, the ring is provided with a circle of annular channels 12 in the middle, and part of the capacitors arranged on the substrate 2 are placed therein. Since part of the capacitance limitation can be eliminated, the width of the ring can be larger L5=10 mm.

[0052] The third warpage suppression group Figure 6 As shown, the ring is the structural form in this embodiment, that is, a first accommodating groove 10 is opened at the location where some capacitors are set, so that some capacitors arranged on the substrate 2 are placed therein. Since part of the capacitance limitation can be eliminated, the width of the ring can be larger L5=10mm.

[0053] Figure 7In the figure, the warping degree of the diagonal of the substrate 2 in the three groups of experimental objects in a high temperature environment (125℃~240℃), in which the two sides of the substrate 2 are warped upwards, forming a smiley warping form. Among them, the ordinate is the warping degree value of the substrate 2, and the abscissa is the distance from each position on the basic diagonal line to the center of the substrate 2. The deformation curves in the figure are the warping changes of the substrate 2 in the first warping suppression group to the third warping suppression group in a 240℃ environment from top to bottom.

[0054] Depend on Figure 7 It can be seen that the ability of the ring to suppress the warping of the substrate 2 in a high temperature environment gradually increases in the order of the first warping suppression group to the third warping suppression group. The third warping suppression group has a 15.4% improvement in the ability to suppress the warping of the substrate 2 relative to the first warping suppression group, and a 6.7% improvement in the ability to suppress the warping of the substrate 2 relative to the second warping suppression group.

[0055] Correspondingly, Figure 8 The figure shows the warping degree of the diagonal of the substrate 2 in the three groups of experimental objects in a normal temperature environment (125℃~30℃). In this environment, the two sides of the substrate 2 are warped downward, forming a crying face warping form. Among them, the ordinate is the warping degree value of the substrate 2, and the abscissa is the distance from each position on the basic diagonal line to the center of the substrate 2. The deformation curves in the figure are the warping changes of the substrate 2 of the first warping suppression group to the third warping suppression group in a 30℃ environment from bottom to top.

[0056] Depend on Figure 8 It can be seen that the ability of the ring to suppress the warping of the substrate 2 in a normal temperature environment gradually increases from the first group to the third group. The third group has a 16.2% improvement in suppressing the warping of the substrate 2 relative to the first group, and a 4.6% improvement in suppressing the warping of the substrate 2 relative to the second group.

[0057] Furthermore, in order to improve the protection degree of the capacitor, the cross section of the first accommodating groove 10 can also be set to be in the shape of an arched door. The cross section in the present invention refers to the cross section in the circumferential direction of the warpage suppression ring 1.

[0058] Furthermore, the setting position of each first accommodating groove 10 corresponds to the installation position of the first target capacitor 21, the volume of the first accommodating groove 10 is larger than the volume of the first target capacitor 21, and the first target capacitor 21 is a capacitor whose installation area on the substrate 2 overlaps with the connection area between the warping suppression ring 1 and the substrate 2.

[0059] In this embodiment, the location of the first accommodating groove 10 is mainly determined by the location of the first accommodating groove 10 on the substrate 2. Thus, the influence of the warpage suppression ring 1 on the capacitor location can be reduced to improve the flexibility of capacitor design.

[0060] As another embodiment of the present invention, Figure 2 As shown, a substrate 2 warping suppression structure further includes: at least one second accommodating through groove 11 .

[0061] The second accommodating through groove 11 is opened on the second connecting end surface and vertically penetrates to the first connecting end surface, and the second accommodating through groove 11 horizontally penetrates to the inner side surface of the warping suppression ring 1. A plurality of second accommodating through grooves 11 are arranged at intervals.

[0062] Specifically, the setting position of each second accommodating groove 11 corresponds to the installation position of the second target capacitor 22, the volume of the second accommodating groove 11 is larger than the volume of the second target capacitor 22, and the second target capacitor 22 is a capacitor in which the installation area on the substrate 2 and the connection area between the warping suppression ring 1 and the substrate 2 partially overlap.

[0063] Since large chips have stronger and more complex power requirements, more capacitors will be arranged in the area around the chip core 3 of the substrate 2. When arranging these capacitors, the most suitable installation positions will be selected according to the requirements, so some capacitors are installed closer to the chip core 3 area. The installation area of ​​some capacitors will partially overlap with the installation area of ​​the warpage suppression ring 1 on the substrate 2.

[0064] In this case, in order to further increase the coverage width of the warpage suppression ring 1, a second accommodating through groove 11 is provided to avoid the second target capacitor 22 there. At the same time, since this area is closer to the chip core 3 area, the temperature in this area will also be higher during actual use, and in order to allow the temperature of this area to be dissipated more smoothly. Therefore, the second accommodating through groove 11 is configured to be vertically through the first connection end face and horizontally through the inner side of the warpage suppression ring 1. As a result, the volume of the open structure in this area is increased, which makes it easier to dissipate the temperature quickly.

[0065] Furthermore, the first accommodating grooves 10 and the second accommodating through grooves 11 are arranged alternately in the circumferential direction of the warping suppression ring 1. This structural arrangement can avoid a situation where the solid area of ​​a certain area on the warping suppression ring 1 is greatly reduced, resulting in a significant reduction in the rigidity of the area, thereby reducing the overall rigidity of the warping suppression ring 1. The control capability of the warping suppression ring 1 on the warping deformation of the substrate 2 can be improved.

[0066] According to a second aspect of the present invention, Fig. 9 As shown, a chip packaging structure is also provided, which includes: a cover plate 4, a flexible heat dissipation layer 7 and a warping suppression structure.

[0067] The cover plate 4 is used to be fixedly arranged right above the chip core 3 , and the cover plate 4 has a first heat dissipation end surface arranged close to the chip core 3 .

[0068] The cover plate 4 is mainly used to cover the chip core 3 to physically encapsulate the chip core 3, thereby providing physical protection for the chip core 3 and preventing the chip core 3 from being damaged. The shape of the cover plate 4 should be adapted to the general shape of the chip core 3 to be encapsulated, and the specific shape can be set according to actual conditions. The cover plate 4 is usually in the shape of a rectangular parallelepiped.

[0069] Preferably, the cover plate 4 is a copper heat dissipation cover plate 4 .

[0070] Specifically, the conventional cover plate 4 needs to consider both protection and heat conduction efficiency, so copper can be selected as the heat dissipation cover plate 4 .

[0071] More preferably, Fig. 9 As shown, the cover plate 4 is a vacuum chamber heat spreader, and the end surface of the vacuum chamber heat spreader on one side of the evaporation end 41 is a first heat dissipation end surface. The vacuum chamber heat spreader is a VC heat spreader.

[0072] VC vapor chambers (vapor chambers) are similar to heat pipes in principle, but differ in the way they are conducted. Heat pipes conduct heat in a one-dimensional linear manner, while heat in a vapor chamber is conducted on a two-dimensional surface, so it is more efficient.

[0073] Specifically, the VC heat spreader has an evaporation end 41, a steam chamber 42 (vacuum chamber) and a condensation end 43. After absorbing the heat of the chip, the liquid at the evaporation end 41 evaporates and diffuses into the vacuum chamber, conducts the heat to the heat dissipation fins at the condensation end 43, and then condenses into liquid and returns to the bottom of the evaporation end 41. This evaporation and condensation process, similar to that of a refrigerator or air conditioner, circulates rapidly in the vacuum chamber, which can greatly improve the heat dissipation efficiency.

[0074] Specifically, the flexible heat dissipation layer 7 is fixedly connected to the first heat dissipation end surface by electroplating, chemical plating or welding.

[0075] like Fig. 9 As shown, the thickness of the flexible heat dissipation layer 7 is greater than the distance H1 between the first heat dissipation end surface and the upper surface of the chip core 3 , and the material of the flexible heat dissipation layer 7 is a flexible metal with adaptive deformation capability under external force.

[0076] The bottom surface area of ​​the flexible heat dissipation layer 7 is greater than or equal to the top surface area of ​​the chip core 3. The flexible metal includes nickel, copper, gold and silver.

[0077] Specifically, the distance between the first heat dissipation end surface and the upper surface of the chip core 3 described in this embodiment includes the convex and / or concave deformation of the upper surface of the chip core 3 due to temperature influence (such as Fig.10 As shown in the figure, the distance between the first heat dissipation end surface and the upper surface of the chip core 3 is the maximum distance between the two. Thus, it can be ensured that the flexible heat dissipation layer 7 is in a compressed state in any state, that is, the flexible heat dissipation layer 7 is always squeezed by external force. Thus, the thickness of the flexible heat dissipation layer 7 will also change adaptively, so that the flexible heat dissipation layer 7 is always in close contact with the TIM1.

[0078] Preferably, Fig. 9 As shown, the area of ​​the first heat dissipation end surface is larger than the upper surface area of ​​the chip core 3. This arrangement can make the area covered by the cover plate 4 larger than the area of ​​the chip core 3. After the corresponding packaging is completed, the volume of the internal space surrounded by the cover plate 4 is larger than the total volume of the chip core 3. In addition, a cavity 9 is formed in the outer area of ​​the edge of the chip core 3, and the cavity 9 can be used as a space for accommodating the extended and overflowed portion of the flexible heat dissipation layer 7 after being compressed.

[0079] The existing chip packaging structure and heat dissipation method will cause the heat dissipation end surface to have different contact degrees with TIM1 (thermal interface material 5 on chip core 3) due to the different spacing between the bottom surface of the heat dissipation cover and the upper surface of each Die (chip core 3). Specifically, the area with smaller spacing has good contact with TIM1, while the area with larger spacing has poor contact with TIM1. In addition, when the temperature of chip core 3 rises or falls, the upper surface of chip core 3 will be deformed to be convex and / or concave, such as Fig.10 In this state, the poor contact between the heat dissipation end surface and TIM1 is more likely to increase, resulting in the heat transfer path being cut off and the diffusion thermal resistance being increased, thereby greatly increasing the heat dissipation risk on the surface of the chip core 3 and reducing the stability of the chip.

[0080] Usually, the packaging space inside the chip is smaller than the actual installation and use space of the chip. Therefore, when solving the heat dissipation problem of the chip, the general understanding of those skilled in the art is to set a heat dissipation device with higher heat dissipation efficiency on the packaged chip to improve the heat dissipation efficiency, such as the technical solutions in CN115279112A and CN208999928U. Due to this technical bias, the direction of improving the heat dissipation efficiency by making improvements in the packaging space has been abandoned.

[0081] In the present invention, a flexible heat dissipation layer 7 is arranged on the first heat dissipation end surface of the heat dissipation cover close to the chip. Therefore, after the heat dissipation cover is packaged, since the thickness of the flexible heat dissipation layer 7 is greater than the distance between the first heat dissipation end surface and the upper surface of the chip core 3, the flexible heat dissipation layer 7 will be squeezed between the chip core 3 and the first heat dissipation end surface, that is, the flexible heat dissipation layer 7 will be squeezed between the TIM1 and the first heat dissipation end surface, so the area of ​​poor contact between the heat dissipation component and the TIM1 can be reduced to improve the heat dissipation effect.

[0082] At the same time, in actual use, in order to avoid the contamination and corrosion of other components in the chip after the TIM1 overflows, when the TIM1 is set, the actual coverage area of ​​the TIM1 is usually 80%-90% of the total area of ​​the upper surface of the chip core 3. After the extrusion and extension of the flexible heat dissipation layer 7 in the present invention, the coating area of ​​the TIM1 on the upper surface of the chip core 3 can be further increased, and the heat dissipation effect can be further improved.

[0083] In addition, since the flexible heat dissipation layer 7 has the ability to adaptively deform under the action of external force, the flexible heat dissipation layer 7 can change the thickness of different parts of itself according to the degree of external force compression. Therefore, even if the upper surface of the chip core 3 is deformed to be convex and / or concave, the flexible heat dissipation layer 7 can also adaptively adjust its own thickness to ensure the tightness of the fit between itself and the TIM1, ensure the smoothness of the heat transfer path, and thus improve the stability of the chip.

[0084] The packaging structure in this embodiment is experimentally verified by installing the first heat dissipation cover, the second heat dissipation cover, the third heat dissipation cover and the fourth heat dissipation cover in the same chip packaging structure, respectively, and testing the heat dissipation performance of the above four heat dissipation covers in the same operating state and operating environment. The specific results are as follows: Fig.11 As shown. There are a total of 5 packaged chip cores 3, which is a multi-die package. The first heat dissipation cover is an existing copper plate heat dissipation cover; the second heat dissipation cover is a heat dissipation cover with a copper plate as a cover plate 4 in this embodiment (copper plate + flexible heat dissipation layer 7); the third heat dissipation cover is an existing VC heat spreader heat dissipation cover; the fourth heat dissipation cover is a heat dissipation cover with a VC heat spreader as a cover plate 4 in this embodiment (VC heat spreader + flexible heat dissipation layer 7).

[0085] Specifically, Fig.11 The horizontal axis in the figure represents the experimental groups of the first to fourth heat dissipation covers from left to right. The vertical axis represents the temperature value. Each experimental group measures the temperature values ​​at two locations when the chip core 3 is running stably at 200w power consumption. One is to measure the temperature of the location with the highest junction temperature among multiple dies, which is the temperature shown in the T-junction legend in the figure. The other is to measure the highest temperature at the center of the heat dissipation cover, which is the temperature shown in the T-case legend.

[0086] Depend on Fig.11 It can be seen from the experimental data that the heat dissipation capacity of the packaged chip gradually increases in the order of the first heat dissipation cover to the fourth heat dissipation cover. Among them, the heat dissipation capacity of the second heat dissipation group (copper plate + flexible heat dissipation layer 7) is increased by 2.8°C for the junction temperature and 2.3°C for the temperature at the heat dissipation cover compared with the first heat dissipation group (copper plate). The heat dissipation capacity of the second heat dissipation group (copper plate + flexible heat dissipation layer 7) is increased by 2.8°C for the junction temperature and 2.3°C for the temperature at the heat dissipation cover compared with the first heat dissipation group (copper plate). The heat dissipation capacity of the fourth heat dissipation group (VC heat spreader + flexible heat dissipation layer 7) is increased by 2°C for the junction temperature and 1.9°C for the temperature at the heat dissipation cover compared with the third heat dissipation group (VC heat spreader).

[0087] The warping suppression structure is a substrate 2 warping suppression structure in any of the above embodiments, and the first connection end surface of the warping suppression ring 1 is fixedly connected to a portion of the first heat dissipation end surface close to the outer edge. The spacing H2 between the first connection end surface and the second connection end surface is greater than the thickness of the flexible heat dissipation layer 7, and the thickness at this location can be H1.

[0088] In this embodiment, the warpage suppression ring 1 and the cover plate 4 are integrally formed to form a shell that can be buckled on the chip core 3. Usually, the shell is a rectangular shell, and its cross-section is as follows: Fig. 9 Shown in the middle left section.

[0089] Since a flexible heat dissipation layer 7 of a certain thickness is provided on the first heat dissipation end surface of the cover plate 4 in this embodiment, the distance between the first heat dissipation end surface and the upper surface of the substrate 2 is larger than that of the existing heat dissipation cover, thereby making the thickness of the warping suppression ring 1 larger, that is, the distance H2 between the first connection end surface and the second connection end surface larger. Correspondingly, the rigidity of the warping suppression ring 1 itself will be higher, thereby further improving the ability to suppress the warping deformation of the substrate 2.

[0090] As another embodiment of the present invention, the thickness of the flexible heat dissipation layer 7 is positively correlated with the clamping thickness, so that after packaging, the pressure of the flexible heat dissipation layer 7 on the chip core 3 is within the range of 40psi to 90psi.

[0091] The clamping thickness is the distance between the first heat dissipation end surface and the upper surface of the thermal interface material 5 on the chip core 3 after the package is completed.

[0092] Furthermore, the thickness of the flexible heat dissipation layer 7 is 200 um to 300 um.

[0093] Specifically, after the packaging is completed, the flexible heat dissipation layer 7 is sandwiched between the first heat dissipation end surface and the thermal interface material 5. At the same time, due to the reaction force of the flexible heat dissipation layer 7, the upper surface of each chip core 3 will be subjected to a certain pressure. However, when the pressure value is greater than the pressure limit of the chip core 3, the chip core 3 (silicon wafer) will be crushed. Therefore, it is necessary to control the pressure range of the flexible heat dissipation layer 7 on the chip core 3. Usually, the pressure of the flexible heat dissipation layer 7 on the chip core 3 is in the range of 40psi to 90psi, which can ensure that the chip core 3 (silicon wafer) will not be crushed.

[0094] In this embodiment, the thickness of the flexible heat dissipation layer 7 is controlled to control the pressure of the flexible heat dissipation layer 7 on the chip core 3 to be within a normal range. However, since there will be certain processing errors in the heat dissipation cover, the chip core 3 and the warpage suppression ring 1 in actual processing, and the chip core 3 and the substrate 2 will also produce certain deformations in actual use, the thickness of the space between the first heat dissipation end surface and the thermal interface material 5 is in a changing state. Therefore, the range of variation of the thickness of the space between the first heat dissipation end surface and the thermal interface material 5 can be determined according to the actual use scenario, and then the thickness value of the flexible heat dissipation layer 7 that meets the use requirements can be calculated in combination with the magnitude of the reaction force generated by the specific material of the flexible heat dissipation layer 7 after deformation. In this embodiment, the 200um to 300um provided is calculated based on the existing commonly used packaging structure in combination with the above method. This thickness value can be applied to most packaging use scenarios, and at the same time, a larger thickness value can be selected as much as possible if allowed, such as 240um and 250um.

[0095] After the heat dissipation cover packaging in this embodiment is completed, a cavity 9 will be formed in the outer area of ​​the edge of the chip core 3, and the cavity 9 can be used as a storage space for the extended overflow part of the flexible heat dissipation layer 7 after being compressed. Therefore, even if a larger thickness is selected, it can easily overflow in the later extrusion, and then the pressure can be adjusted adaptively. Therefore, after the packaging is completed, it is convenient to install an external heat dissipation device with higher specifications and higher weight. At the same time, a larger thickness can also have a higher buffering performance, which can further reduce the risk of damage to the chip when it is impacted by external forces (such as falling).

[0096] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A substrate warpage suppression structure, characterized in that: include: A warping suppression ring having a first connection end surface and a second connection end surface arranged opposite to each other, wherein the second connection end surface is used for fixed connection with an edge area of ​​the substrate; as well as At least one first accommodating groove is opened on the second connecting end surface and extends toward the first connecting end surface, and the depth of the first accommodating groove is smaller than the distance between the first connecting end surface and the second connecting end surface; multiple first accommodating grooves are arranged at intervals.

2. A substrate warpage suppression structure according to claim 1, characterized in that: The setting position of each first accommodating groove corresponds to the placement position of the first target capacitor, the volume of the first accommodating groove is larger than the volume of the first target capacitor, and the first target capacitor is a capacitor whose installation area on the substrate overlaps with the connection area between the warping suppression ring and the substrate.

3. The substrate warpage suppression structure according to claim 1, characterized in that: The cross section of the warping suppression ring is rectangular, and the first accommodating groove is a rectangular parallelepiped groove.

4. The substrate warpage suppression structure according to claim 1, characterized in that: Also includes: At least one second accommodating through groove is opened on the second connecting end surface and vertically penetrates to the first connecting end surface, and the second accommodating through groove horizontally penetrates to the inner side surface of the warping suppression ring; multiple second accommodating through grooves are arranged at intervals.

5. The substrate warpage suppression structure according to claim 4, characterized in that: The setting position of each of the second accommodating grooves corresponds to the placement position of the second target capacitor, the volume of the second accommodating groove is larger than the volume of the second target capacitor, and the second target capacitor is a capacitor in which the installation area on the substrate partially overlaps with the connection area between the warping suppression ring and the substrate.

6. The substrate warpage suppression structure according to claim 5, characterized in that: The first accommodating grooves and the second accommodating through grooves are alternately arranged in a circumferential direction of the warping suppression ring.

7. A chip packaging structure, characterized in that: include: A cover plate, used for being fixedly arranged just above the chip core, the cover plate having a first heat dissipation end surface arranged close to the chip core; A flexible heat dissipation layer is fixedly arranged on the first heat dissipation end surface, the thickness of the flexible heat dissipation layer is greater than the distance between the first heat dissipation end surface and the upper surface of the chip core, and the material of the flexible heat dissipation layer is a flexible metal with adaptive deformation ability under the action of external force; as well as According to a substrate warping suppression structure as described in any one of claims 1 to 6, the first connecting end face of the warping suppression ring is fixedly connected to a portion of the first heat dissipation end face close to an outer edge; and the spacing between the first connecting end face and the second connecting end face is greater than the thickness of the flexible heat dissipation layer.

8. The chip packaging structure according to claim 7, characterized in that: The cover plate is a vacuum chamber heat spreader, and the end surface of the vacuum chamber heat spreader on one side of the evaporation end is a first heat dissipation end surface.

9. The chip packaging structure according to claim 7, characterized in that: The flexible heat dissipation layer is fixedly connected to the first heat dissipation end surface by electroplating, chemical plating or welding; the flexible metal includes nickel, copper, gold and silver.

10. The chip packaging structure according to claim 7, characterized in that: The area of ​​the first heat dissipation end surface is larger than the upper surface area of ​​the chip core.

Images