Chip packaging heat dissipation cover and chip packaging structure

Abstract

The invention relates to the field of chip packaging, in particular to a chip packaging heat dissipation cover and a chip packaging structure.The chip packaging heat dissipation cover comprises a cover plate and a flexible heat dissipation layer, the flexible heat dissipation layer is fixedly arranged on a first heat dissipation end face, and the thickness of the flexible heat dissipation layer is larger than the distance between the first heat dissipation end face and the upper surface of a chip kernel; the flexible heat dissipation layer is made of flexible metal with self-adaptive deformation capacity under the action of external force. The flexible heat dissipation layer is arranged on the first heat dissipation end face, close to the chip, of the heat dissipation cover, so that after packaging of the heat dissipation cover is completed, the flexible heat dissipation layer can be extruded between the TIM1 and the first heat dissipation end face, the area where a heat dissipation component and the TIM1 are in poor contact can be reduced, and the heat dissipation effect is improved. Besides, even if the upper surface of the chip core is subjected to upward convex and / or inward concave deformation, the flexible heat dissipation layer can adjust the thickness of the flexible heat dissipation layer in a self-adaptive manner, so that the attaching tightness between the flexible heat dissipation layer and the TIM1 is ensured, and the stability of the chip is further improved.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging, and in particular to a chip packaging heat dissipation cover and a chip packaging structure. Background Art

[0002] With the development of advanced technologies such as AI computing, big data, and cloud services, computing power has increased exponentially, which has led to the development of chips with high integration and high power consumption. The corresponding heat consumption and heat flux density of chips are also continuously increasing, and the resulting chip heat dissipation problem has become a technical bottleneck affecting chip functions and reliability.

[0003] Conventional chip packaging uses copper as a heat sink to ensure heat diffusion and transfer. For chips that are packaged in multiple dies (chip cores), the height of each die itself has certain differences due to manufacturing tolerance limitations, which will cause the top surface height of each die sealed on the same substrate to be inconsistent.

[0004] If the above packaging structure and heat dissipation method are used, the distance between the bottom surface of the heat dissipation cover and the upper surface of each die will be different, which will cause the contact degree between the heat dissipation end surface and TIM1 (thermal interface material on the chip core) to be different. Specifically, the area with smaller distance has good contact with TIM1, while the area with larger distance has poor contact with TIM1. In addition, when the temperature of the chip core rises or falls, the upper surface of the chip core will be convex and / or concave, such as Figure 3 In this state, it is easier to increase the degree of poor contact between the heat dissipation end surface and TIM1, resulting in the heat transfer path being cut off and the diffusion thermal resistance being increased, which greatly increases the risk of heat dissipation on the surface of the chip core and reduces the stability of the chip. Summary of the invention

[0005] In view of this, the present invention provides a chip package heat dissipation cover and a chip, which at least partially solve the problems existing in the prior art.

[0006] According to one aspect of the present invention, a chip package heat dissipation cover is provided, comprising:

[0007] A cover plate, used for being fixedly arranged just above the chip core, the cover plate having a first heat dissipation end surface arranged close to the chip core; and

[0008] The flexible heat dissipation layer is fixedly arranged on the first heat dissipation end surface. The thickness of the flexible heat dissipation layer is greater than the distance between the first heat dissipation end surface and the upper surface of the chip core. The material of the flexible heat dissipation layer is a flexible metal with adaptive deformation ability under external force.

[0009] Furthermore, it also includes:

[0010] A warping suppression ring having a first connecting end surface and a second connecting end surface that are arranged opposite to each other;

[0011] The first connection end surface is fixedly connected to the first heat dissipation end surface of the cover plate, and the connection between the first connection end surface and the first heat dissipation end surface is located near the outer edge of the first heat dissipation end surface;

[0012] The second connection end surface is used for fixed connection with the substrate, and the distance between the first connection end surface and the second connection end surface is greater than the thickness of the flexible heat dissipation layer.

[0013] Furthermore, the thickness of the flexible heat dissipation layer is positively correlated with the clamping thickness, so that the pressure of the flexible heat dissipation layer on the chip core after packaging is within the range of 40psi to 90psi;

[0014] The clamping thickness is the distance between the first heat dissipation end surface and the upper surface of the thermal interface material on the chip core after the package is completed.

[0015] Furthermore, the thickness of the flexible heat dissipation layer is 200um to 300um.

[0016] Furthermore, the cover plate is a copper heat dissipation cover plate.

[0017] Furthermore, the cover plate is a vacuum chamber heat spreader, and the end surface of the vacuum chamber heat spreader on one side of the evaporation end is a first heat dissipation end surface.

[0018] Furthermore, the flexible heat dissipation layer is fixedly connected to the first heat dissipation end surface by electroplating, chemical plating or welding; the flexible metal includes nickel, copper, gold and silver.

[0019] Furthermore, the area of ​​the first heat dissipation end surface is larger than the upper surface area of ​​the chip core.

[0020] Furthermore, the bottom surface area of ​​the flexible heat dissipation layer is greater than or equal to the top surface area of ​​the chip core.

[0021] According to a second aspect of the present invention, there is further provided a chip, comprising:

[0022] A substrate, used to fix and place at least one chip core;

[0023] A thermal interface material is fixedly disposed on the upper surface of each chip core; and

[0024] The above-mentioned chip packaging heat dissipation cover, the cover plate is fixedly arranged on the substrate, the flexible heat dissipation layer is sandwiched between the first heat dissipation end surface and the thermal interface material, and there is a gap between the inner wall of the connection between the cover plate and the substrate and the outer wall of the chip core located at the edge to form an extension space for the flexible heat dissipation layer.

[0025] The technical solution of the present invention has at least the following beneficial effects:

[0026] Usually, the packaging space inside the chip is smaller than the actual installation and use space of the chip. Therefore, when solving the heat dissipation problem of the chip, the general understanding of those skilled in the art is to set a heat dissipation device with higher heat dissipation efficiency on the packaged chip to improve the heat dissipation efficiency, such as the technical solutions in CN115279112A and CN208999928U. Due to this technical bias, the direction of improving the heat dissipation efficiency by making improvements in the packaging space has been abandoned.

[0027] In the present invention, a flexible heat dissipation layer is arranged on the first heat dissipation end surface of the heat dissipation cover close to the chip. Therefore, after the heat dissipation cover is packaged, since the thickness of the flexible heat dissipation layer is greater than the distance between the first heat dissipation end surface and the upper surface of the chip core, the flexible heat dissipation layer will be squeezed between the chip core and the first heat dissipation end surface, that is, the flexible heat dissipation layer will be squeezed between TIM1 and the first heat dissipation end surface, so the area of ​​poor contact between the heat dissipation component and TIM1 can be reduced to improve the heat dissipation effect.

[0028] At the same time, in actual use, in order to avoid the contamination and corrosion of other components in the chip after the TIM1 overflows, when the TIM1 is set, the actual coverage area of ​​the TIM1 is usually 80%-90% of the total area of ​​the upper surface of the chip core. After the extrusion and extension of the flexible heat dissipation layer in the present invention, the coating area of ​​the TIM1 on the upper surface of the chip core can be further increased, further improving the heat dissipation effect.

[0029] In addition, since the flexible heat dissipation layer has the ability to adaptively deform under the action of external force, the flexible heat dissipation layer can change the thickness of different parts of itself according to the degree of external force compression. Therefore, even if the upper surface of the chip core is deformed to be convex and / or concave, the flexible heat dissipation layer can also adaptively adjust its own thickness to ensure the tightness of the fit between itself and TIM1, ensure the smoothness of the heat transfer path, and thus improve the stability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 This is a schematic structural diagram of a chip package heat dissipation cover (without a first accommodating groove) packaged onto a chip in an embodiment of the present application;

[0032] Figure 2This is a structural schematic diagram of a chip package heat dissipation cover (with a first accommodating groove) packaged onto a chip in another embodiment of the present application;

[0033] Figure 3 This is a schematic diagram of the upper surface of the chip core being deformed upward and concave due to temperature in another embodiment of the present application;

[0034] Figure 4 This is a schematic diagram of the temperature performance of four heat dissipation experiment groups in another embodiment of the present application;

[0035] Figure 5 This is a schematic diagram of the connection structure between the warping suppression ring and the first accommodating groove in another embodiment of the present application;

[0036] Figure 6 This is a schematic structural diagram of another embodiment of the present application in which a substrate forms a smiling face (right side) or a crying face (left side) shape under the influence of temperature;

[0037] Figure 7 This is a schematic structural diagram of a first warpage suppression group in another embodiment of the present application;

[0038] Figure 8 This is a schematic structural diagram of the first warpage suppression group in another second embodiment of the present application;

[0039] Fig. 9 Schematic diagram of the structure of the first warpage suppression group in another three embodiments of the present application;

[0040] Fig.10 It is a curve change diagram of the warping degree of the diagonal line of the substrate in three groups of experimental objects in another embodiment of the present application in a high temperature environment (240° C.);

[0041] Fig.11 It is a curve change diagram of the warping degree of the diagonal line of the substrate in three groups of experimental objects in another embodiment of the present application in a room temperature environment (30° C.);

[0042] Reference numerals

[0043] 1. Warping suppression ring; 10. First accommodating groove; 12. Annular channel; 2. Substrate; 21. First target capacitor; 3. Chip core; 4. Cover plate; 41. Evaporation end; 42. Steam chamber; 43. Condensation end; 5. Thermal interface material; 6. Solder ball; 7. Flexible heat dissipation layer; 8. PCB board; 9. Cavity. DETAILED DESCRIPTION

[0044] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] It should be noted that the following embodiments and features in the embodiments may be combined with each other in the absence of conflict; and, based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making any creative work are within the scope of protection of the present disclosure.

[0046] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein may be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein may be implemented independently of any other aspect, and two or more of these aspects may be combined in various ways. For example, any number of aspects described herein may be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein may be used to implement this device and / or practice this method.

[0047] As an embodiment of the present invention, Figure 1 As shown, a chip package heat dissipation cover is provided, and the package heat dissipation cover includes: a cover plate 4 and a flexible heat dissipation layer 7.

[0048] The cover plate 4 is used to be fixedly arranged right above the chip core 3 , and the cover plate 4 has a first heat dissipation end surface arranged close to the chip core 3 .

[0049] The cover plate 4 is mainly used to cover the chip core 3 to physically encapsulate the chip core 3, thereby providing physical protection for the chip core 3 and preventing the chip core 3 from being damaged. The shape of the cover plate 4 should be adapted to the general shape of the chip core 3 to be encapsulated, and the specific shape can be set according to actual conditions. The cover plate 4 is usually in the shape of a rectangular parallelepiped.

[0050] Preferably, the cover plate 4 is a copper heat dissipation cover plate 4 .

[0051] Specifically, the conventional cover plate 4 needs to consider both protection and heat conduction efficiency, so copper can be selected as the heat dissipation cover plate 4 .

[0052] More preferably, the cover plate 4 is a vacuum chamber heat spreader, and the end surface of the vacuum chamber heat spreader on one side of the evaporation end 41 is the first heat dissipation end surface. The vacuum chamber heat spreader is a VC heat spreader.

[0053] VC vapor chambers (vapor chambers) are similar to heat pipes in principle, but differ in the way they are conducted. Heat pipes conduct heat in a one-dimensional linear manner, while heat in a vapor chamber is conducted on a two-dimensional surface, so it is more efficient.

[0054] like Figure 1 As shown, specifically, the VC heat spreader has an evaporation end 41, a steam chamber 42 (vacuum chamber) and a condensation end 43. After absorbing the heat of the chip, the liquid at the evaporation end 41 evaporates and diffuses into the vacuum chamber, conducts the heat to the heat dissipation fins at the condensation end 43, and then condenses into liquid and returns to the evaporation end 41 at the bottom. This evaporation and condensation process similar to that of a refrigerator and air conditioner circulates rapidly in the vacuum chamber, which can greatly improve the heat dissipation efficiency.

[0055] Specifically, the flexible heat dissipation layer 7 is fixedly connected to the first heat dissipation end surface by electroplating, chemical plating or welding.

[0056] The thickness of the flexible heat dissipation layer 7 is greater than the distance H1 between the first heat dissipation end surface and the upper surface of the chip core 3. The material of the flexible heat dissipation layer 7 is a flexible metal with adaptive deformation capability under the action of external force. The bottom surface area of ​​the flexible heat dissipation layer 7 is greater than or equal to the upper surface area of ​​the chip core 3. Flexible metals include nickel, copper, gold and silver.

[0057] Specifically, the distance between the first heat dissipation end surface and the upper surface of the chip core 3 described in this embodiment includes the distance between the upper surface of the chip core 3 and the first heat dissipation end surface after the upper surface of the chip core 3 is deformed upward and / or concave due to temperature. And the preferred distance between the first heat dissipation end surface and the upper surface of the chip core 3 is the maximum distance between the two. Thus, it can be ensured that the flexible heat dissipation layer 7 is in a compressed state in any state, that is, the flexible heat dissipation layer 7 is always squeezed by external force. Thus, the thickness of the flexible heat dissipation layer 7 will also change adaptively, so that the flexible heat dissipation layer 7 is always tightly fitted with TIM1 (thermal interface material 5).

[0058] Preferably, the area of ​​the first heat dissipation end surface is larger than the upper surface area of ​​the chip core 3. This configuration can make the area covered by the cover plate 4 larger than the area of ​​the chip core 3. After the corresponding packaging is completed, the volume of the internal space surrounded by the cover plate 4 is larger than the total volume of the chip core 3. Then, a cavity 9 is formed in the outer area of ​​the edge of the chip core 3, such as Figure 1 As shown, the cavity 9 can be used as a storage space for the extended and overflowed portion of the flexible heat dissipation layer 7 after being compressed.

[0059] The packaging structure in this embodiment is experimentally verified by installing the first heat dissipation cover, the second heat dissipation cover, the third heat dissipation cover and the fourth heat dissipation cover in the same chip packaging structure, respectively, and testing the heat dissipation performance of the above four heat dissipation covers in the same operating state and operating environment. The specific results are as follows: Figure 4As shown. There are a total of 5 packaged chip cores 3, which is a multi-die package. The first heat dissipation cover is an existing copper plate heat dissipation cover; the second heat dissipation cover is a heat dissipation cover with a copper plate as a cover plate 4 in this embodiment (copper plate + flexible heat dissipation layer 7); the third heat dissipation cover is an existing VC heat spreader heat dissipation cover; the fourth heat dissipation cover is a heat dissipation cover with a VC heat spreader as a cover plate 4 in this embodiment (VC heat spreader + flexible heat dissipation layer 7).

[0060] Specifically, Figure 4 The horizontal axis in the figure represents the experimental groups of the first to fourth heat dissipation covers from left to right. The vertical axis represents the temperature value. Each experimental group measures the temperature values ​​at two locations when the chip core 3 is running stably at 200w power consumption. One is to measure the temperature of the location with the highest junction temperature among multiple dies, which is the temperature shown in the T-junction legend in the figure. The other is to measure the highest temperature at the center of the heat dissipation cover, which is the temperature shown in the T-case legend.

[0061] Depend on Figure 4 It can be seen from the experimental data that the heat dissipation capacity of the packaged chip gradually increases in the order of the first heat dissipation cover to the fourth heat dissipation cover. Among them, the heat dissipation capacity of the second heat dissipation group (copper plate + flexible heat dissipation layer 7) is increased by 2.8°C for the junction temperature and 2.3°C for the temperature at the heat dissipation cover compared with the first heat dissipation group (copper plate). The heat dissipation capacity of the second heat dissipation group (copper plate + flexible heat dissipation layer 7) is increased by 2.8°C for the junction temperature and 2.3°C for the temperature at the heat dissipation cover compared with the first heat dissipation group (copper plate). The heat dissipation capacity of the fourth heat dissipation group (VC heat spreader + flexible heat dissipation layer 7) is increased by 2°C for the junction temperature and 1.9°C for the temperature at the heat dissipation cover compared with the third heat dissipation group (VC heat spreader).

[0062] As another embodiment of the present invention, Figure 1 As shown, the package heat dissipation cover further includes: a warpage suppression ring 1 .

[0063] The warpage suppression ring 1 has a first connection end surface and a second connection end surface which are arranged opposite to each other.

[0064] The first connection end surface is fixedly connected to the first heat dissipation end surface of the cover plate 4 , and the connection between the first connection end surface and the first heat dissipation end surface is located close to the outer edge of the first heat dissipation end surface.

[0065] The second connection end surface is used for fixed connection with the substrate 2 . The distance H2 between the first connection end surface and the second connection end surface is greater than the thickness of the flexible heat dissipation layer 7 . The thickness at this location may be H1 .

[0066] The warpage suppression ring 1 in this embodiment can be a ring in an existing chip packaging structure, which is arranged in an annular shape, fixedly covered on the edge area of ​​the substrate 2 by welding or gluing, and extends a certain length toward the center area of ​​the substrate 2. The warpage suppression ring 1 can usually be made of stainless steel or copper, and its function is equivalent to a reinforcing rib, which suppresses the deformation of the substrate 2 to a certain extent, thereby reducing the amplitude of the warpage deformation of the substrate 2 after the temperature changes, and further reducing the risk of the solder ball 6 fixed between the substrate 2 and the PCB (Printed Circuit Board) being crushed or torn, so as to further improve the operation stability of the chip.

[0067] In this embodiment, the warpage suppression ring 1 and the cover plate 4 are integrally formed to form a shell that can be buckled on the chip core 3. Usually, the shell is a rectangular shell, and its cross-section is as follows: Figure 1 shown.

[0068] Since a flexible heat dissipation layer 7 of a certain thickness is provided on the first heat dissipation end surface of the cover plate 4 in this embodiment, the distance between the first heat dissipation end surface and the upper surface of the substrate 2 is larger than that of the existing heat dissipation cover, thereby making the thickness of the warping suppression ring 1 larger, that is, the distance between the first connection end surface and the second connection end surface larger. Correspondingly, the rigidity of the warping suppression ring 1 itself will be higher, thereby further improving the ability to suppress the warping deformation of the substrate 2.

[0069] Further, such as Figure 2 As shown, the cross section of the warpage suppression ring 1 is rectangular, and the first accommodating groove 10 is a rectangular groove. The first accommodating groove 10 is opened on the second connection end surface and extends toward the first connection end surface, and the depth of the first accommodating groove 10 is less than the distance H2 between the first connection end surface and the second connection end surface. Multiple first accommodating grooves 10 are arranged at intervals.

[0070] In the prior art, in order to avoid the capacitor on the substrate 2, the coverage width of the ring is generally relatively small, which leads to a reduction in the coverage area of ​​the entire ring, a decrease in its own rigidity, and thus a significant reduction in the ability of the ring to limit the warping of the substrate 2.

[0071] In this embodiment, a corresponding first accommodating groove 10 is also provided on the side of the warpage suppression ring 1 close to the substrate 2. The capacitor cover provided on the substrate 2 can be placed in the first accommodating groove 10. Therefore, through the above-mentioned structural setting, when the warpage suppression ring 1 is connected to the substrate 2, it is not necessary to reduce its own coverage width L5 in order to avoid the capacitor. Instead, without being restricted by the capacitor, the coverage width can be increased as much as possible to increase the coverage area, and finally the ability to suppress the deformation amplitude of the substrate 2 is improved, which can reduce the amplitude of the warping of the substrate 2 and increase the stability of the chip.

[0072] In addition, the cross section of the warpage suppression ring 1 in this embodiment is rectangular, and the first accommodating groove 10 is a rectangular parallelepiped groove. Therefore, at the position where the first accommodating groove 10 is provided, the cross section of the warpage suppression ring 1 is similar to an n-shaped hollow rectangular frame, such as Figure 5 As shown in the enlarged view on the right side of the figure. This cross-sectional shape can further increase the volume of the solid part of the warpage suppression ring 1, while also ensuring the flatness of the upper surface of the warpage suppression ring 1. When encountering external physical impact (such as falling), on the one hand, a larger impact surface can be provided, thereby reducing the impact pressure at each location. On the other hand, since the warpage suppression ring 1 itself has more solid parts, the absorption of impact energy can be increased, thereby reducing the degree of damage to the substrate 2 and the capacitor caused by external physical impact.

[0073] In the present invention, an experimental comparison is made between the warping suppression capability of the existing ring structure and the ring structure in this embodiment on the substrate 2 at different temperatures. The experimental results are as follows: Fig.10 and Fig.11 As shown. Specifically, three groups of rings of different forms are set to package substrates 2 of the same specifications. The core material of the packaged substrate 2 is E705GX, the thickness of the substrate 2 is 2.19mm, the size of the substrate 2 is L1=70mm, L4=58mm, and the diagonal length is 90.9mm. The material of the chip core 3 on the substrate 2 is silicon wafer, and the size of the chip core 3 is L2=44mm, L3=30mm.

[0074] The three sets of rings are made of stainless steel and are fixedly connected to the substrate 2 by conventional glue. However, the structures and widths of the three sets of rings are different, as follows:

[0075] The first warpage suppression group Figure 7 As shown, the ring is a completely solid annular structure, on which there is no first accommodating groove 10 and annular channel 12, and due to the limitation of the capacitor arranged on the substrate 2, the width L5 of the ring is 8 mm.

[0076] The second warpage suppression group Figure 8As shown, the ring is provided with a circle of annular channels 12 in the middle, and part of the capacitors arranged on the substrate 2 are placed therein. Since part of the capacitance limitation can be eliminated, the width of the ring can be larger L5=10 mm.

[0077] The third warpage suppression group Fig. 9 As shown, the ring is the structural form in this embodiment, that is, a first accommodating groove 10 is opened at the location where some capacitors are set, so that some capacitors arranged on the substrate 2 are placed therein. Since part of the capacitance limitation can be eliminated, the width of the ring can be larger L5=10mm.

[0078] Fig.10 The figure shows the degree of diagonal warping of the substrate 2 in the three groups of experimental objects in a high temperature environment (125°C to 240°C). In this environment, both sides of the substrate 2 are warped upward to form a smiley face warping form, such as Figure 6 As shown on the right side of the figure. The ordinate is the warping degree of the substrate 2, and the abscissa is the distance between each position on the basic diagonal line and the center of the substrate 2. The deformation curves in the figure are, from top to bottom, the warping changes of the substrates 2 of the first warping suppression group to the third warping suppression group in a 240°C environment.

[0079] Depend on Fig.10 It can be seen that the ability of the ring to suppress the warping of the substrate 2 in a high temperature environment gradually increases in the order of the first warping suppression group to the third warping suppression group. The third warping suppression group has a 15.4% improvement in the ability to suppress the warping of the substrate 2 relative to the first warping suppression group, and a 6.7% improvement in the ability to suppress the warping of the substrate 2 relative to the second warping suppression group.

[0080] Correspondingly, Fig.11 The figure shows the degree of warping of the diagonal line of the substrate 2 in the three groups of experimental objects in a normal temperature environment (125°C to 30°C). In this environment, both sides of the substrate 2 are warped downward to form a crying face warping form, such as Figure 6 As shown on the left side of the figure. The ordinate is the warping degree of the substrate 2, and the abscissa is the distance between each position on the basic diagonal line and the center of the substrate 2. The deformation curves in the figure are, from bottom to top, the warping changes of the substrates 2 of the first warping suppression group to the third warping suppression group in a 30°C environment.

[0081] Depend on Fig.11 It can be seen that the ability of the ring to suppress the warping of the substrate 2 in a normal temperature environment gradually increases from the first group to the third group. The third group has a 16.2% improvement in suppressing the warping of the substrate 2 relative to the first group, and a 4.6% improvement in suppressing the warping of the substrate 2 relative to the second group.

[0082] Furthermore, in order to improve the protection degree of the capacitor, the cross section of the first accommodating groove 10 can also be set to be in the shape of an arched door. The cross section in the present invention refers to the cross section in the circumferential direction of the warpage suppression ring 1.

[0083] Furthermore, the setting position of each first accommodating groove 10 corresponds to the installation position of the first target capacitor 21, the volume of the first accommodating groove 10 is larger than the volume of the first target capacitor 21, and the first target capacitor 21 is a capacitor whose installation area on the substrate 2 overlaps with the connection area between the warping suppression ring 1 and the substrate 2.

[0084] In this embodiment, the location of the first accommodating groove 10 is mainly determined by the location of the first accommodating groove 10 on the substrate 2. Thus, the influence of the warpage suppression ring 1 on the capacitor location can be reduced to improve the flexibility of capacitor design.

[0085] As another embodiment of the present invention, Figure 1 As shown, the thickness of the flexible heat dissipation layer 7 is positively correlated with the clamping thickness, so that after the packaging is completed, the pressure of the flexible heat dissipation layer 7 on the chip core 3 is within the range of 40psi to 90psi.

[0086] The clamping thickness is the distance between the first heat dissipation end surface and the upper surface of the thermal interface material 5 on the chip core 3 after the package is completed.

[0087] Furthermore, the thickness of the flexible heat dissipation layer 7 is 200 um to 300 um.

[0088] Specifically, after the packaging is completed, the flexible heat dissipation layer 7 is sandwiched between the first heat dissipation end surface and the thermal interface material 5. At the same time, due to the reaction force of the flexible heat dissipation layer 7, the upper surface of each chip core 3 will be subjected to a certain pressure. However, when the pressure value is greater than the pressure limit of the chip core 3, the chip core 3 (silicon wafer) will be crushed. Therefore, it is necessary to control the pressure range of the flexible heat dissipation layer 7 on the chip core 3. Usually, the pressure of the flexible heat dissipation layer 7 on the chip core 3 is in the range of 40psi to 90psi, which can ensure that the chip core 3 (silicon wafer) will not be crushed.

[0089] In this embodiment, the thickness of the flexible heat dissipation layer 7 is controlled to control the pressure of the flexible heat dissipation layer 7 on the chip core 3 to be within a normal range. However, since there will be certain processing errors in the heat dissipation cover, the chip core 3 and the warpage suppression ring 1 in actual processing, and the chip core 3 and the substrate 2 will also produce certain deformations in actual use, the thickness of the space between the first heat dissipation end surface and the thermal interface material 5 is in a changing state. Therefore, the range of variation of the thickness of the space between the first heat dissipation end surface and the thermal interface material 5 can be determined according to the actual use scenario, and then the thickness value of the flexible heat dissipation layer 7 that meets the use requirements can be calculated in combination with the magnitude of the reaction force generated by the specific material of the flexible heat dissipation layer 7 after deformation. In this embodiment, the 200um to 300um provided is calculated based on the existing commonly used packaging structure in combination with the above method. This thickness value can be applied to most packaging use scenarios, and at the same time, a larger thickness value can be selected as much as possible if allowed, such as 240um and 250um.

[0090] After the heat dissipation cover packaging in this embodiment is completed, a cavity 9 will be formed in the outer area of ​​the edge of the chip core 3, and the cavity 9 can be used as a storage space for the extended overflow part of the flexible heat dissipation layer 7 after being compressed. Therefore, even if a larger thickness is selected, it can easily overflow in the later extrusion, and then the pressure can be adjusted adaptively. Therefore, after the packaging is completed, it is convenient to install an external heat dissipation device with higher specifications and higher weight. At the same time, a larger thickness can also have a higher buffering performance, which can further reduce the risk of damage to the chip when it is impacted by external forces (such as falling).

[0091] As another embodiment of the present invention, Figure 1 A chip is also provided, the chip comprising: a substrate 2, a thermal interface material 5 and a heat dissipation cover.

[0092] The substrate 2 is used to mount and fix at least one chip core 3 .

[0093] The thermal interface material 5 is fixedly disposed on the upper surface of each chip core 3. And

[0094] The above-mentioned chip package heat dissipation cover, the cover plate 4 is fixedly arranged on the substrate 2, the flexible heat dissipation layer 7 is sandwiched between the first heat dissipation end surface and the thermal interface material 5, and there is a gap between the inner wall of the connection between the cover plate 4 and the substrate 2 and the outer wall of the chip core 3 located at the edge to form an extension space for the flexible heat dissipation layer 7, and the gap can also be used to install some capacitor components.

[0095] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A chip packaging heat dissipation cover, characterized in that: include: A cover plate, used for being fixedly arranged just above the chip core, the cover plate having a first heat dissipation end surface arranged close to the chip core; as well as A flexible heat dissipation layer is fixedly arranged on the first heat dissipation end surface, the thickness of the flexible heat dissipation layer is greater than the distance between the first heat dissipation end surface and the upper surface of the chip core, and the material of the flexible heat dissipation layer is a flexible metal with adaptive deformation ability under the action of external force.

2. The chip package heat dissipation cover according to claim 1, characterized in that: Also includes: A warping suppression ring having a first connecting end surface and a second connecting end surface that are arranged opposite to each other; The first connection end surface is fixedly connected to the first heat dissipation end surface of the cover plate, and the connection between the first connection end surface and the first heat dissipation end surface is located close to the outer edge of the first heat dissipation end surface; The second connection end surface is used for fixed connection with the substrate, and the distance between the first connection end surface and the second connection end surface is greater than the thickness of the flexible heat dissipation layer.

3. The chip package heat dissipation cover according to claim 1, characterized in that: The thickness of the flexible heat dissipation layer is positively correlated with the clamping thickness, so that after packaging, the pressure of the flexible heat dissipation layer on the chip core is within the range of 40psi to 90psi; The clamping thickness is the distance between the first heat dissipation end surface and the upper surface of the thermal interface material on the chip core after packaging is completed.

4. The chip package heat dissipation cover according to claim 3, characterized in that: The thickness of the flexible heat dissipation layer is 200um-300um.

5. The chip package heat dissipation cover according to claim 1, characterized in that: The cover plate is a copper heat dissipation cover plate.

6. The chip package heat dissipation cover according to claim 1, characterized in that: The cover plate is a vacuum chamber heat spreader, and the end surface of the vacuum chamber heat spreader on one side of the evaporation end is a first heat dissipation end surface.

7. The chip package heat dissipation cover according to claim 1, characterized in that: The flexible heat dissipation layer is fixedly connected to the first heat dissipation end surface by electroplating, chemical plating or welding; the flexible metal includes nickel, copper, gold and silver.

8. The chip package heat dissipation cover according to claim 1, characterized in that: The area of ​​the first heat dissipation end surface is larger than the upper surface area of ​​the chip core.

9. The chip package heat dissipation cover according to claim 8, characterized in that: The bottom surface area of ​​the flexible heat dissipation layer is greater than or equal to the top surface area of ​​the chip core.

10. A chip packaging structure, characterized in that: include: A substrate, used to fix and place at least one chip core; Thermal interface material, fixedly disposed on the upper surface of each chip core; as well as According to any one of claims 1 to 9, the chip package heat dissipation cover, the cover plate is fixedly arranged on the substrate, the flexible heat dissipation layer is sandwiched between the first heat dissipation end surface and the thermal interface material, and there is a gap between the inner wall of the connection between the cover plate and the substrate and the outer wall of the chip core located at the edge to form an extension space for the flexible heat dissipation layer.

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