Semiconductor package and method of manufacturing the same

Abstract

The semiconductor package includes: a first semiconductor chip including a first pad; a second semiconductor chip including a second pad disposed on a front surface facing the first semiconductor chip and in contact with the first pad, and a through electrode electrically connected to the second pad and extending to a rear surface opposite to the front surface; a dielectric layer covering at least a portion of the respective first and second semiconductor chips and having an inner surface facing the first and second semiconductor chips and an outer surface opposite the inner surface; and a bump structure on a portion of the outer surface of the dielectric layer and electrically connected to the through electrode. The dielectric layer includes inorganic particles and polymer chains bonded to at least one side of the respective inorganic particles and connected via the inorganic particles toward the inner surface and the outer surface.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0137966 filed on October 16, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor package and a method of manufacturing the same. Background Art

[0004] Some semiconductor devices installed in electronic devices require high performance and high capacity as well as miniaturization. To this end, a semiconductor package is being developed that interconnects semiconductor chips stacked in a vertical direction using through-electrodes (e.g., through silicon vias). Summary of the invention

[0005] In general, in some aspects, the present disclosure relates to semiconductor packages with simplified processes and improved reliability, and methods of manufacturing the same.

[0006] In general, according to some aspects of the present disclosure, a semiconductor package includes: a first semiconductor chip including a first pad; a second semiconductor chip including a second pad disposed on a front surface facing the first semiconductor chip and in contact with the first pad, and a through electrode electrically connected to the second pad and extending to a rear surface opposite to the front surface; a dielectric layer (dielectric layer) covering at least a portion of the respective first and second semiconductor chips and having an inner surface facing the first and second semiconductor chips and an outer surface opposite to the inner surface; and a bump structure on a portion of the outer surface of the dielectric layer and electrically connected to the through electrode. The dielectric layer includes inorganic particles, and polymer chains bonded to at least one side of the respective inorganic particles and connected toward the inner surface and the outer surface via the inorganic particles (polymer chains connected to the inner surface and the outer surface via the inorganic particles).

[0007] According to some aspects of the present disclosure, a semiconductor package includes: a first semiconductor chip including a first pad; a second semiconductor chip, the second semiconductor chip being below the first semiconductor chip and including a second pad in contact with the first pad and a through electrode electrically connected to the second pad; a dielectric layer covering at least part of the respective first and second semiconductor chips; and a ridge structure below the second semiconductor chip and electrically connected to the through electrode. The dielectric layer is a nanocomposite of inorganic particles and polymer chains combined (combined, bonded) with each other.

[0008] According to some aspects of the present disclosure, a semiconductor package includes: a first semiconductor chip including a first pad; a second semiconductor chip, the second semiconductor chip being below the first semiconductor chip and including a second pad in contact with the first pad and a through electrode electrically connected to the second pad; a dielectric layer, the dielectric layer being below the first semiconductor chip and surrounding a side surface of the second semiconductor chip and a portion of the through electrode protruding from a rear surface of the second semiconductor chip; and a ridge structure being below the second semiconductor chip and electrically connected to the through electrode. The dielectric layer includes polymer chains interconnected by inorganic particles.

[0009] According to some aspects of the present disclosure, a method for manufacturing a semiconductor package includes: preparing a semiconductor wafer including a first solder pad; attaching a preliminary semiconductor chip including a second solder pad arranged on a front surface and a plurality of preliminary through electrodes buried in a preliminary substrate to the semiconductor wafer; etching the preliminary substrate to expose at least a portion of each of the plurality of preliminary through electrodes to a rear surface of the preliminary semiconductor chip; forming a first preliminary dielectric layer covering at least a portion of each of the plurality of preliminary through electrodes exposed from the rear surface of the preliminary semiconductor chip and the preliminary substrate, the preliminary dielectric layer being formed by a spin coating process; polishing the preliminary dielectric layer and the plurality of preliminary through electrodes to form a planar surface formed by the dielectric layer and the plurality of through electrodes; and forming a raised structure on the planar surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be more clearly understood from the following detailed description considered in conjunction with the accompanying drawings.

[0011] Figure 1A is a cross-sectional view of an example of a semiconductor package according to some implementations, and Figure 1B For some implementations along Figure 1A The plane view taken by line I-I'.

[0012] Figures 2A to 2B is a diagram of an example of a dielectric layer according to some implementations, and Figure 2C is a graph of examples of thermal conductivity properties of nanocomposites according to some implementations.

[0013] Figures 3A to 3C is a graph illustrating an example of self-healing properties of a dielectric layer according to some implementations.

[0014] Figures 4A to 4E For manufacturing according to some implementations Figure 1A 0014 is a cross-sectional view of an example of a method of manufacturing a semiconductor package as shown in FIG.

[0015] Figure 5 is a cross-sectional view of an example of a semiconductor package according to some implementations.

[0016] Figure 6 is a cross-sectional view of an example of a semiconductor package according to some implementations.

[0017] Figure 7 is a cross-sectional view of an example of a semiconductor package according to some implementations.

[0018] Figure 8 is a cross-sectional view of an example of a semiconductor package according to some implementations. DETAILED DESCRIPTION

[0019] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. Unless otherwise specified, in the present disclosure, terms such as "upper", "upper surface", "lower", "lower surface", "side", etc. are based on the drawings and may actually vary depending on the direction in which the components are set.

[0020] In addition, ordinal numbers such as "first", "second", "third", etc. can be used as labels for specific elements, step parts, directions, etc. to distinguish each element, step part, direction, etc. from each other. Terms that are not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. In addition, terms referred to by specific ordinal numbers (e.g., "first" in a specific claim) may be described elsewhere with different ordinal numbers (e.g., "second" in the specification or in another claim).

[0021] Figure 1A is a cross-sectional view of a semiconductor package according to some implementations, and Figure 1B For some implementations along Figure 1A The plane view taken by line I-I'.

[0022] exist Figure 1A and 1BIn the embodiment, the semiconductor package 10A may include a first semiconductor chip 100 , a second semiconductor chip 200 , and a dielectric layer 320 . In some implementations, the semiconductor package 10A may further include a ridge structure 412 .

[0023] In some implementations, the active surface of the first semiconductor chip 100 and the active surface of the second semiconductor chip 200 may be combined with each other to significantly reduce the signal transmission path between the first semiconductor chip 100 and the second semiconductor chip 200. The first semiconductor chip 100 and the second semiconductor chip 200 may be logic chips including a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, etc., or memory chips including volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM and flash memory), etc. For example, the first semiconductor chip 100 may include a logic circuit such as an application specific semiconductor (ASIC), and the second semiconductor chip 200 may include a cache storage circuit that provides cache information to the first semiconductor chip 100. The size of the second semiconductor chip 200 may be smaller than the size of the first semiconductor chip 100. For example, the width of the first semiconductor chip 100 may be greater than the width of the second semiconductor chip 200.

[0024] In addition, the first semiconductor chip 100 and the second semiconductor chip 200 may be directly bonded and combined without a separate connection member (e.g., solder bump, copper pillar, etc.). This structure may be referred to as direct bonding, hybrid bonding, etc. formed by metal bonding of pads bonded to each other and dielectric bonding of insulating layers bonded to each other.

[0025] In addition, the dielectric layer 320 may be a nanocomposite containing inorganic particles and polymer chains. The nanocomposite refers to a composite in which nano-sized particles are dispersed in a polymer matrix. According to some implementations, since the dielectric layer 320 is formed using a polymer solution to which inorganic particles are added to form a nanocomposite, the difficulty of the process can be reduced and the turn around time (TAT) can be reduced (see Figure 4C ). The dielectric layer 320 includes inorganic particles connecting polymer chains, and thus the dielectric layer 320 may have improved thermal conductivity properties compared to spin-coated polymer resins. In addition, the dielectric layer 320 formed of the nanocomposite has a self-healing property against cracks, and thus the reliability of the semiconductor package 10A may be improved.

[0026] Hereinafter, respective components of the semiconductor package 10A according to some example embodiments will be described in detail.

[0027] The first semiconductor chip 100 may include a first substrate 110, a first circuit layer 120, a first insulating layer 131 and a first pad 132 (or a "first bonding layer 130"). The first semiconductor chip 100 may have a flat lower surface provided by the first insulating layer 131 and the first pad 132. The first substrate 110 may be a semiconductor wafer including elemental (simple substance) semiconductors such as silicon and germanium, or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) and indium phosphide (InP). The first substrate 110 may have an active surface (e.g., a surface facing the first circuit layer 120) having an active region doped with impurities and a non-active (passive) surface opposite thereto.

[0028] The first circuit layer 120 may be on the active surface of the first substrate 110. The first circuit layer 120 may include an integrated circuit consisting of various devices (individual devices) formed on the active surface of the first substrate 110 and an interconnection structure electrically connecting the various devices to the first pad 132. The various devices may include FETs such as planar FETs or FinFETs, memory devices such as flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, FeRAM, and RRAM, logic elements such as AND, OR, NOT, etc., and various active and / or passive elements such as system LSI, CIS, and MEMS. The interconnection structure may be formed as a multilayer structure including interconnection patterns and through holes formed of, for example, aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or a combination thereof.

[0029] The first insulating layer 131 may be disposed under the first circuit layer 120 and may be formed to surround the first pad 132. The first insulating layer 131 may include a material that may be bonded to the second insulating layer 231 of the second semiconductor chip 200, for example, at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon carbon nitride (SiCN). For example, at least a portion of the first insulating layer 131 may be bonded to the second insulating layer 231 to form a bonding surface between the first semiconductor chip 100 and the second semiconductor chip 200.

[0030] The first pad 132 may be a connection terminal of an integrated circuit electrically connected to the first circuit layer 120. The first pad 132 may be connected to the second pad 232 of the second semiconductor chip 200. The first pad 132 may include any one of copper (Cu), nickel (Ni), titanium (Ti), aluminum (Al), gold (Au) and silver (Ag), or an alloy thereof. The first pad 132 may be formed together with the first insulating layer 131 on a bonding surface between the first semiconductor chip 100 and the second semiconductor chip 200. A barrier layer containing at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN) may be formed between the first insulating layer 131 and the first pad 132.

[0031] The second semiconductor chip 200 may include a second substrate 210, a second circuit layer 220, a second insulating layer 231, a second pad 232 (or a "second bonding layer 230"), and a through electrode 240. The second semiconductor chip 200 may have a flat upper surface provided by the second insulating layer 231 and the second pad 232 and contacting the lower surface of the first semiconductor chip 100. In some implementations, the second semiconductor chip 200 may be provided in a smaller or larger number than the number shown in the figure. For example, the second semiconductor chip 200 may be provided as two or more semiconductor chips horizontally arranged below the first semiconductor chip 100. In addition, in some implementations, the second semiconductor chip 200 may be provided as a plurality of semiconductor chips stacked below the first semiconductor chip 100 in the vertical direction (Z-axis direction).

[0032] Since the second semiconductor chip 200 may have a structure substantially the same as or similar to that of the first semiconductor chip 100, the same or similar components are represented by the same or similar reference numerals, and repeated descriptions of the same components are omitted hereinafter. For example, the second substrate 210 and the second circuit layer 220 have the same or similar properties as the first substrate 110 and the first circuit layer 120 described above, and the corresponding components are represented by similar reference numerals, and overlapping descriptions are omitted.

[0033] The second insulating layer 231 may be formed to surround the second pad 232 by being disposed on the second circuit layer 220. The second insulating layer 231 may include a material that may be bonded to and combined with the first insulating layer 131, for example, at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon carbon nitride (SiCN).

[0034] The second pad 232 may be a connection terminal of an integrated circuit provided on the front surface S1 facing the first semiconductor chip 100 and electrically connected to the second circuit layer 220. The second pad 232 and the second insulating layer 231 may form a bonding surface between the first semiconductor chip 100 and the second semiconductor chip 200. The second pad 232 may include any one of copper (Cu), nickel (Ni), titanium (Ti), aluminum (Al), gold (Au), and silver (Ag), or an alloy thereof. For example, the second pad 232 may be bonded and combined with the first pad 132.

[0035] The through electrode 240 is electrically connected to the second pad 232 and may extend to the rear surface S2 opposite to the front surface S1. The through electrode 240 may penetrate the second substrate 210 and may protrude to the rear surface S2 of the second substrate 210. The through electrode 240 may be electrically connected to the protrusion structure 412. The through electrode 240 may include a through-hole plug and a side barrier film (not shown) surrounding the side of the through-hole plug. The through-hole plug may include, for example, tungsten (W), titanium (Ti), aluminum (Al) or copper (Cu), and may be formed by a plating (electroplating) process, a PVD process or a CVD process. The side barrier film may include titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN), and may be formed by a plating process, a PVD process or a CVD process. A side insulating film containing an insulating material (eg, high aspect ratio process (HARP) oxide) such as silicon oxide, silicon nitride, or silicon oxynitride may be formed between the through electrode 240 and the second substrate 210 .

[0036] The dielectric layer 320 may be formed to cover at least a portion of the first semiconductor chip 100 and the second semiconductor chip 200, respectively. The dielectric layer 320 may have an inner surface 320S1 facing the first semiconductor chip 100 and the second semiconductor chip 200, and an outer surface 320S2 opposite to the inner surface 320S1. In some implementations, the dielectric layer 320 may be formed to surround the side surface of the second semiconductor chip 200 and a portion of the through electrode 240 protruding from the rear surface S2 of the second semiconductor chip 200. The dielectric layer 320 may include a nanocomposite having improved thermal and self-healing properties. This will be referred to Figures 2A to 2C and 3A to 3C are described in detail.

[0037] The ridge structure 412 may be disposed under the second semiconductor chip 200 and electrically connected to the through-electrode 240. The ridge structure 412 may be disposed on a portion of the outer surface 320S2 of the dielectric layer 320, for example, on a lower surface of the dielectric layer 320.

[0038] The semiconductor package 10A may be connected to an external device, such as a module substrate, a main board, etc., through the raised structure 412. For example, the raised structure 412 may include a column portion 412P and a solder portion 412S. The column portion 412P includes copper (Cu) or an alloy of copper (Cu), and the solder portion 412S may include a low melting point metal, such as tin (Sn) or an alloy containing tin (Sn) (Sn-Ag-Cu). Depending on the example embodiment, the raised structure 412 may include only the column portion 412P or only the solder portion 412S. A protective layer 411 surrounding the raised structure 412 may be formed below the dielectric layer 320. The protective layer 411 may protect the raised structure 412 from external physical / chemical damage. The protective layer 411 may be formed using prepreg, Ajinomoto Build-up Film (ABF), FR-4, bismaleimide triazine (BT), photoimageable dielectric (PID), photo solder resist, etc. In some implementations, the protective layer 411 may be formed to cover the lower surface of the pillar portion 412P or may be omitted.

[0039] In the following, reference is made to Figures 2A to 2C and Figures 3A to 3C , describing the dielectric layer 320 of an example embodiment.

[0040] Figures 2A to 2B is a diagram of an example of a dielectric layer 320 according to some implementations, and Figure 2C is a graph of examples of thermal conductivity properties of nanocomposites according to some implementations. Figures 3A to 3C is a graph of an example of the self-healing properties of the dielectric layer 320 according to some implementations. Figures 2A to 2BIn the embodiment of the present invention, the dielectric layer 320 may be a nanocomposite in which inorganic particles 321 and polymer chains 322 are combined. For example, the nanocomposite may be manufactured by adding inorganic particles 321 to a polymer solution in which polymer chains 322 are dissolved. The polymer solution may include a polymer resin, a solvent, a reaction initiator, a dispersant for the inorganic particles 321, and the like. The polymer resin may include, for example, polyimide, benzocyclobutene, polyhydroxystyrene, polybenzoxazole, epoxy resin series, and the like. The solvent may include an organic solvent capable of dissolving the polymer resin. For example, the solvent may include propylene glycol monomethyl ether (PGME), propylene glycol methyl ether acetate (PGMEA), γ-butyrolactone (GBL), dimethyl sulfoxide (DMSO), N-methyl-2-pyrrolidone (NMP), cyclopentanone, mesitylene, and the like. The reaction initiator may include a photoinitiator, a thermal initiator, and the like. The content of the inorganic particles 321 added to the polymer solution may be adjusted depending on the physical properties of the nanocomposite. For example, the inorganic particles 321 may be added in an amount ranging from about 0.1 wt % to about 50 wt % based on the total weight of the polymer solution, but is not limited thereto. The dielectric layer 320 may be formed by curing the nanocomposite. The nanocomposite may be cured by a soft baking step at about 80° C. to about 180° C. and a hard baking step at about 180° C. to about 300° C.

[0041] The inorganic particles 321 and the polymer chains 322 may be physically and / or chemically bonded. At least one side of each of the inorganic particles 321 may have a negative polarity (δ-), and the polymer chains 322 may be physically bonded to at least one side of the inorganic particles 321. For example, the polymer chains 322 may connect the surfaces 321S of the inorganic particles 321 having a negative polarity (δ-) in a face-to-face manner. The polymer chains 322 may be arranged (aligned) via the inorganic particles 321. The polymer chains 322 may be connected toward the inner surface 320S1 and the outer surface 320S2 of the dielectric layer 320 via the inorganic particles 321. The polymer chains 322 arranged via the inorganic particles 321 may provide a heat conduction path, thereby improving the heat dissipation characteristics of the dielectric layer 320.

[0042] The inorganic particles 321 may include, for example, aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), silicon carbide (SiC), silicon nitride (Si 3 N 4), boron nitride (BN) and at least one of silicates. The silicate may include a material based on smectite (selected from, for example, montmorillonite, nontronite, beidellite, volcanoite, hectorite, saponite, laponite, sauconite, nadalite, and nadalite), a material based on vermiculite, a material based on illite, or at least one substance selected from derivatives thereof. The derivative may be understood as a compound obtained by chemically changing some of the above substances, such as a compound obtained by replacing a hydrogen atom or a specific atomic group in a compound with other atoms or groups.

[0043] The polymer chain 322 may include at least one of epoxy resin, polyimide (PI), benzocyclobutene (BCB), polyhydroxystyrene (PHS), polyhydroxyalkanoate (PHB) and polybenzoxazole, but is not limited thereto. The polymer chain 322 may include a functional group (R) physically bonded to the inorganic particle 321. For example, the functional group (R) may be connected to the inorganic particle 321 by a hydrogen bond (HB). The functional group (R) may include at least one of nitrogen (N), oxygen (O) and fluorine (F). The functional group (R) may include, for example, an amine group, a hydroxyl group, a carboxyl group, an amide group, etc.

[0044] In some implementations, the dielectric layer 320 may include inorganic particles 321 that align polymer chains 322 to have more improved thermal conductivity properties.

[0045] Figure 2C 1 shows the thermal conductivity of nanocomposites composed of polymer resin and inorganic particles. G1 shows the change of thermal conductivity depending on the content of silicon carbide (SiC) in a nanocomposite composed of polystyrene and silicon carbide (SiC). G2 shows the change of thermal conductivity depending on the content of boron nitride (BN) in a nanocomposite composed of epoxy resin and boron nitride (BN). G3 shows the change of thermal conductivity depending on the content of boron nitride (BN) in a nanocomposite composed of polyethylene and aluminum oxide (Al 2 O 3 ) depends on the composition of the nanocomposite 2 O 3 G4 represents the change of thermal conductivity of the nanocomposite composed of polystyrene and aluminum nitride (AlN) depending on the content of aluminum nitride (AlN).

[0046] exist Figure 2C The content of inorganic particles increases and the thermal conductivity of the nanocomposite increases. Figure 2CExperimental examples for all of the above-mentioned inorganic particles 321 are not shown. However, the dielectric layer 320 (or nanocomposite) may have a thermal conductivity greater than that of a material containing only the above-mentioned polymer chains 322. For example, the thermal conductivity of a material consisting of only the polymer chains 322 is about 0.2 W / mK or less, and the thermal conductivity of the dielectric layer 320 may be about 0.4 W / mK or more. For example, the thermal conductivity of the dielectric layer 320 may range from about 0.4 W / mK to about 1.3 W / mK, from about 0.4 W / mK to about 1.2 W / mK, from about 0.4 W / mK to about 1.0 W / mK, etc., but the present disclosure is not limited thereto.

[0047] exist Figure 2A In the embodiment, the dielectric layer 320 may have a self-healing property, wherein the disconnected (broken) polymer chains 322 are recombined (reorganized) with the adjacent inorganic particles 321 .

[0048] Figures 3A to 3C 321a and 321b. Figure 3A In the embodiment, at least some 322' of the polymer chains 322 constituting the dielectric layer 320 may be cut. The cut polymer chains 322' may have first and second ends T1 and T2 spaced apart from each other.

[0049] exist Figure 3B In the embodiment, the cut polymer chain 322' may diffuse toward the adjacent inorganic particles 321a and 321b. For example, the first end T1 of the cut polymer chain 322' may diffuse toward the adjacent first inorganic particle 321a. The second end T2 of the cut polymer chain 322' may diffuse toward the adjacent second inorganic particle 321b.

[0050] exist Figure 3C In the embodiment, the broken polymer chain 322' can be recombined with the adjacent inorganic particles 321a and 321b having a negative polarity (δ-) HB'. For example, the first end T1 of the broken polymer chain 322' can be recombined with the first inorganic particle 321a HB'. The second end T2 of the broken polymer chain 322' can be recombined with the second inorganic particle 321b HB'. The broken polymer chain 322' and the adjacent inorganic particles 321a and 321b can be recombined by hydrogen bonding.

[0051] Figures 4A to 4E For example manufacturing according to the process sequence according to some embodiments Figure 1A A cross-sectional view of an example of a method of manufacturing a semiconductor package 10A. Figure 4A, a semiconductor wafer 100W for the first semiconductor chip 100 may be prepared. The semiconductor wafer 100W may include a plurality of first semiconductor chips 100 separated by scribe lines SL. The semiconductor wafer 100W may have a first circuit layer 120 and a first bonding layer 130 for the first semiconductor chip 100 formed on a first substrate 110. The first bonding layer 130 may include a first insulating layer 131 and a first pad 132. The semiconductor wafer 100W may be placed on a carrier CR so that a first active surface AS1 on which the first pad 132 is provided faces upward.

[0052] Next, the preliminary semiconductor chip 200p may be attached to the semiconductor wafer 100W. The preliminary semiconductor chip 200p may include a preliminary substrate 210p before adjusting the thickness by a back-grinding process, a second circuit layer 220 and a second bonding layer 230 disposed on the front surface of the preliminary substrate 210p, and a plurality of preliminary through electrodes 240p buried in the preliminary substrate 210p. The preliminary semiconductor chip 200p may be disposed on the semiconductor wafer 100W so that the second active surface AS2 on which the second pad 232 is disposed faces downward. The preliminary semiconductor chip 200p may be arranged so that the second active surface AS2 contacts the first active surface AS1.

[0053] Thereafter, a thermal compression process may be performed to combine the first semiconductor chip 100 and the preliminary semiconductor chip 200 p. The thermal compression process may be performed in a thermal atmosphere ranging from about 100° C. to about 300° C. However, the temperature in the thermal atmosphere is not limited to the above range and may vary.

[0054] exist Figure 4B In the process, the preliminary substrate 210p may be etched so that at least a portion of each of the plurality of preliminary through electrodes 240p is exposed to the rear surface S2 of the preliminary semiconductor chip 200p. The substrate 210 having a desired thickness may be formed by applying a back grinding process and an etch-back process to the preliminary substrate 210p. For example, a back grinding process may be performed to reduce the preliminary substrate 210p to a certain thickness, and by applying an etch-back process under appropriate conditions, the plurality of preliminary through electrodes 240p may be sufficiently exposed.

[0055] exist Figure 4CIn the process, a preliminary dielectric layer 310p may be formed to cover the preliminary semiconductor chip 200p. The preliminary dielectric layer 320p may entirely cover the rear surface S2 of the preliminary semiconductor chip 200p and the plurality of corresponding preliminary through electrodes 240 exposed from the preliminary substrate 210p. The preliminary dielectric layer 320p may be formed by applying a polymer solution using a spin coating process and then curing it. When the polymer solution is cured, a nanocomposite may be formed by combining polymer chains with inorganic particles added to the polymer solution. Therefore, the preliminary dielectric layer 320p may include inorganic particles and polymer chains, the polymer chains being bonded to at least one side of each of the inorganic particles and being arranged over the entire thickness of the preliminary dielectric layer 320p via the inorganic particles (see Figure 2A and 2B ).

[0056] exist Figure 4D In the embodiment of the present invention, a polishing process is applied to the preliminary dielectric layer 320p and the plurality of preliminary through electrodes 240p, and a flat surface consisting of the dielectric layer 320 and the plurality of through electrodes 240 may be formed. The polishing process may include a chemical mechanical polishing (CMP) process. The dielectric layer 320 may have an inner surface 320S1 in contact with the semiconductor wafer 100W and the preliminary semiconductor chip 200p and an outer surface 320S2 exposed to the top. The outer surface 320S2 of the dielectric layer 320 and the upper surfaces of the plurality of corresponding through electrodes 240 may be substantially coplanar.

[0057] exist Figure 4E In the embodiment, the protective layer 411 and the protruding structure 412 may be sequentially formed on a flat surface formed by a polishing process. The protective layer 411 may be formed using, for example, a photosensitive resin such as PID or PSR (Photo Solder Resist). The protruding structure 412 may include a column portion 412P and a solder portion 412S. Then, the semiconductor packages may be separated from each other by performing a cutting process along the scribe line SL.

[0058] Figure 5 is a cross-sectional view of an example of a semiconductor package according to some implementations. Figure 5 In the embodiment, the semiconductor package 10B may have the same Figures 1A to 4E The same or similar features as those described, except further including a via structure 330 penetrating the dielectric layer 320 .

[0059] The through hole structure 330 may be disposed around the second semiconductor chip 200 and electrically connected to the first semiconductor chip 100. For example, the second pad 232 of the second semiconductor chip 200 is connected to the first inner pad 132a of the first semiconductor chip 100, and the through hole structure 330 may be connected to the first outer pad 132b of the first semiconductor chip 100. The first inner pad 132a may include a signal pad, and the first outer pad 132b may include a power pad and / or a ground pad, but the inventive concept is not limited thereto. According to some implementations, the through hole structure 330 may have a width greater than that of the through electrode 240, but is not limited thereto.

[0060] The via structure 330 may be electrically connected to at least some of the ridge structures 412 that do not vertically overlap the second semiconductor chip 200. The via structure 330 may include any one of copper (Cu), nickel (Ni), titanium (Ti), aluminum (Al), gold (Au), and silver (Ag), or an alloy thereof.

[0061] Figure 6 is a cross-sectional view of an example of a semiconductor package according to some implementations. Figure 6 In the embodiment, the semiconductor package 10C may have the same Figures 1A to 5 The same or similar features as those described, except further including a redistribution structure 510 of the redistribution through-electrodes 240. The redistribution structure 510 is disposed below the dielectric layer 320, and may include an insulating material layer 511, a redistribution pattern layer 512, and redistribution vias 513.

[0062] In some implementations, the redistribution pattern layer 512 may be directly disposed on the lower surface of the dielectric layer 320. For example, the redistribution pattern layer 512 may include an upper pattern layer directly contacting the first dielectric layer 320 and buried in the insulating material layer 511, and a lower pattern layer disposed below the insulating material layer 511. In this case, the redistribution vias 513 may extend vertically within the insulating material layer 511 to connect the lower pattern layer and the upper pattern layer. In this way, by introducing the redistribution structure 510, the layout of the ridge structure 412 can be designed in a variety of ways.

[0063] The insulating material layer 511 may be formed using a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride, or a photosensitive resin such as PID. The insulating material layer 511 may be formed of a plurality of layers depending on the number of layers of the redistribution pattern layer 512. Depending on the process, the boundaries between at least some of the plurality of insulating material layers 511 may not be clear. According to some implementations, the column portion 412P of the protrusion structure 412 may be exposed from the insulating material layer 511, and the protective layer ( Figure 1A The '411' in FIG. 4 may be formed under the redistribution structure 510 to protect the raised structure 412 .

[0064] The redistribution pattern layer 512 may electrically connect the ridge structure 412 and the through electrode 240. The redistribution pattern layer 512 may include a metal substance, including, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. The redistribution pattern layer 512 may include, for example, a ground pattern, a power pattern, and a signal pattern. The signal pattern may transmit a data signal transmitted from the first semiconductor chip 100 and the second semiconductor chip 200 to the outside, or transmit a data signal transmitted from the outside to the first semiconductor chip 100 and the second semiconductor chip 200. The redistribution pattern layer 512 may be formed by more or less layers than those (three layers) shown in the figure.

[0065] The redistribution via 513 may extend vertically within the insulating material layer 511 and be connected to the redistribution pattern layer 512. The redistribution via 513 may have a form of a filled via in which the interior of a via hole is filled with a metal material or a form of a conformal via in which a metal material is formed along the inner wall of the via hole. The redistribution via 513 may be integrated with the redistribution pattern layer 512, but the present disclosure is not limited thereto. Corresponding to the redistribution pattern layer 512, the redistribution via 513 may be formed in a larger or smaller number of layers than shown in the figure.

[0066] Figure 7 is a cross-sectional view of an example of a semiconductor package according to some implementations. Figure 7 In the embodiment, the semiconductor package 10D may have the same Figure 6 The redistribution structure 510 may include the same or similar features as those described above, except that the top redistribution pattern layer 512 is spaced apart from the dielectric layer 320. The redistribution structure 510 in this implementation may include an insulating material layer 511 disposed directly on the lower surface of the dielectric layer 320, a redistribution pattern layer 512 disposed below the insulating material layer 511, and redistribution vias 513 in the insulating material layer 511 connected to the redistribution pattern layer 512 and the through-electrode 240. In this way, by separating the dielectric layer 320 and the top redistribution pattern layer 512, adhesion of the redistribution pattern layer 512 may be ensured, and the redistribution pattern layer 512 may be implemented at a fine pitch.

[0067] Figure 8 is a cross-sectional view of an example of a semiconductor package according to some implementations. Figure 8 In the embodiment, the semiconductor package 10E may include a bonding structure BS, a wiring board 600, and a heat dissipation structure 630. The bonding structure BS may include a first semiconductor chip 100, a second semiconductor chip 200, a dielectric layer 310, etc., and may have the same structure as that of the reference 10. Figures 1A to 7Features that are the same or similar to those described herein.

[0068] The wiring board 600 is a support board on which the bonding structure BS is mounted, and may be a substrate for a semiconductor package such as a printed circuit board (PCB), a ceramic substrate, a wiring board with a tape (tape wiring board), etc. The wiring board 600 may include a lower pad 612, an upper pad 611, and a wiring circuit 613 electrically connecting the lower pad 612 and the upper pad 611. The body of the wiring board 600 may contain different materials depending on the type of the board. For example, when the wiring board 600 is a printed circuit board, the wiring board 600 may have a form in which an interconnection layer is additionally laminated on one side or both sides of the main copper-clad laminate or the copper-clad laminate. The upper pad 611, the lower pad 612, and the wiring circuit 613 may form an electrical path connecting the lower surface and the upper surface of the wiring board 600. An external connection ridge 620 connected to the lower pad 612 may be provided on the lower surface of the wiring board 600. The external connection bump 620 may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or alloys thereof.

[0069] The heat dissipation structure 630 may be provided to cover the upper portion of the bonding structure BS. The heat dissipation structure 630 may be attached to the wiring board 600 using an adhesive (not shown). The adhesive may be a thermally conductive tape, thermally conductive grease, a thermally conductive adhesive, etc. The heat dissipation structure 630 may be attached to the upper portion of the bonding structure BS through a heat transfer material layer 631. The heat transfer material layer 631 may include, for example, a thermally conductive tape, thermally conductive grease, a thermally conductive adhesive, etc.

[0070] The heat dissipation structure 630 may include a conductive (electrically conductive) material having excellent thermal conductivity. For example, the heat dissipation structure 630 may include a metal or metal alloy including gold (Au), silver (Ag), copper (Cu), iron (Fe), etc., or a conductive (electrically conductive) material such as graphite, graphene, etc. The heat dissipation structure 630 may have a shape different from that shown in the figure, and, for example, may have a shape that covers only the upper surface of the bonding structure BS.

[0071] As described above, according to some implementations, by introducing a dielectric layer including a nano-composite, a semiconductor package having a simplified process and improved reliability and a method of manufacturing the same may be provided.

[0072] Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of the protection that can be claimed. Some features described in the context of separate implementations in the present disclosure may also be implemented in combination in a single implementation. Conversely, multiple features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable sub-combination. In addition, although features may be described above as working in a certain combination, one or more features from the combination may be deleted from the combination in some cases, and the combination may lead to a sub-combination or a variation of the sub-combination.

[0073] While the subject matter of the present disclosure has been particularly shown and described with reference to various implementations, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. Semiconductor package, comprising: a first semiconductor chip including a first pad; a second semiconductor chip including a second pad disposed on a front surface facing the first semiconductor chip and contacting the first pad, and a through electrode electrically connected to the second pad and extending to a rear surface opposite to the front surface; a dielectric layer covering at least a portion of the respective first and second semiconductor chips, the dielectric layer having an inner surface facing the first and second semiconductor chips and an outer surface opposite to the inner surface; as well as a raised structure on a portion of the outer surface of the dielectric layer and electrically connected to the through electrode, wherein the dielectric layer comprises inorganic particles and polymer chains bonded to at least one side of the corresponding inorganic particles, and The polymer chains are connected toward the inner surface and the outer surface via the inorganic particles.

2. The semiconductor package according to claim 1, wherein said at least one side of said corresponding inorganic particle has a negative polarity, and The polymer chain includes a functional group physically bonded to the at least one side. 3 . The semiconductor package according to claim 2 , wherein the functional group is hydrogen bonded to the at least one side. 4 . The semiconductor package according to claim 2 , wherein the functional group includes at least one of nitrogen (N), oxygen (O), and fluorine (F).

5. The semiconductor package according to claim 1, wherein the inorganic particles include at least one of aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), boron nitride (BN), and silicate.

6. The semiconductor package according to claim 5, wherein the silicate is a smectite-based material selected from montmorillonite, nontronite, beidellite, volcanoite, hectorite, saponite, laponite, sauconite, malachite, and daptomite, a vermiculite-based material, an illite-based material, or at least one material selected from derivatives thereof. 7 . The semiconductor package of claim 1 , wherein the polymer chain comprises at least one of epoxy resin, polyimide (PI), benzocyclobutene (BCB), polyhydroxystyrene (PHS), polyhydroxyalkanoate (PHB), and polybenzoxazole. The semiconductor package according to claim 1 , wherein a thermal conductivity of the dielectric layer is 0.4 W / mK or more.

9. The semiconductor package according to claim 1, The first semiconductor chip further comprises a first insulating layer surrounding the first pad, wherein the second semiconductor chip further comprises a second insulating layer surrounding the second pad, and The second insulating layer is in contact with the first insulating layer. 10 . The semiconductor package of claim 9 , wherein the first insulating layer and the second insulating layer include at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon carbon nitride (SiCN). 11 . The semiconductor package according to claim 1 , wherein a width of the first semiconductor chip is greater than a width of the second semiconductor chip.

12. The semiconductor package according to claim 1, further comprising: a redistribution pattern layer electrically connecting the protrusion structure and the through-electrode; as well as An insulating material layer covers the redistribution pattern layer. 13 . The semiconductor package according to claim 12 , wherein the insulating material layer comprises a photosensitive resin. 14 . The semiconductor package according to claim 1 , wherein at least some of the raised structures do not overlap with the second semiconductor chip. 15 . The semiconductor package of claim 14 , further comprising a via structure penetrating the dielectric layer and electrically connecting the at least some of the bump structures and some of the first pads.

16. A semiconductor package, comprising: a first semiconductor chip including a first pad; a second semiconductor chip below the first semiconductor chip, the semiconductor chip including a second pad in contact with the first pad and a through electrode electrically connected to the second pad; a dielectric layer covering at least a portion of the respective first semiconductor chip and the second semiconductor chip; as well as a raised structure under the second semiconductor chip and electrically connected to the through-electrode, The dielectric layer is a nanocomposite of inorganic particles and polymer chains combined with each other. 17 . The semiconductor package of claim 16 , wherein the inorganic particles and the polymer chains are bonded by hydrogen bonding. 18 . The semiconductor package of claim 16 , wherein a thermal conductivity of the nanocomposite is greater than a thermal conductivity of the polymer chain. The semiconductor package according to claim 18 , wherein the thermal conductivity of the nanocomposite is 0.4 W / mK or more.

20. Semiconductor package, comprising: a first semiconductor chip including a first pad; a second semiconductor chip below the first semiconductor chip, the second semiconductor chip including a second pad in contact with the first pad and a through electrode electrically connected to the second pad; a dielectric layer under the first semiconductor chip and surrounding a side surface of the second semiconductor chip and a portion of the through-electrode protruding from a rear surface of the second semiconductor chip; as well as a raised structure under the second semiconductor chip and electrically connected to the through-electrode, The dielectric layer comprises polymer chains interconnected by inorganic particles.

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