Package substrate, semiconductor device, and method of forming package substrate

Abstract

The invention discloses a package substrate, a semiconductor device and a method of forming the package substrate. The package substrate includes a first dielectric layer, a second dielectric layer, and a core layer. The first dielectric layer includes a first electrical interconnect structure. The second dielectric layer includes a second electrical interconnect structure. The core layer is located between the first dielectric layer and the second dielectric layer and includes a plurality of semiconductor dies stacked on top of each other between the first dielectric layer and the second dielectric layer. A first semiconductor die of the plurality of semiconductor dies is a capacitive die electrically connected to the first electrical interconnect structure of the first dielectric layer. The package substrate not only can integrate a high-efficiency logic device and a plurality of peripheral devices, but also can provide sufficient mechanical strength and effective power management.

Description

Technical Field

[0001] The present application relates to a packaging substrate, and more particularly to a packaging substrate with an embedded capacitor die, a semiconductor capacitor device, and a method for forming the packaging substrate. Background Art

[0002] As technology advances, logic components (e.g., circuit components of logic integrated circuits (ICs)) continue to be miniaturized, which reduces the operating voltage of logic components, resulting in lower tolerance for voltage variations. For example, assuming that the voltage tolerance range is 10% of the rated value, the allowable range of variation for a 3.3 volt supply voltage is ±0.3 volts, while the allowable range of variation for a 0.7 volt supply voltage is only ±0.07 volts. However, transmitting voltage to logic components typically involves transmitting power through long traces on a circuit board, which can cause significant voltage fluctuations and further weaken the stability and performance of the logic components. Therefore, there is a need in the art for an improved solution to reduce the adverse effects caused by power transmission. Summary of the invention

[0003] Embodiments of the present application disclose a package substrate with an embedded capacitor die, a semiconductor capacitor device, and a method for forming the package substrate.

[0004] Certain embodiments of the present application include a packaging substrate. The packaging substrate includes a first dielectric layer, a second dielectric layer, and a core layer. The first dielectric layer includes a first electrical interconnect structure. The second dielectric layer includes a second electrical interconnect structure. The core layer is located between the first dielectric layer and the second dielectric layer, and includes a plurality of semiconductor dies stacked one above the other between the first dielectric layer and the second dielectric layer. A first semiconductor die among the plurality of semiconductor dies is a capacitor die electrically connected to the first electrical interconnect structure of the first dielectric layer.

[0005] Certain embodiments of the present application include a semiconductor device. The semiconductor device includes a packaging substrate and a semiconductor chip. The packaging substrate has a core layer. The core layer includes an embedded capacitor device. The embedded capacitor device includes a plurality of semiconductor bare chips and a plurality of adhesive layers. The plurality of semiconductor bare chips are stacked one above the other. The first semiconductor bare chip among the plurality of semiconductor bare chips is a capacitor bare chip with exposed terminal electrodes. A plurality of adhesive layers are alternately stacked with the plurality of semiconductor bare chips. Each adhesive layer is respectively combined with two semiconductor bare chips on the opposite side of the adhesive layer. The semiconductor chip is located on the first side of the packaging substrate and is electrically connected to the embedded capacitor device.

[0006] Certain embodiments of the present application include a method for forming a package substrate. The method includes: combining a first semiconductor die and a second semiconductor die to form a semiconductor capacitor stack structure, wherein at least one of the first semiconductor die and the second semiconductor die is a capacitor die; embedding the semiconductor capacitor stack structure into a core layer of the package substrate; and forming a first dielectric layer and a second dielectric layer on opposite sides of the core layer, respectively, wherein an electrical interconnection structure of the first dielectric layer is electrically connected to the capacitor die.

[0007] Through the substrate structure disclosed in the present application, the package substrate can not only integrate high-performance logic devices and multiple peripheral devices, but also provide sufficient mechanical strength and effective power management. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The various aspects of the present application can be clearly understood by reading the following embodiments in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the art, the various features in the drawings are not necessarily drawn to scale. In fact, in order to be able to describe clearly, the size of certain features can be arbitrarily enlarged or reduced.

[0009] Figure 1 is a schematic diagram of an implementation of a substrate package according to certain embodiments.

[0010] Figure 2 is a schematic diagram of an exemplary packaging substrate according to some embodiments of the present application.

[0011] Figure 3 According to some embodiments of the present application Figure 2 A schematic diagram of an embodiment of a packaging substrate is shown.

[0012] Figure 4 According to some embodiments of the present application Figure 2 A schematic diagram of another embodiment of a packaging substrate is shown.

[0013] Figure 5 According to some embodiments of the present application Figure 2 A schematic diagram of another embodiment of a packaging substrate is shown.

[0014] Figure 6 According to some embodiments of the present application Figure 2 A schematic diagram of another embodiment of a packaging substrate is shown.

[0015] Figure 7 According to some embodiments of the present application Figure 2 A schematic diagram of another embodiment of a packaging substrate is shown.

[0016] Figure 8 is a flow chart of an exemplary method of forming a package substrate according to some embodiments of the present application.

[0017] Fig. 9 According to some embodiments of the present application Figure 3 A schematic diagram of combining multiple semiconductor dies is shown.

[0018] Fig.10 According to some embodiments of the present application, Figure 3 Schematic diagram of the semiconductor capacitor stack structure shown.

[0019] Fig.11 In some embodiments of the present invention, the wafer stack is cut to form Figure 3 FIG. 1 is a schematic diagram of an embodiment of a semiconductor capacitor stack structure.

[0020] Fig.12 In some embodiments of the present invention, the wafer stack is cut to form Figure 3 FIG. 1 is a schematic diagram of another embodiment of a semiconductor capacitor stack structure.

[0021] Fig.13 According to some embodiments of the present application Figure 3 Schematic diagram of a semiconductor capacitor device embedded in a core layer.

[0022] Fig.14 According to some embodiments of the present application Figure 2 A schematic diagram of another embodiment of a packaging substrate is shown. DETAILED DESCRIPTION

[0023] The following disclosure discloses a variety of implementations or illustrations that can be used to implement different features of the present application. The specific examples of components and arrangements described below are used to simplify the present application. As can be imagined, these descriptions are only examples and are not intended to limit the present application. For example, the present application may reuse component symbols and / or labels in the embodiments. This repetition is based on the purpose of simplicity and clarity, and does not itself represent the relationship between the different embodiments and / or configurations discussed.

[0024] In addition, if one component is described as being “connected to” or “coupled to” another component, the two components may be directly connected or coupled, or other intervening components may be present between the two components.

[0025] Furthermore, for ease of description, spatially relative terms such as "below," "above," "left," "right," and the like may be used herein to describe the relationship of one component or member to another component or members as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. Moreover, the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein shall be interpreted accordingly.

[0026] In order to effectively manage power consumption and improve the overall performance of integrated circuits (ICs), heterogeneous integration has been proposed to integrate multiple chips or devices on a common substrate. Figure 1, the logic device 102 and the peripheral device 104 can be integrated on the same packaging substrate 100 to reduce the energy loss of long-distance signal transmission. The logic device 102 can be (but not limited to) a central processing unit (CPU) chip, a graphic processing unit (GPU) chip, a general-purpose computing on graphics processing unit (GPGPU) chip, an application processor (AP) chip, a control chip, or other forms of logic devices / chips. The peripheral device 104 can be (but not limited to) a memory chip, a system on a chip (SoC), a video chip, an audio chip, a radio frequency (RF) chip, a power management chip, or other forms of peripheral devices / chips. Since the logic device 102 and the peripheral device 104 are integrated on the same substrate and the distance between them is very short, the signal transmission speed can be improved and the energy loss can be reduced.

[0027] exist Figure 1 In the example shown, the package substrate 100 includes a dielectric layer 110, a dielectric layer 120 and a core layer 130. The dielectric layer 110 has a multilayered internal structure and includes an electrical interconnect structure, which can be implemented by a metal sub-layer, a metal trace and / or a via. A bump structure 114 formed below the dielectric layer 110 can be used as a contact point for interconnection. For example, the dielectric layer 110 can be electrically connected to a printed circuit board (PCB) (not shown) through a bump structure embedded 114. Similarly, the dielectric layer 120 has a multilayered internal structure and includes an electrical interconnect structure, which can be implemented by a metal sub-layer, a metal trace and / or a via. The dielectric layer 120 can be electrically connected to the logic device 102 and the peripheral device 104 through a bump structure 124.

[0028] The core layer 130 includes a plurality of conductive structures 132 and a capacitor die 136. The plurality of conductive structures 132 are used to provide conductive paths between the electrical interconnection structures of the dielectric layers 110 and 120. Each conductive structure 132 can be implemented by a plated through-hole (PTH). The capacitor die 136 is embedded in the cavity 138 of the core layer 130. In addition, the capacitor die 136 can be a die manufactured and separated from a wafer. The capacitor die 136 has a large number of capacitor structures (including electrodes and dielectric layer structures formed by semiconductor processes), thereby providing a larger capacitor surface area and a higher capacitance value. For example (but the present application is not limited thereto), the capacitor die 136 can be a trench capacitor die having a plurality of trench capacitor structures (such as a plurality of trench metal-insulator-metal capacitors (MIM capacitors)).

[0029] The capacitor die 136 is used to store electrical energy and can provide the stored electrical energy to the logic device 102, thereby maintaining the power supply stability of the logic device 102. For example, the capacitor die 136 can receive and store electrical energy through the electrical interconnection structure of the dielectric layer 110 and the bump structure 114, and can provide the stored electrical energy to the logic device 102 through the electrical interconnection structure of the dielectric layer 120 and the bump structure 124. In the case where the logic device 102 is disposed on the packaging substrate 100 having the capacitor die 136, the energy transmission path between the capacitor die 136 and the logic device 102 is obviously much shorter than the energy transmission path from the power source (not shown) on the printed circuit board to the logic device 102. Therefore, the packaging substrate 100 can effectively reduce energy loss and increase power supply integrity and system stability.

[0030] For high-end products that require powerful computing power or multiple functions (e.g., artificial intelligence (AI) products, high-performance computing (HPC) products, 5G communication applications), one logic device will be used to control multiple peripheral devices, which will increase the substrate area for heterogeneous integration. Figure 1For example, in the case where the package substrate 100 is used to integrate a logic device 102 and three peripheral devices 104, the area of ​​the package substrate 100 can be represented by SA. When the package substrate 100 is used to integrate a logic device 102 and six peripheral devices 104, the area of ​​the package substrate 100 may require 4 times the SA. As the substrate area increases, the thickness of the core layer needs to be increased accordingly to provide sufficient mechanical support. In addition, in the case where the logic device 102 is a high-end semiconductor chip (for example, a graphics processor chip or a central processing unit chip with high computing performance), the dielectric layer of the package substrate 100 may need to be thicker to accommodate more metal routing counts, which may require the thickness of the core layer 130 to be further increased to provide sufficient mechanical support. However, when the thickness of the core layer 130 increases, the capacitor die 136 may be separated from the dielectric layer, making it difficult for the capacitor die 136 to store electrical energy through the dielectric layer, or difficult to provide electrical energy to the logic device 102 through the dielectric layer.

[0031] Embodiments of the present application disclose a variety of exemplary packaging substrates, each of which includes a core layer having a plurality of semiconductor dies stacked one above the other. At least one semiconductor die is a capacitor die. The thickness of the packaging substrate is greater than the thickness of a single semiconductor die, so sufficient mechanical support can be provided. For example, the thickness of the core layer may be approximately equal to the overall thickness of the semiconductor dies stacked one above the other. In some embodiments, adjacent semiconductor dies may be combined using an adhesive layer (such as a glue, a polymer adhesive, or a photosensit ive adhesive). In some embodiments, at least one semiconductor die (such as a capacitor die) may be electrically connected to a logic device disposed on the packaging substrate through an electrical interconnect structure. In some embodiments, the packaging substrate may be disposed on a printed circuit board, and at least one semiconductor die (such as a capacitor die) may store electrical energy provided by a power supply on the printed circuit board through an electrical interconnect structure. In some embodiments, at least one semiconductor die may be a dummy die, which is electrically isolated from the conductive structure (electroconductive structure) of the packaging substrate.

[0032] The embodiments of the present application also disclose a variety of exemplary methods for forming a package substrate. The exemplary method disclosed in the present application can form a plurality of semiconductor dies (including at least one capacitor die) stacked one above the other in the core layer of the package substrate. In addition, the embodiments of the present application disclose a variety of exemplary semiconductor devices, each of which can include a package substrate and a semiconductor chip formed on the package substrate. The package substrate includes a capacitor device, which can be embedded in the core layer of the package substrate. The capacitor device includes a semiconductor die stack, and in addition, the semiconductor dies adjacent to each other in the semiconductor die stack can be combined using an adhesive layer (such as an adhesive, a polymer adhesive, or a photosensitive adhesive). In some embodiments, the semiconductor dies adjacent to each other can be electrically connected to each other through a conductive structure (e.g., a through-substrate via (TSV) structure). This conductive structure can pass through the adhesive layer between the semiconductor dies adjacent to each other. The structure and method disclosed in the present application can not only heterogeneously integrate a logic device with high computing performance and a plurality of peripheral devices on a package substrate, but also provide sufficient mechanical strength to support multiple devices / chips on the package substrate.

[0033] Figure 2 is a schematic diagram of an exemplary packaging substrate according to certain embodiments of the present application. The packaging substrate 200 includes (but is not limited to) a dielectric layer 210, a dielectric layer 220 and a core layer 230. The dielectric layer 210 includes an electrical interconnection structure 212, which can be implemented by (but is not limited to) a metal layer, a metal trace and / or a through hole. Similarly, the dielectric layer 220 includes an electrical interconnection structure 222, which can be implemented by (but is not limited to) a metal layer, a metal trace and / or a through hole. In this embodiment, both the dielectric layers 210 and 220 can have a multi-layer internal structure. For example, the dielectric layers 210 / 220 can be implemented using Ajinomoto build-up film (ABF), organic materials, or other dielectric structures that can provide electrical interconnection.

[0034] The core layer 230 is located between the dielectric layers 210 and 220 and can serve as the main support layer of the package substrate 200 to provide mechanical strength and support. For example (but the present application is not limited thereto), the core layer 230 can be filled with glass fiber and resin material to provide sufficient mechanical support. The core layer 230 may include (but is not limited to) a plurality of conductive structures 232 and a semiconductor capacitor device (for the sake of simplicity, it may also be referred to as a capacitor device) 236. Each conductive structure 232 is used to provide a conductive path between the dielectric layers 210 and 220. At least one conductive structure 232 can be implemented by (but is not limited to) a plated through hole.

[0035] The semiconductor capacitor device 236 is embedded in the core layer 230 and may have a thickness that matches the thickness of the core layer 230. In this embodiment, the semiconductor capacitor device 236 may be located in the cavity 238. The cavity 238 may be filled with a filling material to provide mechanical support and protect the semiconductor capacitor device 236. The filling material may be (but is not limited to) silicone gel, silicone resin, or other thermally conductive adhesives.

[0036] The semiconductor capacitor device 236 includes a plurality of semiconductor dies 236_1-236_n (n is an integer greater than 1), which are stacked one above the other between the dielectric layer 210 and the dielectric layer 220. At least one of the semiconductor dies 236_1-236_n is a capacitor die. In this embodiment, two adjacent semiconductor dies can be combined with each other through an adhesive layer 240, that is, a plurality of adhesive layers 240 can be alternately stacked with the plurality of semiconductor dies 236_1-236_n. Each adhesive layer 240 can be implemented by a film, an adhesive, an adhesive or a polymer adhesive. The thickness of the adhesive layer 240 can be between (but not limited to) 35 and 50 microns.

[0037] For example, semiconductor dies 236_1-236_n can be dies manufactured and separated from n wafers respectively. Each semiconductor die implemented as a capacitor die has a large number of capacitors, which can be designed according to power management requirements. At least one wafer can be prepared using semiconductor process technology to form multiple semiconductor capacitor structures with electrodes and dielectric layers. After the n wafers are stacked on each other using the adhesive layer 240, the stacked wafers can be cut to form multiple semiconductor capacitor devices. In this way, each semiconductor capacitor device can have semiconductor dies stacked on each other.

[0038] Note that each semiconductor capacitor structure may be a three-dimensional (3D) capacitor with high charge storage capacity for efficient power management in high performance computing applications. For example, since the capacitance density is proportional to the dielectric constant and the capacitor surface area, a high dielectric constant (high-k) 3D capacitor may be used to increase the charge storage capacity. In some embodiments, at least one wafer may be prepared using a dynamic random access memory (DRAM) process to form a plurality of semiconductor capacitor structures. Thus, at least one of the semiconductor dies 236_1-236_n may have a plurality of 3D capacitors formed by a DRAM process. These 3D capacitors may be (but are not limited to) cylindrical capacitors, trench capacitors, or pillar capacitors.

[0039] At least one of the semiconductor dies 236_1-236_n may be electrically connected to the electrical interconnect structure of the dielectric layer to receive electrical energy provided by a power supply (not shown) on the circuit board. Additionally or alternatively, at least one of the semiconductor dies 236_1-236_n may be electrically connected to the electrical interconnect structure of the dielectric layer to provide the stored electrical energy to a device / chip disposed on the dielectric layer. For example, in a case where the semiconductor die 236_n is implemented as a capacitor die and is electrically connected to the electrical interconnect structure 222 of the dielectric layer 220, the semiconductor die 236_n may receive and store electrical energy through the electrical interconnect structure 222, and provide the stored electrical energy to one or more chips (not shown; such as a capacitor die) located on the dielectric layer 220 through the electrical interconnect structure 222. Figure 1 Similarly, when the semiconductor die 236_1 is implemented as a capacitor die and is electrically connected to the electrical interconnect structure 212 of the dielectric layer 210, the semiconductor die 236_1 can receive and store electrical energy through the electrical interconnect structure 212, and provide the stored electrical energy to one or more chips (not shown; such as Figure 1 Logic device 102 shown).

[0040] Compared to the transmission path from the external power source (located outside the package substrate 200) to the chip on the dielectric layer 220, the transmission path from the semiconductor bare die 236_1-236_n to the chip on the dielectric layer 220 is relatively short. Therefore, using the semiconductor capacitor device 236 embedded in the core layer 230 to provide power can effectively reduce power noise and improve overall performance. In addition, by embedding the stacked semiconductor bare dies 236_1-236_n into the core layer 230, the package substrate 200 can not only have sufficient mechanical support to meet the application of a large substrate area, but also provide sufficient power storage capacity to achieve effective power management, thereby improving system performance.

[0041] To facilitate understanding of the content of this application, some embodiments are provided below to further illustrate the substrate structure disclosed in this application. Figure 2 Other implementations of the core layer architecture shown are within the scope of this application. Figure 1 The logic device 102 and a plurality of peripheral devices (eg, Figure 1 The substrate structure disclosed in the present application is described by taking the peripheral device 104 as an example of integrating multiple peripheral devices similar to the peripheral device 104 on the same substrate. Those skilled in the art should understand that the substrate structure disclosed in the present application can be used for heterogeneous integration of other devices / chips without departing from the scope of the present application.

[0042] Figure 3 3 is a schematic diagram of an exemplary semiconductor device according to some embodiments of the present application. The semiconductor device 30 includes (but is not limited to) a package substrate 300, a circuit board (such as a printed circuit board) 306, and Figure 1 The logic device 102 is shown. The package substrate 300 may be Figure 2 The embodiment of the package substrate 200 is shown. The logic device 102 and the circuit board 306 can be located on opposite sides of the package substrate 300 .

[0043] The area of ​​the package substrate 300 used to accommodate the device (for example, the cross-sectional area of ​​the package substrate 300 in the xy plane) is larger than Figure 1 The area of ​​the package substrate 100 shown is used to accommodate the device. Therefore, the number of chips / devices arranged on the package substrate 300 can be greater than Figure 1 The number of chips / devices disposed on the package substrate 100 shown. In this embodiment, the package substrate 300 is used to accommodate at least Figure 1The logic device 102 and the plurality of peripheral devices 1041 and 1042 are shown. The logic device 102 may be (but not limited to) a semiconductor chip having high computing performance, or a semiconductor chip fabricated using an advanced process technology node. For example, the logic device 102 may be a semiconductor chip including a gate-all-around (GAA) transistor structure, wherein the gate-all-around transistor structure may be fabricated using a 3nm or 2nm process. In another example, the logic device 102 may be a semiconductor chip including a fin field-effect transistor (FinFET) structure, wherein the FinFET structure may be fabricated using a 3nm process.

[0044] The peripheral devices 1041 and 1042 may be (but not limited to) memory chips, system-level chips, video chips, audio chips, radio frequency chips, power management chips, or other types of semiconductor chips. Each peripheral device may also be (but not limited to) a semiconductor chip including a full-surround gate transistor structure or a fin field effect transistor structure. In addition, the thickness of the packaging substrate 300 (the dimension of the packaging substrate 300 in the z direction) is greater than Figure 1 The thickness of the package substrate 100 is shown, so it can provide strong mechanical support. Figure 3 The number of logic devices and / or the number of peripheral devices shown are for illustrative purposes only and are not intended to limit the scope of the present application.

[0045] The package substrate 300 includes a dielectric layer 310, a dielectric layer 320 and a core layer 330, which can be Figure 2 3. The dielectric layer 210, dielectric layer 220 and core layer 230 are shown in the embodiment. The bump structure 314 located below the dielectric layer 310 can be used as a contact point for interconnection. For example, the dielectric layer 310 can be electrically connected to the circuit board 306 through the bump structure 314. The dielectric layer 320 can be electrically connected to the logic device 102 and the peripheral devices 1041 and 1042 through the bump structure 324. Figure 3 In the illustrated embodiment, the thickness of the dielectric layer 320 may be greater than Figure 1 The thickness of dielectric layer 120 shown can accommodate more metal wiring for use by logic device 102 and peripheral devices 1041 and 1042. Similarly, the thickness of dielectric layer 310 can be greater than Figure 1 The dielectric layer 110 is shown to accommodate a larger number of metal wirings.

[0046] The core layer 330 may include a plurality of conductive structures 332 and a semiconductor capacitor device 336. Each conductive structure 332 is used to provide a conductive path between the dielectric layer 310 and the dielectric layer 320. The semiconductor capacitor structure 336 may be Figure 2The embodiment of the semiconductor capacitor device 236 shown includes a plurality of semiconductor dies 336_1 and 336_2 stacked on each other between the dielectric layer 310 and the dielectric layer 320. The semiconductor dies 336_1 and 336_2 may be bonded / joined by the adhesive layer 240. The thickness of the semiconductor capacitor structure 336 is substantially equal to the thickness of the core layer 330. For example, the thickness of the semiconductor capacitor structure 336 may be greater than or equal to 1200 microns; for another example, before the semiconductor dies 336_1 / 336_2 are cut out from a wafer, the wafer may be thinned so that the thickness of the semiconductor capacitor structure 336 may be greater than or equal to 1000 microns or 800 microns.

[0047] exist Figure 3 In the illustrated embodiment, the semiconductor die 336_1 may be a capacitor die electrically connected to the electrical interconnect structure 312 of the dielectric layer 310. For example, the semiconductor die 336_1 may include a conductive layer ML1 (such as a metal layer including an upper electrode and a lower electrode), which is electrically connected to the electrical interconnect structure 312. The semiconductor die 336_1 may receive and store electrical energy through the conductive layer ML1 and the electrical interconnect structure 312. In addition, the semiconductor die 336_1 may provide the stored electrical energy to the logic device 102 through the conductive layer ML1, the electrical interconnect structure 312, the conductive structure 332, and the electrical interconnect structure 332.

[0048] In addition, the semiconductor die 336_2 may be a capacitor die electrically connected to the electrical interconnect structure 322 of the dielectric layer 320. For example, the semiconductor die 336_2 may include a conductive layer ML2 (such as a metal layer including an upper electrode and a lower electrode) electrically connected to the electrical interconnect structure 322. The semiconductor die 336_2 may receive and store electrical energy through the conductive layer ML2 and the electrical interconnect structure 322.

[0049] In some embodiments, at least one semiconductor die embedded in the core layer may be a dummy die. Figure 4 , which is according to some embodiments of the present application Figure 2 FIG. 4 is a schematic diagram of another embodiment of the package substrate 200 shown in FIG. 4. In addition to the semiconductor capacitor device 436, the structure of the package substrate 400 is similar to that of the package substrate 200. Figure 3 The structure of the package substrate 300 is substantially the same / similar. The die stack included in the semiconductor capacitor device 436 may be composed of a semiconductor die 436_1 and a Figure 3336_2 is implemented by semiconductor die 336_2 shown in FIG. Semiconductor die 436_1 is a dummy die bonded to semiconductor die 336_2 by adhesive layer 240 and electrically isolated from external components (such as semiconductor die 336_2 and electrical interconnect structures 312 / 322). In some examples, semiconductor die 436_1 may be a bare die without any functional circuit components; in some examples, except for the lack of terminal electrodes (or conductive layers that can be electrically connected to the outside (such as Figure 3 In addition to the electrode of the conductive layer ML1) shown in FIG. Figure 3 The semiconductor die 336_1 is implemented by the same or similar semiconductor process. The semiconductor capacitor device 436 can use the semiconductor die 336_2 to store electrical energy and use the semiconductor die 436_1 and the semiconductor die 336_2 to provide mechanical support. The overall thickness of the semiconductor die 436_1 and the semiconductor die 336_2 after stacking is substantially equal to the thickness of the core layer 430.

[0050] Figure 5 According to some embodiments of the present application Figure 2 FIG. 2 is a schematic diagram of another embodiment of the package substrate 200 shown in FIG. 2 . In addition to the semiconductor capacitor device 536, the structure of the package substrate 500 is similar to that of the package substrate 200. Figure 3 The structure of the package substrate 300 is substantially the same / similar. The die stack included in the semiconductor capacitor device 536 may be composed of a semiconductor die 536_2 and a Figure 3 336_1 is implemented as shown. Semiconductor die 536_2 is a dummy die bonded to semiconductor die 336_1 by adhesive layer 240 and is electrically isolated from external components (such as semiconductor die 336_1 and electrical interconnect structure 312 / 322). In some examples, semiconductor die 536_2 may be a die without any functional circuit components; in some examples, semiconductor die 536_2 may be a capacitor die without terminal electrodes. Semiconductor capacitor device 536 may utilize semiconductor die 336_1 to store electrical energy, and utilize semiconductor die 336_1 and semiconductor die 536_2 to provide mechanical support. The overall thickness of semiconductor die 336_1 and semiconductor die 536_2 after being stacked is approximately equal to the thickness of core layer 530.

[0051] In some embodiments, a plurality of semiconductor capacitor devices may be embedded in the core layer, each semiconductor capacitor device comprising a plurality of semiconductor dies stacked between opposite sides of the core layer. Figure 6 According to some embodiments of the present application Figure 2FIG. 6 is a schematic diagram of another embodiment of the package substrate 200 shown in FIG. Figure 3 The structure of the package substrate 300 shown is substantially the same / similar. The core layer 630 may be composed of Figure 3 The semiconductor capacitor device 336 is shown with Figure 4 The semiconductor capacitor device 436 shown in the figure is implemented. Through multiple embedded semiconductor capacitor devices, the package substrate 600 can not only effectively reduce power noise, but also provide sufficient power storage capacity, thereby improving system performance. Figures 1 to 5 After reading the relevant paragraphs of the description, the structure of the packaging substrate 600 should be understood, so further description is not repeated here.

[0052] Figure 7 According to some embodiments of the present application Figure 2 FIG. 2 is a schematic diagram of another embodiment of the package substrate 200 shown in FIG. 2 . Except for the core layer 730, the structure of the package substrate 700 is similar to that of the package substrate 200. Figure 6 The structure of the package substrate 600 shown is substantially the same / similar. In this embodiment, the thickness of the core layer 730 may be greater than Figure 6 For example, the core layer 730 may include semiconductor capacitors 736A-736C, each of which may be Figure 2 An embodiment of the semiconductor capacitor device 236 is shown. Each semiconductor capacitor device included in the core layer 730 may have three stacked semiconductor dies and have a thickness substantially equal to that of the core layer 730 .

[0053] The semiconductor capacitor device 736A includes semiconductor dies 736_1A-736_3A stacked one above the other. The semiconductor die 736_1A is electrically connected to the electrical interconnect structure 312 of the dielectric layer 310, and the semiconductor dies 736_2A and 736_3A are electrically connected to the electrical interconnect structure 322 of the dielectric layer 320. Figure 7In the example shown, the semiconductor die 736_3A may include a conductive layer ML3A (e.g., a metal layer including an upper electrode and a lower electrode) electrically connected to the electrical interconnect structure 322; the semiconductor die 736_2A may include a conductive layer ML2A (e.g., a metal layer including an upper electrode and a lower electrode) electrically connected to the electrical interconnect structure 322 through the conductive layer ML3A. For example, the semiconductor die 736_3A may include one or more conductive structures CS (such as substrate through vias) electrically connected to the conductive layers ML3A and ML2A. The semiconductor die 736_2A is electrically connected to the electrical interconnect structure 322 through the conductive layer ML2A, the conductive structure CS, and the conductive layer ML3A. Note that the through via on the conductive layer ML2A is located in the adhesive layer 240 between the semiconductor dies 736_3A and 736_2A.

[0054] The semiconductor capacitor device 736B includes semiconductor dies 736_1B-736_3B stacked one above the other. The structure of the semiconductor capacitor device 736B is substantially the same / similar to the structure of the semiconductor capacitor device 736A, except that the semiconductor die 736_1B is implemented as a dummy die. The semiconductor capacitor device 736C includes semiconductor dies 736_1C-736_3C stacked one above the other. The semiconductor die 736_1C is electrically connected to the electrical interconnect structure 312 of the dielectric layer 310; the semiconductor die 736_2C is implemented as a dummy die; and the semiconductor die 736_3C is electrically connected to the electrical interconnect structure 322 of the dielectric layer 320. Figure 7 In the example shown, semiconductor die 736_1C may include a conductive layer ML1C electrically connected to electrical interconnect structure 312; semiconductor die 736_3C may include a conductive layer ML3C electrically connected to electrical interconnect structure 322. Figures 1 to 6 After reading the relevant paragraphs of the description, the structure of the packaging substrate 700 should be understood, so further description is not repeated here.

[0055] Figure 8 is a flow chart of an exemplary method for forming a package substrate according to some embodiments of the present application. Figure 3 The method 800 is described with reference to the package substrate 300 shown in FIG. A person skilled in the art will appreciate that the method 800 can be applied to Figure 2 The package substrate 200 shown in FIG. Figures 4 to 7 The illustrated package substrates 400 to 700 , as well as other package substrates having embedded semiconductor dies, may be used without departing from the scope of the present application. Additionally, in some embodiments, the method 800 may include other steps / operations.

[0056] In step 810, a first semiconductor die and a second semiconductor die are combined to form a semiconductor capacitor stack structure. At least one of the first semiconductor die and the second semiconductor die is a capacitor die, such as a capacitor die with an exposed terminal electrode. For example, the semiconductor die 336_1 and 336_2 can be combined using an adhesive layer 240 to form a semiconductor capacitor stack structure (i.e., semiconductor capacitor device 336).

[0057] In step 820 , the semiconductor capacitor stack structure is embedded into the core layer of the package substrate. For example, the semiconductor capacitor device 336 is embedded into the core layer 330 .

[0058] In step 830, a first dielectric layer and a second dielectric layer are formed on opposite sides of the core layer. The electrical interconnection structure of the first dielectric layer is electrically connected to the capacitor die in the semiconductor capacitor stack structure. For example, a dielectric layer 310 and a dielectric layer 320 may be formed on opposite sides of the core layer 330. The electrical interconnection structure 312 of the dielectric layer 310 is electrically connected to the semiconductor die 336_1, and the electrical interconnection structure 322 of the dielectric layer 320 is electrically connected to the semiconductor die 336_2.

[0059] In some embodiments, the first semiconductor die and the second semiconductor die combined in step 810 can be separated from their respective corresponding wafers. Fig. 9 , which is according to some embodiments of the present application Figure 3 FIG. 3 is a schematic diagram showing the semiconductor die 336_1 and 336_2 being combined. Fig. 9 In the illustrated embodiment, a first wafer (not shown) having a plurality of semiconductor dies and a second wafer (not shown) having a plurality of semiconductor dies may be provided. The semiconductor die 336_1 is one of the plurality of semiconductor dies included in the first wafer, and the semiconductor die 336_2 is one of the plurality of semiconductor dies included in the second wafer. In addition, the first wafer including the semiconductor die 336_1 and the second wafer including the semiconductor die 336_2 may be temporarily bonded to a carrier 951 and a carrier 952, respectively.

[0060] Next, the first wafer and the second wafer may be combined to form a wafer stack, which includes semiconductor dies 336_1 and 336_2 combined together by the adhesive layer 240. For example, the adhesive layer 240 may be coated on the first wafer to combine the first wafer and the second wafer. After the first wafer and the second wafer are combined together, the carriers 951 and 952 may be removed.

[0061] In addition, after the first wafer and the second wafer are combined together, the wafer stack can be cut to form a plurality of semiconductor capacitor stack structures. Fig.10 , which is formed according to some embodiments of the present application Figure 3 The schematic diagram of the semiconductor capacitor stack structure is shown in Figure 1. Fig.10 In the illustrated embodiment, a wafer stack (including semiconductor dies 336_1 and 336_2 stacked on each other) may be placed on a dicing tape 1060 and the wafer may be cut according to the position of a scribe line (indicated by a dotted arrow) to form a semiconductor capacitor stack structure including the semiconductor dies 336_1 and 336_2.

[0062] For example, see Fig.11 , which is a method of cutting a wafer stack to form a Figure 3 A schematic diagram of an implementation of a semiconductor capacitor stack structure is shown. Fig.11 In the illustrated embodiment, wafer 1101 includes semiconductor dies 336_1, 336_1a, and 336_1b, and wafer 1102 includes semiconductor dies 336_2, 336_2a, and 336_2b. After applying adhesive layer 240 to wafer 1101, wafer 1102 may be aligned and overlapped with wafer 1101. Next, wafer dicing may be performed from one side of wafer 1102 according to the position of scribe line SL.

[0063] In some embodiments, the width of the scribe line SL may be between (but not limited to) 160-300 microns. In some embodiments, the thickness of the core layer (the overall height H after the wafer 1101 and the wafer 1102 are stacked) may be between (but not limited to) 800-1500 microns. In some embodiments, the ratio of the width of the scribe line SL to the thickness of the core layer may be between (but not limited to) 5%-30%.

[0064] Fig.12 In some embodiments of the present invention, the wafer stack is cut to form Figure 3 A schematic diagram of another embodiment of a semiconductor capacitor stack structure is shown. Fig.12In the illustrated embodiment, wafer 1101 and wafer 1102 may be pre-cut or pre-etched to form a groove (or gap) SG on the scribe line SL. After wafer 1102 is bonded to wafer 1101 via adhesive layer 240, a portion of adhesive layer 240 may be removed according to the position of groove SG to form an internal gap AG. For example, adhesive layer 240 may be photosensitive, so an exposure and development technique may be used to remove the adhesive material corresponding to the position of groove SG. Next, wafer cutting may be performed according to the position of scribe line SL. In this embodiment, cutting may be performed from both sides of the wafer stack. Since the adhesive material corresponding to the cutting position may be removed in advance, the adhesive material will not (or will hardly) stick to the cutting tool when the wafer is cut.

[0065] In some embodiments, the depth of the groove SG may be less than (but not limited to) 100 micrometers. In some embodiments, the depth of the gap AG may be less than (but not limited to) 200 micrometers. In some embodiments, the ratio of the depth of the groove SG to the thickness of the core layer may be less than (but not limited to) 30%. In some embodiments, the ratio of the depth of the gap AG to the thickness of the core layer may be less than (but not limited to) 30%. In some embodiments, the ratio of the width of the scribe line SL to the depth of the groove SG may be less than (but not limited to) 10%.

[0066] In some embodiments, the embedded semiconductor capacitor stack structure may be located in a cavity of the core layer. Fig.13 , which is according to some embodiments of the present application Figure 3 FIG. 3 is a schematic diagram showing a semiconductor capacitor device 336 embedded in the core layer 330. Fig.13 In the embodiment shown, the semiconductor capacitor device 336 can be placed in the cavity 338, and then the cavity 338 is filled with a filling material (indicated by the diagonal area) to provide mechanical support, protection and / or thermal conductivity. The filling material may include (but is not limited to) resin, epoxy resin or other organic materials.

[0067] In some embodiments, the embedded semiconductor capacitor stack structure may be surrounded by a core layer material. Fig.14 According to some embodiments of the present application Figure 2 14 is a schematic diagram of another embodiment of the package substrate 200 shown in FIG. Figure 3The structure of the package substrate 300 shown is substantially the same / similar. In this embodiment, the semiconductor capacitor device 336 can be surrounded by the filling material (such as glass fiber and resin material) of the core layer 1430. For example, after the semiconductor capacitor device 336 is cut out from the wafer stack, the semiconductor capacitor device 336 can be placed on a carrier, and the glass fiber and resin material can be formed on the carrier to cover the semiconductor capacitor device 336, thereby forming a core layer 1430 surrounding the semiconductor capacitor device 336.

[0068] Since those skilled in the art should understand that the above method of forming a package substrate can be applied to a capacitor stack structure having more than three semiconductor dies, repeated descriptions are not repeated here. Through the structure and method disclosed in this application, the package substrate can not only integrate high-performance logic devices and multiple peripheral devices, but also provide sufficient mechanical support and effective power management.

[0069] The above description briefly presents the features of certain embodiments of the present application, so that those skilled in the art can more fully understand the various aspects of the present application. Those skilled in the art will understand that they can easily use the content of the present application as a basis to design or modify other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments still belong to the spirit and scope of the present application, and they can be variously changed, replaced and modified without departing from the spirit and scope of the present application.

Claims

1. A packaging substrate, comprising: a first dielectric layer including a first electrical interconnect structure; a second dielectric layer including a second electrical interconnect structure; as well as A core layer is located between the first dielectric layer and the second dielectric layer, and the core layer includes a plurality of semiconductor dies stacked one above the other between the first dielectric layer and the second dielectric layer, wherein a first semiconductor die among the plurality of semiconductor dies is a capacitor die electrically connected to the first electrical interconnection structure of the first dielectric layer. 2 . The packaging substrate of claim 1 , wherein a second semiconductor die of the plurality of semiconductor dies is a capacitor die electrically connected to the second electrical interconnect structure of the second dielectric layer.

3. The packaging substrate of claim 1, wherein a second semiconductor die among the plurality of semiconductor dies is a dummy die, the dummy die being electrically isolated from the first electrical interconnect structure of the first dielectric layer and the second electrical interconnect structure of the second dielectric layer. 4 . The packaging substrate of claim 1 , wherein the first semiconductor die comprises a through substrate via structure, and a second semiconductor die among the plurality of semiconductor dies is a capacitor die electrically connected to the first electrical interconnect structure of the first dielectric layer through the through substrate via structure. The packaging substrate according to claim 1 , wherein a thickness of the core layer is greater than or equal to 800 μm. The packaging substrate of claim 1 , wherein the plurality of semiconductor dies are located in cavities of the core layer.

7. The packaging substrate according to claim 1, wherein the core layer further comprises: An adhesive layer is formed between two adjacent semiconductor dies to bond the two semiconductor dies. The packaging substrate of claim 7 , wherein the adhesive layer comprises a polymer adhesive. 9 . The packaging substrate according to claim 7 , wherein the adhesive layer has photosensitivity.

10. The packaging substrate according to claim 1, wherein the core layer further comprises: The conductive structure passes through the core layer and is electrically connected between the first dielectric layer and the second dielectric layer. 11 . The package substrate of claim 1 , wherein at least one of the plurality of semiconductor dies has a plurality of three-dimensional capacitors formed by a dynamic random access memory process.

12. A semiconductor device comprising: A packaging substrate having a core layer, wherein the core layer includes an embedded capacitor device, and the embedded capacitor device includes: a plurality of semiconductor dies stacked one above the other, a first semiconductor die of the plurality of semiconductor dies being a capacitor die having exposed terminal electrodes; and a plurality of adhesive layers alternately stacked with the plurality of semiconductor dies, wherein each adhesive layer is bonded to two semiconductor dies on opposite sides of the adhesive layer; and The semiconductor chip is located on the first side of the packaging substrate and is electrically connected to the embedded capacitor device. 13 . The semiconductor device of claim 12 , wherein a second semiconductor die of the plurality of semiconductor dies is a dummy die.

14. The semiconductor device according to claim 12, wherein the first semiconductor die comprises a through substrate via structure, A second semiconductor die of the plurality of semiconductor dies is a capacitor die electrically connected to the through substrate via structure. 15 . The semiconductor device according to claim 12 , wherein the adhesive layer comprises a polymer adhesive or a photosensitive adhesive. 16 . The semiconductor device according to claim 12 , wherein the semiconductor chip comprises a gate-all-around transistor structure.

17. The semiconductor device according to claim 12, further comprising: The circuit board is located on a second side of the packaging substrate, the second side is opposite to the first side, and the core layer is located between the first side and the second side.

18. A method for forming a packaging substrate, comprising: Combining a first semiconductor die and a second semiconductor die to form a semiconductor capacitor stack structure, wherein at least one of the first semiconductor die and the second semiconductor die is a capacitor die; Embedding the semiconductor capacitor stack structure into the core layer of the packaging substrate; as well as A first dielectric layer and a second dielectric layer are formed on opposite sides of the core layer, respectively, wherein the electrical interconnection structure of the first dielectric layer is electrically connected to the capacitor die.

19. The method according to claim 18, wherein the step of combining the first semiconductor die and the second semiconductor die to form the semiconductor capacitor stack structure comprises: providing a first wafer having a plurality of first semiconductor dies; providing a second wafer having a plurality of second semiconductor dies; combining the first wafer and the second wafer to form a wafer stack; as well as The wafer stack is cut to form a plurality of semiconductor capacitor stack structures, wherein the embedded semiconductor capacitor stack structure is one of the plurality of semiconductor capacitor stack structures.

20. The method according to claim 19, wherein the step of cutting the wafer stack to form the plurality of semiconductor capacitor stack structures comprises: forming a groove at each scribe line on the first wafer; removing a portion of the adhesive layer formed between the first wafer and the second wafer according to each groove position on the first wafer; as well as The wafer stack is cut according to the position of each groove on the first wafer.

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