Post-CMP treatments for hybrid bonds

Abstract

The invention relates to post-CMP processing for hybrid bonding. Devices and techniques include process steps for forming openings through stacked and bonded structures. After planarization of the bonding layer (by chemical mechanical polishing (CMP) or the like) and before bonding, an opening is formed by pre-etching through one or more layers of the prepared die. For example, the opening is etched through one or more layers of the die to be bonded prior to bonding the die to form a component.

Description

[0001] Divisional Application Instructions

[0002] This application is a divisional application of an invention patent application with an international application date of July 16, 2019, international application number PCT / US2019 / 042050, entering the Chinese national stage on January 22, 2021, Chinese national application number 201980049187.5, and invention name “Post-CMP Treatment for Hybrid Bonding”. Technical Field

[0003] The following description relates to integrated circuits ("ICs"). More specifically, the following description relates to manufacturing IC dies and wafers. Background Art

[0004] Microelectronic components typically include a thin flat plate of semiconductor material, such as silicon or gallium arsenide, commonly referred to as a semiconductor wafer. The wafer may be formed to include a plurality of integrated chips or bare dies on the surface of the wafer and / or partially embedded within the wafer. The bare dies separated from the wafer are typically provided as separate, pre-packaged units. In some package designs, the bare die is mounted to a substrate or chip carrier, which in turn is mounted on a circuit board, such as a printed circuit board (PCB). For example, many bare dies are provided in a package suitable for surface mounting.

[0005] Packaged semiconductor dies may also be provided in a "stacked" arrangement, where one package is provided, for example, on a circuit board or other carrier, and another package is mounted on top of the first package. These arrangements may allow several different dies or devices to be mounted within a single footprint on a circuit board, and may further facilitate high-speed operation by providing short interconnects between packages. Typically, the interconnect distance may be only slightly greater than the thickness of the die itself. For interconnections to be achieved within a stack of die packages, interconnect structures for mechanical and electrical connections may be provided on both sides (e.g., faces) of each die package (except the topmost package).

[0006] Additionally, as part of various microelectronic packaging schemes, dies or wafers can be stacked in a three-dimensional arrangement. This can include stacking layers of one or more dies, devices, and / or wafers on a larger base die, device, wafer, substrate, etc., thereby stacking multiple dies or wafers in a vertical or horizontal arrangement, as well as various combinations of the two.

[0007] The dies or wafers may be bonded in a stacked arrangement using a variety of bonding techniques including direct dielectric bonding, non-adhesive techniques such as ) or hybrid joining techniques (such as ), both available from Invensas Bonding Technologies, Inc (formerly Ziptronix, Inc), Xperi Corporation (see, e.g., U.S. Patent Nos. 6,864,585 and 7,485,968, the contents of which are incorporated herein in their entirety). The corresponding mating surfaces of the bonded die or wafers typically include embedded conductive interconnect structures, etc. In some examples, the bonding surfaces are arranged and aligned so that the conductive interconnect structures from the corresponding surfaces are connected during bonding. The connected interconnect structures form a continuous conductive interconnect (for signals, power, etc.) between the stacked die or wafers.

[0008] There may be a variety of challenges in achieving stacked die and wafer arrangements. When stacked die are bonded using direct bonding or hybrid bonding techniques, it is generally desirable that the surfaces of the die to be bonded be extremely flat, smooth, and clean. For example, typically, the surfaces should have very low variations (i.e., nanometer-scale variations) in surface topography so that the surfaces can be closely matched to form a durable bond.

[0009] The conductive interconnect structure at the bonding surface can be slightly recessed, just below the insulating material of the bonding surface. The amount of recess below the bonding surface can be determined by the dimensional tolerances, specifications, or physical limitations of the device or application. The hybrid surface can be prepared for bonding to another die, wafer, or other substrate using a chemical mechanical polishing (CMP) process, etc.

[0010] Additionally, in some applications, it is desirable to form wire bonding pads, test pads, and other structures on or next to the bonding surface, or within a cavity at the bonding surface, which after bonding will typically be accessed from outside the stacked and bonded device. The openings or cavities can be used to create access points for sensor applications, physical and electrical access (e.g., for wire bonding, testing, electrical connections, etc.), low impedance, low loss connections, air bridges, etc. Forming cavities to accommodate these structures, connections, access, and other purposes by stacking and bonding dies, wafers, and substrates can be problematic, especially when the desired cavity will have a small pitch and / or significant depth. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The detailed description is described with reference to the accompanying drawings. In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears. The use of the same reference numbers in different drawings indicates similar or identical items.

[0012] For discussion purposes, the devices and systems shown in the figures are shown as having multiple components. As described herein, various implementations of devices and / or systems may include fewer components and remain within the scope of the present disclosure. Alternatively, other implementations of devices and / or systems may include additional components or various combinations of the components described and remain within the scope of the present disclosure.

[0013] Figure 1 and Figure 2 An example graphical flow diagram of an example process for preparing a bonding surface according to one embodiment is shown.

[0014] Figure 3 An example assembly formed from a stacked and bonded device having hybrid bond pads, and peripheral pads according to one embodiment is shown.

[0015] Figure 4 and Figure 5 FIG. 1 is a diagram illustrating a method for forming a Figure 3 A graphical flow chart of an example process for a device in which components of a device are assembled.

[0016] FIG. 5A to FIG. 5C FIG. 1 is a diagram illustrating a method of performing a multi-step process according to an embodiment of the present invention. Figure 4 and Figure 5 An optional step of the example process described herein.

[0017] Figure 6 An example assembly formed from a stacked and bonded device having hybrid bond pads and peripheral pads inside the die perimeter is shown according to one embodiment.

[0018] Figure 7 and Figure 8 A graphical flow chart showing a method for forming a Figure 6 An example process of a device in a device of a component.

[0019] Fig. 9 and Fig.10 A graphical flow chart showing a method for forming a Figure 6 An example process of a device having a component in another device.

[0020] Fig.11 and Fig.12 A graphical flow chart showing an example process for forming an example assembly formed from a stacked and bonded device having hybrid bond pads and peripheral pads inside the perimeter of a die is illustrated according to one embodiment.

[0021] Fig.13A graphical flow chart showing an example process for forming an example assembly formed from a stacked and bonded device having hybrid bond pads and peripheral pads inside the perimeter of a die is illustrated in accordance with one embodiment.

[0022] Fig.14 and Fig.15 A graphical flow chart showing an example process for forming a cavity using a sealing ring or a contacting hybrid joining surface is illustrated according to one embodiment.

[0023] Fig.16 and Fig.17 A graphical flow chart showing an example process of street etching a wafer prior to singulation is illustrated in accordance with one embodiment.

[0024] Figures 18 to 23 An example of an assembly formed from a stacked and bonded device having hybrid bond pads and peripheral pads according to various embodiments is shown.

[0025] Figure 24 to Figure 26 An example of an assembly formed from a stacked and bonded device having an internal cavity and a sealing ring according to various embodiments is shown.

[0026] Fig. 27 An example of an assembly formed from a stacked and bonded device having a hybrid bond pad and seal ring, and at least one peripheral pad outside the perimeter of the die is shown according to one embodiment.

[0027] Fig.28 An example of an assembly formed from multiple stacked and bonded devices having hybrid bond pads and seal rings according to one embodiment is shown.

[0028] Figure 29 to Figure 32 Example stacked and bonded microelectronic assemblies are shown with etched openings through the microelectronic assembly layers according to various embodiments.

[0029] Fig.33 is a flow chart illustrating an example process for preparing a die for bonding according to one embodiment. Summary of the invention

[0030] Representative techniques and devices are disclosed, including process steps for forming holes, cavities, openings, recesses, etc. (hereinafter referred to as "openings") through stacked and bonded structures. As discussed above, of particular interest are tightly bonded structures that are formed using direct bonding and hybrid bonding techniques without adhesives. In various embodiments, the openings are formed by pre-etching through one or more layers of a prepared wafer or die after planarization of the bonding layer (by chemical mechanical polishing (CMP) or the like) and before bonding. For example, the openings are etched through one or more layers of the die to be bonded before bonding the die to form an assembly.

[0031] In various implementations, a microelectronic assembly includes: a first substrate having a bonding surface, the bonding surface having a planarized topography of an inorganic dielectric material or an insulator; and a first plurality of electrically conductive features embedded in a dielectric layer, one surface of which is exposed at the bonding surface of the first substrate; and a second substrate having a bonding surface, the bonding surface having a planarized topography of an inorganic dielectric material or an insulator and bonded to the bonding surface of the first substrate. The second substrate includes a second plurality of electrically conductive features embedded in a dielectric layer, one surface of which is exposed at the bonding surface of the second substrate, the second plurality of electrically conductive features being bonded to the first plurality of electrically conductive features. The first plurality of electrically conductive features and the second plurality of electrically conductive features are directly bonded, such as using a hybrid bonding technique, without the use of solder or other added bonding materials. The term "conductive feature" will be used herein to specifically refer to these directly bonded conductive features.

[0032] One or more electrically conductive contact pads separated from the directly bonded electrically conductive features are disposed within the insulating layer of the second substrate and below the bonding surface of the second substrate. The one or more electrically conductive contact pads may be disposed outside or inside the perimeter of the first plurality of electrically conductive features and the second plurality of electrically conductive features, or in one or more designated areas. The electrically conductive contact pads may include any conductive structure other than an electrically conductive feature, which may be used as a conductive interconnect for wire bonding, terminals, test pads, ball grids, etc.

[0033] Where a "conductive feature" of one die or wafer has a matching or mating conductive feature on a second, directly bonded die or wafer, the "contact pads" are not matched for purposes of die-to-die, wafer-to-wafer, or die-to-wafer direct bonding. For example, the contact pads of one die or wafer typically do not have a mating contact pad on a second bonded die or wafer to which to directly bond. Furthermore, the contact pads are typically on a different (e.g., "lower") layer in the die or wafer than the electrically conductive features and may be disposed or buried below the bonding surface of the die or wafer.

[0034] In one implementation, the microelectronic assembly further comprises one or more secondary openings in the insulating layer of the second substrate aligned with the one or more electrically conductive contact pads. The one or more secondary openings extend from the bonding surface of the second substrate to the one or more electrically conductive contact pads, thereby providing access to the one or more electrically conductive contact pads.

[0035] In another implementation, the microelectronic assembly further comprises one or more primary openings in the insulating layer of the first substrate, the one or more primary openings being aligned with the one or more secondary openings and with the electrically conductive contact pads. The one or more primary openings extend to the one or more secondary openings, thereby providing access to the one or more electrically conductive contact pads.

[0036] In another implementation, the microelectronic assembly further comprises one or more tertiary openings in the base layer of the first substrate, the one or more tertiary openings being aligned with the one or more primary openings in the insulating layer of the first substrate and with the electrically conductive contact pads. The one or more tertiary openings extend from the outer side surface of the first substrate to the one or more primary openings, thereby providing access to the one or more electrically conductive contact pads from outside the outer side surface of the first substrate.

[0037] In one embodiment, a microelectronic assembly includes one or more electrically conductive structures disposed within one or more of the one or more secondary openings, the one or more primary openings, and the one or more tertiary openings and electrically coupled to the one or more electrically conductive contact pads.

[0038] In another implementation, a microelectronic assembly includes: a first substrate having a bonding surface, the bonding surface having a planarized topography, the first substrate having a first plurality of electrically conductive features at the bonding surface of the first substrate; and a second substrate having a bonding surface, the bonding surface having a planarized topography, bonded to the bonding surface of the first substrate. The second plurality of electrically conductive features are disposed at the bonding surface of the second substrate and bonded to the first plurality of electrically conductive features while being misaligned with the first plurality of electrically conductive features to a first degree. One or more electrically conductive contact pads are disposed within an insulating layer of the second substrate and below the bonding surface of the second substrate. The one or more electrically conductive contact pads are disposed outside the perimeter of the first plurality of electrically conductive features and the second plurality of electrically conductive features, or in one or more designated areas. One or more secondary openings in the insulating layer of the second substrate are aligned with the one or more electrically conductive contact pads, and the one or more secondary openings extend from the bonding surface of the second substrate to the one or more electrically conductive contact pads. One or more primary openings in the insulating layer of the first substrate are misaligned with the one or more secondary openings to a first degree, and the one or more primary openings extend to the one or more secondary openings and provide access to the one or more electrically conductive contact pads.

[0039] In an additional implementation, a microelectronic assembly includes: a first substrate having a hybrid bonding surface, the hybrid bonding surface including an insulator material having one or more metal features therein, and a planarized topography; and a second substrate having a hybrid bonding surface, the hybrid bonding surface including an insulator material having one or more metal features embedded therein, having a planarized topography and bonded to the hybrid bonding surface of the first substrate. The one or more metal features of the second substrate are bonded to the one or more metal features of the first substrate. A cavity is disposed at a bonding joint between the first substrate and the second substrate, at which the hybrid bonding surface of the first substrate contacts the hybrid bonding surface of the second substrate. The cavity is formed by at least a recess in the hybrid bonding layer of the first substrate. A continuous seal is formed by the one or more metal features of the first substrate and the one or more metal features of the second substrate, and is disposed around the perimeter of the cavity at the bonding joint.

[0040] Various implementations and devices are discussed with reference to electrical and electronic components and various carriers. Although specific components (i.e., bare die, wafer, integrated circuit (IC) chip bare die, substrate, etc.) are mentioned, this is not meant to be restrictive and is for the convenience of discussion and illustration. The techniques and devices discussed with reference to wafers, bare die, substrates, etc. can be applied to any type or quantity of electronic components, circuits (e.g., integrated circuits (IC), hybrid circuits, ASICS, memory devices, processors, etc.), component groups, packaged components, structures (e.g., wafers, panels, boards, PCBs, etc.), etc., which can be coupled to each other and to interfaces of external circuits, systems, carriers, etc. Each of these different components, circuits, groups, packages, structures, etc. can be collectively referred to as "microelectronic components". For simplicity, unless otherwise specified, a component engaged with another component will be referred to as a "bare die" in this article.

[0041] This summary of the invention is not intended to give a complete description. A plurality of examples are used below to explain the implementation in more detail. Although various implementations and examples are discussed here and below, further implementations and examples are possible by combining the features and elements of the individual implementations and examples. DETAILED DESCRIPTION

[0042] Overview

[0043] Patterned layers of metal and inorganic dielectric material (such as silicon oxide) are often used as hybrid bonds or The oxide is provided on a die, wafer or other substrate (hereinafter "die") as a surface layer. The dielectric layer is typically highly planar (typically to nanometer-scale roughness), while the metal layer (e.g., embedded conductive features) is at or just recessed below the oxide surface. The amount of recess below the oxide is typically determined by dimensional tolerances, specifications, or physical limitations. The hybrid surface is typically prepared using a chemical mechanical polishing (CMP) step for bonding to another die, wafer or other substrate.

[0044] The devices and techniques disclosed herein allow further etching of oxide (or other insulating layers) after the CMP step to form openings, cavities, or recesses in or through the bonding layer. The openings or recesses allow features or structures to be formed and accessed, such as wire bonding pads, test pads, die cavities, etc. Forming such cavities may mean that additional openings need to be etched into the hybrid bonding surface layer after the CMP step but before bonding. Such cavities can be used to create access points for sensor applications (e.g., DNA analysis), physical and electrical access (e.g., for testing, wire bonding, electrical connections, etc.), low impedance, low loss connections, air bridges, etc.

[0045] The techniques described herein are useful for forming shallower cavities, recesses, or openings in separate dies or wafers prior to bonding, thereby avoiding the need to etch a deeper single cavity in both dies or wafers after bonding. The process can also result in cleaner bond pad surfaces and better pitch performance than would be possible with an oxide etch process after bonding. Additionally, the process also allows for the formation of cavities of different sizes in the top and bottom wafers or dies. For example, a trench opening can be formed in the bottom die and a point opening can be formed in the top die, or vice versa. Alternatively, the opening formed in the bottom die can be larger than the opening formed in the top die, or vice versa (see Figure 29 to Figure 32 ).

[0046] As will be appreciated, the cavity etching technique can also improve metal seal rings or electrical contacts for micro-electromechanical systems (MEMS) or other sensor applications. The techniques described herein also improve bonding by the process of etching before die singulation. This can improve cutting by reducing debris and can improve the reliability of transistors in the art.

[0047] Figures 1 to 33 Representative devices and processes for forming and preparing various microelectronic components (e.g., such as die 102) for bonding, such as for direct bonding without adhesive, are illustrated. The process includes: providing a bonding surface (e.g., such as bonding surface 108) on the microelectronic component, or in some examples, providing two bonding surfaces (not shown); providing conductive interconnect features or structures embedded in the bonding surface; repairing or mitigating corrosion, recesses, etc. in the bonding surface caused by processing or defects; pre-etching one or more openings in the bonding surface; forming a microelectronic assembly by directly bonding microelectronic components at the bonding surface, etc.

[0048] The order in which the process is described is not intended to be construed as limiting, and any number of process blocks described in the process may be combined in any order to implement the process or an alternative process. Additionally, individual blocks may be deleted from any process without departing from the spirit and scope of the subject matter described herein. Furthermore, the process may be implemented in any suitable hardware, software, firmware, or combination thereof without departing from the scope of the subject matter described herein. In alternative implementations, other technologies may be included in the process in various combinations and still be within the scope of the present disclosure.

[0049] refer to Figure 1 and Figure 2, and correspondingly processes 100 and 200, a representative "bare die" 102 may be formed using various techniques to include a base substrate 104 and an insulating or dielectric layer 106. The base substrate 104 may include silicon, germanium, glass, quartz, a dielectric surface, a direct or indirect interstitial semiconductor material or layer, or another suitable material, and a plurality of metal wiring layers in the insulating dielectric, which are generally referred to as "back end of line" (BEOL) layers. The insulating layer 106 is deposited or formed over the substrate 104, and may include a layer of an inorganic dielectric material, such as an oxide, nitride, oxynitride, oxycarbide, carbide, carbonitride, diamond, diamond-like material, glass, ceramic, glass ceramic, etc. For example, the insulating layer 106 may be the last layer of the BEOL, or an additional layer deposited specifically for hybrid bonding.

[0050] The bonding surfaces 108 of the dies 102 may include conductive features 110, such as interconnect structures, embedded in the insulating layer 106 and arranged so that the conductive features 110 from the corresponding bonding surfaces 108 of the opposing dies 102 may mate or couple during bonding, as desired. The coupled conductive features 110 may form a continuous conductive interconnect (for signal, power, etc.) between the stacked dies 102.

[0051] A damascene process (or similar process) may be used to form embedded conductive features 110 in insulating layer 106. Conductive features 110 may include metal (e.g., copper, etc.) or other conductive materials or combinations of materials, and include structures, traces, pads, patterns, etc. Conductive features 110 may be included in insulating layer 106 to provide electrical and / or thermal paths, or may alternatively be configured to balance the metallization of bonding surface 108 by using additional pads or so-called dummy pads, traces, patterns, etc. After conductive features 110 are formed, the exposed surface of die 102, including insulating layer 106 and electrically conductive features 110, may be planarized (e.g., via CMP) to form a flat bonding surface 108.

[0052] like Figure 1 and Figure 2As shown, at block A of processes 100 and 200, one or more bonding surfaces 108 in the die 102, including the embedded interconnect structure 110, may be planarized (using chemical mechanical polishing (CMP), etc.) to prepare the surface(s) 108 for bonding. Forming the bonding surface 108 includes finishing the surface 108 to meet the dielectric roughness specification and the metal layer (e.g., copper, etc.) recess specification, thereby preparing the surface 108 for direct bonding. In other words, the bonding surface 108 is formed to be as flat and smooth as possible, with very small surface topography variations. Various conventional processes such as chemical mechanical polishing (CMP) can be used to achieve low surface roughness. The process provides a flat, smooth surface 108, resulting in reliable bonding between the die 102.

[0053] In some cases, such as Figure 1 As shown in block A of process 100, the exposed surface of electrically conductive feature 110 may be intentionally recessed, for example, by a depth "d1" relative to bonding surface 108 to allow for material expansion, particularly during heat annealing (if performed). In other cases, such as Figure 2 As shown in block A of process 200, the exposed surface of the conductive feature 110 can be formed to exceed the recess specification and can protrude to a height "d2" above the bonding surface 108 to allow oxidation of the conductive feature 110 during later processing. For example, this can be achieved by selectively etching the dielectric layer 106.

[0054] During polishing or other process steps (such as forming openings in the bonding layer 108 after a polishing step), the conductive features 110 at the bonding layer 108 may change (e.g., become oxidized) and become outside of the desired specification. Figure 1 and Figure 2 1 and 200 are illustrated in block B of processes 100 and 200 , where oxidation is shown at 112 .

[0055] The conductive feature 110 can be Figure 1 and Figure 2 The conductive features 110 are adjusted at block C of processes 100 and 200 to improve subsequent bonding and electrical connection. The adjustment may be achieved by selectively wet etching the conductive features 110 (e.g., using a chemical etch that selectively dissolves metal oxides (e.g., copper oxide) formed on the conductive features 110) or by a touch-up CMP process, etc. After the adjustment, the recess of the conductive features 110 relative to the bonding surface 108 is within the specified tolerances (e.g., "d3" and "d4").

[0056] Example Embodiments

[0057] refer to Figure 3 , a microelectronic assembly 300 is shown, which includes at least two directly bonded (e.g., without adhesive) dies 102 and 302. Alternatively, the microelectronic component 302 can include a wafer or other substrate, etc. However, the microelectronic component 302 includes one or more contact pads 306 disposed outside the perimeter of the die 102.

[0058] Embedded electrically conductive features 110 (e.g., hybrid bond pads, etc.) of both dies 102 and 302 extend to the bonding surfaces 108 of dies 102 and 302 and are bonded together to form a bonded interconnect structure 304. In one embodiment, first die 102 may be formed at process 100 or 200 as described above.

[0059] Due to the openings 308 in the insulating layer 106 of the die 302, the contact pads 306 (i.e., the exposed non-hybrid electrically conductive pads) of the die 302 are exposed through the bonding surface 108 of the die 302. As discussed above, the pads 306 may be used for testing, wire bonding, other electrical connections, etc. with respect to the die 302. In some embodiments, for example, a conductive coating 310 including nickel, gold, or other metal may be disposed over the contact pads 306 to protect the pads 306 from oxidation, corrosion, etc.

[0060] In one implementation, the second die 302 can be formed as described in the process 400, including forming the opening 308 before bonding the second die 302 to the first die 102. Alternatively, in some embodiments having the structure 300, the opening 308 can be formed in the second die 302 after the second die 302 is bonded to the first die 102.

[0061] refer to Figure 4 Process 400 (see also for textual flowchart Fig.33 , to supplement Figure 4 and Figure 5 ) At block A, a die 302 is formed and prepared for direct bonding, including: forming an insulating layer 106 on a base substrate 104, forming one or more conductive features 110 in the insulating layer 106, and forming a highly planar bonding layer 108 as described above. In one implementation, the process 400 includes forming a buried contact pad 306 within the insulating layer 106.

[0062] At block B, process 400 includes forming a patterned resist layer 402 over bonding surface 108, wherein patterned gaps in resist layer 402 are aligned over buried contact pads 306. Optionally, patterned resist layer 402 may include gaps over scribe lines, if desired. At block C, process 400 includes etching insulating layer 106 through the gaps in resist layer 402, thereby forming openings 308 to expose buried contact pads 306.

[0063] refer to Figure 5 At block D, if it is desired to protect the pads 306, the process 400 includes optionally covering the uncovered contact pads 306 with a protective metal layer 310 (e.g., nickel, gold, silver, solder, etc.). The protective layer 310 may be applied, for example, using electroless plating, or if desired using another technique such as immersion plating.

[0064] At block E, process 400 includes removing resist 402 from bonding surface 108. For example, resist 402 may be removed by using a wet stripping process followed by oxygen plasma ashing. In some cases, the removal step of resist 402 may cause the surface of electrically conductive feature 110 to oxidize (e.g., forming copper oxide 404). Figure 5 As shown, depending on the amount of oxide 404 , the surface of the electrically conductive feature 110 may protrude above the bonding surface 108 .

[0065] At block F, process 400 includes removing oxide 404 from conductive features 110. For example, oxide 404 may be 1 to 100 nm thick. Alternatively, in some cases, the oxide may be thicker. In any case, it may be important to control the rate at which material is removed, including the rate at which oxide 404 is removed, and the rate at which some of the metal of conductive structure 110 (e.g., copper, etc.) is removed to meet recess specifications. For example, removing the correct amount of material may avoid having to re-manufacture die 302, including reforming insulating layer 106 and / or conductive structure 110. Unfortunately, it may be easy to over-etch material using many of the commonly used techniques.

[0066] In various embodiments, a controlled, selective etching technique is used to remove oxide 404, which may include etching oxide 404 using a dilute recipe such as a 1:20 ratio of sulfuric or sulfonic acid to water. Alternatively, a light CMP using a slurry formulated for polishing a barrier layer such as a barrier layer deposited into a cavity of insulating layer 106 prior to copper deposition during a damascene process may be used to selectively remove oxide 404. However, the removal of nanoscale material may be more easily controlled using chemical etching. Designated recesses for conductive features 110 may be achieved as part of the oxide 404 removal step using controlled material removal.

[0067] refer to FIG. 5A to FIG. 5C As an alternative step to process 400, or in addition to the process steps in blocks D through F, one or more optional layers may be deposited over the exposed contact pads 306 (and protective metal layer 310), which may include depositing (multiple) layers over the bonding surface 108 of the die 302. For example, in some cases, electrochemical enhancement of etching may be experienced on some electrically conductive features 110 due to bimetallic and photovoltaic effects on the conductive features 110 coupled to circuits, or exposed bonding pads. These effects may result in corrosion of the contact pads 306.

[0068] In these cases, (ref. Figure 5A , at block G), a layer 502 of approximately 10 to 200 nm of oxide and / or barrier metal may be deposited over the bonding surface 108 and the contact pads 306 (including the protective metal layer 310). As shown at block H, CMP (or a similar method) may be used to re-expose the electrically conductive features 110 on the bonding surface 108. The layer 502 remains on the contact pads 306. At block I, the first die or wafer 102 is directly bonded to the second die 302 without the need for an adhesive.

[0069] refer to Figure 5B At block J, after the second die 302 is bonded to the first die or wafer 102, the top base layer 104 of the first die or wafer 102 may be thinned. At block K, a patterned resist layer 402 is applied to the top surface of the die 102 with gaps in the resist at locations where the base layer 104 is desired to be removed (e.g., above the opening 602, as desired, and other locations). At block L, openings are etched in the base layer 104 of the wafer or die 102 to access the contact pads 306. The openings in the base layer 104 of the die 102 may be formed to be the same size as the openings in the insulating layer 106 of one or both of the die 102 and the die 302, or the openings in the base layer 104 of the die 102 may be larger or smaller than the mating openings in the die 102 and / or the die 302.

[0070] refer to Figure 5C At block M, using the opening created in the base layer 104 of the wafer or die 102, the thin layer 502 above the contact pads 306 can be removed using a short blanket dry etch or similar technique. Then, as shown, the photoresist 402 can be removed at block N. For example, the resist 402 can be removed using a wet strip. At block N, the resulting microelectronic assembly 500 is shown.

[0071] refer to Figure 6 , a microelectronic assembly 600 is shown, which includes at least two directly bonded (e.g., without adhesive) dies 102 and 302. Alternatively, the microelectronic assemblies 102 and 302 can include two dies, two wafers, a die and a wafer or other substrates, etc. However, the microelectronic component 302 includes one or more contact pads 306 disposed inside the perimeter of the die 102.

[0072] Embedded conductive features 110 (eg, hybrid bond pads, etc.) of both dies 102 and 302 extend to the bonding surfaces 108 of dies 102 and 302 and are bonded together to form a bonded interconnect structure 304. In one embodiment, first die 102 may be formed as described in process 700.

[0073] refer to Figure 7 At block A, the die 102 is formed and prepared for direct bonding, including: forming an insulating layer 106 on a base substrate 104, forming one or more electrically conductive features 110 in the insulating layer 106, and forming a highly planar bonding layer 108 (e.g., using CMP) as described above. In various implementations, block A can be performed on a wafer, and the steps of process 700 can be performed before singulation (if desired).

[0074] At block B, process 700 includes forming a patterned resist layer 402 over bonding surface 108, wherein once dies 102 and 302 are aligned and bonded, a patterned gap in resist layer 402 is aligned over a portion of insulating layer 106 corresponding to the location of buried contact pad 306 in die 302. Optionally, the opening in die 102 can be formed to be the same as the opening in die 302, or it can be larger or smaller than the mating opening in die 302. Optionally, if desired, patterned resist layer 402 can include a gap over the scribe line. At block C, process 700 includes etching insulating layer 106 (and, if desired, some of base substrate 104) through the gap in resist layer 402, thereby forming opening 702 in insulating layer 106.

[0075] refer to Figure 8 At block D, process 700 includes removing resist 402 from bonding surface 108. For example, resist 402 can be removed by using wet stripping followed by oxygen plasma ashing. In some cases, the resist 402 removal step can cause the surface of conductive feature 110 to oxidize (e.g., to form copper oxide 404). Figure 8 As shown, depending on the amount of oxide 404 , the surface of conductive feature 110 may protrude above bonding surface 108 .

[0076] At block E, the process 700 includes removing the oxide 404 from the conductive feature 110 while controlling the material removal rate on the conductive feature 110 using a CMP process using a slurry, the slurry being formulated for polishing a barrier layer, etc., and / or using a wet etching process as described above. For example, a selective etching technique is used to remove the oxide 404, which may include etching the oxide 404 using a dilute recipe such as a 1:20 ratio of sulfuric acid or sulfonic acid to water. The designated recess of the conductive feature 110 may be achieved as part of the oxide 404 removal step using controlled material removal.

[0077] In some cases, due to, for example, bimetallic and photovoltaic effects, electrochemical enhancement of etching may be experienced on some conductive features 110. In these cases, 10 nm to 200 nm of oxide and / or barrier metal may be deposited over the bonding surface 108 and contact pads 306. CMP (or similar) may be used to re-expose the conductive features 110 on the bonding surface 108.

[0078] In one implementation, the second die 302 can be formed as described in the process 900 , including forming the opening 308 in the insulating layer 106 of the die 302 before bonding the second die 302 to the first die 102 .

[0079] refer to Fig. 9 In the process 900 of FIG. 1 , at block A, the die 302 is formed and prepared for direct bonding, including: forming an insulating layer 106 on a base substrate 104, forming one or more conductive features 110 in the insulating layer 106, and forming a highly planar bonding layer 108 as described above. In one implementation, the process 900 includes: forming buried contact pads 306 within the insulating layer 106. In various implementations, block A can be performed on a wafer, and the steps of the process 900 can be performed before singulation (if desired).

[0080] At block B, the process 900 includes forming a patterned resist layer 402 over the bonding surface 108, wherein patterned gaps in the resist layer 402 are aligned over the buried contact pads 306. Optionally, the patterned resist layer 402 can include gaps over the scribe lines, if desired. At block C, the process 900 includes etching the insulating layer 106 through the gaps in the resist layer 402, thereby forming openings 308 to expose the buried contact pads 306.

[0081] refer to Fig.10 At block D, if protection of the pads 306 is desired, the process 900 includes optionally plating the uncovered contact pads 306 with a protective metal layer 310 (e.g., nickel, gold, silver, solder, etc.). The protective layer 310 may be applied, for example, using electroless plating, or if desired, another technique such as immersion plating, etc.

[0082] At block E, process 900 includes removing resist 402 from bonding surface 108. For example, resist 402 may be removed using wet stripping followed by oxygen plasma ashing. In some cases, the resist 402 removal step may cause the surface of conductive feature 110 to oxidize (e.g., to form copper oxide 404). Fig.10 As shown, depending on the amount of oxide 404 , the surface of conductive feature 110 may protrude above bonding surface 108 .

[0083] At block F, process 900 includes removing oxide 404 from conductive feature 110 using a CMP process and / or using a wet etching process as described above, while controlling the rate of removal of material on conductive feature 110. For example, a selective etching technique is used to remove oxide 404, which may include etching oxide 404 using a dilute recipe (such as a 1:20 ratio of sulfuric acid (or sulfonic acid) to water) or a light CMP using a slurry, etc., the slurry is formulated for polishing a barrier layer. Designated recesses for conductive feature 110 may be implemented as part of the oxide 404 removal step using controlled material removal.

[0084] In some cases, electrochemical enhancement of etching may be experienced on some conductive features 110, for example due to bimetallic effects and photovoltaic effects. In these cases, approximately 10 nm to 200 nm of oxide and / or barrier metal may be deposited over the bonding surface 108, and over the contact pads 306 (not shown). CMP (or similar) may be used to re-expose the conductive features 110 on the bonding surface 108. After the second die 302 is bonded to the first die 102, the contact pads 306 may be accessed through the openings created in the first die 102, and the pads 306 may be uncovered using a dry etch.

[0085] Return to reference Figure 6 , directly bonding the prepared dies 102 and 302 at the bonding surface 108 of each produces the microelectronic assembly 600. As shown, the opening 308 in the die 302 combines with the opening 702 in the die 102 to form the cavity 602 above the contact pad 306. In some embodiments, the base substrate 104 (e.g., which may include silicon) of the first die 102 can be etched over the cavity 602 and the contact pad 306 to provide access to the contact pad 306 from outside the microelectronic assembly 600 (if necessary). In such an embodiment, when the first die 102 is bonded to the second die 302, etching only through the base layer 104 is preferred to etching through the base layer 104 and the insulating layer 106 of the die 102. In the case where the insulating layer 106 has been removed, it is easier to etch through the single layer 104, which improves the manufacturing process. Furthermore, this can result in finer pitch openings over pads 306 than when etching through both base layer 104 and insulating layer 106 of die 102. Additionally, this allows for different sized and shaped openings in each of the two dies 102 and 302 bonded together, if desired.

[0086] refer to Fig.11 , a process 1100 for forming a microelectronic assembly 1200 is shown, which includes at least two directly bonded (e.g., without adhesive) dies 102 and 302. Alternatively, the microelectronic component 302 can include a wafer or other substrate, etc. However, the microelectronic component 302 includes one or more contact pads 306, which are disposed inside the perimeter of the die 102.

[0087] Embedded conductive features 110 (e.g., hybrid bond pads, etc.) of both dies 102 and 302 extend to the bonding surfaces 108 of the dies 102 and 302 and are bonded together to form a bonded interconnect structure 304. In one embodiment, the first die 102 can be formed at process 700 as described above, and the second die 302 can be formed at process 900 as described above. Thus, process 1100 begins with microelectronic assembly 600 or the like, where the first die 102 can have a footprint that is smaller, larger, or substantially the same size as the second die 302. In some cases, the first die 102 and the second die 302 can be substantially aligned, or the first die 102 and the second die 302 can be slightly misaligned, but within hybrid bonding tolerances.

[0088] refer to Fig.11 , at block A, an example microelectronic assembly is shown, such as the previously discussed microelectronic assembly 600. At block B, process 1100 includes thinning the top base wafer 104 of the first die 102 as desired. At block C, process 1100 includes forming a patterned resist layer 1102 over the base layer 104 of the first die 102, wherein patterned gaps in the resist layer 1102 are aligned over portions of the base layer 104 corresponding to locations where portions of the base layer 104 are desired to be removed, including, for example, over the cavity 602, and the buried contact pads 306 in the die 302, over inactive areas of the die 102, and over other areas of the die 102 as desired.

[0089] refer to Fig.12 At block D, process 1100 includes etching the material (e.g., silicon, etc.) of base layer 104 of die 102 to reveal the area below, including contact pads 306 in second die 302 (or other structures (in cavity 602)). As shown, islands 1202 of active base material (e.g., silicon) can be retained on the top surface of die 102 in the active area of ​​die 102. At block E, process 1100 includes removing resist 1102 from base layer 104. For example, resist 1102 can be removed by using wet stripping followed by oxygen plasma ashing. This produces microelectronic element 1200 as shown. At block F, process 1100 can include optional steps in which base material islands 1202 can be electrically insulated and / or EMI shielded, etc. In the case of image sensors, lasers, light emitting diodes (LEDs), etc., anti-reflective coatings 1204, etc. can be applied to islands 1202.

[0090] refer to Fig.13, a process 1300 for forming a microelectronic assembly 1302 is shown, which includes at least two directly bonded (e.g., without adhesive) dies 102 and 302. Alternatively, the microelectronic component 302 can include a wafer or other substrate, etc. However, the microelectronic component 302 includes one or more contact pads 306, which are disposed inside the perimeter of the die 102.

[0091] Embedded conductive features 110 (e.g., hybrid bond pads, etc.) of both dies 102 and 302 extend to the bonding surfaces 108 of the dies 102 and 302 and are bonded together to form a bonded interconnect structure 304. In one embodiment, the first die 102 can be formed at process 700 as described above, and the second die 302 can be formed at process 900 as described above. Thus, process 1300 begins with microelectronic assembly 600 or the like, where the first die 102 can have a footprint that is smaller, larger, or substantially the same size as the second die 302. In some cases, the first die 102 and the second die 302 can be substantially aligned, or the first die 102 and the second die 302 can be slightly misaligned, but within hybrid bonding tolerances.

[0092] At block A, an example microelectronic assembly is shown, such as the previously discussed microelectronic assembly 600. At block B, the process 1300 includes forming a patterned resist layer 1102 over the base layer 104 of the first die 102, wherein patterned gaps in the resist layer 1102 are aligned over portions of the base layer 104 corresponding to locations for the cavity 602 and for the buried contact pads 306 in the die 302. Additionally, as shown in block B, resist may be deposited at other locations, such as at predetermined portions of the bonding layer 108 of the die 302, etc. The resist is placed at additional locations to prevent etching of material at these locations.

[0093] At block C, process 1300 includes etching the material (e.g., silicon, etc.) of base layer 104 of die 102 to reveal contact pads 306 in second die 302. At block D, process 1300 includes removing resist 1102 from base layer 104. Resist 1102 can be removed, for example, by using wet stripping followed by oxygen plasma ashing. This produces microelectronic element 1302 as shown.

[0094] Additional Embodiments

[0095] refer to Fig.14, a process 1400 for forming a microelectronic assembly 1500 is shown. In various embodiments, the assembly 1500 is formed from a prepared die 102 having a metal sealing ring 1402 that is desirably disposed within the die 102 (e.g., embedded within the insulating layer 106 and in some cases extending into the base substrate 104). In some examples, the hermeticity of the processed assembly 1500 can be based on the size of the sealing ring 1402.

[0096] The die 102 is prepared as described in process 100 or 200, for example, using a damascene process (or the like) to form the seal ring 1402. The assembly 1500 also includes one or more cavities 1404, which may terminate inside the insulating layer 106, terminate at the interface of the insulating layer 106 and the base layer 104, or extend through the insulating layer 106 and may also extend at least partially through the base layer 104 of the die 102. Therefore, the assembly 1500 is well suited for applications with cavities, such as MEMS, sensors, etc. The assembly 1500 can be formed and prepared for direct bonding to another die, wafer, substrate, etc. or another assembly, such as another assembly 1500 described herein.

[0097] At block A, the process 1400 includes, for example, using a CMP process, as desired, planarizing the hybrid bonding surface 108 of the first die 102. At block B, the process 1400 includes forming a patterned resist layer 402 over the bonding surface 108 of the first die 102, wherein patterned gaps in the resist layer 402 are aligned over portions of the insulating layer 104 corresponding to locations for locations to be formed of the cavities 1404. For example, the cavities 1404 may be formed inside the perimeter of the seal ring 1402.

[0098] At block C, the process 1400 includes etching (partially or fully) the material (eg, oxide, silicon, etc.) of the insulating layer 106 , and optionally partially into the base layer 104 of the die 102 to a desired depth to form one or more cavities 1404 .

[0099] refer to Fig.15 At block D, the process 1400 includes removing the resist 402 from the bonding surface 108. For example, the resist 402 may be removed by using a wet stripping method followed by an oxygen plasma ashing. In some cases, the resist 402 removal step may cause the surface of the sealing ring 1402 to oxidize (e.g., thereby forming copper oxide 404). Fig.15 As shown, depending on the amount of oxide 404 , the surface of the sealing ring 1402 may protrude above the bonding surface 108 .

[0100] At block E, process 1400 includes removing oxide 404 from seal ring 1402 using a CMP process and / or a wet etching process as described above while controlling the rate of removal of material on seal ring 1402. For example, a selective etching technique is used to remove oxide 404, which may include etching oxide 404 using a dilute recipe (such as a 1:20 ratio of sulfuric acid to water), using a trim CMP of a slurry, etc., the slurry being formulated to polish the barrier layer. A designated recess of seal ring 1402 (if applicable) may be implemented as part of the oxide 404 removal step using controlled material removal.

[0101] In some cases, electrochemical enhancement of etching may be experienced on some seal rings 1402, for example due to bimetallic effects and photovoltaic effects. In these cases, approximately 10 to 200 nm of oxide and / or barrier metal may be deposited over the bonding surface 108. For example, CMP (or the like) with a barrier slurry may be used for contact polishing and re-exposing the seal ring 1402 on the bonding surface 108. Because the edge of the insulating layer 106 meets the seal ring 1402, care must be taken to avoid rounding (e.g., erosion) the edge of the insulating layer 106. The result of the process 1400 is the microelectronic element 1500 as shown, which is ready for direct bonding.

[0102] refer to Fig.16 and Fig.17 , a process 1600 for street etching prior to singulation of the die 102 is shown. In various embodiments, the wafer 1602 may be formed and prepared as described in the process 100 or 200, such as using a damascene process (or the like) to form one or more conductive features 110 (or seal rings 1402, etc.). At box A, the process 1600 includes, for example, using a CMP process, planarizing the hybrid bonding surface 108 as desired. At box B, the process 1600 includes forming a patterned resist layer 402 over the bonding surface 108 of the die 102 of the wafer 1602, wherein the patterned gaps in the resist layer 402 are aligned over portions of the insulating layer 106 corresponding to portions of the scribe lines 1604 for singulation of the chips 102. For example, the scribe lines 1604 are disposed between the die 102 formed by the wafer 1602.

[0103] At block C, the process 1600 includes etching the insulating layer 104 and the material (eg, oxide, silicon, etc.) of the base layer 104 of the die 102 to a desired depth to form scribe line 1604 channels or recesses 1606 .

[0104] refer to Fig.17At block D, process 1600 includes removing resist 402 from bonding surface 108. For example, resist 402 may be removed by using wet stripping followed by oxygen plasma ashing. In some cases, the resist 402 removal step may result in surface oxidation of conductive feature 110 (e.g., or seal ring 1402) (e.g., thereby forming copper oxide 404). Fig.17 As shown, depending on the amount of oxide 404 , the surface of conductive feature 110 may protrude above bonding surface 108 .

[0105] At block E, process 1600 includes removing oxide 404 from conductive feature 110 using a CMP process and / or a wet etching process as described above while controlling the rate of removal of material on conductive feature 110. For example, a selective etching technique may be used to remove oxide 404, which may include etching oxide 404 using a dilute recipe such as a 1:20 ratio of sulfuric acid and water, or by light CMP using a slurry, etc., the slurry being formulated to polish the barrier layer. Designated recessing of conductive feature 110 (if applicable) may be achieved as part of the oxide 404 removal step using controlled material removal.

[0106] In some cases, electrochemical enhancement of etching may be experienced on some conductive features 110, for example due to bimetallic effects and photovoltaic effects. In these cases, approximately 10 nm to 200 nm of oxide and / or barrier metal may be deposited over the bonding surface 108. For example, CMP (or the like) with a barrier slurry may be used to contact polish and re-expose the conductive features 110 on the bonding surface 108. Because the edges of the insulating layer 106 meet the conductive features 110, care must be taken to avoid rounding (e.g., erosion) the edges of the insulating layer 106.

[0107] At block F, as an option, a protective coating 1702 may be applied to the bonding surface, and within the scribe line recesses 1606, if desired. The protective coating may protect the bonding surface 108 during singulation into individual dies 102, which occurs within the scribe line recesses 1606.

[0108] In various embodiments, wafers (such as wafer 1602), dies (such as dies 102 and 302), and other substrates having hybrid bonding surfaces 108 may be contact polished after long-term storage has resulted in a certain degree of oxidation of metal features (such as conductive features 110, seal rings 1402, etc.). Contact polishing may include using a CMP process and / or a wet etching process as described above while controlling the material removal rate on the metal features. For example, selective etching techniques are used to remove oxides, which may include etching oxides using a dilute recipe (such as a 1:20 ratio of sulfuric acid and water), contact polishing using a slurry, and the like, the slurry being formulated for polishing a barrier layer. Designated recesses of metal features (if applicable) may be restored as part of the oxide removal step using controlled material removal.

[0109] In some cases, electrochemical enhancement of etching may be experienced on some metal features, for example due to bimetallic effects and photovoltaic effects. In these cases, approximately 10 nm to 200 nm of oxide and / or barrier metal may be deposited on the bonding surface 108. For example, CMP (or the like) with a barrier slurry may be used for contact polishing and re-exposing the metal features on the bonding surface 108. As the edges of the insulating layer 106 meet the metal features, care must be taken to avoid rounding (e.g., erosion) the edges of the insulating layer 106. After contact polishing, the wafer, die, substrate, etc. is prepared for direct bonding.

[0110] Additional sample components

[0111] refer to Figures 18 to 32 In various embodiments, various microelectronic assemblies may be formed based on or associated with assemblies 300, 600, 1200, 1302, 1500, etc. In other words, various microelectronic assemblies include two or more directly bonded dies 102 and / or 302, wafers 1602, substrates, or the like, in various combinations thereof.

[0112] refer to Fig.18 , at box A, a microelectronic assembly 1800 is shown, which includes the assembly 600 having one or more contact pads 306 disposed inside the perimeter of the die 102. The assembly 1800 includes an opening etched through the base layer 104 of the die 102 to reveal the second die 302 and the contact pads 306 in the cavity 602, as shown. Fig.12 As shown in box E.

[0113] like Fig.18As shown, in some cases, the first die 102 and the second die 302 (and the corresponding conductive features 110) can be substantially aligned, or the first die 102 and the second die 302 can be slightly misaligned, but within the hybrid bonding tolerance. The openings 702 and 308 in the first die 102 and the second die 302 can also be slightly misaligned, but still form the cavity 602 and still provide sufficient access to the contact pad 306.

[0114] Optionally, as shown in block B, one or more conductive interconnect structures 1802 may be electrically coupled to contact pads 306 to provide electrical access from the top of assembly 1800 to contact pads 306. For example, in some cases, conductive interconnect structures 1802 may protrude above the top of base layer 104 of die 102.

[0115] In one embodiment, Fig.19 As shown, the first die 102 of the assembly 1800 may have a smaller footprint than the second die 302. In another embodiment, as shown in FIG. Fig.19 As shown, not all of the cavities 602 may include the conductive interconnect structure 1802. Access to the contact pads 306 may be from inside the cavities 602, or the like.

[0116] In one embodiment, Fig. 20 As shown, microelectronic assembly 2000 can include assembly 300, wherein first die 102 of assembly 2000 has a smaller footprint than second die 302, and wherein non-hybrid contact pads 306 of second die 302 are disposed outside the perimeter of first die 102. In an alternative implementation, assembly 200 includes one or more conductive interconnect structures 1802 electrically coupled to contact pads 306 to provide electrical access to contact pads 306 from a top of assembly 2000.

[0117] In one embodiment, Fig.21As shown, the microelectronic assembly 2100 may include an assembly 1200, wherein the first die 102 of the assembly 2000 has a smaller, larger, or substantially the same size footprint than the second die 302, and wherein the non-hybrid peripheral contact pads 306 of the second die 302 are disposed inside the perimeter of the first die 102. In addition, the first die 102 includes an island 1202 formed by etching away the top base layer 104 of the die 102 in the non-active region of the die 102. For example, an active base material (e.g., silicon) island 1202 may be retained on the top surface of the die 102 in the active region of the die 102. In some embodiments, the base material island 1202 may be electrically insulated and / or EMI shielded, etc. In the case of image sensors, lasers, light emitting diodes (LEDs), etc., an anti-reflective coating may be applied to the island 1202.

[0118] In an alternative embodiment, if Fig. 22 As shown, the assembly 2100 includes at least one metal layer 2202 on the exposed insulating layer 106 of the first die 102. In various examples, the metal layer 2202 can provide EMI protection, heat dissipation, or other functions as desired.

[0119] In another alternative embodiment, if Fig.23 As shown, the assembly 2100 may include deposited metal 2302 in one or more cavities 602, the deposited metal 2302 being electrically coupled to the contact pads 306 for interconnection to the pads 306. For example, in some cases, terminals 2304 (such as solder balls, etc.) may be coupled to the deposited metal 2302 to facilitate the desired interconnection.

[0120] refer to Figure 24 to Figure 26 , a direct bonded assembly 2400 having a cavity 1404 and a sealing ring 1402 is shown. In various implementations, the assembly 2400 is formed by at least one pair of assemblies 1500 that are directly bonded without an adhesive (e.g., a hybrid bond). Fig.24 In one embodiment shown, the cavity 1404 of each of the assemblies 1500 is etched through the insulating layer 106 and partially through the base layer 104. In various alternative embodiments, the cavity 1404 may be etched more or less into one assembly 1500 of the assemblies than another assembly 1500'. See below for some example etch depth options.

[0121] In one example, if Fig.25 As shown, cavity 1404 is etched into first component 1500, but not into second component 1500'. Fig.25The example etch depth shown in the figures of FIG. 1 is through the insulating layer 106 and partially into the base layer 104. Alternatively, the etch depth may be only partially through the insulating layer 106, or through the insulating layer 106 but not into the base layer 104. In alternative embodiments, the cavity 1404 may be etched into the second component 1500' but not into the first component 1500 (e.g., see above for example etch depth options). In addition, as Fig.26 As shown, assembly 2400 may include one or more components 2602 (e.g., components, structures, circuits, elements, etc.) mounted inside cavity 1404. Since assembly 2400 includes sealing ring 1402, cavity 1404 may be hermetically sealed, thereby providing an ideal environment for various sensors, MEMS, etc.

[0122] refer to Figure 27 to Figure 28 In another embodiment, the assembly 2700 includes the assembly 2400, wherein the second assembly 1500' has a larger footprint than the footprint of the first assembly 1500. In one example, the second assembly 1500' includes a peripheral bonding pad 2702 outside the perimeter of the first assembly 155, which can be used for wire bonding 2704 or similar electrical connections. The cavity 1404 of the assembly can include one or more components 2602, and the cavity 1404 can be hermetically sealed due to the presence of the sealing ring 1402. Moreover, the assembly 2700 can include one or more conductive features 110 for electrical interconnection within the assembly 2700 and to external components, such as using through-silicon vias (e.g., through-silicon vias, TSVs) 2706, etc.

[0123] like Fig.28 As shown, multiple components 2700 may be stacked to form component 2800. Alternatively, as shown, at least one or more of multiple components 2700 may not include substrate 104 on one of components 1500 and / or 1500'. As shown, the component may include sealing ring 1402 and conductive features 110 (these are arranged to electrically couple components 2700 together with or without vias 2706).

[0124] refer to Figure 29 to Figure 32 , shows a microelectronic assembly 2900 that includes an assembly 500 having one or more contact pads 306 disposed inside the perimeter of a die 102. For example, in Fig.29 and Fig.31, a microelectronic assembly 2900 is shown in which a contact pad 306 is disposed between two active areas (2902 and 2904) of the assembly 2900. Thus, the contact pad 306 can be disposed at a preselected area that is not necessarily located at the periphery of the dies 102 and 302. For example, the contact pad 306 can be disposed within the perimeter of the active areas of the dies 102 and 302. The assembly 2900 includes an opening etched through the base layer 104 and the insulating layer 106 of the die 102, and the insulating layer 106 of the die 302 to reveal the cavity 602 in the second die 302 and the contact pad 306.

[0125] Fig.30 A top view of assembly 2900 or the like is illustrated, showing that contact pads 306 may be in the form of conductive strips or other shaped structures. For example, stacked dynamic random access memory (DRAM) assemblies typically have TSVs in the center strip (or similar location) of die 302. The device may also be used with other assemblies.

[0126] like Fig.31 As shown, the etched openings in the base layer 104 and the insulating layer 106 of the first die 102, and the insulating layer 106 of the second die 302 do not need to be perfectly aligned, the openings forming the cavity 602 for access to the contact pad 306. Additionally, as shown Fig.32 As shown, the base layer 104 and the insulating layer 106 of the first die 102, and the etching openings in the insulating layer 106 of the second die 302 may have different sizes, shapes, footprints, etc. For example, Fig.32 As shown, the opening 3202 in the base layer 104 of the first die 102 may include a first shape (e.g., for this example, a rectangle, but may include any geometric or irregular shape), which exposes the first die 102 and / or the second die 302 (multiple) insulating layers 106. Additionally, the openings 3204 and 3206 in the insulating layers 106 of the first die 102 and the second die 302 may have the same or different shapes (e.g., in this example, an ellipse and a rectangle, respectively, but may include any geometric or irregular shape), which expose the contact pads 306 of the second die 302.

[0127] In various embodiments, some process steps may be modified or eliminated compared to those described herein.

[0128] The techniques, components and devices described herein are not limited to Figures 1 to 28The techniques, components, and devices described herein may be applied to other designs, types, devices, and configurations (including with other electrical components) without departing from the scope of the present disclosure. In some cases, additional or alternative components, techniques, sequences, or processes may be used to implement the techniques described herein. Furthermore, the components and / or techniques may be arranged and / or combined in various combinations while producing similar or substantially the same results.

[0129] in conclusion

[0130] Although the implementation of the present disclosure has been described in language specific to structural features and / or methodological acts, it should be understood that the implementation is not necessarily limited to the specific features or acts described. Instead, the specific features and acts are disclosed as representative forms of implementing example devices and techniques.

Claims

1. A microelectronic assembly comprising: a first substrate having a bonding surface, the bonding surface of the first substrate having a planarized topography; a first plurality of electrically conductive features at the bonding surface of the first substrate; a second substrate having a bonding surface, the bonding surface of the second substrate having a planarized topography and bonded to the bonding surface of the first substrate; a second plurality of electrically conductive features at the bonding surface of the second substrate and bonded to the first plurality of electrically conductive features; as well as One or more electrically conductive contact pads are disposed within the insulating layer of the second substrate and below the bonding surface of the second substrate, and the one or more electrically conductive contact pads are disposed in a region different from the first plurality of electrically conductive features and the second plurality of electrically conductive features.

2. The microelectronic assembly of claim 1 , further comprising one or more secondary openings in the insulating layer of the second substrate, the one or more secondary openings being aligned with the one or more electrically conductive contact pads, the one or more secondary openings extending from the bonding surface of the second substrate to the one or more electrically conductive contact pads, thereby providing access to the one or more electrically conductive contact pads.

3. The microelectronic assembly of claim 2 further comprising one or more primary openings in the insulating layer of the first substrate, the one or more primary openings being aligned with the one or more secondary openings and with the electrically conductive contact pads, the one or more primary openings extending to the one or more secondary openings to provide access to the one or more electrically conductive contact pads.

4. The microelectronic assembly of claim 3, wherein the one or more primary openings have a footprint that is a different size and / or shape than the one or more secondary openings.

5. The microelectronic assembly of claim 3 , further comprising one or more tertiary openings in the base layer of the first substrate, the one or more tertiary openings being aligned with the one or more primary openings in the insulating layer of the first substrate and with the electrically conductive contact pads, the one or more tertiary openings extending from the outer side surface of the first substrate to the one or more primary openings, thereby providing access to the one or more electrically conductive contact pads from outside the outer side surface of the first substrate.

6. The microelectronic assembly of claim 5 , further comprising one or more electrically conductive structures disposed within one or more of: the one or more secondary openings, the one or more primary openings, and the one or more tertiary openings, and electrically coupled to the one or more electrically conductive contact pads.

7. The microelectronic assembly of claim 6 , further comprising a terminal member coupled to one or more of the electrically conductive structures and configured to provide electrical access to the one or more electrically conductive contact pads from outside the outer side surface of the first substrate.

8. The microelectronic assembly of claim 6, wherein one or more of the electrically conductive structures protrude beyond the outer side surface of the first substrate.

9. The microelectronic assembly of claim 5, wherein the one or more tertiary openings have a footprint that is a different size and / or shape than the one or more primary openings and / or the one or more secondary openings.

10. The microelectronic assembly of claim 1, further comprising one or more electrically conductive interconnects electrically coupled to one or more of the electrically conductive contact pads.

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