Scheduling virtual oscillator control method of adaptive virtual resistor based on consistency algorithm

Abstract

The invention belongs to the field of inverter network type control, and discloses a schedulable virtual oscillator control method for adaptive virtual resistance based on a consistency algorithm. P1 and Q1 output by an inverter are input into a schedulable virtual oscillator, ua and ubeta two-phase output voltages are output, and coordinate transformation is carried out on the output voltages to obtain ud3 and uq3; inputting the reactive power Q1 of the inverter side and the reactive power Q2 of the load side into reactive power distribution control to obtain a distribution error uQ1 and further obtain a virtual impedance correction item deltaQ1, inputting the deltaQ1 into adaptive virtual impedance to obtain dynamic impedance LV1 and RV1, and multiplying id and iq by LV1 and RV1 to obtain virtual voltage ud2 and uq2; the ud2 and the ud3 are subtracted to obtain ud4, the uq2 and the uq3 are subtracted to obtain uq4, and the ud4 and the uq4 are input into a voltage and current double closed loop to obtain a pwm signal. The problem that the dynamic stability of an existing virtual oscillator has strict requirements for the line parameter ratio can be solved, and when the resistance-inductance ratio of the line changes, the electric energy quality can be guaranteed, the design difficulty is reduced, and the dynamic stability of the system is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of inverter grid-type control, and in particular relates to a schedulable virtual oscillator control method based on a consistency algorithm and adaptive virtual resistance. Background Art

[0002] Virtual oscillator control is an emerging inverter grid control method in recent years. Compared with existing grid control methods such as droop control and virtual synchronous machine control, it has advantages in dynamic response speed and large disturbance stability. The basic idea of ​​schedulable virtual oscillator control (dVOC) is to minimize the voltage amplitude and phase error of the voltage rating and synchronous feedback measurement, and operate at the rated angular frequency in steady state. By introducing the instantaneous power rating and voltage quantity in the virtual oscillator, VOC has the ability of power scheduling, outputs stable voltage and current, and implies quasi-droop characteristics. The schedulable virtual oscillator control can provide a limit circle rotating at a constant angular frequency in steady state, thereby generating an ideal sinusoidal reference voltage.

[0003] The existing virtual oscillator design lacks universality. At present, there are three main aspects that limit the development of virtual oscillator control technology, namely power dispatching capability, anti-interference stable operation capability, and practical application capability. The present invention mainly provides ideas for improving dynamic stability with respect to anti-interference stable operation capability, and performs simulation design and verification. At present, the factor that has the greatest impact on the dynamic stability of VOC is the resistance-inductance ratio of the line. When the system topology is relatively complex and the line parameters are different, in order to enable the inverter to enable the inverter to operate synchronously and stably, it is necessary to perform a stricter design and more precise restrictions on the line resistance-inductance ratio. When the external resistance-inductive load or the inductance resistance parameters of the line change, resulting in a change in the overall line resistance-inductance ratio, the virtual oscillator line parameters need to be redesigned, which increases the workload of the virtual oscillator in system design, greatly reduces the universality in application, and makes it difficult to guarantee the output power quality and dynamic stability. Summary of the invention

[0004] The present invention provides a schedulable virtual oscillator control method based on a consistency algorithm adaptive virtual resistance, which can solve the problem that the dynamic stability of the existing virtual oscillator has strict requirements on the line parameter ratio. When the line resistance-inductance ratio parameter changes, the stability of the overall system can still be maintained, the output power quality is guaranteed, the design difficulty of the virtual oscillator in use is reduced, and the reliability and dynamic stability of the system are increased.

[0005] The invention also provides a computer device.

[0006] The present invention also provides a computer-readable storage medium.

[0007] The present invention is achieved through the following technical solutions:

[0008] A schedulable virtual oscillator control method based on consistency algorithm adaptive virtual resistance, the control method comprising the following steps:

[0009] Step 1: Set the voltage u on the inverter output side abc and current i abc Perform dq coordinate transformation to get u d1 、u q1 and i d 、i q , the current i on the load side abc1 Perform dq coordinate transformation to obtain i d1 、i q1 ;

[0010] Step 2: Connect the inverter output side of step 1 to the d 、i q and u d1 、u q1 Perform power calculation to obtain active power P1 and reactive power Q1;

[0011] Step 3: Connect the u d1 、u q1 and i d1 、i q1 Perform power calculation to obtain active power P2 and reactive power Q2;

[0012] Step 4: Input the active power P1 and reactive power Q1 obtained in step 2 into the schedulable virtual oscillator to obtain the corresponding output u a and u β Two-phase output voltage;

[0013] Step 5: For u obtained in step 4 a and u β The two-phase output voltage is transformed into dq coordinates to obtain u d3 、u q3 ;

[0014] Step 6: Reactive power Q1 and Q2 enter the reactive power distribution control link to obtain reactive power distribution error uQ1;

[0015] Step 7: Input the reactive power distribution error uQ1 obtained in step 6 into the PI controller to obtain the virtual impedance correction term δQ1;

[0016] Step 8: Input the virtual impedance correction term δQ1 obtained in step 7 into the adaptive virtual impedance link, and update the dynamic virtual impedance to obtain L V1 and R V1 ,i d 、i qDynamic impedance L with adaptive virtual impedance output V1 and R V1 Multiply them to get the virtual voltage u d2 and u q2 ;

[0017] Step 9: Substitute u obtained in step 8 d2 with u d3 Subtract to get u d4 ,u q3 with u q2 Subtract to get u q4 , will u d4 and u q4 Input into the voltage and current double closed loop to get the PWM signal.

[0018] Furthermore, the active power P1 and reactive power Q1 obtained in step 2 and the active power P2 and reactive power Q2 obtained in step 3 are specifically:

[0019]

[0020] Inverter output port voltage vector

[0021] Furthermore, the step 4 is specifically as follows: the inverter output port voltage vector u i =[u i α u i β ] T , the current measurement value i at the inverter output port i =[i i α i i β ] T , ω0 is the nominal grid frequency, and is substituted into the equation

[0022]

[0023] where ω0Ju i is the standard equation of the oscillator in rectangular coordinates, K i u i -R(k)i i is the phase error term, Φ(u i ) i is the amplitude error term, the R(k) matrix is ​​a two-dimensional rotation matrix, J = R(π / 2), η is the power regulation parameter, and α is the voltage regulation parameter;

[0024]

[0025] where the operator ||·|| is the Euclidean norm, η>0, α>0 and 0≤k≤π are design parameters, P i * , Q i * and u i * are the set values ​​of active power, reactive power and voltage amplitude respectively; k is the parameter for adjusting the resistance and inductance of the line. When k=0, it corresponds to a resistance line, and when k=π / 2, it corresponds to an inductive circuit.

[0026] Furthermore, after polar coordinate simplification, it can be observed that the dVOC equation exhibits the following nonlinear droop characteristics:

[0027]

[0028] When k = π / 2, the final dVOC droop equation is obtained:

[0029]

[0030] When k=0, a resistance droop characteristic of VOC is generated.

[0031] Further, the step 5 is specifically, when The line impedance ratio is stable when ||u i ||≈u i * When , the voltage deviation is very small, and a more intuitive droop equation can be obtained.

[0032]

[0033] Substituting the above equation into the aβ coordinate system, we get the following equation:

[0034]

[0035] u m =Au α -ωu β (16)

[0036] u n =Au β +ωu α (17)

[0037] Among them, η is the power regulation parameter, A is the voltage gain parameter, ω is the output frequency, α is the voltage regulation parameter, and u ref is the reference voltage, u m After integration, we get u α ,u n After integration, we get u β .u α and uβ As the two-phase voltage output by the virtual oscillator in the αβ coordinate system. α and u β After dq coordinate transformation, the output voltage u is obtained d3 and u q3 .

[0038] Further, the step 6 is specifically, according to the consistency control protocol, the reactive power distribution error uQ i It is an auxiliary control that can realize reactive power distribution. It is necessary to synchronize the state quantities of all nodes in the system to an unspecified common uQ1.

[0039]

[0040] The distribution error uQ1 of the two reactive powers is obtained from the above formula;

[0041] Specifically, step 7 is to feed back uQ1 to a proportional-integral controller to obtain a virtual impedance correction term δQ1:

[0042]

[0043] Among them, K uq and K iq is the proportional coefficient and integral coefficient of the proportional-integral controller, and the reactive power distribution error u Q1 The relationship with the virtual impedance correction term δQ1 can be established by a PI regulator.

[0044] Furthermore, the step 8 is specifically to obtain reactive power distribution information of adjacent ports through a distributed communication network, obtain a distribution error, and then obtain a virtual inductance of an adaptive virtual impedance according to the following formula:

[0045] L v1 =L v1 * -k ql ·δQ1 (20)

[0046] Among them, L v1 is the adaptive virtual inductance obtained by reactive power distribution error, L v1 * k is the virtual inductance set to ensure that the line equivalent impedance is inductive. ql It is the proportional gain factor used to adjust the virtual inductance;

[0047] The adaptive virtual resistor constructed according to the following formula can provide a certain damping effect on the microgrid system

[0048] R v1 =R v1 * -kqr ·δQ1 (21)

[0049] Among them, R v1 is the adaptive virtual resistance obtained by adjusting the reactive power distribution error, R v1 * is the static virtual resistance, k qr Adjust the proportional gain coefficient of the virtual resistor;

[0050] Adaptive virtual impedance adjusts line impedance, which is realized in the inverter control system in the form of output voltage drop. The virtual resistance R obtained by the above method is v1 and virtual inductance L v1 , in the synchronous reference frame, and the inverter output current i d and i q Multiplying by the angular frequency ω, the voltage drop across the virtual impedance is calculated.

[0051] The voltage drop of the virtual impedance can be obtained by the following formula:

[0052] u d2 =i d R v1 -i q ωL v1 (twenty two)

[0053] u q2 =i q R v1 +i d ωL v1 (twenty three)

[0054] Furthermore, the step 9 is specifically as follows: d2 and u q2 The virtual voltage in the dq axis is:

[0055] u d4 =u d3 -u d2 (twenty four)

[0056] u q4 =u q3 -u q2 (25)

[0057] will u d4 and u q4 After the input voltage and current double closed loop, the PWM modulation wave is obtained.

[0058] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the above method is implemented.

[0059] A computer-readable storage medium stores a computer program, and the computer program implements the above method when executed by a processor.

[0060] The beneficial effects of the present invention are:

[0061] The present invention enhances the dynamic stability of a schedulable virtual oscillator and introduces an adaptive virtual impedance based on a consistency algorithm in a control link. When the system topology is complex and the line parameters are different, the synchronous and stable operation of the virtual oscillator can be achieved. The adaptability of the virtual oscillator to changes in line parameters is increased, and the requirements for the virtual oscillator to precise and strict restrictions on line parameters are reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 This is a structural diagram of the present invention for controlling a three-phase inverter.

[0063] Figure 2 The circuit diagram of the present invention is used during black start of an isolated microgrid with two inverters.

[0064] Figure 3 This is a frequency characteristic diagram of the output when the isolated microgrid of two inverters is black started without using the present invention.

[0066] Figure 4 This is a frequency characteristic diagram of the output when the present invention is used during black start of an isolated microgrid with two inverters.

[0067] Figure 5 This is a power characteristic diagram of the output when the two inverters are isolated and the microgrid is black started without using the present invention.

[0069] Figure 6 This is a power characteristic diagram of the output when the present invention is used during black start of an isolated microgrid with two inverters.

[0070] Figure 7 This is a power characteristic diagram of the output when the two inverters are isolated and the microgrid is black started without using the present invention.

[0072] Figure 8 This is a power characteristic diagram of the output when the present invention is used during black start of an isolated microgrid with two inverters.

[0073] Fig. 9 The figure is a characteristic diagram of voltage and current output of the first inverter when two inverter lines adopting the present invention are in black start operation.

[0075] Fig.10The figure is a voltage and current output characteristic diagram of the second inverter when two inverter lines adopting the present invention are in black start operation.

[0076] Fig.11 The figure is a power output characteristic diagram of the first inverter when two inverter lines adopting the present invention are in black start operation.

[0077] Fig.12 The figure is a power output characteristic diagram of the second inverter when two inverter lines adopting the present invention are in black start operation.

[0078] Fig.13 The inverter circuit diagram of the present invention is used when black starting an isolated microgrid with two inverters.

[0079] Fig.14 The voltage and current output characteristic diagram of the first inverter when the inverter line of the present invention is operated in black start when the line resistance-inductance ratio is changed.

[0080] Fig.15 The voltage and current output characteristic diagram of the second inverter when the line resistance-inductance ratio is changed and the inverter line of the present invention is operated in black start.

[0081] Fig.16 The power output characteristic diagram of the first inverter when the inverter line of the present invention is operated in black start mode when the line resistance-inductance ratio is changed.

[0082] Fig.17 When the line resistance-inductance ratio is changed, the power output characteristic diagram of the second inverter is shown when the inverter line of the present invention is operated in black start. DETAILED DESCRIPTION

[0083] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0084] It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0085] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, the singular forms "a", "an" and "the" are intended to include plural forms unless the context clearly indicates otherwise.

[0086] The following is attached to this application specification Figure 1-17 , the technical solutions in the embodiments of the present application are clearly and completely described. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

[0087] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0088] Implementation Method 1

[0089] This embodiment provides a schedulable virtual oscillator control method based on a consistency algorithm adaptive virtual resistance, the control method comprising the following steps:

[0090] Step 1: Set the voltage u on the inverter output side abc and current i abc Perform dq coordinate transformation to get u d1 、u q1 and i d 、i q , the current i on the load side abc1 Perform dq coordinate transformation to obtain i d1 、i q1 ;

[0091] Step 2: Connect the inverter output side of step 1 to the d 、i q and u d1 、u q1 Perform power calculation to obtain active power P1 and reactive power Q1;

[0092] Step 3: Connect the u d1 、u q1 and i d1 、i q1 Perform power calculation to obtain active power P2 and reactive power Q2;

[0093] Step 4: Input the active power P1 and reactive power Q1 obtained in step 2 into the schedulable virtual oscillator to obtain the corresponding output u a and u β Two-phase output voltage;

[0094] Step 5: For u obtained in step 4 a and u β The two-phase output voltage is transformed into dq coordinates to obtain u d3 、u q3 ;

[0095] Step 6: Reactive power Q1 and Q2 enter the reactive power distribution control link to obtain reactive power distribution error uQ1;

[0096] Step 7: Input the reactive power distribution error uQ1 obtained in step 6 into the PI controller to obtain the virtual impedance correction term δQ1;

[0097] Step 8: Input the virtual impedance correction term δQ1 obtained in step 7 into the adaptive virtual impedance link, and update the dynamic virtual impedance to obtain L V1 and R V1 ,i d 、i q Dynamic impedance L with adaptive virtual impedance output V1 and R V1 Multiply them to get the virtual voltage u d2 and u q2 ;

[0098] Step 9: Substitute u obtained in step 8 d2 with u d3 Subtract to get u d4 ,u q3 with u q2 Subtract to get u q4 , will u d4 and u q4 Input into the voltage and current double closed loop to get the PWM signal.

[0099] Furthermore, the active power P1 and reactive power Q1 obtained in step 2 and the active power P2 and reactive power Q2 obtained in step 3 are specifically:

[0100]

[0101]

[0102] Inverter output port voltage vector u i =[u i α u i β ] T (In the αβ coordinate system).

[0103] Furthermore, the step 4 is specifically as follows: the inverter output port voltage vector u i =[u i α u i β ] T (in the αβ coordinate system), the current measurement value i at the inverter output port i =[i i α i i β] T (In the αβ coordinate system), ω0 is the nominal grid frequency, and is substituted into the equation

[0104]

[0105] Among them, R(k) matrix is ​​a two-dimensional rotation matrix, J = R(π / 2), η is the power regulation parameter, α is the voltage regulation parameter;

[0106]

[0107] where the operator ‖·‖ is the Euclidean norm, η>0, α>0 and 0≤k≤π are design parameters, P i * , Q i * and u i * are the set values ​​of active power, reactive power and voltage amplitude respectively; k is the parameter for adjusting the resistance and inductance of the line. When k=0, it corresponds to a resistance line, and when k=π / 2, it corresponds to an inductive circuit.

[0108] Furthermore, after polar coordinate simplification, it can be observed that the dVOC equation exhibits the following nonlinear droop characteristics:

[0109]

[0110] When k = π / 2, the final dVOC droop equation is obtained:

[0111]

[0112] When k=0, a resistance droop characteristic of VOC is generated.

[0113] Further, the step 5 is specifically, when The line impedance ratio is stable when ||u i ||≈u i * When , the voltage deviation is very small, and a more intuitive droop equation can be obtained.

[0114]

[0115] Substituting the above equation into the aβ coordinate system, we get the following equation:

[0116]

[0117] u m =Au α -ωu β (16)

[0118] u n =Au β +ωu α (17)

[0119] Among them, η is the power regulation parameter, A is the voltage gain parameter, ω is the output frequency, α is the voltage regulation parameter, and u ref is the reference voltage, u m After integration, we get u α ,u n After integration, we get u β .u α and u β As the two-phase voltage output by the virtual oscillator in the αβ coordinate system. α and u β After dq coordinate transformation, the output voltage u is obtained d3 and u q3 .

[0120] Further, the step 6 is specifically, according to the consistency control protocol, the reactive power distribution error uQ i It is an auxiliary control that can realize reactive power distribution. It is necessary to synchronize the state quantities of all nodes in the system to an unspecified common uQ1.

[0121]

[0122] The distribution error uQ1 of the two reactive powers is obtained from the above formula;

[0123] Specifically, step 7 is to feed back uQ1 to a proportional-integral controller to obtain a virtual impedance correction term δQ1:

[0124]

[0125] Among them, K uq and K iq is the proportional coefficient and integral coefficient of the proportional-integral controller, and the reactive power distribution error u Q1 The relationship with the virtual impedance correction term δQ1 can be established by a PI regulator.

[0126] Furthermore, the step 8 is specifically to obtain reactive power distribution information of adjacent ports through a distributed communication network, obtain a distribution error, and then obtain a virtual inductance of an adaptive virtual impedance according to the following formula:

[0127] L v1 =L v1 * -k ql ·δQ1 (20)

[0128] Among them, L v1 is the adaptive virtual inductance obtained by reactive power distribution error, L v1 * k is the virtual inductance set to ensure that the line equivalent impedance is inductive. ql It is the proportional gain factor used to adjust the virtual inductance;

[0129] The adaptive virtual resistor constructed according to the following formula can provide a certain damping effect on the microgrid system

[0130] R v1 =R v1 * -k qr ·δQ1 (21)

[0131] Among them, R v1 is the adaptive virtual resistance obtained by adjusting the reactive power distribution error, R v1 * is the static virtual resistance, k qr Adjust the proportional gain coefficient of the virtual resistor;

[0132] Adaptive virtual impedance adjusts line impedance, which is realized in the inverter control system in the form of output voltage drop. The virtual resistance R obtained by the above method is v1 and virtual inductance L v1 , in the synchronous reference frame, and the inverter output current i d and i q Multiplying by the angular frequency ω, the voltage drop across the virtual impedance is calculated.

[0133] The voltage drop of the virtual impedance can be obtained by the following formula:

[0134] u d2 =i d R v1 -i q ωL v1 (twenty two)

[0135] u q2 =i q R v1 +i d ωLv1 (twenty three)

[0136] Furthermore, the step 9 is specifically as follows: d2 and u q2 The virtual voltage in the dq axis is:

[0137] u d4 =u d3 -u d2 (twenty four)

[0138] u q4 =u q3 -u q2 (25)

[0139] will u d4 and u q4 After the input voltage and current double closed loop, the PWM modulation wave is obtained.

[0140] The effectiveness of the proposed virtual oscillator control strategy is verified through a specific example:

[0141] Figure 2 The main circuit parameters are shown as follows: dc =700V, L1=50mH, L2=50mH, R1=1Ω,

[0142] R2=1Ω,C1=600uF,C2=600uf,ω n =314rad / s, the resistance of load 1 is 5Ω, the inductance is 1.5mH, the resistance of load 2 is 5Ω, the inductance is 1.5mH, and switches S1, S2, and S3 are closed after 0.5S.

[0143] Figure 3 This is the output frequency characteristic diagram of the isolated microgrid of two inverters when the present invention is not used during black start. The frequency reaches 50Hz at 0.6s. Figure 4 When the two inverters are isolated and the microgrid is black-started, the output frequency characteristic diagram of the present invention is adopted, and the frequency reaches 50.025Hz at 0.05s and enters the steady state, and the upper and lower fluctuations are less than 0.03Hz, which meets the standard of frequency fluctuation less than 0.2Hz. This reflects the excellent dynamic response of the present invention in frequency response.

[0144] Figure 5 is a characteristic diagram of active power and reactive power output by the inverter when the present invention is not adopted, Figure 6

[0145] The active power and reactive power characteristic diagram of the inverter output when the present invention is adopted,

[0146] Figure 7 and Figure 8It is an output power characteristic diagram and its enlarged diagram. It can be seen from the diagram that when the present invention is not adopted, the fluctuation of the active power and reactive power output by the inverter is greater than the power fluctuation when the present invention is adopted. The output power performance of the inverter adopting the present invention is better and more stable power quality can be output.

[0147] Fig. 9 After the first inverter is black started, it can output stable three-phase sinusoidal voltage and three-phase sinusoidal current.

[0148] Fig.10 The stable three-phase sinusoidal voltage and current output by the second inverter after black start 0.5s later

[0149] Fig.11 This is the characteristic diagram of the stable active power and reactive power output of the first inverter after black start.

[0150] Fig.12 This is the characteristic diagram of the second inverter outputting stable active power and reactive power after black start.

[0151] Fig.13 This is the circuit diagram for changing the line parameters (changing the line resistance-inductance ratio). The main circuit parameters are as follows: dc =700V, L1=30mH, L2=50mH, R1=1Ω, C1=600uF, R2=1Ω, C2=600uF, ω n =314rad / s, the resistance of load 1 is 5Ω, the inductance is 1.5mH, the resistance of load 2 is 5Ω, the inductance is 1.5mH, and switches S1, S2, and S3 are closed after 0.5S.

[0152] Fig.14 When the line inductance parameters change, after the two inverters are black started, the first inverter outputs a stable three-phase sinusoidal voltage and a stable three-phase sinusoidal current.

[0153] Fig.15 When the line inductance parameters change, after the two inverters are black started, the second inverter outputs a stable three-phase sinusoidal voltage and a stable three-phase sinusoidal current.

[0154] Fig.16 When the line inductance parameters change, the first inverter outputs stable active power and reactive power after the two inverters are black started.

[0155] Fig.17 When the line inductance parameters change. After the two inverters are black started, the second inverter outputs stable active power and reactive power.

[0156] Implementation Method 2

[0157] When the present invention is used during black start of an isolated microgrid with two inverters, the specific scheme is as follows:

[0158] The inverter 1 is connected to one end of the inductor L1, the other end of the inductor L1 is connected to one end of the resistor R1, the other end of the resistor R1 is respectively connected to one end of the switch S1 and one end of the capacitor C1, the other end of the capacitor C1 is grounded, and the other end of the switch S1 is respectively connected to the resistive-inductive load 1 and one end of the switch S2;

[0159] The inverter 2 is connected to one end of the inductor L2, the other end of the inductor L2 is connected to one end of the resistor R2, the other end of the resistor R2 is respectively connected to one end of the switch S3 and one end of the capacitor C2, the other end of the capacitor C2 is grounded, and the other end of the switch S3 is respectively connected to the resistive-inductive load 2 and the other end of the switch S2.

[0160] Implementation Method 3

[0161] An embodiment of the present invention provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the memory is used to store software programs and modules, and the processor executes various functional applications and data processing by running the software programs and modules stored in the memory. The memory and the processor are connected via a bus. Specifically, the processor implements any step in the first embodiment above by running the computer program stored in the memory.

[0162] It should be understood that in the embodiments of the present invention, the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0163] The memory may include a read-only memory, a flash memory, and a random access memory, and provides instructions and data to the processor. A part or all of the memory may also include a nonvolatile random access memory.

[0164] It can be seen from the above that the electronic device provided in the embodiment of the present invention can realize the schedulable virtual oscillator control based on the consistency algorithm adaptive virtual resistance as described in the first embodiment by running a computer program, which can solve the problem that the dynamic stability of the existing virtual oscillator has strict requirements on the line parameter ratio. When the line resistance-inductance ratio parameters change, the stability of the overall system can still be maintained to ensure the output power quality, reduce the design difficulty of the virtual oscillator in use, and increase the reliability and dynamic stability of the system.

[0165] It should be understood that if the above-mentioned integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the present invention implements all or part of the processes in the above-mentioned implementation method, and can also be completed by instructing the relevant hardware through a computer program. The above-mentioned computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method implementations when executed by the processor. Among them, the above-mentioned computer program includes computer program code, and the above-mentioned computer program code can be in source code form, object code form, executable file or some intermediate form. The above-mentioned computer-readable medium may include: any entity or device capable of carrying the above-mentioned computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the above-mentioned computer-readable storage medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction.

[0166] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest range consistent with the principles and novel features disclosed herein.

[0167] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the above-mentioned device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the implementation method can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method implementation method, which will not be repeated here.

[0168] It should be noted that the methods and detailed examples provided in the above embodiments can be combined with the devices and equipment provided in the embodiments, and references can be made to each other, and no further details will be given.

[0169] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0170] In the embodiments provided by the present invention, it should be understood that the disclosed device / terminal equipment and method can be implemented in other ways. For example, the device / equipment implementation described above is only illustrative, for example, the division of the above modules or units is only a logical function division, and in actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0171] The above-mentioned embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the above-mentioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above-mentioned embodiments, or replace some of the technical features therein by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A schedulable virtual oscillator control method based on consistency algorithm adaptive virtual resistance, characterized in that: The control method comprises the following steps: Step 1: Set the voltage u on the inverter output side abc and current i abc Perform dq coordinate transformation to get u d1 、u q1 and i d 、i q , the current i on the load side abc1 Perform dq coordinate transformation to obtain i d1 、i q1 ; Step 2: Connect the inverter output side of step 1 to the d 、i q and u d1 、u q1 Perform power calculation to obtain active power P1 and reactive power Q1; Step 3: Connect the u d1 、u q1 and i d1 、i q1 Perform power calculation to obtain active power P2 and reactive power Q2; Step 4: Input the active power P1 and reactive power Q1 obtained in step 2 into the schedulable virtual oscillator to obtain the corresponding output u a and u β Two-phase output voltage; Step 5: For u obtained in step 4 a and u β The two-phase output voltage is transformed into dq coordinates to obtain u d3 、u q3 ; Step 6: Reactive power Q1 and Q2 enter the reactive power distribution control link to obtain reactive power distribution error uQ1; Step 7: Input the reactive power distribution error uQ1 obtained in step 6 into the PI controller to obtain the virtual impedance correction term δQ1; Step 8: Input the virtual impedance correction term δQ1 obtained in step 7 into the adaptive virtual impedance link, and update the dynamic virtual impedance to obtain L V1 and R V1 ,i d 、i q Dynamic impedance L with adaptive virtual impedance output V1 and R V1 Multiply them to get the virtual voltage u d2 and u q2 ; Step 9: Substitute u obtained in step 8 d2 with u d3 Subtract to get u d4 ,u q3 with u q2 Subtract to get u q4 , will u d4 and u q4 Input into the voltage and current double closed loop to get the PWM signal.

2. The schedulable virtual oscillator control method according to claim 1, characterized in that: The active power P1 and reactive power Q1 obtained in step 2 and the active power P2 and reactive power Q2 obtained in step 3 are specifically: Inverter output port voltage vector u i =[u i α u i β ] T .

3. The schedulable virtual oscillator control method according to claim 1, characterized in that: The step 4 is specifically as follows: the inverter output port voltage vector u i =[u i α u i β ] T , the current measurement value i at the inverter output port i =[i i α i i β ] T ,ω0 is the nominal grid frequency, substitute into the equation where ω0Ju i is the standard equation of the oscillator in rectangular coordinates, K i u i -R(k)i i is the phase error term, Φ(u i ) i is the amplitude error term, the R(k) matrix is ​​a two-dimensional rotation matrix, J = R(π / 2), η is the power regulation parameter, and α is the voltage regulation parameter; where the operator ||·|| is the Euclidean norm, η>0, α>0 and 0≤k≤π are design parameters, and P i * , Q i * and u i * are the set values ​​of active power, reactive power and voltage amplitude respectively; k is the parameter for adjusting the resistance and inductance of the line. When k=0, it corresponds to a resistance line, and when k=π / 2, it corresponds to an inductive circuit.

4. The schedulable virtual oscillator control method according to claim 3, characterized in that: After polar coordinate simplification, it can be observed that the dVOC equation exhibits the following nonlinear droop characteristics: When k = π / 2, the final dVOC droop equation is obtained: When k=0, a resistance droop characteristic of VOC is generated.

5. The schedulable virtual oscillator control method according to claim 4, characterized in that: The step 5 is specifically as follows: The line impedance ratio is stable when ||u i ||≈u i * When , the voltage deviation is very small, and a more intuitive droop equation can be obtained. Substituting the above equation into the aβ coordinate system, we get the following equation: in m =Au α -ωu β (16) in n =Au β +ωu α (17) Among them, η is the power regulation parameter, A is the voltage gain parameter, ω is the output frequency, α is the voltage regulation parameter, and u ref is the reference voltage, u m After integration, we get u α ,u n After integration, we get u β .u α and u β As the two-phase voltage output by the virtual oscillator in the αβ coordinate system. α and u β After dq coordinate transformation, the output voltage u is obtained d3 and u q3 .

6. The schedulable virtual oscillator control method according to claim 1, characterized in that: The step 6 is specifically as follows: according to the consistency control protocol, the reactive power distribution error uQ i It is an auxiliary control to achieve reactive power distribution, which requires synchronizing the state quantities of all nodes in the system to an unspecified common uQ1. The distribution error uQ1 of the two reactive powers is obtained from the above formula; Specifically, step 7 is to feed back uQ1 to a proportional-integral controller to obtain a virtual impedance correction term δQ1: Among them, K uq and K iq is the proportional coefficient and integral coefficient of the proportional-integral controller, and the reactive power distribution error u Q1 The relationship with the virtual impedance correction term δQ1 is established through a PI regulator.

7. The schedulable virtual oscillator control method according to claim 4, characterized in that: Specifically, step 8 is to obtain reactive power distribution information of adjacent ports through a distributed communication network, obtain a distribution error, and then obtain a virtual inductance of an adaptive virtual impedance according to the following formula: L v1 =L v1 * -k ql ·δQ1 (20) Among them, L v1 is the adaptive virtual inductance obtained by reactive power distribution error, L v1 * k is the virtual inductance set to ensure that the line equivalent impedance is inductive. ql It is the proportional gain factor used to adjust the virtual inductance; The adaptive virtual resistor constructed according to the following formula can provide a certain damping effect on the microgrid system R v1 =R v1 * -k qr ·δQ1 (21) Among them, R v1 is the adaptive virtual resistance obtained by adjusting the reactive power distribution error, R v1 * is the static virtual resistance, k qr Adjust the proportional gain coefficient of the virtual resistor; Adaptive virtual impedance adjusts line impedance, which is realized in the inverter control system in the form of output voltage drop. The virtual resistance R obtained by the above method is v1 and virtual inductance L v1 , in the synchronous reference frame, and the inverter output current i d and i q Multiplying by the angular frequency ω, the voltage drop across the virtual impedance is calculated. The voltage drop of the virtual impedance is obtained by the following formula: u d2 =i d R v1 -i q ωL v1 (22) u q2 =i q R v1 +i d ωL v1 (23) 8. The schedulable virtual oscillator control method according to claim 7, characterized in that: The step 9 is specifically as follows: d2 and u q2 The virtual voltage in the dq axis is: in d4 =in d3 -in d2 (24) in q4 =in q3 -in q2 (25) will u d4 and u q4 After the input voltage and current double closed loop, the PWM modulation wave is obtained.

9. A computer device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method according to any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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