Motor control chip, protection method during motor driving and motor

Abstract

The invention discloses a motor control chip, a protection method during motor driving and a motor, and the chip comprises a plurality of comparison registers which are configured to trigger the phase current sampling of a motor and the generation of a motor control waveform in each motor control period; and the safety lock register is configured to prohibit the motor control chip from executing a preloading event in the updating process of the plurality of comparison registers, so that the motor phase current sampled in each motor control period is matched with the generated motor control waveform. The chip can ensure that triggering of phase current sampling is matched with generation of a motor control waveform in the motor driving process, the possible motor oscillation problem is avoided, and the reliability of the chip is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of chip design, and in particular to a motor control chip, a motor driving protection method, and a motor. Background Art

[0002] In the vector control of brushless DC motors, the sampling of motor phase current is an important link. At present, the relevant technology usually adopts the method of setting a single sampling resistor for phase current sampling, that is, a shunt resistor is connected in series with the ground line, and the motor phase current is measured through an operational amplifier and a controller. This solution has low economic cost and mature application, so it is widely used in motor driver chips. However, this type of solution has high requirements for software, and the chip needs to strictly execute procedures such as wave generation, sampling, interruption and preloading. Otherwise, correct phase current sampling and wave generation cannot be performed, and it may even cause the motor to oscillate, making the chip reliability poor. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first purpose of the present invention is to provide a motor control chip, by setting multiple comparison registers and safety lock registers in the chip, during the update process of the multiple comparison registers, the safety lock register can prohibit the motor control chip from executing the preload event, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform, so that the chip can achieve correct phase current sampling and motor control waveform generation, avoid the possible motor oscillation problem, and effectively improve the reliability of the chip.

[0004] A second objective of the present invention is to provide a motor controller.

[0005] The third object of the present invention is to provide a protection method for motor driving.

[0006] A fourth object of the present invention is to provide a motor.

[0007] To achieve the above-mentioned objectives, an embodiment of the first aspect of the present invention proposes a motor control chip, comprising: multiple comparison registers, configured to trigger motor phase current sampling and motor control waveform generation in each motor control cycle; a safety lock register, configured to prohibit the motor control chip from executing a preloading event during the update process in the multiple comparison registers, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform.

[0008] According to the motor control chip of the embodiment of the present invention, by setting multiple comparison registers and safety lock registers in the chip, during the update process of the multiple comparison registers, the safety lock register can prohibit the motor control chip from executing preloading events, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform, so that the chip can achieve correct phase current sampling and motor control waveform generation, avoiding possible motor oscillation problems and effectively improving the reliability of the chip.

[0009] According to one embodiment of the present invention, the safety lock register is further configured to allow the motor control chip to execute a preload event after the plurality of comparison registers are updated.

[0010] According to an embodiment of the present invention, when the safety lock register performs a set operation, the motor control chip is allowed to perform a preload event.

[0011] According to an embodiment of the present invention, in the current motor control cycle, if multiple comparison registers are updated, the safety lock register performs a setting operation.

[0012] According to an embodiment of the present invention, the safety lock register is further configured to prohibit the motor control chip from executing the preloading event if the preloading event occurs before the updating of the plurality of comparison registers in the current motor control cycle.

[0013] According to an embodiment of the present invention, when the motor control chip completes the execution of the preloading event, the safety lock register performs a clearing operation.

[0014] According to an embodiment of the present invention, in the current motor control cycle, if an event occurs that prohibits the motor control chip from executing preloading, the motor control chip drives the motor in the next motor control cycle based on the motor phase current sampling value and the motor control waveform used in the current motor control cycle.

[0015] According to one embodiment of the present invention, the plurality of comparison registers include first to eighth comparison registers, the first to sixth comparison registers among the first to eighth comparison registers are used to trigger the generation of a motor control waveform, and the seventh and eighth comparison registers among the first to eighth comparison registers are used to trigger motor phase current sampling.

[0016] To achieve the above-mentioned object, a second embodiment of the present invention provides a motor controller, including the aforementioned motor control chip.

[0017] The motor controller according to the embodiment of the present invention can achieve correct phase current sampling and motor control waveform generation through the aforementioned motor control chip, thereby avoiding possible motor oscillation problems and effectively improving the reliability of the motor controller.

[0018] To achieve the above-mentioned purpose, an embodiment of the third aspect of the present invention proposes a protection method for motor driving, which is applied to a motor control chip. The motor control chip includes multiple comparison registers and a safety lock register. The multiple comparison registers are configured to trigger motor phase current sampling and motor control waveform generation in each motor control cycle. The method includes: during the update process of the multiple comparison registers, the motor control chip is prohibited from executing preloading events through the safety lock register so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform.

[0019] According to the protection method for motor driving of an embodiment of the present invention, the motor control chip is prohibited from executing preloading events through the safety lock register during the update process of multiple comparison registers, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform, so that the chip can achieve correct phase current sampling and motor control waveform generation, avoiding possible motor oscillation problems and effectively improving the reliability of the chip.

[0020] According to an embodiment of the present invention, the method further includes: after the plurality of comparison registers are updated, controlling the safety lock register to perform a set operation to allow the motor control chip to perform a preload event.

[0021] According to an embodiment of the present invention, in the current motor control cycle, if multiple comparison registers have completed updating, the safety lock register is controlled to perform a setting operation.

[0022] According to an embodiment of the present invention, the method further includes: in the current motor control cycle, if the preloading event occurs before the updating of the plurality of comparison registers, prohibiting the motor control chip from executing the preloading event through the safety lock register.

[0023] According to an embodiment of the present invention, when the motor control chip completes the execution of the preloading event, the method further includes: controlling the safety lock register to perform a clearing operation.

[0024] According to one embodiment of the present invention, during the current motor control cycle, if an event occurs that prohibits the motor control chip from executing preloading, the method further includes: driving the motor in the next motor control cycle based on the motor phase current sampling value and the motor control waveform used in the current motor control cycle.

[0025] To achieve the above-mentioned purpose, a fourth aspect of the present invention provides a motor, including the aforementioned motor control chip, or the aforementioned motor controller.

[0026] According to the motor of the embodiment of the present invention, through the aforementioned motor control chip or the aforementioned motor controller, correct phase current sampling and motor control waveform generation can be achieved, thereby avoiding possible motor oscillation problems and effectively improving the reliability of the motor.

[0027] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic diagram of the structure of a motor control chip according to an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of a control cycle of a motor control chip according to an embodiment of the present invention;

[0030] Figure 3a to Figure 3c A schematic diagram of the triggering timing of phase current sampling and preloading events of a three-phase motor according to an embodiment of the present invention;

[0031] Figure 4 is a schematic structural diagram of a motor controller according to an embodiment of the present invention;

[0032] Figure 5 is a flow chart of a protection method for motor driving according to an embodiment of the present invention;

[0033] Figure 6a to Figure 6b Schematic diagram of the structure of a motor according to some embodiments of the present invention. DETAILED DESCRIPTION

[0034] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0035] The following describes a motor control chip and a motor controller, a motor driving protection method, and a motor provided in embodiments of the present invention with reference to the accompanying drawings.

[0036] Figure 1 is a schematic diagram of the structure of a motor control chip according to an embodiment of the present invention, referring to Figure 1 As shown, the motor control chip 100 includes: a plurality of comparison registers CCR1-CCRN and a safety lock register ASJ.

[0037] Among them, multiple comparison registers CCR1~CCRN are configured to trigger motor phase current sampling and motor control waveform generation in each motor control cycle; the safety lock register ASJ is configured to prohibit the motor control chip 100 from executing preloading events during the update process of multiple comparison registers CCR1~CCRN, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform.

[0038] Specifically, in the current motor phase current acquisition scheme, single resistor sampling is a relatively economical method. Taking a three-phase motor as an example, a sampling resistor can be connected in series to the ground wire of the three-phase bridge arm, and the two-phase bridge arm current can be obtained by sampling twice, and then the remaining phase current can be obtained by calculation, thereby obtaining the corresponding three-phase current sampling value. The trigger point of the phase current sampling is stored in some comparison memories in multiple comparison memories CCR1~CCRN. The specific principle of obtaining the motor three-phase current by single resistor sampling is not expanded here. Reference Figure 2 As shown, a motor control cycle of the motor control chip 100 generally includes a complete triangle wave cycle, and the specific steps are as follows: the motor control chip 100 samples the phase current of the three-phase motor according to the two phase current sampling trigger points stored in the multiple comparison registers CCR1~CCRN to obtain the motor phase current sampling value; then the motor control chip 100 sends an interrupt signal, such as Figure 2 The peak of the PWM triangle wave is shown; the motor control chip 100 performs calculations according to the preset control method and the acquired motor phase current sampling value after the interrupt signal, for example, by Figure 2 The FOC (field oriented control, vector control) calculation shown in the figure is used to determine the wave comparison value of the three-phase bridge arm (U phase, V phase, W phase) and the phase current sampling trigger point for triggering the motor phase current sampling in the next motor control cycle, and store them in multiple comparison registers CCR1~CCRN; finally, the motor control chip 100 executes the preload event, such as Figure 2 As shown in the trough of the PWM triangle wave, the updated phase current sampling trigger points and the wave generation comparison values ​​in the multiple comparison registers are written into the shadow registers corresponding to the multiple comparison registers. The motor control chip 100 can generate waves according to the wave generation comparison values ​​stored in the multiple shadow registers to generate PWM waves to drive the motor to operate normally. The specific generation principle of the PWM wave is not expanded here. In addition, in the next motor control cycle, the motor control chip 100 can also perform phase current sampling of the next motor control cycle according to the phase current sampling trigger points stored in the multiple shadow registers.

[0039] From the above, it can be seen that within a single motor control cycle, the motor control chip 100 needs to complete phase current sampling, FOC calculation, update multiple comparison registers and execute preloading events in sequence. At the same time, the motor control chip also needs to generate a motor control waveform based on the wave comparison value stored in the shadow register. Among them, multiple comparison registers CCR1~CCRN have two functions of triggering motor phase current sampling and triggering motor control waveform generation, and in each motor control cycle, multiple comparison registers CCR1~CCRN need to update the internally stored phase current sampling trigger point and wave comparison value. The update process takes a while. At the same time, the phase current sampling process or the execution of the preloading event is easily delayed due to various interrupt signals during the motor driving process. Therefore, it is easy to have the problem that the update of the phase current sampling trigger point and the wave comparison value has not yet been completed in the motor control cycle, and the preloading event has already started to execute, such as Figure 2 In this case, the multiple comparison registers CCR1-CCRN have not been updated yet, so the phase current sampling trigger points and wave generation comparison values ​​written into the multiple comparison registers CCR1-CCRN may be partially from the data of the previous motor control cycle and partially from the data of the current motor control cycle, which results in abnormal sampling and wave generation of the motor control chip 100, causing the motor phase current to not match the generated motor control waveform, and further causing the motor to oscillate.

[0040] The motor control chip 100 of the embodiment of the present invention solves the above-mentioned motor oscillation problem by means of a built-in safety lock register ASJ. In each motor control cycle, when the motor control chip 100 samples the motor phase current and updates multiple comparison registers CCR1~CCRN, the safety lock register ASJ can prohibit the motor control chip 100 from executing preloading events, thereby avoiding the above-mentioned problems of abnormal sampling and wave generation of the motor control chip 100, ensuring that the motor phase current sampled in each motor control cycle matches the generated motor control waveform, so that the chip can achieve correct phase current sampling and motor control waveform generation, thereby avoiding possible motor oscillation, ensuring that the motor can run stably, and effectively improving the reliability of the chip.

[0041] In some embodiments, the security lock register ASJ is further configured to allow the motor control chip 100 to execute a preload event after the plurality of comparison registers CCR1 ˜CCRN are updated.

[0042] Specifically, in the motor control strategy, between adjacent phase current sampling and multiple comparison register update processes, the motor control chip needs to execute a preload event so that the motor control chip can obtain the updated phase current sampling trigger point and wave comparison value to drive the motor. Figure 3aAs shown, after the motor control chip 100 completes the phase current sampling and updates the multiple comparison registers CCR1-CCRN, when the motor control chip 100 executes the preload event, the preload event will not conflict with the process of updating the multiple comparison registers CCR1-CCRN by the motor control chip 100, thereby affecting the stable operation of the motor. Therefore, the safety lock register ASJ can allow the motor control chip 100 to execute the preload event after the multiple comparison registers CCR1-CCRN are updated, so that the motor can operate normally.

[0043] In some embodiments, the safety lock register is further configured to prohibit the motor control chip from executing the preloading event if the preloading event occurs before the updating of the plurality of comparison registers in the current motor control cycle.

[0044] Specifically, refer to Figure 3b As shown, in the current motor control cycle, if the preload event occurs before the update of multiple comparison registers, the multiple comparison registers may not store data or store the phase current sampling trigger point and the wave comparison value of the previous cycle. In this case, the motor control chip 100 executes the preload event and cannot reflect the phase current sampling value of the current motor control cycle. Therefore, the safety lock register can prohibit the motor control chip from executing the preload event to avoid executing an invalid preload event.

[0045] In some embodiments, the safety lock register ASJ allows the motor control chip 100 to perform a preload event when a set operation is performed.

[0046] Furthermore, in the current motor control cycle, if multiple comparison registers are updated, the safety lock register performs a set operation.

[0047] Furthermore, when the motor control chip 100 completes the execution of the preloading event, the safety lock register ASJ performs a clearing operation.

[0048] Specifically, the two functions of the security lock register ASJ, i.e., prohibiting preloading events and allowing preloading events, can be realized by setting and clearing the security lock register ASJ. For example, when the update of multiple comparison registers CCR1 to CCRN is completed, the security lock register ASJ can be set (i.e., all the security lock registers ASJ are set to binary number "1" by external writing), and when the motor control chip 100 completes the execution of the preloading event, the security lock register ASJ can be controlled to perform a clearing operation. The specific principle is as follows:

[0049] When the multiple comparison registers CCR1~CCRN are updated, the motor control chip 100 will not affect the stable operation of the motor when executing the preload event. At this time, the safety lock register ASJ can perform a set operation to allow the motor control chip to execute the preload event so that the chip 100 can drive the motor to operate normally. When the preload event is completed, the multiple comparison registers CCR1~CCRN updated in the current motor control cycle have all been written to the shadow register, and there is no need to execute the preload event again. Therefore, the safety lock register ASJ can be cleared. At this time, until the safety lock register of the next motor control cycle is set, the motor control chip cannot execute the preload event, thereby ensuring that the motor control chip cannot execute the preload event during the phase current sampling and the update process of the multiple comparison registers CCR1~CCRN in the next motor control cycle. Subsequently, the multiple comparison registers in the next motor control cycle execute the phase current sampling and the update process of the multiple comparison registers again, and the safety lock register ASJ performs the set operation again. This process is repeated so that the preload event will not be executed during the motor phase current sampling and multiple comparison register update process, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform, thereby improving the reliability of the motor control chip.

[0050] In some embodiments, in the current motor control cycle, if an event occurs that prohibits the motor control chip 100 from executing preloading, the motor control chip 100 drives the motor in the next motor control cycle based on the motor phase current sampling values ​​and motor control waveforms used in the current motor control cycle.

[0051] Specifically, in the current motor control cycle, the motor control chip needs to perform phase current sampling and generate motor control waveforms according to the phase current sampling point information and wave comparison value stored in the shadow register. At the same time, in the current motor control cycle, if the motor control chip 100 is prohibited from executing the preloading event, the phase current sampling trigger point and the wave comparison value generated in the current motor control cycle cannot be written into the multiple shadow registers, and the multiple shadow registers are not updated. Then, in the next motor control cycle, the motor control chip will control the motor according to the unupdated phase current sampling trigger point and wave comparison value stored in the shadow register. Therefore, in the next motor control cycle, the motor control chip will use the same phase current sampling value and motor control waveform as the current motor control cycle to drive the motor. The above method can ensure that the motor control chip can still drive the motor to run smoothly when the preloading event is prohibited, thereby improving the reliability of the motor control chip.

[0052] The following takes the motor control chip 100 driving a three-phase motor using a single resistor sampling as an example to illustrate the working principle of the motor control chip 100 according to the embodiment of the present invention. Figure 3a As shown, the motor control chip 100 includes the first to the eighth comparison registers CCR1 to CCR8, wherein the first to the sixth comparison registers CCR1 to CCR6 are used to store six wave comparison values ​​to trigger the generation of the motor control waveform. The six comparison registers correspond to the six switch tubes of the three-phase bridge arm (U phase, V phase, W phase). The comparison registers corresponding to the specific switch tubes are as follows: Figure 3a As shown, it will not be expanded here; the seventh and eighth comparison registers CCR7-CCR8 are used to store two phase current sampling trigger points to trigger motor phase current sampling. In each control cycle, the motor control chip 100 needs to update two phase current sampling trigger points and six wave comparison values. This update process corresponds to Figure 3a The shaded part in the upper left control cycle, and the setting operation of the safety lock register ASJ corresponds to the black part in the control cycle. When the eight comparison registers CCR1~CCR8 of the motor control chip are updated, the safety lock register ASJ performs the setting operation. At this time, the occurrence time of the motor preload event can be divided into three situations:

[0053] In the first case, refer to Figure 3a As shown, the preloading event of the motor control chip 100 occurs before the update of the eight comparison registers CCR1 to CCR8, and at this time, the safety lock register ASJ is in a cleared state, so the safety lock register ASJ prohibits the execution of the preloading event in the current motor control cycle to avoid the execution of invalid preloading events. After the comparison registers CCR1 to CCR8 of the current motor control cycle are updated, the safety lock register ASJ performs a set operation. At this time, in the next motor control cycle, the preloading event can be executed normally to write the updated content of the comparison registers CCR1 to CCR8 of the current motor control cycle into the shadow register. After the preloading event ends, the safety lock register ASJ performs a clear operation.

[0054] In the second case, refer to Figure 3b As shown, when the preload event occurs after the update of the eight comparison registers CCR1~CCR8, since the safety lock register ASJ has performed the set operation in the current motor control cycle, the safety lock register ASJ also allows the preload event to be executed. At this time, the safety lock register ASJ will not affect the motor control chip 100.

[0055] The third case, refer to Figure 3cAs shown, the preloading event of the motor control chip 100 occurs in the update process of multiple comparison registers CCR1~CCRN. At this time, since the multiple comparison registers CCR1~CCRN have not been updated and the safety lock register ASJ has not been set, the safety lock register ASJ prohibits the occurrence of the preloading event, thereby avoiding the phase current sampling trigger point and the wave comparison value written in the shadow register from coming from different control cycles, ensuring the stable operation of the motor, and thus improving the reliability of the motor control chip.

[0056] To summarize, according to the motor control chip of the embodiment of the present invention, by setting multiple comparison registers and safety lock registers in the chip, during the update process of the multiple comparison registers, the safety lock register can prohibit the motor control chip from executing preloading events, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform, so that the chip can achieve correct phase current sampling and motor control waveform generation, avoiding possible motor oscillation problems and effectively improving the reliability of the chip.

[0057] Corresponding to the above embodiment, the present invention further provides a motor controller 1000, referring to Figure 4 As shown, the motor controller 1000 includes the aforementioned motor control chip 100 .

[0058] The motor controller according to the embodiment of the present invention can achieve correct phase current sampling and motor control waveform generation through the aforementioned motor control chip, thereby avoiding possible motor oscillation problems and effectively improving the reliability of the motor controller.

[0059] Corresponding to the above embodiment, the present invention also provides a motor driving protection method, which is applied to Figure 1 The motor control chip shown in the figure is Figure 1 As shown, the motor control chip 100 includes a plurality of comparison registers CCR1-CCRN and a safety lock register ASJ, and the plurality of comparison registers are configured to trigger motor phase current sampling and motor control waveform generation in each motor control cycle. Figure 5 As shown, the method includes:

[0060] S11, during the updating process of the multiple comparison registers, the motor control chip is prohibited from executing the preloading event through the safety lock register, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform.

[0061] According to an embodiment of the present invention, the method further includes: after the plurality of comparison registers are updated, controlling the safety lock register to perform a set operation to allow the motor control chip to perform a preload event.

[0062] According to an embodiment of the present invention, in the current motor control cycle, if multiple comparison registers have completed updating, the safety lock register is controlled to perform a setting operation.

[0063] According to an embodiment of the present invention, the method further includes: in the current motor control cycle, if the preloading event occurs before the updating of the plurality of comparison registers, prohibiting the motor control chip from executing the preloading event through the safety lock register.

[0064] According to an embodiment of the present invention, when the motor control chip completes the execution of the preloading event, the method further includes: controlling the safety lock register to perform a clearing operation.

[0065] According to one embodiment of the present invention, during the current motor control cycle, if an event occurs that prohibits the motor control chip from executing preloading, the method further includes: driving the motor in the next motor control cycle based on the motor phase current sampling value and the motor control waveform used in the current motor control cycle.

[0066] It should be noted that, for the description of the protection method during motor driving of the embodiment of the present invention, please refer to the description of the motor control chip in this application, and the details will not be repeated here.

[0067] According to the protection method for motor driving of an embodiment of the present invention, the motor control chip is prohibited from executing preloading events through the safety lock register during the update process of multiple comparison registers, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform, so that the chip can achieve correct phase current sampling and motor control waveform generation, avoiding possible motor oscillation problems and effectively improving the reliability of the chip.

[0068] Corresponding to the above embodiment, the embodiment of the present invention further provides a motor, referring to Figure 6a-6b As shown, the motor 10000 includes the aforementioned motor control chip 100 , or the aforementioned motor controller 1000 .

[0069] According to the motor of the embodiment of the present invention, through the aforementioned motor control chip or the aforementioned motor controller, correct phase current sampling and motor control waveform generation can be achieved, thereby avoiding possible motor oscillation problems and effectively improving the reliability of the motor.

[0070] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0071] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0072] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0073] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0074] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0075] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A motor control chip, characterized in that: include: a plurality of compare registers configured to trigger motor phase current sampling and motor control waveform generation during each motor control cycle; The safety lock register is configured to prohibit the motor control chip from executing a preload event during the updating process of the plurality of comparison registers, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform.

2. The motor control chip according to claim 1, characterized in that: The safety lock register is further configured to allow the motor control chip to execute a preload event after the plurality of compare registers are updated.

3. The motor control chip according to claim 2, characterized in that: When the safety lock register performs a set operation, the motor control chip is allowed to perform a preload event.

4. The motor control chip according to claim 3, characterized in that: In the current motor control cycle, if the multiple comparison registers are updated, the safety lock register performs a setting operation.

5. The motor control chip according to claim 1, characterized in that: The safety lock register is further configured to prohibit the motor control chip from executing the preloading event if the preloading event occurs before the updating of the plurality of comparison registers in the current motor control cycle.

6. The motor control chip according to any one of claims 1 to 5, characterized in that: When the motor control chip completes the execution of the preloading event, the safety lock register performs a clearing operation.

7. The motor control chip according to claim 5, characterized in that: In the current motor control cycle, if an event occurs that prohibits the motor control chip from executing preloading, the motor control chip drives the motor in the next motor control cycle based on the motor phase current sampling values ​​and motor control waveforms used in the current motor control cycle.

8. The motor control chip according to claim 1, characterized in that: The multiple comparison registers include first to eighth comparison registers, the first to sixth comparison registers among the first to eighth comparison registers are used to trigger the generation of the motor control waveform, and the seventh and eighth comparison registers among the first to eighth comparison registers are used to trigger motor phase current sampling.

9. A motor controller, characterized in that: Comprising a motor control chip according to any one of claims 1-8.

10. A protection method for motor driving, characterized in that: Applied to a motor control chip, the motor control chip includes a plurality of comparison registers and a safety lock register, the plurality of comparison registers are configured to trigger motor phase current sampling and motor control waveform generation in each motor control cycle, the method includes: During the updating process of the plurality of comparison registers, the motor control chip is prohibited from executing a preload event through the safety lock register, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform.

11. The method according to claim 10, characterized in that Also includes: After the plurality of comparison registers are updated, the safety lock register is controlled to perform a setting operation to allow the motor control chip to perform a preloading event.

12. The method according to claim 11, characterized in that In the current motor control cycle, if the multiple comparison registers have completed updating, the safety lock register is controlled to perform a setting operation.

13. The method according to claim 10, characterized in that Also includes: In the current motor control cycle, if the preloading event occurs before the multiple comparison registers are updated, the motor control chip is prohibited from executing the preloading event through the safety lock register.

14. The method according to claim 11, characterized in that When the motor control chip completes the execution of the preloading event, the method further includes: Control the security lock register to perform a clearing operation.

15. The method according to any one of claims 10 to 14, characterized in that: In the current motor control cycle, if an event occurs that prohibits the motor control chip from executing preloading, the method further includes: The motor is driven in a next motor control cycle based on the motor phase current sampling values ​​and the motor control waveform used in the current motor control cycle.

16. A motor, characterized in that: It comprises a motor control chip according to any one of claims 1 to 8, or a motor controller according to claim 9.

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