Protection method during motor driving, motor control chip and motor

Abstract

The invention discloses a protection method during motor driving, a motor control chip and a motor, the method is applied to the motor control chip, the motor control chip comprises a plurality of comparison registers, and the plurality of comparison registers are configured to trigger motor phase current sampling and motor control waveform generation in each motor control period. The method comprises the following steps: in the updating process of a plurality of comparison registers, forbidding a motor control chip to execute a preloading event, so that motor phase current sampled in each motor control period is matched with a generated motor control waveform. According to the method, the motor phase current sampled in each motor control period can be matched with the generated motor control waveform so as to ensure that the chip executes correct phase current sampling and motor control waveform generation, the possible motor oscillation problem is avoided, and the reliability of the chip is further improved.

Description

Technical Field

[0001] The present invention relates to the field of motor driving, and in particular to a motor driving protection method, a motor control chip, and a motor. Background Art

[0002] In the vector control of brushless DC motors, the sampling of motor phase current is an important link. At present, the relevant technology usually adopts the method of setting a single sampling resistor for phase current sampling, that is, a shunt resistor is connected in series with the ground line, and the motor phase current is measured through an operational amplifier and a controller. This solution has low economic cost and mature application, so it is widely used in motor drive solutions. However, this type of solution has high requirements for software, and the chip needs to strictly execute procedures such as wave generation, sampling, interruption and preloading. Otherwise, correct phase current sampling and wave generation cannot be performed, and it may even cause the motor to oscillate, making the reliability of the solution poor. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first purpose of the present invention is to propose a protection method for motor driving, by prohibiting the motor control chip from executing a preload event during the update process of multiple comparison registers in the motor control chip, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform, thereby ensuring that the chip performs correct phase current sampling and motor control waveform generation, avoiding possible motor oscillation problems, and effectively improving the reliability of the chip.

[0004] A second object of the present invention is to provide a computer-readable storage medium.

[0005] The third objective of the present invention is to provide a motor control chip.

[0006] The fourth objective of the present invention is to provide another motor control chip.

[0007] A fifth object of the present invention is to provide a motor controller.

[0008] A sixth object of the present invention is to provide a motor.

[0009] To achieve the above-mentioned purpose, an embodiment of the first aspect of the present invention proposes a protection method for motor driving, which is applied to a motor control chip. The motor control chip includes multiple comparison registers, and the multiple comparison registers are configured to trigger motor phase current sampling and motor control waveform generation in each motor control cycle. The method includes: during the update process of the multiple comparison registers, prohibiting the motor control chip from executing preloading events so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform.

[0010] According to the protection method for motor driving of an embodiment of the present invention, during the update process of multiple comparison registers in the motor control chip, the motor control chip is prohibited from executing preloading events, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform, thereby ensuring that the chip performs correct phase current sampling and motor control waveform generation, avoiding possible motor oscillation problems and effectively improving the reliability of the chip.

[0011] According to one embodiment of the present invention, the motor control chip also includes a counter, which is configured to count the number of updates of multiple comparison registers. The method also includes: when it is determined that the count value of the counter reaches a first preset value, allowing the motor control chip to execute a preloading event, wherein the first preset value is adapted to the number of multiple comparison registers.

[0012] According to an embodiment of the present invention, determining that the count value of the counter reaches the first preset value includes: in the current motor control cycle, if multiple comparison registers are updated respectively, determining that the count value of the counter reaches the first preset value.

[0013] According to an embodiment of the present invention, when it is determined that the count value of the counter reaches the first preset value, the method further includes: generating a hardware flag bit, so as to allow the motor control chip to execute a preloading event when the hardware flag bit is detected.

[0014] According to an embodiment of the present invention, the method further includes: in the current motor control cycle, if the preloading event occurs before the updating of the plurality of comparison registers, prohibiting the motor control chip from executing the preloading event.

[0015] According to an embodiment of the present invention, when the motor control chip completes the execution of the preloading event, the method further includes: clearing the hardware flag bit and resetting the counter.

[0016] According to one embodiment of the present invention, in the current motor control cycle, if an event occurs that prohibits the motor control chip from executing preloading, the method further includes: driving the motor in the next motor control cycle based on the motor phase current sampling value and the motor control waveform used in the current motor control cycle.

[0017] To achieve the above-mentioned purpose, a second embodiment of the present invention proposes a computer-readable storage medium, on which a protection program for motor driving is stored. When the protection program is executed by a processor, the aforementioned protection method for motor driving is implemented.

[0018] According to the computer-readable storage medium of an embodiment of the present invention, through the aforementioned motor driving protection method, it is possible to ensure that the chip performs correct phase current sampling and motor control waveform generation, avoid possible motor oscillation problems, and effectively improve the reliability of the chip.

[0019] To achieve the above-mentioned purpose, the third aspect of the embodiment of the present invention proposes a motor control chip, including: a memory, a processor, and a motor driving protection program stored in the memory and runnable on the processor. When the processor executes the protection program, the aforementioned motor driving protection method is implemented.

[0020] According to the motor control chip of the embodiment of the present invention, through the aforementioned protection method during motor driving, it can ensure that the chip performs correct phase current sampling and motor control waveform generation, avoids possible motor oscillation problems, and effectively improves the reliability of the chip.

[0021] To achieve the above-mentioned purpose, the fourth aspect of the present invention proposes another motor control chip, including: multiple comparison registers, which are configured to trigger motor phase current sampling and motor control waveform generation in each motor control cycle; a main control unit, which is configured to prohibit the motor control chip from executing preloading events during the update process of the multiple comparison registers, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform.

[0022] According to the motor control chip of the embodiment of the present invention, during the update process of multiple comparison registers in the motor control chip, the main control unit prohibits the motor control chip from executing preloading events, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform, thereby ensuring that the chip executes correct phase current sampling and motor control waveform generation, avoiding possible motor oscillation problems, and effectively improving the reliability of the chip.

[0023] According to one embodiment of the present invention, the chip also includes a counter, which is configured to count the number of updates of multiple comparison registers. The main control unit is also configured to allow the motor control chip to execute a preloading event when it is determined that the count value of the counter reaches a first preset value, wherein the first preset value is adapted to the number of multiple comparison registers.

[0024] According to an embodiment of the present invention, the main control unit is further configured to determine that the count value of the counter reaches a first preset value if multiple comparison registers have completed updating respectively within the current motor control cycle.

[0025] According to one embodiment of the present invention, the chip also includes a flag register, which is configured to generate a hardware flag when the count value of the counter reaches a first preset value, so that the main control unit allows the motor control chip to execute a preloading event when the hardware flag is detected.

[0026] According to an embodiment of the present invention, the main control unit is further configured to prohibit the motor control chip from executing the preloading event if the preloading event occurs before the updating of the plurality of comparison registers in the current motor control cycle.

[0027] According to an embodiment of the present invention, the main control unit is further configured to, when the motor control chip completes the execution of the preloading event, control the flag register to clear the hardware flag bit and control the counter to be cleared.

[0028] According to one embodiment of the present invention, the main control unit is also configured to drive the motor based on the motor phase current sampling value and motor control waveform used in the current motor control cycle in the next motor control cycle if an event occurs that prohibits the motor control chip from executing preloading.

[0029] According to one embodiment of the present invention, the plurality of comparison registers include first to eighth comparison registers, the first to sixth comparison registers among the first to eighth comparison registers are used to trigger the generation of a motor control waveform, and the seventh and eighth comparison registers among the first to eighth comparison registers are used to trigger motor phase current sampling.

[0030] To achieve the above-mentioned purpose, a fifth aspect of the present invention provides a motor controller, including the aforementioned motor control chip or the aforementioned another motor control chip.

[0031] The motor controller according to the embodiment of the present invention can ensure that the motor controller performs correct phase current sampling and motor control waveform generation through one of the two motor control chips mentioned above, avoids possible motor oscillation problems, and effectively improves the reliability of the motor controller.

[0032] To achieve the above-mentioned purpose, a sixth aspect of the present invention provides a motor, comprising the aforementioned motor control chip; or, the aforementioned motor controller.

[0033] According to the motor controller of the embodiment of the present invention, through one of the two motor control chips mentioned above, or the motor controller mentioned above, it is possible to achieve correct phase current sampling and motor control waveform generation, avoid possible motor oscillation problems, and effectively improve the reliability of the motor.

[0034] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic diagram of the structure of a motor control chip according to an embodiment of the present invention;

[0036] Figure 2 A schematic diagram of a control cycle of a motor control chip according to an embodiment of the present invention;

[0037] Figure 3 is a flow chart of a protection method for motor driving according to an embodiment of the present invention;

[0038] Figures 4a to 4c A schematic diagram of the triggering timing of phase current sampling and preloading events of a three-phase motor according to an embodiment of the present invention;

[0039] Figure 5 is a schematic structural diagram of a motor control chip according to another embodiment of the present invention;

[0040] Figure 6 is a schematic diagram of the structure of a motor control chip according to another embodiment of the present invention;

[0041] Figure 7 is a schematic diagram of the structure of a motor control chip according to another embodiment of the present invention;

[0042] Figure 8a-8b is a schematic diagram of the structure of a motor controller according to some embodiments of the present invention;

[0043] Figures 9a to 9c Schematic diagram of the structure of a motor according to some embodiments of the present invention. DETAILED DESCRIPTION

[0044] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0045] The following describes the motor driving protection method and computer-readable storage medium, motor control chip, motor controller, and motor provided in the embodiments of the present invention with reference to the accompanying drawings.

[0046] It should be noted that the protection method of the embodiment of the present invention can be applied to different motor control chips including multiple comparison registers. Figure 1The motor control chip shown illustrates the protection method of the embodiment of the present invention. Figure 1 As shown, the motor control chip 100 includes a plurality of comparison registers CCR1 ˜CCRN, and the plurality of comparison registers CCR1 ˜CCRN are configured to trigger motor phase current sampling and motor control waveform generation in each motor control cycle.

[0047] Specifically, in the current motor phase current acquisition scheme, single resistor sampling is a relatively economical method. Taking a three-phase motor as an example, a sampling resistor can be connected in series with the ground wire of the three-phase bridge arm, and the two-phase bridge arm current can be obtained by sampling twice, and then the remaining phase current can be obtained by calculation, thereby obtaining the corresponding three-phase current sampling value. The trigger point of the phase current sampling is stored in some comparison memories in multiple comparison memories CCR1~CCRN. The specific principle of obtaining the motor three-phase current by single resistor sampling is not expanded here.

[0048] refer to Figure 2 As shown, a motor control cycle of the motor control chip 100 generally includes a complete triangle wave cycle, and the specific steps are as follows: First, the motor control chip 100 samples the phase current of the three-phase motor according to the two phase current sampling trigger points stored in the multiple comparison registers CCR1~CCRN to obtain the motor phase current sampling value; then, the motor control chip 100 sends an interrupt signal, such as Figure 2 The peak of the PWM triangle wave is shown; the motor control chip 100 performs calculations according to the preset control method and the acquired motor phase current sampling value after the interrupt signal, for example, by Figure 2 The FOC (field oriented control, vector control) calculation shown in the figure is used to determine the wave comparison value of the three-phase bridge arm (U phase, V phase, W phase) and the phase current sampling trigger point for triggering the motor phase current sampling in the next motor control cycle, and store them in multiple comparison registers CCR1~CCRN; finally, the motor control chip 100 executes the preload event, such as Figure 2 As shown in the trough of the PWM triangle wave, the preload event is to write the phase current sampling trigger point and the wave generation comparison value into the shadow register corresponding to the multiple comparison registers; the motor control chip 100 can generate waves according to the wave generation comparison value and the triangle wave stored in the multiple shadow registers to generate a PWM wave to drive the motor to operate normally. The specific generation principle of the PWM wave is not expanded here. In addition, in the next motor control cycle, the motor control chip 100 can also perform phase current sampling for the next control cycle according to the phase current sampling trigger points stored in the multiple shadow registers.

[0049] Figure 3 is a flowchart of a motor driving protection method according to an embodiment of the present invention, referring to Figure 3 As shown, the method includes:

[0050] S11, during the updating process of the plurality of comparison registers, prohibiting the motor control chip from executing a preloading event, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform.

[0051] Specifically, from the above, it can be seen that within a single motor control cycle, the motor control chip needs to complete phase current sampling, FOC calculation, update multiple comparison registers and execute preloading events in sequence. At the same time, the motor control chip also needs to generate a motor control waveform based on the wave comparison value stored in the shadow register. Among them, multiple comparison registers have two functions: triggering motor phase current sampling and triggering motor control waveform generation. In each motor control cycle, multiple comparison registers need to update the internally stored phase current sampling trigger points and wave comparison values. This update process takes some time. At the same time, the motor driving process is prone to delays in the phase current sampling process or the execution of preloading events due to various interrupt signals. Therefore, it is easy to have problems in the motor control cycle where the update of the phase current sampling trigger point and the wave comparison value has not yet been completed, and the preloading event has already started to execute, such as Figure 2 In this case, multiple comparison registers have not been updated, so the phase current sampling trigger points and wave generation comparison values ​​written to the multiple comparison registers may be partially from the data of the previous motor control cycle and partially from the data of the current motor control cycle, which leads to abnormal sampling and wave generation of the motor control chip, causing the motor phase current to not match the generated motor control waveform, and thus causing the motor to oscillate.

[0052] In the method of the embodiment of the present invention, the motor control chip is prohibited from executing preloading events during the update process of multiple comparison registers in each motor control cycle, thereby avoiding the above-mentioned problems of abnormal sampling and wave generation of the motor control chip, ensuring that the motor phase current sampled in each motor control cycle matches the generated motor control waveform, so that the chip can achieve correct phase current sampling and motor control waveform generation, thereby avoiding possible motor oscillation and ensuring that the motor can operate stably.

[0053] In the above embodiment, during the update process of multiple comparison registers in the motor control chip, the motor control chip is prohibited from executing preloading events so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform, thereby ensuring that the chip performs correct phase current sampling and motor control waveform generation, avoiding possible motor oscillation problems and effectively improving the reliability of the chip.

[0054] In some embodiments, the motor control chip also includes a counter, which is configured to count the number of updates of multiple comparison registers. The method also includes: when it is determined that the count value of the counter reaches a first preset value, allowing the motor control chip to execute a preloading event, wherein the first preset value is adapted to the number of multiple comparison registers.

[0055] Further, determining that the count value of the counter reaches a first preset value includes: in the current motor control cycle, if multiple comparison registers are updated respectively, determining that the count value of the counter reaches the first preset value.

[0056] Specifically, in the motor control strategy, between two adjacent phase current sampling and multiple comparison register update processes, the motor control chip needs to execute a preload event so that the motor control chip can obtain the updated phase current sampling trigger point and the wave comparison value to drive the motor. In an embodiment of the present invention, since the first preset value is adapted to the number of multiple comparison registers, for example, the first preset value can be equal to the number N of comparison registers in the multiple comparison registers CCR1~CCRN. In the current motor control cycle, each time a comparison register is updated, the counter automatically increases by one. When the counter reaches the first preset value, it indicates that multiple comparison registers have been updated separately. At this time, refer to Figure 4a As shown, the preload event will occur after the comparison register is updated, and the preload event will not conflict with the process of the motor control chip updating multiple comparison registers, thereby affecting the stable operation of the motor. Therefore, when it is determined that the count value of the counter reaches the first preset value, the motor control chip can be allowed to execute the preload event to enable the motor to operate normally.

[0057] In some embodiments, the method further includes: if the preloading event occurs before the updating of the plurality of comparison registers in the current motor control cycle, prohibiting the motor control chip from executing the preloading event.

[0058] Specifically, refer to Figure 4b As shown, in the current motor control cycle, if the preload event occurs before the update of multiple comparison registers, the multiple comparison registers may not store data or store the phase current sampling trigger point and the wave comparison value of the previous cycle. In this case, the motor control chip cannot reflect the phase current sampling value of the current motor control cycle when executing the preload event, so the motor control chip can be prohibited from executing the preload event in the current control cycle to avoid executing invalid preload events.

[0059] In some embodiments, when it is determined that the count value of the counter reaches the first preset value, the method further includes: generating a hardware flag bit, so as to allow the motor control chip to execute a preloading event when the hardware flag bit is detected.

[0060] Furthermore, when the motor control chip completes the execution of the preloading event, the method further includes: clearing the hardware flag bit and resetting the counter.

[0061] Specifically, the two functions of prohibiting preloading events and allowing preloading events in the above method can be achieved by generating a hardware flag bit, clearing the flag bit and clearing the counter. The specific principles are as follows:

[0062] When the multiple comparison registers are updated, the count value of the counter reaches the first preset value, and the motor control chip executing the preload event will not affect the stable operation of the motor. The motor control chip can be controlled to generate a hardware flag through a specific register or the like; when the hardware flag is detected, the motor control chip can be allowed to execute the preload event so that the chip can drive the motor to operate normally. When the preload event is executed, the multiple comparison registers updated in the current motor control cycle have all been written into the shadow register, and there is no need to execute the preload event again, so the hardware flag can be cleared and the counter can be cleared. At this time, until the hardware flag is generated in the next motor control cycle, the motor control chip cannot execute the preload event, thereby ensuring that the motor control chip cannot execute the preload event during the phase current sampling and the updating of multiple comparison registers in the next motor control cycle. Subsequently, when the multiple comparison registers in the next motor control cycle complete the phase current sampling and the updating of multiple comparison registers again, the motor control chip is controlled to generate a hardware flag again to allow the motor control chip to execute the preload event. This process is repeated so that the motor control chip will not execute preload events during the motor phase current sampling and multiple comparison register update process, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform, thereby improving the reliability of the motor control chip.

[0063] In some embodiments, in the current motor control cycle, if an event occurs that prohibits the motor control chip from executing preloading, the method further includes: driving the motor in the next motor control cycle based on the motor phase current sampling value and the motor control waveform of the current motor control cycle.

[0064] Specifically, in the current motor control cycle, the motor control chip needs to perform phase current sampling and generate motor control waveforms according to the phase current sampling point information and wave comparison value stored in the shadow register. At the same time, in the current motor control cycle, if a situation occurs that prohibits the motor control chip from executing a preloading event, the phase current sampling trigger points and wave comparison values ​​generated in the current motor control cycle cannot be written into multiple shadow registers, and multiple shadow registers are not updated. Then, in the next motor control cycle, the motor control chip will control the motor according to the unupdated phase current sampling trigger points and wave comparison values ​​stored in the shadow register. Therefore, in the next motor control cycle, the motor control chip will use the same phase current sampling value and motor control waveform as the current motor control cycle to drive the motor. The above method can ensure that the motor control chip can still drive the motor to run smoothly when a preloading event is prohibited, thereby improving the reliability of the motor control chip.

[0065] The following takes a motor control chip driving a three-phase motor using a single resistor sampling as an example to illustrate the working principle of the motor driving protection method of the embodiment of the present invention. Figure 4a As shown, the motor control chip includes the first to eighth comparison registers CCR1 to CCR8, wherein the first to sixth comparison registers CCR1 to CCR6 are used to store six wave comparison values ​​to trigger the generation of the motor control waveform. The six comparison registers correspond to the six switch tubes of the three-phase bridge arm (U phase, V phase, W phase). The comparison registers corresponding to the specific switch tubes are as follows Figure 4a As shown, it will not be expanded here; the seventh and eighth comparison registers CCR7-CCR8 are used to store two phase current sampling trigger points to trigger motor phase current sampling. At this time, the first preset value is eight. In each control cycle, the motor control chip needs to update two phase current sampling trigger points and six wave comparison values. This update process corresponds to Figure 4a The shaded part in the upper left control cycle, and the hardware circuit generates the hardware flag corresponding to the black part in the control cycle. When the multiple comparison registers of the motor control chip are updated, the motor control chip generates the hardware flag. At this time, the occurrence of the motor preload event can be divided into three situations:

[0066] In the first case, refer to Figure 4aAs shown, the preloading event of the motor control chip occurs before the update of the eight comparison registers. At this time, the count value of the counter is zero, so the motor control chip does not generate a hardware flag, and the preloading event is prohibited in the current motor control cycle to avoid executing invalid preloading events. After the comparison register of the current motor control cycle is updated, the motor control chip generates a hardware flag. At this time, in the next motor control cycle, the motor control chip drives the motor with the same phase current sampling value and motor control waveform as the current motor control cycle to make the motor run smoothly; at the same time, the preloading event can be executed normally to write the update content of the comparison register of the current motor control cycle into the shadow register. After the preloading event ends, the motor control chip clears the hardware flag and clears the counter.

[0067] In the second case, refer to Figure 4b As shown, when the preloading event occurs after the update of multiple comparison registers, the count value of the counter reaches the first preset value, which can control the motor control chip to generate a hardware control bit to allow the motor control chip to execute the preloading event. At this time, the motor control chip can execute the preloading event normally. After the preloading event ends, the motor control chip clears the hardware flag and resets the counter.

[0068] The third case, refer to Figure 4c As shown, the preloading event of the motor control chip occurs in the update process of multiple comparison registers. At this time, since the multiple comparison registers have not been updated, the count value of the counter has not reached the first preset value, and the hardware flag bit has not been generated, the motor control chip is prohibited from executing the preloading event, thereby avoiding the phase current sampling trigger point and the wave comparison value written in the shadow register from different control cycles, ensuring the stable operation of the motor, and thus improving the reliability of the motor control chip.

[0069] To summarize, according to the protection method for motor driving according to the embodiment of the present invention, during the update process of multiple comparison registers in the motor control chip, a counter is used to count the update number of multiple comparison registers, and when the counter reaches a first preset value, the motor control chip is controlled to generate a hardware flag, and the motor control chip is allowed to execute a preloading event when the hardware flag is detected, and the motor control chip is prohibited from executing the preloading event when the hardware flag is not detected; at the same time, after the motor control chip executes the preloading event, the hardware flag is cleared and the counter is reset to zero, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform, ensuring that the chip performs correct phase current sampling and motor control waveform generation, avoiding possible motor oscillation problems, and effectively improving the reliability of the chip.

[0070] Corresponding to the above embodiment, an embodiment of the present invention further provides a computer-readable storage medium, on which a protection program for motor driving is stored. When the protection program is executed by a processor, the above-mentioned protection method for motor driving is implemented.

[0071] According to the computer-readable storage medium of an embodiment of the present invention, through the aforementioned motor driving protection method, it is possible to ensure that the chip performs correct phase current sampling and motor control waveform generation, avoid possible motor oscillation problems, and effectively improve the reliability of the chip.

[0072] Corresponding to the above embodiment, the embodiment of the present invention further provides a motor control chip, referring to Figure 5 As shown, the motor control chip 200 includes: a memory 210, a processor 220, and a motor driving protection program stored in the memory 210 and executable on the processor 220. When the processor 220 executes the protection program, the aforementioned motor driving protection method is implemented.

[0073] According to the motor control chip of the embodiment of the present invention, through the aforementioned protection method during motor driving, it can ensure that the chip performs correct phase current sampling and motor control waveform generation, avoids possible motor oscillation problems, and effectively improves the reliability of the chip.

[0074] Corresponding to the above embodiment, the embodiment of the present invention further provides another motor control chip, referring to Figure 6 As shown, the chip 300 includes: a plurality of comparison registers CCR1 -CCRN and a main control unit 310 .

[0075] Among them, multiple comparison registers CCR1~CCRN are configured to trigger motor phase current sampling and motor control waveform generation in each motor control cycle; the main control unit 310 is configured to prohibit the motor control chip 300 from executing preloading events during the update process of multiple comparison registers CCR1~CCRN, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform.

[0076] According to one embodiment of the present invention, referring to Figure 7 As shown, the chip 300 also includes a counter 320, which is configured to count the number of updates of multiple comparison registers CCR1~CCRN. The main control unit 310 is also configured to allow the motor control chip 300 to execute a preloading event when it is determined that the count value of the counter 320 reaches a first preset value, wherein the first preset value is adapted to the number of the multiple comparison registers CCR1~CCRN.

[0077] According to an embodiment of the present invention, the main control unit 310 is further configured to determine that the count value of the counter 320 reaches a first preset value if the multiple comparison registers CCR1 -CCRN are updated respectively within the current motor control cycle.

[0078] According to one embodiment of the present invention, referring to Figure 7 As shown, the chip 300 also includes a flag register 330, which is configured to generate a hardware flag when the count value of the counter 320 reaches a first preset value, so that the main control unit 310 allows the motor control chip 300 to execute a preload event when the hardware flag is detected.

[0079] According to one embodiment of the present invention, referring to Figure 7 As shown, the main control unit 310 is further configured to prohibit the motor control chip 300 from executing the preloading event if the preloading event occurs before the updating of the plurality of comparison registers CCR1 ˜CCRN in the current motor control cycle.

[0080] According to an embodiment of the present invention, the main control unit 310 is further configured to control the flag register 330 to clear the hardware flag bit and control the counter 320 to be cleared when the motor control chip 300 completes the execution of the preloading event.

[0081] According to one embodiment of the present invention, the main control unit 310 is also configured to drive the motor based on the motor phase current sampling value and motor control waveform of the current motor control cycle in the next motor control cycle if an event occurs that prohibits the motor control chip 300 from executing preloading during the current motor control cycle.

[0082] According to one embodiment of the present invention, multiple comparison registers CCR1~CCRN include first to eighth comparison registers CCR1~CCR1, the first to sixth comparison registers CCR1~CCR6 among the first to eighth comparison registers CCR1~CCR8 are used to trigger the generation of motor control waveforms, and the seventh and eighth comparison registers CCR7~CCR8 among the first to eighth comparison registers CCR1~CCRN are used to trigger motor phase current sampling.

[0083] It should be noted that, for the description of the motor control chip in this application, please refer to the above-mentioned description of the protection method during motor driving, which will not be repeated here.

[0084] According to the motor control chip of the embodiment of the present invention, during the update process of multiple comparison registers in the motor control chip, a counter is used to count the update quantity of multiple comparison registers, and when the counter reaches a first preset value, a main control unit controls the flag register to generate a hardware flag, and the main control unit allows the motor control chip to execute a preloading event when the hardware flag is detected, and prohibits the motor control chip from executing the preloading event when the hardware flag is not detected; at the same time, after the motor control chip executes the preloading event, the main control unit clears the hardware flag and resets the counter to zero, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform, ensuring that the chip executes correct phase current sampling and motor control waveform generation, avoiding possible motor oscillation problems, and effectively improving the reliability of the chip.

[0085] Corresponding to the above embodiment, the embodiment of the present invention further provides a motor controller, referring to Figure 8a to Figure 8b The motor controller 1000 may include the aforementioned motor control chip 200 , or the aforementioned motor control chip 300 .

[0086] The motor controller according to the embodiment of the present invention can ensure that the motor controller performs correct phase current sampling and motor control waveform generation through one of the two motor control chips mentioned above, avoids possible motor oscillation problems, and effectively improves the reliability of the motor controller.

[0087] Corresponding to the above embodiment, the embodiment of the present invention further provides a motor, referring to Figure 9a As shown, the motor 10000 may include the aforementioned motor control chip 200; or, referring to Figure 9b As shown, the motor 10000 may include the motor chip 300 described above; or, referring to Fig.9c As shown, the motor 10000 may include the aforementioned motor controller 1000 .

[0088] According to the motor controller of the embodiment of the present invention, through one of the two motor control chips mentioned above, or the motor controller mentioned above, it is possible to achieve correct phase current sampling and motor control waveform generation, avoid possible motor oscillation problems, and effectively improve the reliability of the motor.

[0089] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0090] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0091] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0092] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0093] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0094] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A protection method for motor driving, characterized in that: Applied to a motor control chip, the motor control chip includes a plurality of comparison registers, the plurality of comparison registers are configured to trigger motor phase current sampling and motor control waveform generation in each motor control cycle, the method includes: During the updating process of the plurality of comparison registers, the motor control chip is prohibited from executing a preloading event, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform.

2. The method according to claim 1, characterized in that The motor control chip further includes a counter, wherein the counter is configured to count the update quantity of the plurality of comparison registers, and the method further includes: When it is determined that the count value of the counter reaches a first preset value, the motor control chip is allowed to execute the preloading event, wherein the first preset value is adapted to the number of the plurality of comparison registers.

3. The method according to claim 2, characterized in that Determining that the count value of the counter reaches a first preset value includes: In the current motor control cycle, if the plurality of comparison registers are respectively updated, it is determined that the count value of the counter reaches a first preset value.

4. The method according to claim 2, characterized in that: In the case where it is determined that the count value of the counter reaches a first preset value, the method further includes: A hardware flag is generated to allow the motor control chip to execute the preload event when the hardware flag is detected.

5. The method according to claim 1, characterized in that Also includes: In the current motor control cycle, if the preloading event occurs before the updating of the plurality of comparison registers, the motor control chip is prohibited from executing the preloading event.

6. The method according to claim 4, characterized in that When the motor control chip completes the execution of the preloading event, the method further includes: Clear the hardware flag bit and reset the counter.

7. The method according to any one of claims 1 to 6, characterized in that In the current motor control cycle, if an event occurs that prohibits the motor control chip from executing preloading, the method further includes: The motor is driven in a next motor control cycle based on the motor phase current sampling values ​​and the motor control waveform used in the current motor control cycle.

8. A computer-readable storage medium, characterized in that: A motor driving protection program is stored thereon, and when the motor driving protection program is executed by a processor, a motor driving protection method according to any one of claims 1 to 7 is implemented.

9. A motor control chip, characterized in that: include: A memory, a processor, and a motor driving protection program stored in the memory and executable on the processor. When the processor executes the protection program, the motor driving protection method according to any one of claims 1 to 7 is implemented.

10. A motor control chip, characterized in that: include: a plurality of compare registers configured to trigger motor phase current sampling and motor control waveform generation in each motor control cycle; The main control unit is configured to prohibit the motor control chip from executing a preload event during the updating process of the plurality of comparison registers, so that the motor phase current sampled in each motor control cycle matches the generated motor control waveform.

11. The motor control chip according to claim 10, characterized in that: It also includes a counter, which is configured to count the number of updates of the multiple comparison registers. The main control unit is also configured to allow the motor control chip to execute the preloading event when it is determined that the count value of the counter reaches a first preset value, wherein the first preset value is adapted to the number of the multiple comparison registers.

12. The motor control chip according to claim 11, characterized in that: The main control unit is further configured to determine that the count value of the counter reaches a first preset value if the multiple comparison registers have completed updating respectively within the current motor control cycle.

13. The motor control chip according to claim 11, characterized in that: It also includes a flag register, which is configured to generate a hardware flag bit when the count value of the counter reaches a first preset value, so that the main control unit allows the motor control chip to execute the preloading event when the hardware flag bit is detected.

14. The motor control chip according to claim 10, characterized in that: The main control unit is further configured to, in a current motor control cycle, if the preloading event occurs before the updating of the plurality of comparison registers, prohibit the motor control chip from executing the preloading event.

15. The motor control chip according to claim 13, characterized in that: The main control unit is further configured to, when the motor control chip completes the execution of the preloading event, control the flag register to clear the hardware flag bit and control the counter to be cleared.

16. The motor control chip according to any one of claims 10-15, characterized in that: The main control unit is further configured to, if an event occurs during a current motor control cycle that prohibits the motor control chip from executing preloading, drive the motor during a next motor control cycle based on the motor phase current sampling values ​​and motor control waveforms used during the current motor control cycle.

17. The motor control chip according to any one of claims 10-15, characterized in that: The multiple comparison registers include first to eighth comparison registers, the first to sixth comparison registers among the first to eighth comparison registers are used to trigger the generation of the motor control waveform, and the seventh and eighth comparison registers among the first to eighth comparison registers are used to trigger motor phase current sampling.

18. A motor controller, characterized in that: It comprises the motor control chip according to claim 9 or the motor control chip according to any one of claims 10-17.

19. A motor, characterized in that: Comprising a motor control chip according to any one of claims 9 to 17; or, a motor controller according to claim 18.

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