All-digital dual-mixing phase discrimination filtering system and metastable state median filtering method

Abstract

The invention provides an all-digital dual-mixing phase discrimination filtering system and a metastable state median filtering method, and relates to the technical field of signal processing. The system provided by the invention is completely realized by an FPGA (Field Programmable Gate Array), and frequency mixing processing is carried out on a tested clock signal by adopting a multi-stage frequency mixing link, so that the influence of a metastable state on a DDMTD (Digital Division Multiplexing Time Division Multiplexing) frequency mixing result is reduced; in addition, a DDMTD burr filtering module arranged in the multi-path filtering module is used for simultaneously carrying out metastable state filtering on multi-path DDMTD frequency mixing results of the same clock signal, and the edge of each path of DDMTD frequency mixing result is accurately recovered; in addition, DDMTD clock phase difference measurement is carried out on each path of DDMTD frequency mixing result edge after filtering recovery through a clock phase difference measurement module; and finally, the mean value filtering module is used for finishing mean value processing on the multi-channel DDMTD clock phase difference measurement result, so that the measurement precision of the digital double-mixing phase discrimination filtering system is further improved.

Description

Technical Field

[0001] The invention relates to the technical field of signal processing, in particular to a full digital double-mixing phase-detection filtering system and a metastable median filtering method. Background Art

[0002] Time synchronization is an important basic guarantee in the fields of telecommunications, electricity, etc. It is of great significance to study the time synchronization technology based on wired network for high-precision time transmission. The network time synchronization protocol uses the existing network data link to achieve high-precision time synchronization between master and slave devices by exchanging time information between master and slave devices.

[0003] The Precision Time Protocol (PTP) is a common two-way network time synchronization protocol defined by the Precision Clock Synchronization Protocol for Network Measurement and Control Systems standard (IEEE 1588). The IEEE 1588v1 version was released in 2002, the IEEE 1588v2 version was released in 2008, and it was upgraded to the IEEE 1588v2.1 (IEEE 1588-2019) version in 2019.

[0004] In IEEE 1588-2019, some concepts from the White Rabbit (WR) project of the European Organization for Nuclear Research (CERN) are introduced, including the use of Synchronous Ethernet (Sync-E) technology at the physical layer to achieve clock frequency transmission between master and slave devices; the use of the PTP protocol to achieve time synchronization; and the use of the Digital Dual Mixer Time Difference (DDMTD) technology to improve the timestamp synchronization accuracy to the sub-nanosecond level. Therefore, the DDMTD technology is the core key technology for improving the timing accuracy of the IEEE1588-2019 protocol.

[0005] The all-digital dual-mixing phase detection technology (DDMTD) is a high-precision clock phase difference measurement technology that can complete the high-precision phase difference measurement between two clock signals with the same period. In the all-digital dual-mixing phase detection technology, the periods of the two clock signals with the same period are amplified by using the mixing clock sampling through the D flip-flop, and then the phase difference of the two amplified clock signals is measured, and the original clock phase difference is calculated according to the formula to complete the high-precision measurement of the clock signal phase difference.

[0006] The fully digital dual-mixing phase detection technology (DDMTD) is completely implemented by FPGA. Compared with the traditional TDC phase detection, it has higher theoretical phase detection accuracy. The phase detection accuracy of the TDC chip is about tens of picoseconds, while the phase detection accuracy of the DDMTD can reach femtoseconds. At the same time, it can also save the hardware cost of the TDC chip.

[0007] However, in the actual digital circuit environment, the measured clock signal and the mixing clock signal have jitter and close frequencies, and the actual clock edge will last for a period of time and cannot complete the level conversion instantly. Therefore, the DDMTD mixing result will have a metastable phenomenon, and the edge of the mixing result will jitter. The exact position of the edge of the mixing result cannot be directly found. Therefore, the existence of metastable will greatly affect the measurement accuracy of the clock phase difference, and thus affect the timing accuracy of the IEEE 1588-2019 protocol.

[0008] Therefore, in order to ensure high-precision measurement of clock phase difference and high-precision timing of IEEE 1588-2019 protocol, it is necessary to provide a fully digital dual-mixing phase-detection filtering system and a metastable median filtering method, which can recover the accurate position of the edge from the mixing result affected by metastable state. Summary of the invention

[0009] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a fully digital dual-mixing phase-detection filtering system and a metastable median filtering method, aiming to solve the problem that when the metastable state occurs in the prior art, the measurement accuracy of the clock phase difference will be greatly affected, thereby affecting the timing accuracy of the IEEE 1588-2019 protocol.

[0010] The purpose of the present invention is achieved through the following technical solutions:

[0011] On the one hand, the present invention provides a fully digital dual-mixing phase-detection filtering system, which is deployed on an FPGA and includes a signal input port, a PLL phase-locked loop, a multi-stage mixing link, a multi-channel filtering module and a mean filtering link; wherein,

[0012] The multi-stage frequency mixing link is provided with a plurality of frequency mixing branches, each frequency mixing branch adopts the same D-type trigger group frequency mixing structure; wherein the D-type trigger group frequency mixing structure comprises a first D-type trigger, a second D-type trigger, a third D-type trigger and a fourth D-type trigger; the Q end of the first D-type trigger is electrically connected to the D end of the second D-type trigger, and the Q end of the third D-type trigger is electrically connected to the D end of the fourth D-type trigger;

[0013] The signal input port is used to receive the first clock signal clk A and the second clock signal clk B and the first clock signal clk A The second clock signal clk is input to the PLL phase-locked loop and the D terminal of the first D-type flip-flop respectively. B are respectively input to the D terminal of the third D-type flip-flop;

[0014] The PLL phase-locked loop is generated by an FPGA IP core; wherein the PLL phase-locked loop is generated according to the first clock signal clkA Generate DDMTD mixing clock signal clk ddmtd , and are respectively input to the clk terminals of the first D-type flip-flop, the second D-type flip-flop, the third D-type flip-flop and the fourth D-type flip-flop;

[0015] The multi-channel filtering module includes a plurality of DDMTD glitch filtering modules corresponding to the frequency mixing branches; wherein the input end of the DDMTD glitch filtering module is electrically connected to the Q end of the second D-type flip-flop and the fourth D-type flip-flop of the corresponding frequency mixing branch respectively;

[0016] The mean filtering link includes a number of clock phase difference measurement modules and mean filtering modules arranged corresponding to the mixing branches; wherein the input ends of the clock phase difference measurement modules are electrically connected to the output ends of the corresponding DDMTD burr filtering modules, and the output ends of the clock phase difference measurement modules are electrically connected to the mean filtering modules.

[0017] As a further solution, the DDMTD mixing clock signal clk generated by the PLL phase-locked loop ddmtd and the first clock signal clk A The signal frequency satisfies the following equation:

[0018]

[0019] Where N is a positive integer, Indicates the DDMTD mixing clock signal clk ddmtd The signal frequency, Indicates the first clock signal clk A signal frequency.

[0020] As a further solution, an FPGA dual-port RAM is also provided; wherein the FPGA dual-port RAM is used to provide data cache space, and the data cache space is used to store DDMTD mixing results, high-order result count values ​​and atomic time count values.

[0021] On the other hand, the present invention provides a metastable median filtering method, which is applied to a fully digital dual-mixing phase-detection filtering system as described in any one of the above items, wherein the DDMTD burr filtering module performs a metastable median filtering algorithm by the following steps:

[0022] Step 1: Use DDMTD to mix the clock signal clk ddmtd Perform atomic time counting; wherein, the atomic time counting accompanies the entire metastable median filter execution process, and the atomic time counting value is written into the FPGA dual-port RAM;

[0023] Step 2: Initialize the high-order result count value to 0, the low-order result count value to 0, and the write address of the FPGA dual-port RAM to 0. Determine whether the metastable process of the rising edge of the DDMTD mixing result has started. If it has started, go to step 3; otherwise, loop to execute step 2.

[0024] Step 3: Each clk ddmtd The clock cycle determines the DDMTD mixing result;

[0025] If the mixing result is high-order result data, the high-order result count value is increased by 1, and the mixing result, the updated high-order result count value and the real-time atomic time count value are written into the FPGA dual-port RAM. After the data writing is completed, step 4 is executed;

[0026] If the mixing result is low-order result data, the high-order result count value remains unchanged, and the mixing result, high-order result count value and real-time atomic time count value are written into the FPGA dual-port RAM. After the data writing is completed, execute step 4;

[0027] Step 4: Determine whether the rising edge metastable process is finished. If not, add 1 to the write address of the FPGA dual-port RAM and return to step 3; if finished, proceed to step 5;

[0028] Step 5: Read FPGA dual-port RAM data in reverse order;

[0029] If the mixing result in the read data is low-order result data, the low-order result count value is increased by 1, and the updated low-order result count value is compared with the high-order result count value in the read data;

[0030] If the count values ​​are equal, go to step 6; if they are less than, reduce the read address of the FPGA dual-port RAM by 1 and repeat step 5;

[0031] Step 6: Record the corresponding atomic time count value in the FPGA dual-port RAM and proceed to step 7;

[0032] Step 7: Continue to read the DDMTD mixing results of the FPGA dual-port RAM data in reverse order; if the first mixing result is the high-order result data, the atomic time count value recorded in step 6 is used as the rising edge position of the restored DDMTD mixing result.

[0033] As a further solution, in step 7, if the first result data that appears is low-order, continue to read the DDMTD mixing results in reverse order until the first high-order result data appears, and extract the atomic time count value corresponding to the high-order result data at this time, and perform average processing on it with the atomic time count value recorded in step 6, and the average result is used as the rising edge position of the restored DDMTD mixing result.

[0034] As a further solution, the DDMTD burr filter module recovers the first clock signal clk by the metastable median filter algorithm. A and the second clock signal clk B The rising edge position of the DDMTD mixing result, and the atomic time count value corresponding to the rising edge position of the DDMTD mixing result is sent to the clock phase difference measurement module of the corresponding mixing branch; the clock phase difference measurement module is based on the first clock signal clk A and the second clock signal clk B The DDMTD clock phase difference is calculated from the atomic time count value corresponding to the rising edge position of the DDMTD mixing result.

[0035] As a further solution, the clock phase difference measurement module uses a subtractor to convert the second clock signal clk B The atomic time count value corresponding to the rising edge position of the DDMTD mixing result minus the first clock signal clk A The atomic time count value corresponding to the rising edge position of the DDMTD mixing result is used to obtain the phase difference of the DDMTD mixing result; and the DDMTD clock phase difference is calculated by the following formula:

[0036]

[0037] Among them, ncycles represents the phase difference of the DDMTD mixing result, φ[ns] represents the DDMTD clock phase difference, and all calculations are performed in nanoseconds.

[0038] As a further solution, the mean filtering module receives the DDMTD clock phase differences calculated by each clock phase difference measurement module and performs mean processing; wherein, the mean filtering module divides each DDMTD clock phase difference into several 2-way combinations; in the 2-way combination: the DDMTD clock phase difference measurement results of the 2-way combination are added by an adder through the FPGA IP core, and the added result is shifted right by one position to complete the mean processing of the DDMTD clock phase difference of the 2-way combination; all 2-way combinations are traversed to perform mean processing, and the corresponding DDMTD clock phase difference phase detection mean result is obtained and sent to the CPU.

[0039] Compared with the related art, the all-digital dual-mixing phase-detection filtering system and metastable median filtering method provided by the present invention have the following advantages:

[0040] 1. The present invention realizes the all-digital dual-mixing phase detection technology based on FPGA, provides high-precision measurement of clock phase difference, has higher theoretical phase detection accuracy compared with traditional TDC phase detection, and can also save the hardware cost of TDC chip;

[0041] 2. The present invention performs multi-stage D flip-flop mixing on the clock under test through a multi-stage mixing link, which can reduce the influence of metastable state on the DDMTD clock phase detection result;

[0042] 3. Aiming at the edge metastable process appearing in the DDMTD mixing result, the present invention proposes a median filtering algorithm to process it, restore the accurate position of its edge, ensure the DDMTD phase detection accuracy, and improve the timing accuracy of the IEEE 1588-2019 protocol.

[0043] 4. The present invention performs multi-channel DDMTD phase detection on the clock under test simultaneously, and then performs mean filtering on the multi-channel DDMTD phase detection results, which can further improve the DDMTD clock phase detection accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of the structure of a fully digital dual-mixing phase-detection filtering system provided by the present invention;

[0045] Figure 2 This is the architecture block diagram of the all-digital dual-mixing phase-detection technology;

[0046] Figure 3 It is a schematic diagram of the DDMTD principle;

[0047] Figure 4 It is a schematic diagram of the steps of a metastable median filtering method;

[0048] Figure 5 A schematic diagram of the DDMTD filtering median algorithm provided by the present invention;

[0049] Figure 6 This is a schematic diagram of an example of the DDMTD median filtering algorithm provided by the present invention. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0051] Example 1

[0052] See also Figure 1 The present invention provides a fully digital dual-mixing phase-detection filtering system, which is deployed on an FPGA and includes a signal input port, a PLL phase-locked loop, a multi-stage mixing link, a multi-channel filtering module and a mean filtering link; wherein,

[0053] The multi-stage frequency mixing link is provided with a plurality of frequency mixing branches, each frequency mixing branch adopts the same D-type trigger group frequency mixing structure; wherein the D-type trigger group frequency mixing structure comprises a first D-type trigger, a second D-type trigger, a third D-type trigger and a fourth D-type trigger; the Q end of the first D-type trigger is electrically connected to the D end of the second D-type trigger, and the Q end of the third D-type trigger is electrically connected to the D end of the fourth D-type trigger;

[0054] The signal input port is used to receive the first clock signal clk A and the second clock signal clk B and the first clock signal clk A The second clock signal clk is input to the PLL phase-locked loop and the D terminal of the first D-type flip-flop respectively. B are respectively input to the D terminal of the third D-type flip-flop;

[0055] The PLL phase-locked loop is generated by an FPGA IP core; wherein the PLL phase-locked loop is generated according to the first clock signal clk A Generate DDMTD mixing clock signal clk ddmtd , and are respectively input to the clk terminals of the first D-type flip-flop, the second D-type flip-flop, the third D-type flip-flop and the fourth D-type flip-flop;

[0056] The multi-channel filtering module includes a plurality of DDMTD glitch filtering modules corresponding to the frequency mixing branches; wherein the input end of the DDMTD glitch filtering module is electrically connected to the Q end of the second D-type flip-flop and the fourth D-type flip-flop of the corresponding frequency mixing branch respectively;

[0057] The mean filtering link includes a number of clock phase difference measurement modules and mean filtering modules arranged corresponding to the mixing branches; wherein the input ends of the clock phase difference measurement modules are electrically connected to the output ends of the corresponding DDMTD burr filtering modules, and the output ends of the clock phase difference measurement modules are electrically connected to the mean filtering modules.

[0058] It should be noted that the full digital dual-mixing phase detection technology architecture is as follows: Figure 2 As shown, the input signal under test (clk A and clk B ) is the clock square wave signal, clk A and clk B The frequency is close, DDMTD mixing clock (clk ddmtd ) is determined by the input clock (clk A ) is generated by the PLL phase-locked loop, the DDMTD mixing clock signal clk ddmtdThe frequency is slightly different from the input clock frequency. The mixer uses a simple D-type flip-flop and the mixer clock uses the DDMTD mixer clock (clk ddmtd ), using DDMTD technology to measure clock clk A and clk B The phase difference between them.

[0059] The principle of DDMTD can be explained in a more intuitive way, such as Figure 3 (a) shows a vernier caliper with two scales, a main scale in millimeters and a small vernier scale with units slightly smaller than the main scale. For a typical caliper, the vernier caliper is divided into 10 intervals. If the length of the object being measured has a fractional part, one scale bar on the vernier caliper will align with one scale bar on the main scale to complete a higher precision measurement. In DDMTD, the main scale is the input clock under test, where each interval represents one cycle, and the vernier scale is the DDMTD mixing clock (clk ddmtd ), when the main scale is aligned with the vernier scale, it means that the rising edge of the DDMTD mixing clock is aligned with the rising edge of the measured clock, and the measurement of the measured clock phase in the DDMTD mixing clock domain is completed.

[0060] like Figure 3 As shown in (b), input A is clk A , input B is clk B , offset clock is clk ddmtd , outputA is clk A After the output of the D flip-flop, output B is clk B After the output of the D flip-flop, when the DDMTD mixing clock (clk ddmtd ) An example of DDMTD clock phase detection when parameter N = 8. The DDMTD mixer output phase difference is N+1 times the measured clock input phase difference (φ). The measured clock input phase difference (φ) and the DDMTD mixer clock frequency The general relationship can be expressed as formula 1:

[0061]

[0062] Figure 3 (b) shows an ideal situation. In the actual circuit, both the measured clock and the DDMTD mixing clock have jitter, and the actual clock edge will last for a period of time and cannot complete the level conversion instantly. Therefore, the DDMTD mixing will encounter metastable state, and the edge of the DDMTD mixing result will be metastable.

[0063] To this end, the all-digital dual-mixing phase-detection filtering system proposed in this embodiment is completely implemented by FPGA, and a multi-stage mixing link is used to mix the clock signal under test ( Figure 1 Only the case of a two-stage mixing link is shown, but in actual use, the corresponding number of stages can be set to expand according to needs), thereby reducing the impact of metastable states on DDMTD mixing results; the DDMTD glitch filtering module set by the multi-channel filtering module performs metastable filtering on multiple channels of DDMTD mixing results at the same time, and accurately restores the edge of the DDMTD mixing result; the clock phase difference measurement module completes the phase difference measurement of the edge of the DDMTD mixing result after filtering and recovery, and calculates the DDMTD clock phase difference according to formula (1); the mean filtering module completes the mean processing of the DDMTD clock phase difference on multiple channels at the same time, further improving the measurement accuracy of the DDMTD clock phase difference, and finally sends the DDMTD clock phase difference measurement mean result to the CPU.

[0064] Example 2

[0065] See also Figure 4 The present invention provides a metastable median filtering method, which is applied to a fully digital dual-mixing phase-detection filtering system as described in any one of the above items, wherein the DDMTD burr filtering module performs a metastable median filtering algorithm by the following steps:

[0066] Step 1: Use DDMTD to mix the clock signal clk ddmtd Perform atomic time counting; wherein, the atomic time counting accompanies the entire metastable median filter execution process, and the atomic time counting value is written into the FPGA dual-port RAM;

[0067] Step 2: Initialize the high-order result count value to 0, the low-order result count value to 0, and the write address of the FPGA dual-port RAM to 0. Determine whether the metastable process of the rising edge of the DDMTD mixing result has started. If it has started, go to step 3; otherwise, loop to execute step 2.

[0068] Step 3: Each clk ddmtd The clock cycle determines the DDMTD mixing result;

[0069] If the mixing result is high-order result data, the high-order result count value is increased by 1, and the mixing result, the updated high-order result count value and the real-time atomic time count value are written into the FPGA dual-port RAM. After the data writing is completed, step 4 is executed;

[0070] If the mixing result is low-order result data, the high-order result count value remains unchanged, and the mixing result, high-order result count value and real-time atomic time count value are written into the FPGA dual-port RAM. After the data writing is completed, execute step 4;

[0071] Step 4: Determine whether the rising edge metastable process is finished. If not, add 1 to the write address of the FPGA dual-port RAM and return to step 3; if finished, proceed to step 5;

[0072] Step 5: Read FPGA dual-port RAM data in reverse order;

[0073] If the mixing result in the read data is low-order result data, the low-order result count value is increased by 1, and the updated low-order result count value is compared with the high-order result count value in the read data;

[0074] If the count values ​​are equal, go to step 6; if they are less than, reduce the read address of the FPGA dual-port RAM by 1 and repeat step 5;

[0075] Step 6: Record the corresponding atomic time count value in the FPGA dual-port RAM and proceed to step 7;

[0076] Step 7: Continue to read the DDMTD mixing results of the FPGA dual-port RAM data in reverse order; if the first mixing result is the high-order result data, use the atomic time count value recorded in step 6 as the recovered DDMTD mixing result rising edge position; if the first result data that appears is the low-order result data, continue to read the DDMTD mixing results in reverse order until the first high-order result data appears, and extract the atomic time count value corresponding to the high-order result data at this time, and perform average processing with the atomic time count value recorded in step 6, and the average result is used as the recovered DDMTD mixing result rising edge position.

[0077] It should be noted that the metastable median filtering algorithm is used in the DDMTD glitch filtering module. It mainly restores the exact position of the edge of the DDMTD mixing result based on the distribution of "0" (low-order result data) and "1" (high-order result data) in the metastable process of the DDMTD mixing result. The core idea is that the number of "1" distributions before the restored DDMTD mixing result edge is equal to the number of "0" distributions after it.

[0078] The median filter algorithm works as follows Figure 5 As shown, start is the time when the metastable process starts, stop is the time when the metastable process ends, and during the period of time when the metastable state lasts, time t T The number of "1" distributions before it is equal to the number of "0" distributions after it, so time t T It is the edge position of the DDMTD mixing result restored by the filtering algorithm.

[0079] like Figure 6As shown, in a specific embodiment, starting from the start position, the DDMTD mixing result, the '1' calculation value in the metastable process and the atomic time count value are written into the FPGA dual-port ram until the stop position ends; then the DDMTD mixing result in the FPGA dual-port ram data is read in reverse order, and the data with the mixing result of "0" is counted until the count value is equal to the count value of the DDMTD mixing result of "1" in the read data, and at t T When the count values ​​are found to be equal, the corresponding atomic time count value in the data currently read from the FPGA dual-port RAM is recorded, and the next DDMTD mixing result is "1" in reverse order. Therefore, the rising edge position of the DDMTD mixing result restored by the algorithm is t T .

[0080] The DDMTD glitch filter module takes the first clock clk A and clock clk B After the rising edge position of the DDMTD mixing result is restored, the atomic time count value corresponding to the recovered rising edge position will be sent to the clock phase difference measurement module. The clock phase difference measurement module will calculate the phase difference of the DDMTD mixing result based on the atomic time count value of the rising edge position of the two measured clocks after mixing. The specific use of clock clk B The atomic time count value corresponding to the rising edge position restored from the mixing result minus the clock clk A The atomic time count value corresponding to the rising edge position recovered from the mixing result is implemented in FPGA using a subtractor (FPGA IP core). The phase difference result is represented by a signed number; the sign bit is "0" indicating that the clock clk A Phase and clock clk B Phase comparison is relative to the previous phase. The sign bit is "1" which means that the clock clk A Phase and clock clk B The phase comparison is relatively delayed.

[0081] After the phase difference of the DDMTD mixing result is obtained, the DDMTD clock phase difference is calculated according to formula (1), and finally the calculated DDMTD clock phase difference is sent to the mean filter module; the mean filter module performs mean processing on multiple groups of DDMTD clock phase difference measurement results. The specific FPGA implementation uses an adder (FPGA IP core) to add two groups of DDMTD clock phase differences, and then right-shifts the added result by one bit to complete the mean processing of the DDMTD clock phase difference measurement results. The mean processing can further improve the DDMTD clock phase difference measurement accuracy. Finally, the DDMTD clock phase difference phase detection mean result is sent to the CPU.

[0082] The above embodiments only express preferred implementation modes, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present invention. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention.

Claims

1. A fully digital dual-mixing phase-detection filtering system, deployed on FPGA, characterized in that: It includes a signal input port, a PLL phase-locked loop, a multi-stage mixing link, a multi-channel filtering module and a mean filtering link; wherein, The multi-stage frequency mixing link is provided with a plurality of frequency mixing branches, each frequency mixing branch adopts the same D-type trigger group frequency mixing structure; wherein the D-type trigger group frequency mixing structure comprises a first D-type trigger, a second D-type trigger, a third D-type trigger and a fourth D-type trigger; the Q end of the first D-type trigger is electrically connected to the D end of the second D-type trigger, and the Q end of the third D-type trigger is electrically connected to the D end of the fourth D-type trigger; The signal input port is used to receive the first clock signal clk A and the second clock signal clk B and the first clock signal clk A The second clock signal clk is input to the PLL phase-locked loop and the D terminal of the first D-type flip-flop respectively. B are respectively input to the D terminal of the third D-type flip-flop; The PLL phase-locked loop is generated by an FPGA IP core; wherein the PLL phase-locked loop is generated according to the first clock signal clk A Generate DDMTD mixing clock signal clk ddmtd , and are respectively input to the clk terminals of the first D-type flip-flop, the second D-type flip-flop, the third D-type flip-flop and the fourth D-type flip-flop; The multi-channel filtering module includes a plurality of DDMTD glitch filtering modules corresponding to the frequency mixing branches; wherein the input end of the DDMTD glitch filtering module is electrically connected to the Q end of the second D-type flip-flop and the fourth D-type flip-flop of the corresponding frequency mixing branch respectively; The mean filtering link includes a number of clock phase difference measurement modules and mean filtering modules arranged corresponding to the mixing branches; wherein the input ends of the clock phase difference measurement modules are electrically connected to the output ends of the corresponding DDMTD burr filtering modules, and the output ends of the clock phase difference measurement modules are electrically connected to the mean filtering modules.

2. A fully digital dual-mixing phase-detection filtering system according to claim 1, characterized in that: The PLL phase-locked loop generates a DDMTD mixing clock signal clk ddmtd and the first clock signal clk A The signal frequency satisfies the following equation: Where N is a positive integer, Indicates the DDMTD mixing clock signal clk ddmtd The signal frequency, Indicates the first clock signal clk A signal frequency.

3. The all-digital dual-mixing phase-detection filtering system according to claim 1, characterized in that: An FPGA dual-port RAM is also provided; wherein the FPGA dual-port RAM is used to provide a data cache space, and the data cache space is used to store DDMTD mixing results, high-order result count values ​​and atomic time count values.

4. A metastable median filtering method, applied to a fully digital double-mixing phase-detection filtering system as claimed in any one of claims 1 to 3, characterized in that: The DDMTD glitch filter module performs a metastable median filter algorithm by the following steps: Step 1: Use DDMTD to mix the clock signal clk ddmtd Perform atomic time counting; wherein, the atomic time counting accompanies the entire metastable median filter execution process, and the atomic time counting value is written into the FPGA dual-port RAM; Step 2: Initialize the high-order result count value to 0, the low-order result count value to 0, and the write address of the FPGA dual-port RAM to 0. Determine whether the metastable process of the rising edge of the DDMTD mixing result has started. If it has started, go to step 3; otherwise, loop to execute step 2. Step 3: Each clk ddmtd The clock cycle determines the DDMTD mixing result; If the mixing result is high-order result data, the high-order result count value is increased by 1, and the mixing result, the updated high-order result count value and the real-time atomic time count value are written into the FPGA dual-port RAM. After the data writing is completed, step 4 is executed; If the mixing result is low-order result data, the high-order result count value remains unchanged, and the mixing result, high-order result count value and real-time atomic time count value are written into the FPGA dual-port RAM. After the data writing is completed, execute step 4; Step 4: Determine whether the rising edge metastable process is finished. If not, add 1 to the write address of the FPGA dual-port RAM and return to step 3; if finished, proceed to step 5; Step 5: Read FPGA dual-port RAM data in reverse order; If the mixing result in the read data is low-order result data, the low-order result count value is increased by 1, and the updated low-order result count value is compared with the high-order result count value in the read data; If the count values ​​are equal, go to step 6; if they are less than, reduce the read address of the FPGA dual-port RAM by 1 and repeat step 5; Step 6: Record the corresponding atomic time count value in the FPGA dual-port RAM and proceed to step 7; Step 7: Continue to read the DDMTD mixing results of the FPGA dual-port RAM data in reverse order; if the first mixing result is the high-order result data, the atomic time count value recorded in step 6 is used as the rising edge position of the restored DDMTD mixing result.

5. A metastable median filtering method according to claim 4, characterized in that: In step 7, if the first result data that appears is the low-order data, continue to read the DDMTD mixing results in reverse order until the first high-order result data appears, and extract the atomic time count value corresponding to the high-order result data at this time, and perform average processing on it with the atomic time count value recorded in step 6. The average result is used as the rising edge position of the restored DDMTD mixing result.

6. A metastable median filtering method according to claim 5, characterized in that: The DDMTD burr filtering module recovers the first clock signal clk through the metastable median filtering algorithm A and the second clock signal clk B The rising edge position of the DDMTD mixing result is determined, and the atomic time count value corresponding to the rising edge position of the DDMTD mixing result is sent to the clock phase difference measurement module of the corresponding mixing branch; the clock phase difference measurement module is based on the first clock signal clk A and the second clock signal clk B The DDMTD clock phase difference is calculated from the atomic time count value corresponding to the rising edge position of the DDMTD mixing result.

7. A metastable median filtering method according to claim 6, characterized in that: The clock phase difference measurement module uses a subtractor to convert the second clock signal clk B The atomic time count value corresponding to the rising edge position of the DDMTD mixing result minus the first clock signal clk A The atomic time count value corresponding to the rising edge position of the DDMTD mixing result is used to obtain the phase difference of the DDMTD mixing result; and the DDMTD clock phase difference is calculated by the following formula: Among them, ncycles represents the phase difference of the DDMTD mixing result, φ[ns] represents the DDMTD clock phase difference, and all calculations are performed in nanoseconds.

8. A metastable median filtering method according to claim 6, characterized in that: The mean filtering module receives the DDMTD clock phase differences calculated by each clock phase difference measurement module and performs mean processing; wherein, the mean filtering module divides each DDMTD clock phase difference into a number of 2-way combinations; in the 2-way combination: the DDMTD clock phase difference measurement results of the 2-way combination are added by an adder through the FPGA IP core, and the result after addition is shifted right by one position to complete the mean processing of the DDMTD clock phase difference of the 2-way combination; all 2-way combinations are traversed to perform mean processing, and the corresponding DDMTD clock phase difference phase detection mean result is obtained and sent to the CPU.

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