A Constant Transconductance Circuit of a DDA Instrumentation Amplifier and a DDA Instrumentation Amplifier

Abstract

The present invention discloses a constant transconductance circuit for a DDA instrumentation amplifier and a DDA instrumentation amplifier. The constant transconductance circuit includes a BJT input pair transistor, which is used to convert a pair of differential input voltages into a pair of differential output currents, and generate a pair of emitter voltages and a pair of collector voltages; a source degeneration circuit and a transconductance replication circuit. When a pair of differential input voltages change, the transconductance replication circuit generates a transconductance replication current according to a pair of collector voltages, so as to introduce the current change generated by the BJT input pair transistor with the change of a pair of differential input voltages into the source degeneration circuit, thereby ensuring that the ratio between a pair of differential output currents and a pair of differential input voltages is constant. The present invention adopts BJT devices, which have lower noise and offset compared with traditional CMOS transconductance circuits. By using the source degeneration and transconductance replication technologies of the input pair transistor, it is possible to maintain a constant transconductance within a wider input voltage range, ensuring high linearity within a wide input range.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and particularly to a constant transconductance circuit of a DDA instrumentation amplifier and a DDA instrumentation amplifier. Background Art

[0002] A DDA (Differential Difference Amplifier) instrumentation amplifier has characteristics such as low power consumption, low noise, high input impedance, and high common-mode rejection ratio. It can amplify the weak electrical signals generated by sensors without distortion for subsequent signal acquisition, so it has been widely used in instrumentation detection equipment.

[0003] Existing DDA instrumentation amplifiers mostly use a CMOS transconductance circuit to convert differential voltage signals into differential current signals to achieve the function of signal amplification. However, the inherent characteristics of CMOS devices determine that the CMOS transconductance circuit has relatively large noise and offset. In addition, the CMOS transconductance circuit can maintain a constant transconductance when the input signal is small, but as the input signal increases, the transconductance will degenerate. Therefore, input signals beyond the range will reduce the linearity of the CMOS transconductance circuit. Moreover, the source terminal of the CMOS device in the CMOS transconductance circuit is directly connected to the power supply, which makes it easy for power supply noise to be coupled into the CMOS transconductance circuit, thereby weakening the ability of the CMOS transconductance circuit to resist power supply and ground interference. Summary of the Invention

[0004] The present invention provides a constant transconductance circuit of a DDA instrumentation amplifier and a DDA instrumentation amplifier to solve at least one of the above technical problems.

[0005] The technical solution of the present invention to solve the above technical problems is as follows: A constant transconductance circuit of a DDA instrumentation amplifier includes:

[0006] A differential input terminal group for accessing a pair of differential input voltages;

[0007] A BJT input pair transistor, including a base group, a collector group, and an emitter group; the base group is connected to the differential input terminal group in one-to-one correspondence, and the BJT input pair transistor is used to convert the pair of differential input voltages into a pair of differential output currents and output them at the collector group, generate a pair of emitter voltages at the emitter group, and generate a pair of collector voltages at the collector group;

[0008] A source degeneration circuit and a transconductance replication circuit, wherein the source degeneration circuit is connected to the emitter group of the BJT input pair transistor; the transconductance replication circuit is connected to the collector group of the BJT input pair transistor and the source degeneration circuit;

[0009] When the pair of differential input voltages change, the transconductance replication circuit generates a transconductance replication current according to the pair of collector voltages, so as to introduce the current change generated by the BJT input pair transistors with the change of the pair of differential input voltages into the source degeneration circuit, thereby making the ratio of the pair of differential output currents to the pair of differential input voltages constant.

[0010] On the basis of the above technical solution, the present invention can be further improved as follows.

[0011] Further, it further includes a power supply terminal; the differential input terminal group includes a first differential input terminal and a second differential input terminal; the BJT input pair transistors include a first triode and a second triode; the base of the first triode is connected to the first differential input terminal, the collector is connected to the power supply terminal, and the emitter is connected to the source degeneration circuit; the base of the second triode is connected to the second differential input terminal, the collector is connected to the power supply terminal, and the emitter is connected to the source degeneration circuit;

[0012] The pair of differential input voltages are converted into the pair of differential output currents through the first triode and the second triode, and are output corresponding to the collectors of the first triode and the second triode one by one.

[0013] Further, the source degeneration circuit includes:

[0014] A first source degeneration resistor, one end of which is connected to the emitter of the first triode and the other end is grounded;

[0015] A second source degeneration resistor, one end of which is connected to the emitter of the second triode and the other end is grounded.

[0016] Further, the transconductance replication circuit includes:

[0017] A first MOS transistor, the gate of the first MOS transistor is connected to the collector of the first triode, the source is connected to the power supply terminal, and the drain is connected to one end of the first source degeneration resistor, and is used to generate a first transconductance current according to the collector voltage of the first triode, so as to introduce the current change generated by the first triode with the change of a differential input voltage into the first source degeneration resistor;

[0018] A second MOS transistor, the gate of the second MOS transistor is connected to the collector of the second triode, the source is connected to the power supply terminal, and the drain is connected to one end of the second source degeneration resistor, and is used to generate a second transconductance current according to the collector voltage of the second triode, so as to introduce the current change generated by the second triode with the change of the other differential input voltage into the second source degeneration resistor.

[0019] Further, it also includes a first differential current output terminal and a second differential current output terminal; the transconductance replication circuit further includes:

[0020] A third MOS transistor, the gate of the third MOS transistor is connected to the gate of the first MOS transistor, the source is connected to the power supply terminal, and the drain is connected to the first differential current output terminal;

[0021] A fourth MOS transistor, the gate of the fourth MOS transistor is connected to the gate of the second MOS transistor, the source is connected to the power supply terminal, and the drain is connected to the second differential current output terminal.

[0022] Further, it also includes a power supply isolation control circuit, which is connected to the power supply terminal, the source of the first MOS transistor, the source of the second MOS transistor, the source of the third MOS transistor, the source of the fourth MOS transistor and the collector group of the BJT input pair transistor, and is used to isolate the direct connection of the source of the first MOS transistor, the source of the second MOS transistor, the source of the third MOS transistor and the source of the fourth MOS transistor to the power supply terminal.

[0023] Further, the power supply isolation control circuit includes:

[0024] A common-mode detection circuit, connected to the collector group of the BJT input pair transistor, and is used to generate a common-mode voltage signal according to a pair of collector voltages of the BJT input pair transistor;

[0025] A comparator, the non-inverting input terminal is connected to a fixed reference voltage signal, and the inverting input terminal is connected to the common-mode detection circuit, and is used to compare the common-mode voltage signal with the fixed reference voltage signal to generate a comparison result;

[0026] A current source, connected to the output terminal of the comparator, the power supply terminal, and the source of the first MOS transistor, the source of the second MOS transistor, the source of the third MOS transistor and the source of the fourth MOS transistor, and is used to adjust the voltages of the source of the first MOS transistor, the source of the second MOS transistor, the source of the third MOS transistor and the source of the fourth MOS transistor according to the comparison result.

[0027] Further, it also includes a first bias current source and a second bias current source; the first bias current source is connected between the power supply terminal and the collector of the first triode, and is used to provide a constant bias current for the first triode; the second bias current source is connected between the power supply terminal and the collector of the second triode, and is used to provide a constant bias current for the second triode.

[0028] Further, it further includes a current limiting source, one end of which is connected between the first source degeneration resistor and the second source degeneration resistor, and the other end is grounded, for providing a constant limiting current.

[0029] The beneficial effects of the present invention are as follows: The constant transconductance circuit of a DDA instrumentation amplifier of the present invention uses BJT devices as input pair transistors. The noise and offset of BJT devices are lower than those of CMOS devices. Therefore, compared with the traditional CMOS transconductance circuit, the constant transconductance circuit of the present invention has lower noise and offset. At the same time, the present invention uses a source degeneration circuit and a transconductance replication circuit in cooperation with the input pair transistors. When a pair of differential input voltages change, the transconductance replication circuit generates a transconductance replication current according to a pair of collector voltages, so as to introduce the current change generated by the BJT input pair transistors with the change of a pair of differential input voltages into the source degeneration circuit, and further make the ratio relationship between a pair of differential output currents and a pair of differential input voltages constant. By utilizing the source degeneration and transconductance replication technologies of BJT input pair transistors, the present invention can achieve maintaining a constant transconductance in a wider input voltage range, ensuring high linearity in a wide input range.

[0030] Based on the above constant transconductance circuit of a DDA instrumentation amplifier, the present invention further provides a DDA instrumentation amplifier.

[0031] A DDA instrumentation amplifier includes:

[0032] Differential voltage output terminals, for outputting differential voltage amplified signals;

[0033] A transconductance closed-loop circuit, which includes a resistance ratio feedback circuit, a transconductance amplification circuit, and a current-voltage conversion circuit;

[0034] Wherein, the resistance ratio feedback circuit is connected to the differential voltage output terminals, for sampling the differential voltage amplified signals to generate differential sampling voltages;

[0035] The transconductance amplification circuit, connected to the resistance ratio feedback circuit, for amplifying the differential sampling voltages and converting them into differential sampling currents;

[0036] At least one constant transconductance circuit as described above, at least one of the constant transconductance circuits accesses at least a pair of differential input voltages and converts the at least a pair of differential input voltages into at least a pair of differential output currents;

[0037] An addition circuit, connected to the transconductance amplification circuit and at least one of the constant transconductance circuits, for performing an addition operation on the differential sampling currents and the at least a pair of differential output currents to generate differential total currents;

[0038] The current-voltage conversion circuit is connected to the addition circuit and the differential voltage output terminal, and is configured to perform voltage conversion on the differential total current to generate the differential voltage amplification signal.

[0039] The beneficial effects of the present invention are as follows: A DDA instrumentation amplifier of the present invention uses the above-mentioned constant transconductance circuit for voltage-current conversion. Therefore, the DDA instrumentation amplifier of the present invention also has lower noise and offset, and can maintain high linearity in a relatively wide input voltage range. In addition, the DDA instrumentation amplifier of the present invention uses multi-transconductance multiplexing, which can realize multi-input applications, and the number of constant transconductance circuits can be flexibly set according to the number of actual input signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a structural block diagram of a constant transconductance circuit of a DDA instrumentation amplifier according to the present invention;

[0041] Figure 2 is Figure 1 the circuit schematic diagram of

[0042] Figure 3 is a structural schematic diagram of a constant transconductance circuit of a DDA instrumentation amplifier according to the present invention;

[0043] Figure 4 is Figure 3 the circuit schematic diagram of

[0044] Figure 5 is a structural block diagram of a DDA instrumentation amplifier according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] The principles and features of the present invention will be described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0046] As Figure 1 shown, a constant transconductance circuit 100 of a DDA instrumentation amplifier includes:

[0047] A differential input terminal group 1, configured to access a pair of differential input voltages VIP / VIN;

[0048] A BJT input pair transistor 2, including a base group B1 / B2, a collector group C1 / C2, and an emitter group E1 / E2; the base group B1 / B2 is connected to the differential input terminal group 1 in a one-to-one correspondence, and the BJT input pair transistor 2 is configured to convert the pair of differential input voltages VIP / VIN into a pair of differential output currents IOP / ION and output them at the collector group C1 / C2, and generate a pair of emitter voltages VE1 / VE2 at the emitter group E1 / E2, and generate a pair of collector voltages VC1 / VC2 at the collector group C1 / C2;

[0049] A source degeneration circuit 3 and a transconductance replication circuit 4, wherein the source degeneration circuit 3 is connected to the emitter groups E1 / E2 of the BJT input pair transistors 2; the transconductance replication circuit 4 is connected to the collector groups C1 / C2 of the BJT input pair transistors 2 and the source degeneration circuit 3;

[0050] When the pair of differential input voltages VIP / VIN changes, the transconductance replication circuit 4 generates a transconductance replication current according to the pair of collector voltages VC1 / VC2, so as to introduce the current change generated by the BJT input pair transistors 2 with the change of the pair of differential input voltages VIP / VIN into the source degeneration circuit 3, and further make the ratio of the pair of differential output currents IOP / ION to the pair of differential input voltages VIP / VIN constant.

[0051] The constant transconductance circuit 100 of a DDA instrumentation amplifier according to the present invention uses BJT devices as input pair transistors. The noise and offset of BJT devices are lower than those of CMOS devices. Therefore, the constant transconductance circuit 100 of the present invention has lower noise and offset compared with traditional CMOS transconductance circuits. At the same time, the present invention uses a source degeneration circuit 3 and a transconductance replication circuit 4 in cooperation with the input pair transistors. When a pair of differential input voltages VIP / VIN changes, the transconductance replication circuit 4 generates a transconductance replication current according to a pair of collector voltages VC1 / VC2, so as to introduce the current change generated by the BJT input pair transistors 2 with the change of the pair of differential input voltages VIP / VIN into the source degeneration circuit 3, and further make the proportional relationship between the pair of differential output currents IOP / ION and the pair of differential input voltages VIP / VIN constant. By utilizing the source degeneration and transconductance replication technologies of the BJT input pair transistors 2, the present invention can achieve a constant transconductance in a wider input voltage range, ensuring high linearity in a wide input range.

[0052] In some embodiments, as Figure 2 shown, the constant transconductance circuit 100 of the present invention further includes a power supply terminal 5; the differential input terminal group 1 includes a first differential input terminal 11 and a second differential input terminal 12; the BJT input pair transistors 2 include a first triode NPN1 and a second triode NPN2; the base B1 of the first triode NPN1 is connected to the first differential input terminal 11, the collector C1 is connected to the power supply terminal 5, and the emitter E1 is connected to the source degeneration circuit 3; the base B2 of the second triode NPN2 is connected to the second differential input terminal 12, the collector C2 is connected to the power supply terminal 5, and the emitter E2 is connected to the source degeneration circuit 3;

[0053] The pair of differential input voltages VIP / VIN are converted into the pair of differential output currents IOP / ION by the first NPN transistor NPN1 and the second NPN transistor NPN2, and are output corresponding to the collector C1 of the first NPN transistor NPN1 and the collector C2 of the second NPN transistor NPN2 one by one.

[0054] Specifically, both the first NPN transistor NPN1 and the second NPN transistor NPN2 are BJT devices. Compared with CMOS devices, BJT devices have significant advantages in terms of noise and offset, and these advantages stem from the characteristics of the devices themselves. Therefore, the BJT input pair transistor 2 composed of the first NPN transistor NPN1 and the second NPN transistor NPN2 is adopted in the present invention. Compared with the traditional CMOS architecture, not only the noise level is reduced, but also the matching accuracy between devices is improved. Such an improvement enables the present invention to provide a clearer and more stable output during signal amplification, thus surpassing the conventional CMOS solutions in terms of performance.

[0055] In some embodiments, as Figure 2 shown, the source degeneration circuit 3 includes:

[0056] A first source degeneration resistor R1, one end of which is connected to the emitter E1 of the first NPN transistor NPN1, and the other end is grounded;

[0057] A second source degeneration resistor R2, one end of which is connected to the emitter E2 of the second NPN transistor NPN2, and the other end is grounded.

[0058] Specifically, in the transconductance of the CMOS architecture, the source degeneration resistor effectively limits the change of the drain-source voltage by introducing a resistor between the source and the ground. When the drain-source voltage changes, the source degeneration resistor will absorb a part of the voltage change, reducing the nonlinear distortion of the input transistor transconductance.

[0059] In this application, the input pair transistor is a BJT device, and the emitter of the BJT device is equivalent to the source of the CMOS transistor. Therefore, the first source degeneration resistor R1 and the second source degeneration resistor R2 introduced between the emitter and the ground in the present invention can also limit the change of the voltage between the collector and the emitter. When the voltage between the collector and the emitter changes, the source degeneration resistor will absorb a part of the voltage change, thereby reducing the nonlinear distortion of the input transistor transconductance, and further improving the transconductance of the BJT input pair transistor 2.

[0060] In some embodiments, as Figure 2 shown, the transconductance replication circuit 4 includes:

[0061] The first MOS transistor M1, the gate of the first MOS transistor M1 is connected to the collector C1 of the first NPN transistor NPN1, the source is connected to the power supply terminal 5, and the drain is connected to one end of the first source degeneration resistor R1, and is used to generate a first transconductance current according to the collector voltage VC1 of the first NPN transistor NPN1, so as to introduce the current change generated by the first NPN transistor NPN1 with the change of a differential input voltage VIP into the first source degeneration resistor R1;

[0062] The second MOS transistor M2, the gate of the second MOS transistor M2 is connected to the collector C2 of the second NPN transistor NPN2, the source is connected to the power supply terminal 5, and the drain is connected to one end of the second source degeneration resistor R2, and is used to generate a second transconductance current according to the collector voltage VC2 of the second NPN transistor NPN2, so as to introduce the current change generated by the second NPN transistor NPN2 with the change of another differential input voltage VIN into the second source degeneration resistor R2.

[0063] Specifically, when a pair of differential input voltages VIP / VIN change, that is, the base voltages of the first NPN transistor NPN1 and the second NPN transistor NPN2 change, then the collector voltages of the first NPN transistor NPN1 and the second NPN transistor NPN2 change, and further the gate voltages of the first MOS transistor M1 and the second MOS transistor M2 change, so that the drain currents of the first MOS transistor M1 and the second MOS transistor M2 change. The drain currents of the first MOS transistor M1 and the second MOS transistor M2 are the transconductance copy currents.

[0064] Since the BJT input pair transistor 2 is used to convert a pair of differential input voltages VIP / VIN into a pair of differential output currents IOP / ION and output at the collector groups C1 / C2; therefore, the change of the drain currents of the first MOS transistor M1 and the second MOS transistor M2 reflects the change of a pair of differential output currents IOP / ION.

[0065] The present invention adopts the source degeneration circuit 3 and the transconductance copy circuit 4 to cooperate with the input pair transistor. When a pair of differential input voltages VIP / VIN change, the transconductance copy circuit 4 generates a transconductance copy current according to a pair of collector voltages VC1 / VC2, so as to introduce the current change generated by the BJT input pair transistor 2 with the change of a pair of differential input voltages VIP / VIN into the source degeneration circuit 3, and further make the ratio of a pair of differential output currents IOP / ION to a pair of differential input voltages VIP / VIN constant.

[0066] In some embodiments, as Figure 2 shown, the constant transconductance circuit 100 of the present invention further includes a differential current output terminal group 6, and the differential current output terminal group 6 includes a first differential current output terminal 61 and a second differential current output terminal 62; the transconductance copy circuit 4 further includes:

[0067] The third MOS transistor M3, the gate of the third MOS transistor M3 is connected to the gate of the first MOS transistor M1, the source is connected to the power supply terminal 5, and the drain is connected to the first differential current output terminal 61;

[0068] The fourth MOS transistor M4, the gate of the fourth MOS transistor M4 is connected to the gate of the second MOS transistor M2, the source is connected to the power supply terminal 5, and the drain is connected to the second differential current output terminal 62.

[0069] Specifically, the third MOS transistor M3 and the first MOS transistor M1 form a current mirror for replicating the drain current of the first MOS transistor M1; at the same time, the fourth MOS transistor M4 and the second MOS transistor M2 form a current mirror for replicating the drain current of the second MOS transistor M2; therefore, the currents output from the first differential current output terminal 61 and the second differential current output terminal 62 connected to the drains of the third MOS transistor M3 and the fourth MOS transistor M4 represent a pair of differential output currents IOP / ION.

[0070] The transconductance replication circuit 4 composed of the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 has a simple structure and is easy to implement.

[0071] In some embodiments, as Figure 3 shown, the constant transconductance circuit 100 of the present invention further includes a power supply isolation control circuit 7, and the power supply isolation control circuit 7 is connected to the power supply terminal 5, the source of the first MOS transistor M1, the source of the second MOS transistor M2, the source of the third MOS transistor M3, the source of the fourth MOS transistor M4, and the collector group C1 / C2 of the BJT input pair transistor 2, for isolating the source of the first MOS transistor M1, the source of the second MOS transistor M2, the source of the third MOS transistor M3, and the source of the fourth MOS transistor M4 from being directly connected to the power supply terminal 5.

[0072] Specifically, the power supply isolation control circuit 7 is used to isolate the sources of the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 from being directly connected to the power supply terminal 5, to avoid the interference of the power supply being directly coupled to the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4, resulting in a sudden change in the output current, thereby improving the power supply rejection ratio and enhancing the anti-interference ability of the power supply and the ground.

[0073] In some embodiments, as Figure 4 shown, the power supply isolation control circuit 7 includes:

[0074] A common-mode detection circuit 71 is connected to the collector groups C1 / C2 of the BJT input pair transistors 2, and is configured to generate a common-mode voltage signal VCOM according to a pair of collector voltages VC1 / VC2 of the BJT input pair transistors 2;

[0075] A comparator A has its non-inverting input terminal connected to a fixed reference voltage signal VCM, and its inverting input terminal is connected to the common-mode detection circuit 71. The comparator A is configured to compare the common-mode voltage signal VCOM with the fixed reference voltage signal VCM to generate a comparison result;

[0076] A current source I0 is connected to the output terminal of the comparator A, the power supply terminal 5, and the source electrodes of the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4, and is configured to adjust the voltages of the source electrodes of the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 according to the comparison result.

[0077] Specifically, the common-mode detection circuit 71 is configured to detect the common-mode voltage of a pair of collector voltages VC1 / VC2 to obtain a common-mode voltage signal VCOM, that is, VCOM = (VC1 + VC2) / 2; the comparator A compares the common-mode voltage signal VCOM with the input fixed reference voltage signal VCM to obtain a comparison result. Then, according to the comparison result, the current source I0 is adjusted to change the source voltages of the first MOS transistor M1 and the second MOS transistor M2; the change in the source voltages of the first MOS transistor M1 and the second MOS transistor M2 causes a change in the drain currents of the first MOS transistor M1 and the second MOS transistor M2; the change in the drain currents of the first MOS transistor M1 and the second MOS transistor M2 causes a change in the gate voltages of the first MOS transistor M1 and the second MOS transistor M2; the change in the gate voltages of the first MOS transistor M1 and the second MOS transistor M2 is the change in a pair of collector voltages VC1 / VC2 of the BJT input pair transistors 2. For example, when the common-mode voltage signal VCOM is less than the fixed reference voltage signal VCM, the comparator A controls the current source I0 to decrease, and then a pair of collector voltages VC1 / VC2 increases.

[0078] The common-mode detection circuit 71, the comparator A, and the current source I0 form a closed-loop feedback system with a sufficiently large gain. The common-mode voltage signal VCOM = (VC1 + VC2) / 2 and the fixed reference voltage signal VCM are the inputs of the closed loop, making the final error zero, that is, VCOM = (VC1 + VC2) / 2 = VCM. The purpose of this is to make the current source I0 not affected by the power supply, thereby avoiding the direct coupling of power supply interference to the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4, resulting in an abrupt change in the output current, thereby improving the power supply rejection ratio and enhancing the anti-interference ability of the power supply and ground.

[0079] In some embodiments, as Figure 4 shown, the constant transconductance circuit 100 of the present invention further includes a first bias current source I1 and a second bias current source I2; the first bias current source I1 is connected between the power supply terminal 5 and the collector of the first triode NPN1 for providing a constant bias current to the first triode NPN1; the second bias current source I2 is connected between the power supply terminal 5 and the collector of the second triode NPN2 for providing a constant bias current to the second triode NPN2.

[0080] Specifically, the first bias current source I1 and the second bias current source I2 provide constant bias currents for the first triode NPN1 and the second triode NPN2; when a pair of differential input voltages VIP / VIN changes, the emitter voltages of the first triode NPN1 and the second triode NPN2 change, so that the voltages across the first source degeneration resistor R1 and the second source degeneration resistor R2 change, and further the currents flowing through the first source degeneration resistor R1 and the second source degeneration resistor R2 change. Since the first triode NPN1 and the second triode NPN2 are biased at a constant current, the currents flowing through the first triode NPN1 and the second triode NPN2 remain unchanged; due to the change of a pair of differential input voltages VIP / VIN and the unchanged currents flowing through the first triode NPN1 and the second triode NPN2, the gate voltages of the first MOS transistor M1 and the second MOS transistor M2 change, and further the drain currents of the first MOS transistor M1 and the second MOS transistor M2 change.

[0081] The first triode NPN1 and the second triode NPN2 are biased at a constant current, which can reduce the influence of power supply fluctuations on the circuit, ensure the stability of the circuit, and improve the anti-interference ability of the circuit.

[0082] In some embodiments, as Figure 4 shown, the constant transconductance circuit 100 of the present invention further includes a current limiting source I3, one end of which is connected between the first source degeneration resistor R1 and the second source degeneration resistor R2, and the other end is grounded for providing a constant limiting current.

[0083] Specifically, the change in a pair of differential input voltages VIP / VIN causes the change in the currents flowing through the first source degeneration resistor R1 and the second source degeneration resistor R2, as well as the change in the drain currents of the first MOS transistor M1 and the second MOS transistor M2. Since the currents flowing through the first NPN transistor NPN1 and the second NPN transistor NPN2 remain unchanged and the current source I3 is constant, the change in the drain currents of the first MOS transistor M1 and the second MOS transistor M2 is equal to the change in the currents of the first source degeneration resistor R1 and the second source degeneration resistor R2. Therefore, when a pair of differential input voltages VIP / VIN changes, the transconductance replication circuit 4 generates a transconductance replication current according to a pair of collector voltages VC1 / VC2, so as to introduce the current change generated by the BJT input pair transistor 2 with the change of a pair of differential input voltages VIP / VIN into the source degeneration circuit 3, and further make the ratio of a pair of differential output currents IOP / ION to a pair of differential input voltages VIP / VIN constant.

[0084] Based on the above constant transconductance circuit 100 of a DDA instrumentation amplifier, the present invention further provides a DDA instrumentation amplifier.

[0085] As Figure 5 shown, a DDA instrumentation amplifier includes:

[0086] A differential voltage output terminal 200 for outputting a differential voltage amplified signal VOP / VON;

[0087] A transconductance closed-loop circuit 300, the transconductance closed-loop circuit 300 includes a resistance ratio feedback circuit 301, a transconductance amplifier circuit 302 and a current-voltage conversion circuit 303;

[0088] Wherein, the resistance ratio feedback circuit 301 is connected to the differential voltage output terminal 200 for sampling the differential voltage amplified signal VOP / VON to generate a differential sampling voltage;

[0089] The transconductance amplifier circuit 302 is connected to the resistance ratio feedback circuit 301 for amplifying the differential sampling voltage and converting it into a differential sampling current;

[0090] At least one constant transconductance circuit 100 as described above, at least one of the constant transconductance circuits 100 is connected to at least a pair of differential input voltages VIP / VIN and converts the at least a pair of differential input voltages VIP / VIN into at least a pair of differential output currents IOP / ION;

[0091] An adder circuit 400 is connected to the transconductance amplifier circuit 302 and at least one of the constant transconductance circuits 100 for performing an addition operation on the differential sampling current and the at least a pair of differential output currents IOP / ION to generate a differential total current;

[0092] The current-voltage conversion circuit 303 is connected to the addition circuit 400 and the differential voltage output terminal 200, and is configured to perform voltage conversion on the differential total current to generate the differential voltage amplified signals VOP / VON.

[0093] Specifically, the transconductance amplifier circuit 302 may also adopt the constant transconductance circuit 100 of the present invention; the current-voltage conversion circuit 303 is configured to convert a current signal into a voltage signal and provide high gain; the resistor ratio feedback circuit 301 determines the closed-loop gain.

[0094] A DDA instrumentation amplifier of the present invention uses the above-mentioned constant transconductance circuit 100 for voltage-current conversion. Therefore, the DDA instrumentation amplifier of the present invention also has lower noise and offset, and can maintain high linearity in a relatively wide input voltage range; in addition, the DDA instrumentation amplifier of the present invention adopts multi-transconductance multiplexing to achieve multi-input applications, and the number of constant transconductance circuits can be flexibly set according to the number of actual input signals.

[0095] The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A constant transconductance circuit for a DDA instrumentation amplifier, characterized in that, Comprising: A differential input terminal group for accessing a pair of differential input voltages; A BJT input pair transistor, including a base group, a collector group, and an emitter group; A source degeneration circuit and a transconductance replication circuit, wherein the source degeneration circuit is connected to the emitter group of the BJT input pair transistor; It further includes a power supply terminal; the differential input terminal group includes a first differential input terminal and a second differential input terminal; the BJT input pair transistor includes a first triode and a second triode; the base of the first triode is connected to the first differential input terminal, the collector is connected to the power supply terminal, and the emitter is connected to the source degeneration circuit; the base of the second triode is connected to the second differential input terminal, the collector is connected to the power supply terminal, and the emitter is connected to the source degeneration circuit; The source degeneration circuit includes: A first source degeneration resistor, one end of which is connected to the emitter of the first triode and the other end is grounded; A second source degeneration resistor, one end of which is connected to the emitter of the second triode and the other end is grounded; It further includes a first bias current source and a second bias current source, the first bias current source is connected between the power supply terminal and the collector of the first triode, and the second bias current source is connected between the power supply terminal and the collector of the second triode; It further includes a current limiting source, one end of which is connected between the first source degeneration resistor and the second source degeneration resistor and the other end is grounded, for providing a constant limiting current; The transconductance replication circuit includes: A first MOS transistor, the gate of the first MOS transistor is connected to the collector of the first triode, the source is connected to the power supply terminal, and the drain is connected to one end of the first source degeneration resistor; A second MOS transistor, the gate of the second MOS transistor is connected to the collector of the second triode, the source is connected to the power supply terminal, and the drain is connected to one end of the second source degeneration resistor; It further includes a first differential current output terminal and a second differential current output terminal; the transconductance replication circuit further includes: A third MOS transistor, the gate of the third MOS transistor is connected to the gate of the first MOS transistor, the source is connected to the power supply terminal, and the drain is connected to the first differential current output terminal; A fourth MOS transistor, the gate of the fourth MOS transistor is connected to the gate of the second MOS transistor, the source is connected to the power supply terminal, and the drain is connected to the second differential current output terminal; It further includes a power supply isolation control circuit, and the power supply isolation control circuit includes: A common-mode detection circuit, connected to the collector group of the BJT input pair transistor, for generating a common-mode voltage signal according to a pair of collector voltages of the BJT input pair transistor; A comparator, the non-inverting input terminal accesses a fixed reference voltage signal, and the inverting input terminal is connected to the common-mode detection circuit, for comparing the common-mode voltage signal with the fixed reference voltage signal to generate a comparison result; A current source, connected to the output terminal of the comparator, the power supply terminal, and the sources of the first to fourth MOS transistors, for adjusting the voltage of the sources of the first to fourth MOS transistors according to the comparison result.

2. A DDA instrumentation amplifier, characterized in that, Comprising: A differential voltage output terminal for outputting a differential voltage amplification signal; A transconductance closed-loop circuit, the transconductance closed-loop circuit including a resistance ratio feedback circuit, a transconductance amplification circuit, and a current-voltage conversion circuit; Wherein, the resistance ratio feedback circuit is connected to the differential voltage output terminal, and is used for sampling the differential voltage amplification signal to generate a differential sampling voltage; The transconductance amplification circuit, connected to the resistance ratio feedback circuit, is used for amplifying the differential sampling voltage and converting it into a differential sampling current; At least one constant transconductance circuit as claimed in claim 1, at least one of the constant transconductance circuits accessing at least one pair of differential input voltages and converting the at least one pair of differential input voltages into at least one pair of differential output currents; An adder circuit, connected to the transconductance amplification circuit and at least one of the constant transconductance circuits, for performing an addition operation on the differential sampling current and the at least one pair of differential output currents to generate a differential total current; The current-voltage conversion circuit, connected to the adder circuit and the differential voltage output terminal, is used for performing a voltage conversion on the differential total current to generate the differential voltage amplification signal.

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