Multi-channel amplitude-phase delay control device

Abstract

The invention discloses a multi-channel amplitude-phase delay control device, and particularly relates to the field of multi-channel signal control. Comprising at least two radio frequency link units used for performing amplitude phase delay processing on an input radio frequency signal to obtain an analog signal; the input end of the synthesis link unit is connected with all the radio frequency link units, and the synthesis link unit is used for synthesizing all the analog signals to obtain a synthesis signal; the input end of the monitoring unit is connected with the synthesis link unit, and the monitoring unit is used for dividing the synthesis signal into an output signal and a coupling signal and converting the coupling signal into a digital signal; the output end of the logic processing unit is respectively connected with the radio frequency link unit, the monitoring unit and the synthesis link unit, and the logic processing unit is used for correspondingly converting the control instruction into control signals of the radio frequency link unit, the monitoring unit and the synthesis link unit; the input end of the logic processing unit is connected with the output end of the monitoring unit and used for adjusting the control signal according to the digital signal. And the control precision can be improved.

Description

Technical Field

[0001] The present application relates to the field of multi-channel signal control, and in particular to a multi-channel amplitude and phase delay control device. Background Art

[0002] In the fields of wireless communication, radar and signal processing, multi-channel amplitude, phase and delay control devices are widely used in multi-antenna array systems, beamforming and phased array radar systems. The main function of these devices is to accurately control the amplitude, phase and delay of signals from multiple channels to achieve coherent signal synthesis, beam direction control and multipath signal compensation.

[0003] The existing multi-channel amplitude and phase delay control device has reduced control accuracy because the component parameters of its analog circuit change with factors such as temperature and aging. Summary of the invention

[0004] The main purpose of the present application is to provide a multi-channel amplitude-phase delay control device, aiming to solve the problem of low control accuracy in existing control devices.

[0005] To achieve the above-mentioned purpose, the present application provides a multi-channel amplitude and phase delay control device, comprising: at least two RF link units, the RF link unit is used to perform amplitude and phase delay processing on the input RF signal to obtain an analog signal; a synthesis link unit, the input end of which is connected to all the RF link units, and is used to synthesize all the analog signals to obtain a synthesized signal; a monitoring unit, the input end of which is connected to the synthesis link unit, and is used to divide the synthesized signal into an output signal and a coupling signal, and convert the coupling signal into a digital signal; a logic processing unit, the output end of which is respectively connected to the RF link unit, the monitoring unit and the synthesis link unit, and is used to convert the control instruction into the control signal of the RF link unit, the monitoring unit and the synthesis link unit; the input end is connected to the output end of the monitoring unit, and the logic processing unit is also used to adjust the control signal according to the digital signal.

[0006] Optionally, the RF link unit includes a switch, a first attenuator, a first amplifier, a phase shifter, a second attenuator, a first delay device, a third attenuator, a fourth attenuator, a second delay device, a second amplifier, a third amplifier, a fourth amplifier, and a fifth attenuator connected in sequence.

[0007] Optionally, the monitoring unit comprises a coupler and a detector connected in sequence.

[0008] Optionally, the synthesis link unit includes a plurality of combiners, each combiner being used for synthesizing two analog signals.

[0009] Optionally, the radio frequency link unit includes at least two channels.

[0010] Optionally, the logic processing unit includes: a differential chip, used to convert control instructions into differential signals; a serial-to-parallel conversion chip, connected to the differential chip, used to convert differential signals into serial port single-ended signals; an FPGA, connected to the serial-to-parallel conversion chip, used to convert serial port single-ended signals into parallel port signals, perform logic operations, and output high and low level signals.

[0011] Compared with the prior art, the present invention has the following beneficial effects: The multi-channel amplitude and phase delay control device of the present invention is provided with at least two radio frequency link units. By superimposing the radio frequency link units, amplitude and phase delay processing can be performed on the input multi-channel radio frequency signals at the same time. At the same time, the output analog signals are synthesized by the synthesis link unit, and the synthesized signals are coupled. One path is used as the output signal, and the other path is fed back to the logic processing unit A through the monitoring unit. The control signal is adjusted to compensate for the changes in the component parameters in the radio frequency link unit due to factors such as temperature and aging, thereby improving the control accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a structural schematic diagram of a multi-channel amplitude and phase delay control device of the present application; Figure 2 for Figure 1 A schematic diagram of the structure of the radio frequency link unit; Figure 3 This is a structural schematic diagram of an embodiment of a multi-channel amplitude and phase delay control device of the present application; Figure 4 for Figure 3 Schematic diagram of the structure of the RF link unit.

[0013] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0015] The first embodiment of the present invention provides a multi-channel amplitude and phase delay control device, such as Figure 1As shown, it includes a logic processing unit A, at least two RF link units B, a synthesis link unit C, and a monitoring unit D. The RF link unit B is used to perform amplitude and phase delay processing on the input RF signal to obtain an analog signal; the input end of the synthesis link unit C is connected to all the RF link units B, and is used to synthesize all the analog signals to obtain a synthesized signal; the input end of the monitoring unit D is connected to the synthesis link unit C, and is used to divide the synthesized signal into an output signal and a coupling signal, and convert the coupling signal into a digital signal; the output end of the logic processing unit A is respectively connected to the RF link unit B, the monitoring unit D and the synthesis link unit C, and is used to convert the control instruction into the control signal of the RF link unit B and the synthesis link unit C; the input end of the logic processing unit A is connected to the output end of the monitoring unit D, and the logic processing unit A is also used to adjust the control signal according to the digital signal.

[0016] In this embodiment, at least two RF link units B are provided. By superimposing the RF link units B, amplitude and phase delay processing can be performed on the input multi-path RF signals at the same time. At the same time, the output analog signals are synthesized by the synthesis link unit C, and the synthesized signals are coupled. One path is used as the output signal, and the other path is fed back to the logic processing unit A through the monitoring unit D. The control signal is adjusted to compensate for the loss caused by the changes in the component parameters in the RF link unit B due to factors such as temperature and aging, thereby improving the control accuracy.

[0017] Furthermore, each radio frequency link unit B includes at least two channels. The synthesis link unit C includes a plurality of combiners C1, and each combiner C1 is used to synthesize two analog signals.

[0018] Specifically, Figure 2 As shown, the RF link unit B includes a switch B1, a first attenuator B2, a first amplifier B3, a phase shifter B4, a second attenuator B5, a first delay B6, a third attenuator B7, a fourth attenuator B8, a second delay B9, a second amplifier B10, a third amplifier B11, a fourth amplifier B12, and a fifth attenuator B13, which are connected in sequence.

[0019] Among them, switch B1 is used for channel switching and pulse modulation. When the RF signal includes only one channel, only one RF link unit B is kept turned on, and the switches B1 of other RF link units B are disconnected. The function of switch B1 at this time is to perform pulse modulation, which can be modulated to generate various signals.

[0020] In this embodiment, the amplitude of the RF signal is attenuated in sequence by the first attenuator B2, the second attenuator B5, the third attenuator B7, the fourth attenuator B8, and the fifth attenuator B13, so that a minimum attenuation unit of 0.5dB step can be achieved; the first amplifier B3, the second amplifier B10, the third amplifier B11, and the fourth amplifier B12 compensate for the link insertion loss introduced in the link, so that the input power of the link is equal to the output power when no attenuation operation is performed; the phase shifter B4 performs a phase shift operation on the link to achieve a minimum phase shift unit of 5.625°, and the first delay device B6 and the second delay device B9 perform a delay operation on the link to achieve a minimum delay unit of 2.5 Ps.

[0021] For example, Figure 3 As shown, the control device includes two RF link units B, namely, RF link unit 1 and RF link unit 2. Each RF link unit B includes two channels, namely, RF link unit B10 includes channel 1 and channel 2, and RF link unit 20 includes channel 3 and channel 4. Each RF link unit B can process two RF signals at the same time. Specifically, channel 1 includes: switch B1-1, first attenuator B2-1, first amplifier B3-1, phase shifter B4-1, second attenuator B5-1, first delay B6-1, third attenuator B7-1, fourth attenuator B8-1, second delay B9-1, second amplifier B10-1, third amplifier B11-1, fourth amplifier B12-1, and fifth attenuator B13-1; channel 2 includes: switch B1-2, first attenuator B2-2, first amplifier B3-2, phase shifter B4-2, second attenuator B5-2, first delay B6-2, third attenuator B7-2, fourth attenuator B8-2, second delay B9-2, second amplifier B10-2, third amplifier B11-2, fourth amplifier B12-2, fifth attenuator B13- 2; Channel 3 includes: switch B1-3, first attenuator B2-3, first amplifier B3-3, phase shifter B4-3, second attenuator B5-3, first delay B6-3, third attenuator B7-3, fourth attenuator B8-3, second delay B9-3, second amplifier B10-3, third amplifier B11-3, fourth amplifier B12-3, fifth attenuator B13-3; Channel 4 includes: switch B1-4, first attenuator B2-4, first amplifier B3-4, phase shifter B4-4, second attenuator B5-4, first delay B6-4, third attenuator B7-4, fourth attenuator B8-4, second delay B9-4, second amplifier B10-4, third amplifier B11-4, fourth amplifier B12-4, fifth attenuator B13-4. In this embodiment, as Figure 4As shown, the first attenuator B2 is a digitally controlled attenuator with a step of 0.5dB, six bits and a total of 31.5dB. The second attenuator B5 is a digitally controlled attenuator with a step of 1dB, five bits and a total of 31dB. The third attenuator B7 is a digitally controlled attenuator with a step of 16dB, one bit and a total of 16dB. The fourth attenuator B8 is a digitally controlled attenuator with a step of 16dB, one bit and a total of 16dB. The fourth attenuator B8 is a digitally controlled attenuator with a step of 20dB, one bit and a total of 20dB. The first delayer B6 is a digitally controlled delayer with a step of 25ps, six bits and a total of 1575ps. The second delayer B9 is a digitally controlled delayer with a step of 2.5ps, seven bits and a total of 317.5ps. The above-mentioned attenuator can make the numerically controlled attenuation range reach 113.5dB, and the above-mentioned delay device can make the numerically controlled delay reach 1892.5Ps.

[0022] Correspondingly, the combiner C1 includes a first combiner C11, a second combiner C12 and a third combiner C13. The first combiner C11 connects channel 1 and the output end of channel 1, the second combiner C12 connects channel 3 and the output end of channel 4, and the third combiner C13 connects the output ends of the first combiner C11 and the second combiner C12 to output the final synthesized signal.

[0023] In addition, an ultra-low voltage difference regulator can be used in advance to convert the external voltage power supply and then use it as the power supply for the RF link unit B, the synthesis link unit C and the logic processing unit A; and without affecting the working efficiency, the first amplifier B3, the second amplifier B10, the third amplifier B11, and the fourth amplifier B12 are fed in low power consumption mode. This method improves the efficiency by 10% compared with the normal operation of conventional amplifiers, thereby reducing the power consumption of the overall control device.

[0024] The logic processing unit A includes a differential chip, a serial-to-parallel conversion chip, an FPGA and a level conversion chip. The differential chip is used to convert control instructions into differential signals; the serial-to-parallel conversion chip is connected to the differential chip and is used to convert differential signals into serial port single-ended signals; the FPGA is connected to the serial-to-parallel conversion chip and is used to convert serial port single-ended signals into parallel port signals, perform logical operations, and output high and low level signals; the level conversion chip is connected to the FPGA and is used to adapt the required level to the FPGA.

[0025] The monitoring unit D includes a coupler D1 and a detector D2 connected in sequence. Specifically, the coupler D1 couples the synthesized signal into two paths, one of which is directly output as an output signal (output when the output signal meets the threshold, and not output if it does not meet the threshold), and the other is input to the detector D2, which detects the coupled signal and outputs a voltage amplitude signal to the logic processing unit A; the logic processing unit A performs differential and serial-to-parallel conversion on the voltage amplitude signal in sequence, and then performs calculations through the FPGA to adjust the control signal of the radio frequency link unit B. Specifically, the link signal amplitude value is adjusted through each attenuator to control the amplitude consistency between multiple channels; after the amplitude consistency between channels is adjusted, the delayer and phase shifter B4 adjust the corresponding phase and delay of the link; when synthesized by the synthesizer, the synthesized two signals should be approximately the same amplitude, with a phase difference of 180°; the monitoring unit D can feedback a relatively accurate analog signal (digital signal) to the FPGA for logic processing, and at this time, the FPGA adjusts the change amount of the attenuator, delayer, and phase shifter B4 in the radio frequency link unit B again according to the feedback analog signal (digital signal). When the value of the analog signal (digital signal) is ≤ the threshold set by the system, the RF signal is directly output through the monitoring unit D. By adjusting the attenuator, delayer, and phase shifter B4 according to the feedback analog signal through FPGA, the changes of each component due to temperature, aging and other factors can be compensated to ensure the stability of the RF link unit B.

[0026] Since the attenuator will produce ±3~5° phase drift when adjusting the phase, the phase shifter will produce ±0.5dB amplitude drift when adjusting the phase. The delayer will produce ±0.5dB amplitude drift. Through the control of FPGA, the RF link unit B can realize phase shifting, attenuation, and delay while compensating the parasitic amount generated by phase shifting, attenuation, and delay through small phase shifting, attenuation, and delay; and the phase shifting, attenuation, and delay between channels have good consistency.

[0027] The control effect of the control device of the present invention is described below with a specific example.

[0028] In this embodiment, 40 radio frequency signals of different frequencies are used as input, and amplitude and phase delay control is performed through the control device of the present invention. The total attenuation and attenuation error of the radio frequency link unit B are shown in Table 1, and the total delay and error are shown in Table 2.

[0029] Table 1 Total attenuation and attenuation error

[0030] It can be seen from the above table that the attenuation error of this embodiment is ≤±0.6dB; Table 2 Total delay and delay error

[0031] It can be seen from the above table that the delay error is ≤±0.8ps.

[0032] It can be seen from Table 1 and Table 2 that the multi-channel amplitude and phase delay control device of the present invention has high control accuracy.

[0033] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A multi-channel amplitude and phase delay control device, characterized in that: include: At least two radio frequency link units, the radio frequency link units are used to perform amplitude and phase delay processing on input radio frequency signals to obtain analog signals; A synthesis link unit, the input end of which is connected to all the radio frequency link units and is used to synthesize all the analog signals to obtain a synthesized signal; A monitoring unit, the input end of which is connected to the synthesis link unit, and is used to divide the synthesis signal into an output signal and a coupling signal, and convert the coupling signal into a digital signal; A logic processing unit, whose output ends are respectively connected to the radio frequency link unit, the monitoring unit and the synthesis link unit, and is used to convert the control instructions into control signals of the radio frequency link unit, the monitoring unit and the synthesis link unit respectively; The input end is connected to the output end of the monitoring unit, and the logic processing unit is also used to adjust the control signal according to the digital signal.

2. The multi-channel amplitude and phase delay control device according to claim 1, characterized in that: include: The radio frequency link unit includes a switch, a first attenuator, a first amplifier, a phase shifter, a second attenuator, a first delay device, a third attenuator, a fourth attenuator, a second delay device, a second amplifier, a third amplifier, a fourth amplifier, and a fifth attenuator, which are connected in sequence.

3. The multi-channel amplitude and phase delay control device according to claim 1, characterized in that: The monitoring unit comprises a coupler and a detector which are connected in sequence.

4. The multi-channel amplitude and phase delay control device according to claim 1, characterized in that: The synthesis link unit comprises a plurality of combiners, each of which is used for combining two analog signals.

5. The multi-channel amplitude and phase delay control device according to claim 1, characterized in that: The radio frequency link unit includes at least two channels.

6. The multi-channel amplitude and phase delay control device according to claim 1, characterized in that: Said The logical processing unit includes: A differential chip, used to convert control instructions into differential signals; A serial-to-parallel conversion chip, connected to the differential chip, for converting the differential signal into a serial port single-ended signal; The FPGA is connected to the serial-to-parallel conversion chip and is used for converting the serial port single-ended signal into a parallel port signal, performing logic operations, and outputting high and low level signals.

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