Improved abspd clock recovery method at half baud rate sampling

Abstract

The application relates to an improved ABSPD clock recovery method under single baud rate sampling, clock synchronization of transceiving end signals is realized through a full-digital type clock recovery loop, a timing error detector is used to replace numerical multiplication operation with symbol judgment and shift operation when calculating timing error e; after the timing error e is calculated by the timing error detector, the timing error e is input into a loop filter to remove noise and control words W are obtained; then the control words W are used to control a digital controlled oscillator, fractional interval mu k is calculated from the output NCO of the digital controlled oscillator and the control words W k The integer mark m k of the symbol and the calculated fractional interval mu k The received signal is interpolated in an interpolation filter, so that timing correct data are calculated. The application realizes ABSPD clock recovery under single baud rate sampling without multiplication operation, and significantly reduces the complexity of the whole clock recovery loop.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of high-speed optical signal processing, and more particularly to an improved ABSPD clock recovery method under single baud rate sampling. BACKGROUND

[0002] In order to meet the increasing demand for data traffic, it will be a trend in the future to sink coherent technology into short-distance optical interconnection application scenarios to support large-capacity data transmission. However, due to the high complexity of the digital signal processing (DSP) algorithm of the traditional coherent optical communication system, it cannot be directly applied to short-distance data center optical interconnection application scenarios. Therefore, it is necessary to simplify the traditional coherent optical communication algorithm. In the DSP algorithm of the traditional coherent system, the commonly used clock recovery algorithm usually has a large dependence on the oversampling rate of the receiver. The classic time-domain Gardner algorithm, Lee algorithm and frequency-domain Godard algorithm all need double oversampling, resulting in high complexity of the algorithm.

[0003] In order to reduce the complexity of the clock recovery algorithm, existing schemes have proposed an improved time-domain Lee algorithm and an improved frequency-domain Godard algorithm, which can work under non-integer multiple oversampling conditions, thereby reducing the computational complexity of the clock recovery loop. However, these algorithms still require a certain oversampling rate. In order to further reduce the computational complexity of the algorithm, it is necessary to explore a clock recovery algorithm suitable for single baud rate sampling. Mueller & Muller (MM) algorithm is a single baud rate clock recovery algorithm commonly used in intensity modulation direct detection systems, but this algorithm is very sensitive to frequency offset, phase noise and dispersion damage in coherent systems, and various damages need to be compensated in the loop, thereby increasing the complexity and latency of the entire clock recovery loop, so the MM algorithm is not suitable for coherent systems. In addition, a clock recovery algorithm called ABSPD (absolute phase detector) is proposed to be applied to coherent optical communication systems and can work under single baud rate sampling. However, this ABSPD algorithm involves too many multiplication operations in the process of calculating the timing error, resulting in high computational complexity, which affects the implementation of this scheme in actual systems. SUMMARY

[0004] The present application aims to overcome the deficiency of the prior art ABSPD algorithm in the process of calculating the timing error, which involves too many multiplication operations, thereby resulting in high computational complexity, and provides an improved ABSPD clock recovery method under single baud rate sampling, avoids using complex multiplication operations in the timing error calculation process, realizes ABSPD clock recovery under single baud rate sampling without multiplication operations, and significantly reduces the complexity of the entire clock recovery loop.

[0005] To solve the above technical problems, the technical scheme adopted by the present application is:

[0006] The application provides an improved ABSPD clock recovery method under single baud rate sampling, clock synchronization of a transmitting / receiving end signal is realized through a full-digital type clock recovery loop, the full-digital type clock recovery loop comprises an interpolation filter, a timing error detector, a loop filter and a numerically controlled oscillator, when calculating a timing error e, the timing error detector uses symbol judgment and shift operation to replace numerical multiplication operation, after the timing error e is calculated by the timing error detector, the timing error e is input into the loop filter to remove noise, a control word W is obtained, then the control word W is used to control the numerically controlled oscillator, a fractional interval mu k is calculated by the output NCO of the numerically controlled oscillator and the control word W. k k The received signal is interpolated in the interpolation filter, so that the data with correct timing is calculated.

[0007] The application provides an improved ABSPD clock recovery method under single baud rate sampling, multiplication operation involving specific numerical values in a traditional ABSPD algorithm is replaced by symbol judgment and shift operation, so that complex multiplication operation in the timing error calculation process is avoided, ABSPD clock recovery under single baud rate sampling without multiplication operation is realized, and the complexity of the whole clock recovery loop is significantly reduced.

[0008] Preferably, the timing error detector calculates the timing error e in the following manner:

[0009]

[0010] In the formula, x I and x Q are the real part and the imaginary part of the received signal x respectively, N is the length of a data block required for calculating the timing error each time, k represents the pointer of the data in the data block, n represents the time, sign(·) represents the sign operation, and |·| represents the absolute value operation.

[0011] Preferably, for the formula (1), the following is used:

[0012] The related multiplication calculation involving |sign(x I (k))+sign(x I (k-1))| and |sign(x Q (k))+sign(x Q (k-1))| can be realized by using shift operation. As can be seen from the formula (1), sign(x​I (k) ) + sign ( x I (k-1) ) | and | sign ( x Q (k) ) + sign ( x Q (k-1) ) | can only be 0 or 2. Since the multiplication by 2 operation can be realized by a shift operation, the present application does not need to use a complex multiplication operation based on the improved ABSPD clock recovery method.

[0013] Preferably, the timing error detector operates at a single baud rate sampling.

[0014] Preferably, the timing error e is input into a loop filter to filter out noise and obtain a control word W, which is calculated by the following equation:

[0015]

[0016] wherein, L p and L I represent the outputs of the proportional part and the integral part of the loop filter respectively, and k1 and k2 represent the error control coefficients of the proportional part and the integral part respectively.

[0017] Preferably, the control word W is used to control a numerically controlled oscillator, and the control process includes:

[0018] NCO (n) = [NCO (n-1) - W (n-1) ] mod 1 (3)

[0019] wherein, NCO represents the output of the numerically controlled oscillator, and mod represents a modulus operation.

[0020] Preferably, a fractional interval μ k is calculated from the output NCO of the numerically controlled oscillator and the control word W, and is calculated by the following equation:

[0021]

[0022] Preferably, an integer index m k and the calculated fractional interval μ k are used to calculate a timing-corrected data from a received signal in an interpolation filter, and the timing-corrected data is calculated by the following equation:

[0023]

[0024] wherein, T s and T i represent the actual sampling period and the optimal sampling period after clock recovery respectively, and y represents a symbol after clock recovery.

[0025] The application also provides an optical communication method, in the digital signal processing of a transmitting end, first, a pseudo-random bit sequence is mapped to 16QAM symbols, used for generating two 50Gbuad 16QAM signals, and a root raised cosine filter with a roll-off factor of 0 is used for Nyquist shaping of the QAM symbols, and finally, the signal is resampled; in the digital signal processing of a receiving end, the received signal is subjected to dispersion compensation, then the above-mentioned clock recovery method is used for clock recovery at a single baud rate; after clock recovery, an equalizer working at a single baud rate is used for equalization, and finally, a bit error rate is calculated.

[0026] The application also provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above-mentioned method when executing the computer program.

[0027] Compared with the prior art, the application has the following beneficial effects:

[0028] The improved ABSPD clock recovery method under single baud rate sampling of the application can realize clock recovery under single baud rate sampling in a coherent optical communication system, and the numerical multiplication operation in the traditional ABSPD clock recovery algorithm is replaced by symbol judgment and shift operation, so that a large number of multiplication operations are avoided when calculating timing errors in the clock recovery loop, thereby significantly reducing the calculation complexity of the clock recovery loop while ensuring that the algorithm can work under single baud rate sampling. In addition, on the basis of realizing single baud rate sampling clock recovery based on the proposed scheme, the subsequent equalizer can be further simplified from a two-fold oversampling equalizer architecture to a single sampling equalizer architecture, thereby significantly reducing the complexity of the receiving end DSP. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 It is a schematic diagram of a full-digital clock recovery loop structure.

[0030] Figure 2 It is a schematic diagram of the principle of the improved ABSPD clock recovery method of the application.

[0031] Figure 3 It is a simulation system device diagram of embodiment two.

[0032] Figure 4 It is a schematic diagram of an S curve of the traditional ABSPD algorithm.

[0033] Figure 5 It is a schematic diagram of an S curve of the improved ABSPD clock recovery method of the application.

[0034] Figure 6 It is a performance diagram of different ABSPD algorithms when there is a 10ppm sampling frequency offset.

[0035] Figure 7 Performance diagram of different ABSPD algorithms in the presence of 30ppm sampling frequency offset.

[0036] Figure 8 Performance diagram of different ABSPD algorithms in the presence of 40ppm sampling frequency offset. DETAILED DESCRIPTION

[0037] The application will be further described below in connection with the specific embodiments. The accompanying drawings are only used for exemplary illustration, and the representation is only a schematic diagram, not a physical diagram, and cannot be understood as a limitation on the patent; in order to better illustrate the embodiments of the application, some components in the drawings will be omitted, enlarged or reduced, and do not represent the size of the actual product; it can be understood by those skilled in the art that some well-known structures and their descriptions in the drawings can be omitted.

[0038] The same or similar reference numerals in the drawings of the embodiments of the application correspond to the same or similar components; in the description of the application, it should be understood that the orientations or positional relationships indicated by terms such as "upper", "lower", "left", "right" are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the application and simplifying the description, and therefore the terms describing the positional relationship in the drawings cannot be understood as a limitation on the patent, and the above terms can be understood according to the specific meaning by those skilled in the art according to the specific situation.

[0039] Embodiment one

[0040] The present embodiment is a first embodiment of an improved ABSPD clock recovery method under single baud rate sampling, which realizes clock synchronization of the transmitting and receiving end signals through a full-digital type clock recovery loop, Figure 1 The structure of the full-digital type clock recovery loop is given. From Figure 1 It can be seen that the full-digital type clock recovery loop includes an interpolation filter, a timing error detector, a loop filter and a digital controlled oscillator; the timing error detector works at single baud rate sampling, and uses sign judgment and shift operation to replace numerical multiplication operation when calculating the timing error e; Figure 2 The principle block diagram of the application is given; the timing error e is calculated by the timing error detector, and the calculation principle is as follows:

[0041]

[0042] In the formula, x I and x Qrespectively, N is the length of a data block required for calculating timing error each time, k represents the pointer of data in the data block, n represents the time, sign(·) represents the sign operation, and |·| represents the absolute value operation.

[0043] As can be seen from equation (1), the values of |sign(x I (k))+sign(x I (k-1))| and |sign(x Q (k))+sign(x Q (k-1))| can only be 0 or 2. Since the multiplication operation by 2 can be realized by a shift operation, the present application based on the improved ABSPD clock recovery method does not need to use complex multiplication operation.

[0044] After the timing error e is calculated, the timing error e is input into a loop filter to filter out noise and obtain a control word W, which can be described as:

[0045]

[0046] In the formula, LF p and LF I represent the outputs of the proportional part and the integral part of the loop filter respectively, and k1 and k2 represent the error control coefficients of the proportional part and the integral part respectively.

[0047] Then the control word W is used to control a numerically controlled oscillator, and the control process is:

[0048] NCO(n)=[NCO(n-1)-W(n-1)]mod1(3)

[0049] In the formula, NCO represents the output of the numerically controlled oscillator, and mod represents the modulus operation.

[0050] Then, the fractional interval μ k is calculated from the output NCO of the numerically controlled oscillator and the control word W.

[0051]

[0052] Finally, the integer index m k and the calculated fractional interval μ k are used to interpolate the received signal in an interpolation filter, so as to calculate the data with correct timing, which can be described as:

[0053]

[0054] In the formula, T s and T irespectively represent the actual sampling period and the optimal sampling period after clock recovery, and y is a symbol after clock recovery.

[0055] The improved ABSPD clock recovery method under single baud rate sampling of the application replaces the multiplication operation involving specific numerical value in the traditional ABSPD algorithm by symbol judgment and shift operation, thereby avoiding the complex multiplication operation in the timing error calculation process, realizing the ABSPD clock recovery under single baud rate sampling without multiplication operation, and significantly reducing the complexity of the entire clock recovery loop.

[0056] Compared with the commonly used clock recovery algorithms such as the classic time domain Gardner algorithm, Lee algorithm and frequency domain Godard algorithm, the application can effectively reduce the system oversampling rate required for clock recovery at the receiving end, and realize the low-complexity clock recovery under single baud rate.

[0057] Embodiment two

[0058] This embodiment is based on the clock recovery method proposed in embodiment one, and the method is analyzed and verified through simulation.

[0059] The effectiveness of the application is verified in a homodyne coherent system, Figure 3 The simulation system device diagram of the application is given. The optical carrier at the transmitting end is generated by a laser with a line width of 100 kHz, and the output power is 16 dBm. The carrier is divided into two branches by a coupler, the upper branch is used for signal modulation, and the lower branch is used as the local oscillator (LO). In the signal modulation part, the optical carrier for signal modulation is divided into two orthogonal polarized lights by a polarization beam splitter (PBS) and input into two IQ modulators (IQM) for signal modulation. Two 50Gbaud single carrier 16QAM signals generated offline at the transmitting end are loaded into two IQMs to realize electro-optical conversion. The signals output by the two modulators are coupled by a polarization beam combiner (PBC) and then input into an 80-kilometer optical fiber for transmission. In the simulation, an optical signal-to-noise ratio (OSNR) module is used to adjust the OSNR of the system. After the LO is transmitted through the same length of optical fiber to the receiving end, it and the signal are divided into two orthogonal polarization states by a PBS, and then input into two 90° optical mixers and detected by four pairs of photodetectors (PDs). The detected data is processed in the receiving end DSP. The sampling rate of the system is 80GSa / s.

[0060] (1) Transmitter DSP

[0061] In the transmitter DSP, first, a pseudo-random bit sequence is mapped to 16QAM symbols, which are used to generate two 50Gbuad 16QAM signals, and the QAM symbols are Nyquist shaped with a root raised cosine filter with a roll-off factor of 0, and finally the signals are resampled.

[0062] (2) Receiver DSP

[0063] In the receiver DSP, first, the received signal is dispersion compensated, and then the improved ABSPD clock recovery method proposed in Example 1 is used to recover the clock at a single baud rate. After clock recovery, an equalizer working at a single baud rate is used for equalization, and finally the bit error rate is calculated.

[0064] Result analysis:

[0065] Based on the simulation device of Figure 3 , first, the S-curve of the traditional ABSPD algorithm and the S-curve of the improved ABSPD algorithm proposed in the present application are compared, and the results are shown in Figure 4 and Figure 5 . According to the S-curve, the Jitter size at the zero point of the two algorithms can be obtained, and is given in Figure 4 and Figure 5 . From the figure, it can be seen that the Jitter of the traditional ABSPD algorithm and the improved ABSPD algorithm is -40.9dB and -41.3dB, respectively, i.e. the two algorithms show similar Jitter performance.

[0066] Figure 6 The bit error rate performance of the improved ABSPD clock recovery method proposed in the present application and the traditional ABSPD method when the sampling phase deviation and the sampling frequency deviation of the system are 5ps and 10ppm, respectively, is given, and also compared with the case where there is no timing error. From the figure, it can be seen that when there is a sampling phase deviation of 5ps and a sampling frequency deviation of 10ppm, the method of the present application can obtain almost the same performance as the traditional ABSPD algorithm, and compared with the case where there is no timing error, it has almost no optical signal-to-noise ratio loss at the hard decision threshold.

[0067] Figure 7The bit error rate curves of the method of the present application and the conventional ABSPD algorithm when the sampling phase offset and the sampling frequency offset of the system are 5ps and 30ppm respectively are given, and are compared with the case without timing error. It can be seen from the figure that when the sampling phase offset of 5ps and the sampling frequency offset of 30ppm exist, the method of the present application can obtain almost the same performance as the conventional ABSPD algorithm, and compared with the case without timing error, there is only about 0.3dB loss of optical signal-to-noise ratio at the hard decision threshold for the two algorithms.

[0068] Figure 8 The bit error rate performance of the method of the present application and the conventional ABSPD algorithm when the sampling phase offset and the sampling frequency offset of the system are 5ps and 40ppm respectively is given, and is compared with the case without timing error. Similarly, when the sampling phase offset of 5ps and the sampling frequency offset of 40ppm exist, the bit error rate curves of the method of the present application and the conventional ABSPD algorithm almost overlap. Compared with the case without timing error, there is about 0.5dB loss of optical signal-to-noise ratio at the hard decision threshold for the two algorithms.

[0069] Embodiment Three

[0070] The embodiment provides a computer device, including a memory and a processor, characterized in that the memory stores a computer program, and the processor executes the computer program to realize the steps of the method in the embodiment one.

[0071] In the specific content of the foregoing specific embodiments, each technical feature can be combined arbitrarily without contradiction, and to make the description brief, all possible combinations of the foregoing technical features are not described, however, as long as the combinations of the technical features do not exist contradiction, it should be considered that the combinations are within the scope of the present application.

[0072] Obviously, the above embodiments of the present application are only examples for clearly illustrating the present application, and are not intended to limit the implementation modes of the present application. Any modification, equivalent replacement and improvement made on the basis of the above description for those skilled in the art should be included in the protection scope of the present application.

Claims

1. An improved ABSPD clock recovery method at half baud rate sampling, characterized by, Clock synchronization of the transmitting and receiving end signals is realized by a full-digital clock recovery loop, which includes an interpolation filter, a timing error detector, a loop filter and a numerically controlled oscillator (NCO); The timing error detector uses symbol judgment and shift operation to replace numerical multiplication operation when calculating timing error e; After the timing error e is calculated by the timing error detector, the timing error e is input into a loop filter to filter out noise and obtain a control word W; then the control word W is used to control a numerically controlled oscillator, and the fractional interval μ is calculated by the output NCO of the numerically controlled oscillator and the control word W k ; the integer index m k of the symbol and the calculated fractional interval μ k The received signal is interpolated in the interpolation filter, so that the data with correct timing is calculated; The timing error detector calculates timing error e by the following method: where x I and x Q are the real and imaginary parts of the received signal x, respectively, N is the length of one data block required for calculating timing error each time, k represents the pointer of data in the data block, n represents the time, sign(·) represents the sign operation, and |·| represents the absolute value operation. Timing error e is input into the loop filter for noise filtering to obtain control word W, which is calculated by the following formula: wherein, LF p and LF I respectively represent the outputs of the proportional part and the integral part in the loop filter, and k1 and k2 respectively represent the error control coefficients of the proportional part and the integral part. Control word W is used to control the NCO, and the control process includes: NCO(n)=[NCO(n-1)-W(n-1)]mod1(3) In the formula, NCO represents the output of the NCO, and mod represents modulo operation; The fractional interval μ is computed from the output of the numerically controlled oscillator NCO and the control word W k is computed using the following equation: Integer index m of the symbol k and the computed fractional interval μ k The received signal is interpolated in the interpolation filter, so that the timing-correct data is computed by the following formula: In the formula, T s and T i respectively represent the actual sampling period and the optimal sampling period after clock recovery, and y is the symbol after clock recovery.

2. The improved ABSPD clock recovery method at half baud rate sampling as claimed in claim 1, wherein, In the formula (1), the timing error detector works at a single baud rate sampling. |sign(x I (k))+sign(x I (k-1))| and the multiplication operation of |sign(x Q (k))+sign(x Q (k-1))| is implemented using a shift operation.

3. The method for improved ABS PD clock recovery at one-half baud rate sampling as claimed in claim 1, wherein, In the transmitting end digital signal processing, first, a pseudo-random bit sequence is mapped to 16QAM symbols to generate two 50Gbuad 16QAM signals, and a root raised cosine filter with a roll-off factor of 0 is used to perform Nyquist shaping on the QAM symbols, and finally the signal is resampled; in the receiving end digital signal processing, the received signal is color dispersion compensated, and then the clock recovery method of any one of claims 1 to 3 is used to perform clock recovery at a single baud rate; 4. A method of optical communication, characterized by, After clock recovery, an equalizer working at a single baud rate is used for equalization, and finally the bit error rate is calculated. The memory stores a computer program, and the processor executes the computer program to realize the steps of the method of any one of claims 1 to 3. 5.A computer device, comprising a memory and a processor, and characterized in that, ​

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