Method and circuit for rapidly switching on and off bipolar pulse excitation signal of row-column addressing ultrasonic sensor array

Abstract

The invention discloses a method and circuit for rapidly switching on and off bipolar pulse excitation signals of a row-column addressing ultrasonic sensor array, and the method comprises the steps: carrying out the rapid switching on and switching off of row and column circuits in an array through a logic control circuit according to a coding gating sequence generated by an ultrasonic excitation rule; and conduction and cut-off of bipolar pulses during excitation of different array elements are realized. The array elements work in a bidirectional transmit-receive mode, and when the array elements are gated, the corresponding row electrode and column electrode switches are quickly turned on to ensure that bipolar pulse signals pass without distortion, and other array elements are in a turn-off state. According to the switching circuit, rapid gating excitation of different array elements in an array can be achieved, and the circuit system mainly comprises a coding gating sequence decoding circuit, an edge detection circuit and row and column gating switching circuits. The array element can be quickly gated and excited by the row-column addressing ultrasonic sensor array, flexible control of the emission aperture of the row-column addressing array is realized, and excitation bipolar pulses are applied to the array element to generate ultrasonic waves.

Description

Technical Field

[0001] The invention belongs to the field of ultrasonic detection, and relates to a method and a circuit for quickly switching bipolar pulse excitation signals of a row-column addressing ultrasonic sensor array. Background Art

[0002] During ultrasonic testing, as the demand for information about the target increases, as well as the requirements for target image quality and quantification accuracy, the limitations of traditional ultrasonic sensor arrays are becoming increasingly apparent. To this end, row column addressing array (RCA) technology has emerged. Row column addressing ultrasonic arrays can control the array transmit aperture size and focusing law in real time, and can achieve high-precision three-dimensional imaging while reducing the number of array electrodes and excitation channels.

[0003] Although this technology has shown good development potential in the field of industrial detection, most of the two-dimensional row-column addressed ultrasonic sensor arrays at home and abroad currently use piezoelectric films or micro-capacitor structures obtained by micromachining technology, and the emitted sound energy is small, which cannot meet the needs of industrial non-destructive testing. The ultrasonic sensor array in the present invention uses block piezoelectric ceramic materials (PZT), which can ensure the effective transmission and detection requirements of the ultrasonic waves generated by the excitation in industrial materials, but the research and development of the circuit system of the row-column addressed bipolar excitation pulse is in its infancy and cannot meet the actual circuit requirements. The present invention relates to a method and circuit for quickly turning on and off bipolar pulse excitation signals, which can be adapted to a row-column addressed ultrasonic sensor array composed of PZT block array elements, and the method and circuit can be expanded and applied to large-scale ultrasonic sensor addressing excitation arrays. Summary of the invention

[0004] In view of the current situation that the excitation mode and excitation method of the existing ultrasonic sensor array are rigid and lack of specific circuits, and in combination with the needs of the development of row-column addressed arrays, the present invention provides a method and circuit for quickly switching bipolar pulse excitation signals for row-column addressed ultrasonic sensor arrays, the purpose of which is to realize the functions of flexibly selecting the excitation array elements and receiving ultrasonic reflected signals by respectively setting independent control switch circuits on the row electrodes and column electrodes of the array. This solves the technical situation that when the ultrasonic sensor array is excited in the existing methods, only a single array element or the entire array can be excited. Each circuit module of the present invention adopts a modular design, which reduces the circuit scale while improving the circuit utilization rate and saving the system cost. The present invention realizes the effective conduction and cutoff of the bipolar pulse signal, reduces the switch conduction attenuation and improves the switch cutoff attenuation, and at the same time ensures that the conduction and cutoff states of the switch can maintain the characteristics continuously.

[0005] To achieve the above purpose, the specific technical solution of the present invention is as follows:

[0006] Step 1, the bipolar pulse switch circuit includes two inputs and one output signal. The two input signals are the coded selection sequence signal Q and the pulse input signal VIN, and the output signal is the pulse output signal VOUT. Q is connected to the control signal end, VIN is connected to the signal transmitting end, and VOUT is connected to the signal receiving end;

[0007] Step 2, the decoding circuit decodes Q to obtain the switch signal SW of each channel, and then the edge detection circuit receives SW to generate a set of square wave pulse signals with adjustable pulse width, and obtains the gating control signals ON and OFF after power amplification;

[0008] Step 3, when the selection switch circuit is in the cut-off state, ON is set to a low level, the PMOS tube M7 is turned on, and the DC source DC charges the on-voltage latch capacitors C3 and C4 through the diode D1 and the current-limiting resistor R3. When C4 is charged to the on-voltage of the NMOS tube M6, M6 is turned on, and the cut-off voltage latch capacitors C1 and C2 are discharged through the resistor R2. When the voltage of C2 is not enough to keep the NMOS tube M5 turned on, M5 is turned off, so that the discharge loop of C3 and C4 is cut off. ON is set to a high level to turn off M7, and the latching of the on-voltage is completed. At this time, since the sum of the voltages across C3 and C4 is always greater than the on-voltage of the main switches M1 and M2, the selection switch circuit remains in the on state, and VIN and VOUT are in a connected state;

[0009] Step 4, when the selection switch circuit is in the on state, OFF is set to a low level, the PMOS tube M8 is turned on, and the DC source DC charges the cut-off voltage latching capacitors C1 and C2 through the diode D2 and the current limiting resistor R4. When the voltage of C2 is greater than the on voltage of the NMOS tube M5, M5 is turned on, and the on voltage latching capacitors C3 and C4 are discharged through the resistor R1. When the sum of the voltages across C3 and C4 is less than the cut-off voltage of the main switches M1 and M2, the selection switch circuit is cut off, and VIN is disconnected from VOUT. At this time, since the voltage of C4 is not enough to keep the NMOS tube M6 turned on, M6 is cut off, so that the discharge loop of C1 and C2 is cut off. Then set the OFF signal to a high level to cut off M8, and the latching of the cut-off voltage is completed, and the selection switch circuit remains in the off state;

[0010] Step 5: The selection switch circuit composed of NMOS tubes M1 and M2 can meet the conventional industrial ultrasonic detection excitation frequency requirements. The upper limit of the excitation pulse frequency can be increased by adding auxiliary switch NMOS tubes M3 and M4.

[0011] Step 1 is as follows: The control method of the bipolar pulse switch circuit is simple, and only one signal Q is needed to quickly control the conduction and cutoff of the bipolar pulse signal. Q includes multiple channels of SW, which are generated by the microcontroller (MCU), i.e., the control signal end. The signal transmitting end is the circuit that generates the excitation pulse, and the signal receiving end is the sensor array.

[0012] Step 2 is specifically as follows: the decoding circuit decodes Q to obtain the SW of each channel, and the edge detection circuit detects the level change of SW. When SW jumps from a low level to a high level (rising edge trigger), the circuit outputs a square wave pulse signal, which is amplified by power to obtain ON; when SW jumps from a high level to a low level (falling edge trigger), the circuit outputs a square wave pulse signal, which is amplified by power to obtain OFF.

[0013] Step 3 is specifically as follows: when ON becomes a low level, a voltage drop occurs across R5, that is, a negative voltage is generated between the source and gate of M7. When the turn-on voltage is met, the source and drain of M7 are connected, and DC charges C3 and C4 through D1 and R3. C3 and C4 are in a voltage-dividing relationship, and the maximum voltage allocated to C4 should be slightly higher than the turn-on voltage of M6. After M6 is turned on, C1 and C2 discharge through R2. C1 and C2 also meet the voltage-dividing relationship, and the maximum voltage allocated to C2 should be slightly higher than the turn-on voltage of M5. When discharged through R2, M5 can quickly enter the cut-off state, reducing the time for switching the state of the gate switch circuit. Set ON to a high level to turn off M7, and C3 and C4 cannot be reversely discharged to DC through D1, and there is no other discharge circuit, so the latching of the turn-on voltage is completed. At this time, the sum of the voltages across C3 and C4 is always greater than the turn-on voltage of the main switches M1 and M2, and the gate switch circuit can remain in the on state. The DC level has nothing to do with VIN, it only needs to meet the on or off voltage of PMOS and NMOS.

[0014] Step 4 is as follows: the process of turning off the gate switch circuit is similar to that of turning on. OFF is set to a low level, and M5 is turned on by charging C1 and C2, and C3 and C4 are discharged through R1. When the sum of the voltages across C3 and C4 is less than the cut-off voltage of the main switches M1 and M2, the gate switch circuit is turned off. When the discharge loop of C1 and C2 is turned off, OFF is set to a high level to complete the latching of the cut-off voltage, and the gate switch circuit remains in the cut-off state.

[0015] Step 5 is specifically as follows: the sources of M1 and M2 in the gate switch circuit are connected to form a main switch, and the sources of M3 and M4 are connected to form an auxiliary switch to improve the cutoff performance of high-frequency signals. The circuit design of connecting the sources of NMOS tubes enables the gate switch circuit to have the ability to block bipolar pulses. The row-column addressed ultrasonic sensor array fast switch bipolar pulse excitation signal circuit of the present invention mainly comprises a coding selection sequence decoding circuit, an edge detection circuit and a row and column selection switch circuit.

[0016] The coding strobe sequence decoding circuit is composed of a shift register and a peripheral circuit. The input microcontroller (MCU) generates a signal Q according to the ultrasonic excitation method, and cooperates with the clock signal CLK and the enable signal EN to generate the SW of each channel. The high and low levels of SW represent the conduction and cutoff of the strobe switch circuit respectively. The coding strobe sequence decoding circuit can expand the number of channels in the form of shift register cascade to meet the needs of a larger sensor array.

[0017] The edge detection circuit is composed of a pair of re-triggerable monostable multivibrators and a power amplifier circuit, which outputs a square wave pulse signal at the rising and falling edges of SW, and obtains ON and OFF after power amplification. The square wave pulse width is adjusted by changing the feedback capacitor and resistor of the edge detection circuit. In principle, the pulse width needs to be greater than the charging time of the latch capacitor in the gate switch circuit.

[0018] The row and column gating switch circuits have the same structure and can be collectively referred to as gating switch circuits. The circuit is composed of basic electronic components, M1 and M2 are connected at the source to form a main switch, and M3 and M4 are connected at the source to form an auxiliary switch. The use of main and auxiliary switches connected at the source can ensure that the signal distortion of the bipolar pulse signal is reduced when passing through the gating switch circuit. When the gating switch circuit is in the on state, VIN passes through M1 and M2 and outputs VOUT at the output end. Since the on-resistance of the main switch is low, VIN passes through almost without attenuation, and the auxiliary switch does not work at this time. When the gating switch circuit is in the off state, a part of VIN is discharged through the discharge circuit of M3 and M4, thereby reducing the impact on the output load.

[0019] The main switches M1 and M2 described above have smaller inherent parasitic capacitances, greater blocking and attenuation of pulse excitation signals, and faster switch response speeds; and smaller internal on-resistances, smaller signal attenuation during on-state.

[0020] The gate switch circuit maintains the on or off state depending on the voltage distribution on the capacitors C1 to C4, wherein C1 and C2 are the off voltage latch capacitors, latching the voltage required for the gate switch circuit to be turned off; C3 and C4 are the on voltage latch capacitors, latching the voltage required for the gate switch circuit to be turned on, and the latch voltage is not affected by the output pulse excitation voltage. Increasing the capacitance value of C1 to C4 is conducive to maintaining the on and off states of the gate switch circuit, and enhancing the signal attenuation during the off state, but it will reduce the state switching response speed of the gate switch circuit.

[0021] The present invention has the following beneficial effects: 1. Single and bipolar excitation pulse control: Traditional CMOS electronic switches can only realize the switch control of single excitation pulses. The present invention can realize the switch control of not only single polarity excitation pulses but also bipolar excitation pulses. And the opening and closing performance of the switch circuit can ensure the effective passage and cutoff of the excitation pulse signal. 2. The pulse switch circuit achieves fast and accurate on and off control by encoding the selection sequence signal Q, and combines the decoding circuit and the edge detection circuit to generate an adjustable pulse control signal (ON and OFF), which significantly simplifies the control process and improves the flexibility and reliability of array element excitation in the array. 3. In the present invention, by optimizing the capacitor allocation, the stability and response speed of the circuit in the on and off states can be enhanced to meet the requirements of high-frequency signals. 4. The circuit of the present invention adopts a modular design, allowing the number of channels to be expanded through cascaded shift registers, supporting larger-scale ultrasonic sensor arrays, reducing system complexity, and increasing upgrade flexibility to adapt to the application requirements of ultrasonic sensor arrays of different sizes. The method for quickly switching bipolar pulse excitation signals for row-column addressed ultrasonic sensor arrays is different from the traditional ultrasonic array addressing excitation method. The advantage of the present invention is that it is applicable to large-scale row-column addressed arrays, and an independently controllable gate switch circuit is set on the row electrodes and column electrodes of the array to realize the functions of flexibly gate excitation array elements and receive ultrasonic reflected signals. The hardware circuit structure of the present invention is simple and easy to implement, which reduces the circuit scale while improving the circuit utilization. In addition, the present invention realizes the effective conduction and blocking of bipolar pulse signals, reduces conduction attenuation and improves cutoff attenuation, and ensures that the conduction and cutoff states of the gate switch circuit can maintain the characteristics continuously. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The overall system block diagram of the present invention is an example;

[0023] Figure 2 This is a schematic diagram of an exemplary ultrasonic sensor array structure of the present invention;

[0024] Figure 3 An example excitation pulse transmitting circuit for the present invention;

[0025] Figure 4 The exemplary coding selection sequence decoding, edge detection and power amplifier circuit of the present invention;

[0026] Figure 5 This is a timing diagram of the circuit control of the present invention;

[0027] Figure 6 (a) is an example excitation pulse waveform diagram of the present invention, Figure 6(b) is a waveform diagram of an excitation pulse when the row gate switch circuit of the present invention is configured to be cut off;

[0028] Figure 7 To illustrate the present invention, different aperture excitation echo signals are shown. Figure 7 (a) Single-element excitation and single-element reception, Figure 7 (b) The whole row of array elements excites a single array element for reception. Figure 7 (c) The whole array of elements excites a single element to receive. Figure 7 (d) All array elements excite a single array element for reception; DETAILED DESCRIPTION

[0029] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments. It should be noted that the present invention can also be applied through other equivalent implementations. The implementation methods and illustrations provided in the following embodiments only illustrate the basic technical concept of the present invention in an exemplary manner. The models, numbers, sizes, materials and other parameters of the relevant components in the embodiments can be changed in a specific implementation environment. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0030] The row-column addressing ultrasonic sensor array in the present invention adopts an 8+8 scale mainly because it can verify the function of the fast switching bipolar pulse excitation signal circuit, and can be expanded to arrays of other scales.

[0031] In order to facilitate the understanding of the present switching bipolar pulse excitation signal to complete the array element gating excitation method, the exemplary addressing excitation method of the present invention is first described. Figure 1 The figure shows the overall block diagram of the present invention. The sensor array adopts a row-column addressing structure design, the array size is M×N, where M is the number of array rows, N is the number of array columns, and the array element number is [i, j], i and j represent the index of the row and column electrodes respectively. The elements of the same row number in the sensor array are connected in a collinear manner, and the elements of the same column number are connected in a collinear manner. The row collinear electrodes are connected to the excitation pulse source through the row gating switch circuit as the excitation electrodes; the column collinear electrodes are connected to the reference ground through the column gating switch circuit as the reference ground electrode, forming an M-row and N-column gating array. The control signals of the row and column gating switch circuits are generated by the coding gating control circuit, which is a square wave pulse signal. To achieve flexible addressing excitation, the microcontroller (MCU) first needs to generate a coding gating sequence Q according to the ultrasonic excitation method. The high level represents conduction and the low level represents cutoff. Then, the Q is decoded by the decoding circuit to obtain the switch signal SW of each channel. The edge detection circuit detects the level change of SW, and outputs a square wave pulse signal at the rising and falling edges of SW. After power amplification, the ON and OFF signals are obtained. When ON becomes a low level, the PMOS tube M7 in the gating switch circuit is turned on, and the DC source DC charges the conduction voltage latch capacitors C3 and C4 through the diode D1 and the current limiting resistor R3. When C4 is charged to the on-voltage of NMOS tube M6, M6 is turned on, and the cut-off voltage latch capacitors C1 and C2 are discharged through resistor R2. When the voltage of C2 is not enough to keep NMOS tube M5 turned on, M5 is turned off, so that the discharge circuit of C3 and C4 is turned off. Then ON becomes a high level, so that M7 is turned off, and the latching of the on-voltage is completed. At this time, since the sum of the voltages across C3 and C4 is always greater than the on-voltage of the main switches M1 and M2, the gate switch circuit remains on, and VIN and VOUT are connected. Similarly, OFF can control the gate switch circuit to remain in the off state. When it is necessary to excite a single array element [i, j], it is only necessary to set the data position corresponding to the index in Q to a high level and the other data positions to a low level, so that the gate switch circuit on the i-th row and j-th column can remain on, and the other row and column gate switch circuits remain in the off state. Then apply an excitation pulse signal to the row electrode, and the single array element [i, j] is excited to generate ultrasonic waves. By analogy, the excitation of different array elements in the array can be realized. When different time delays are applied to each gated excitation electrical signal, different forms of focused wavefronts can be generated to achieve the purpose of ultrasonic phased array electronic scanning. When some array elements are gated, the array's transmit aperture can be flexibly changed. Circuit connection relationship: The sources of NMOS tubes M1 and M2 are connected to form a main switch; the sources of NMOS tubes M3 and M4 are connected to form an auxiliary switch. The DC source DC, R5, R6, PMOS tubes M7 and M8 together form a controllable voltage source, whose output is controlled by ON and OFF signals. Diodes D1 and D2 and resistors R3 and R4 are connected in series to limit the current size and flow direction. Capacitor C2 is connected in parallel between the gate and source of NMOS tube M5 to control the working state of M5; the connection relationship between capacitor C4 and NMOS tube M6 is the same. Resistors R1 and R2 are connected in series to the drains of M5 and M6 respectively for current limiting. Capacitors C3 and C4 are connected in series between the gate and source of the main switch to determine the working state of the main switch. At the connection point of the source of the main switch, the auxiliary switch is connected in series through the current limiting resistor R7. Diode D5 and resistor R8 are connected in parallel between the gate and source of the auxiliary switch to control the working state of the auxiliary switch.

[0032] Figure 2 The ultrasonic sensor array structure is the target of the present invention. The ultrasonic sensor array includes sensor elements, row electrodes and column electrodes. The elements are made of piezoelectric ceramic sheets and are cut mechanically. The elements are square in structure and have equal sizes and spacings, which are 0.9 mm and 1 mm, respectively. Then, conductive silver paste is applied to the upper and lower surfaces of the elements, and the row electrodes and column electrodes are embossed on the upper and lower surfaces of the elements to combine them into a whole. The gaps between the elements are filled with insulating sound-absorbing materials to reduce crosstalk between the elements. Only when both the row electrodes and the column electrodes are enabled can an effective electrical circuit be generated, and the excitation pulse can generate an ultrasonic signal on the surface of the elements through the inverse piezoelectric effect. Similarly, the elements need to enable both the row electrodes and the column electrodes at the same time to receive the echo signal.

[0033] Figure 3 The excitation pulse transmitting circuit used in the example of the present invention adopts the form of generating sharp pulses with capacitors as energy storage elements. When the control end is at a low level, the MOS tube is not turned on. At this time, the high voltage source and capacitor C charge the energy storage capacitor C0 through resistor R. When the control end becomes a high level, the MOS tube is turned on. At this time, the left side of capacitor C0 is connected to the reference ground, and a negative high voltage is generated at the output end. The adjustable resistor R plays the role of array element impedance matching, adjusting pulse delay and amplitude. The diode D stipulates the return path, limiting the output end to only generate negative pulses.

[0034] Figure 4 The present invention illustrates the coding selection sequence decoding, edge detection and power amplifier circuit, which adopts the form of integrated chip to improve the portability of the circuit and facilitate the later expansion to adapt to a larger sensor array. The clock frequency of the decoding circuit determines the selection frequency of the selection switch circuit. The pulse width generated by the edge detection circuit is adjusted by changing the feedback capacitor and resistor of the edge signal detection circuit.

[0035] Figure 5 This is the circuit control timing diagram of the present invention, showing the conduction and cutoff process of a single gate switch circuit. Before time A, the gate switch circuit is in the initial state. At this time, when a bipolar pulse train signal VIN is applied to the input end, it is greatly attenuated to VOUT through the gate switch circuit. At time A, the switch signal SW changes from 0 to 1, forming a rising edge, the edge detection circuit generates a square wave pulse signal ON, capacitors C3 and C4 are charged, the gate switch circuit is turned on, and the output end VOUT signal follows the input signal VIN. At time B, SW changes from 1 to 0, forming a falling edge, the edge detection circuit generates an OFF signal, capacitors C1 and C2 are charged, the gate switch circuit is cut off, and the VOUT signal is greatly attenuated again. Similarly, at time C, the gate switch circuit is switched to the on state.

[0036] Figure 6 The original waveform of the excitation pulse and the waveform at the end of the excitation pulse are shown in the following figure. Figure 3 The described excitation circuit generates a sharp pulse such as Figure 6 As shown in (a), the pulse amplitude is -56V and the pulse width is 1μs. When the row selection switch circuit where the array element is located is turned off and the column selection switch circuit remains on, the pulse waveform at the time of cutoff is measured as follows Figure 6 (b) At this time, the pulse amplitude is attenuated to -0.2V, and the pulse width is also greatly reduced, which shows that the gate switch circuit shown in the present invention has good pulse isolation performance.

[0037] Figure 7 To illustrate the different aperture excitation echo signals of the present invention, an aluminum test block with a 4mm diameter through hole in the middle is selected as a defective test block. The single array element, the entire row array, the entire column array and all the array elements are addressed and gated to generate ultrasonic arrays with different apertures, and ultrasonic echo signals are received by a single array element. As the number of gated array elements increases, the ultrasonic signal generated by the excitation becomes stronger, and the defect signal received by the single array element is significantly enhanced. In addition, the defect signal in the echo signal is located in the middle of the initial wave and the bottom echo, which is consistent with the actual object.

[0038] The method and circuit for fast switching bipolar pulse excitation signals for row and column addressing arrays of the present invention have the following characteristics:

[0039] S1. This method can select any row electrode to connect it to the excitation pulse source, and select any column electrode to connect it to the reference ground. When an excitation pulse is applied to the row electrode, only the array element where the row and column meet will be excited. Similarly, any array element in the sensor array can be excited.

[0040] S2. This method can effectively turn on or block the bipolar excitation pulse signal, and the gate switch circuit has a smaller on-state attenuation and a larger off-state attenuation, while being able to sustainably maintain the on and off states.

[0041] S3. This method adopts a modular design and can be expanded through multi-channel cascading to adapt to larger-scale row-column addressing ultrasonic sensor arrays. The circuit control method is simple, and the switching characteristics involved can be flexibly adjusted by modifying component parameters according to actual needs.

[0042] The description in the examples is only a specific demonstration of the feasibility of the present invention and is not intended to limit the protection scope of the present invention. Any equivalent implementation or modification that does not deviate from the technical spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for fast switching bipolar pulse excitation signals for row and column addressing ultrasonic sensor arrays, characterized in that: It mainly includes the following steps: Step 1, the bipolar pulse switch circuit includes two input signals and one output signal; wherein the two input signals are the coded selection sequence signal Q and the pulse input signal VIN, and the output signal is the pulse output signal VOUT; Q is connected to the control signal terminal, VIN is connected to the signal transmitting terminal, and VOUT is connected to the signal receiving terminal; Step 2, the decoding circuit decodes Q to obtain the switch signal SW of each channel, and then the edge detection circuit receives SW to generate a set of square wave pulse signals with adjustable pulse width, and obtains the gating control signals ON and OFF after power amplification; Step 3, when the gate switch circuit is in the off state, the ON signal is set to a low level, the PMOS tube M7 is turned on, and the DC source DC charges the on-voltage latch capacitors C3 and C4 through the diode D1 and the current limiting resistor R3; when the capacitor C4 is charged to the on-voltage of the NMOS tube M6, M6 is turned on, and the off-voltage latch capacitors C1 and C2 are discharged through the resistor R2; when the voltage of C2 is not enough to keep the NMOS tube M5 turned on, M5 is turned off, so that the discharge loop of C3 and C4 is turned off; ON is set to a high level to turn off M7, and the latching of the on-voltage is completed. At this time, since the sum of the voltages at both ends of C3 and C4 is always greater than the on-voltage of the main switches M1 and M2, the gate switch circuit remains in the on state, and VIN and VOUT are in a connected state; Step 4: when the gate switch circuit is in the on state, the OFF signal is set to a low level, the PMOS tube M8 is turned on, and the DC source DC charges the cut-off voltage latch capacitors C1 and C2 through the diode D2 and the current limiting resistor R4; when the voltage of C2 is greater than the on voltage of the NMOS tube M5, M5 is turned on, and the on voltage latch capacitors C3 and C4 are discharged through the resistor R1; when the sum of the voltages across C3 and C4 is less than the cut-off voltage of the main switches M1 and M2, the gate switch circuit is turned off and presents a high impedance state, and VIN is disconnected from VOUT; at this time, since the voltage of C4 is not enough to keep the NMOS tube M6 turned on, M6 is turned off, so that the discharge loop of C1 and C2 is turned off; then the OFF signal is set to a high level to turn off M8, so that the latching of the cut-off voltage is completed, and the gate switch circuit remains in the off state; Step 5: The selection switch circuit composed of NMOS tubes M1 and M2 can meet the conventional industrial ultrasonic detection excitation frequency requirements. The upper limit of the excitation pulse frequency can be increased by adding auxiliary switch NMOS tubes M3 and M4.

2. A method according to claim 1, characterized in that In step 1, only one signal Q is needed to quickly control the on and off of the bipolar pulse signal; Q includes switch signals SW of multiple channels, which are generated by the microcontroller MCU to control the signal end; the signal transmitting end signal is generated by the excitation pulse circuit, and the signal receiving end is connected to the row and column switch electrode circuits in the sensor array.

3. A method according to claim 1, characterized in that In step 2, the decoding circuit decodes Q to obtain SW of each channel, and the edge detection circuit detects the level change of SW. When SW jumps from a low level to a high level (rising edge trigger), the circuit outputs a square wave pulse signal, which is amplified by power to obtain ON; when SW jumps from a high level to a low level (falling edge trigger), the circuit outputs a square wave pulse signal, which is amplified by power to obtain OFF.

4. A method according to claim 1, characterized in that In step 3, when ON becomes a low level, a voltage drop occurs at both ends of R5, that is, a negative voltage is generated between the source and gate of the PMOS tube M7. When the turn-on voltage is met, the source and drain of M7 are connected, and the DC source DC charges C3 and C4 through D1 and R3; C3 and C4 are in a voltage-dividing relationship, and the maximum voltage allocated to C4 should be slightly higher than the turn-on voltage of M6; after M6 is turned on, C1 and C2 are discharged through R2; C1 and C2 also meet the voltage-dividing relationship, and the maximum voltage allocated to C2 should be slightly higher than the turn-on voltage of M5, and through R2 During discharge, M5 can quickly enter the cut-off state, reducing the time for switching the state of the gate switch circuit; setting ON to a high level turns off M7, and C3 and C4 cannot discharge reversely to DC through D1, and there is no other discharge loop, so the latching of the on-voltage is completed; at this time, the sum of the voltages across C3 and C4 is always greater than the on-voltage of the main switches M1 and M2, and the gate switch circuit can remain in the on-state; the DC level has nothing to do with VIN, and it only needs to meet the on or off voltage of PMOS and NMOS.

5. A method according to claim 1, characterized in that: In the step 5, the sources of M1 and M2 in the gating switch circuit are connected to form a main switch, and the sources of M3 and M4 are connected to form an auxiliary switch, thereby improving the cutoff performance of high-frequency signals; the circuit design of connecting the sources of NMOS tubes enables the gating switch circuit to have the ability to block bipolar pulses.

6. A fast switching bipolar pulse excitation signal circuit for row and column addressing ultrasonic sensor array, characterized in that: It mainly includes coding selection sequence decoding circuit, edge detection circuit and row and column selection switch circuit; The coding selection sequence decoding circuit is composed of a shift register and a peripheral circuit, and the input signal Q generated by the microcontroller MCU according to the ultrasonic excitation method is matched with the clock signal CLK and the enable signal EN generated by the MCU to generate the SW of each channel; wherein the high and low levels of SW respectively represent the conduction and cutoff of the selection switch circuit; the coding selection sequence decoding circuit can expand the number of channels in the form of shift register cascade to meet the gating requirements of a larger sensor array; The edge detection circuit is composed of a pair of re-triggerable monostable multivibrator and a power amplifier circuit, which outputs a square wave pulse signal at the rising edge and falling edge of SW respectively, and obtains ON and OFF after power amplification; the square wave pulse width is adjusted by changing the feedback capacitor and resistor of the edge detection circuit, and the pulse width should be greater than the charging time of the opening and closing latch capacitor in the gate switch circuit in principle; The row and column selection switch circuits have the same structure and can be collectively referred to as selection switch circuits; in the selection switch circuit, the sources of M1 and M2 are connected to form a main switch, and the sources of M3 and M4 are connected to form an auxiliary switch; the use of the main and auxiliary switches connected by the sources can ensure that the signal distortion of the bipolar pulse signal is reduced when passing through the selection switch circuit; when the selection switch circuit is in the on state, VIN passes through M1 and M2 and outputs VOUT at the output end. Since the on-resistance of the main switch is low, VIN passes through with almost no attenuation, and the auxiliary switch does not work at this time; when the selection switch circuit is in the off state, a part of VIN is discharged through the discharge circuits of M3 and M4, thereby reducing the impact on the output load and improving the cut-off performance of the high-frequency bipolar pulse excitation signal.

7. A circuit according to claim 6, characterized in that: The smaller the inherent parasitic capacitance of M1 and M2, the greater the blocking and attenuation of the pulse excitation signal, and the faster the switch response speed; the smaller the internal on-resistance, the smaller the signal attenuation during conduction.

8. A circuit according to claim 6, characterized in that: Whether the gate switch circuit remains in the on or off state depends on the voltage distribution on capacitors C1 to C4, where C1 and C2 are cut-off voltage latching capacitors that latch the voltage required for the gate switch circuit to be cut off; C3 and C4 are on-voltage latching capacitors that latch the voltage required for the gate switch circuit to be turned on, and the latching voltage is not affected by the output pulse excitation voltage; increasing the capacitance value of C1 to C4 is beneficial to maintaining the on and off states of the gate switch circuit, and enhances the signal attenuation during cut-off.

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