Clock signal bootstrap circuit, cascade circuit, chip and electronic equipment

Abstract

The invention relates to the technical field of integrated circuits, and provides a clock signal bootstrap circuit, a cascade circuit, a chip and electronic equipment. The clock signal bootstrap circuit comprises a first bootstrap module, the first bootstrap module comprises a first transistor, a second transistor, a third transistor and a first capacitor, a first pole of the first transistor is connected with a first pole of the second transistor and serves as a first input end, and a second pole of the first transistor is connected with a first end of the first capacitor and serves as a second input end. The third electrode of the first transistor is connected with the third electrode of the second transistor and the first electrode of the third transistor and serves as an output end, the second electrode of the second transistor is connected with the second electrode of the third transistor and the second end of the first capacitor, and the third electrode of the third transistor is connected with power supply voltage; the first bootstrap module receives the first clock signal and the second clock signal and outputs a third clock signal. The clock signal bootstrap circuit can reduce electric leakage, thereby improving bootstrap efficiency and reducing power consumption.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a clock signal bootstrap circuit, a cascade circuit, a chip, and an electronic device. Background Art

[0002] Some devices in integrated circuits, such as switches, are driven by clock signals. The swing of the clock signal determines the driving ability of the clock signal and also determines the conduction performance of the driven switch. Therefore, in order to improve the performance of the integrated circuit, it is necessary to increase the swing of the clock signal.

[0003] Some integrated circuits are provided with a clock signal bootstrap circuit to increase the swing of the clock signal. However, most of the clock signal bootstrap circuits proposed in the prior art have leakage problems or voltage division problems, resulting in low efficiency of clock signal bootstrap and high power consumption. Summary of the invention

[0004] In view of this, the present disclosure proposes a clock signal bootstrap circuit, a cascade circuit, a chip, and an electronic device. The clock signal bootstrap circuit of the embodiment of the present disclosure can reduce leakage, thereby improving the bootstrap efficiency of the clock signal bootstrap circuit and reducing power consumption.

[0005] According to one aspect of the present disclosure, a clock signal bootstrap circuit is provided, the circuit comprising a first bootstrap module, the first bootstrap module comprising a first transistor, a second transistor, a third transistor, and a first capacitor, the first electrode of the first transistor being connected to the first electrode of the second transistor and serving as the first input terminal of the first bootstrap module, the second electrode of the first transistor being connected to the first end of the first capacitor and serving as the second input terminal of the first bootstrap module, the third electrode of the first transistor being connected to the third electrode of the second transistor and the first electrode of the third transistor and serving as the output terminal of the first bootstrap module, the second electrode of the second transistor being connected to the second electrode of the third transistor and the second end of the first capacitor, and the third electrode of the third transistor being connected to a power supply voltage; the second input terminal of the first bootstrap module receives a first clock signal, the first input terminal of the first bootstrap module receives a second clock signal, the first clock signal and the second clock signal are a pair of differential signals, and the output terminal of the first bootstrap module outputs a third clock signal.

[0006] In a possible implementation, when the first clock signal is at a low level, the second and third electrodes of the first transistor are turned on, the second and third electrodes of the third transistor are turned on, the second and third electrodes of the second transistor are turned off and the gate-source voltage is greater than or equal to 0, the power supply voltage charges the first capacitor through the third transistor, and the third clock signal is at a low level; when the first clock signal is at a high level, the second and third electrodes of the first transistor are turned off and the gate-source voltage is less than 0, the second and third electrodes of the third transistor are turned off, the second and third electrodes of the second transistor are turned on, the first capacitor is discharged, the third clock signal is at a high level and the level of the third clock signal is greater than the level of the first clock signal; when the high level of the first clock signal is equal to the power supply voltage, when the second and third electrodes of the second transistor are turned off, the gate-source voltage of the second transistor is equal to 0; when the high level of the first clock signal is greater than the power supply voltage, when the second and third electrodes of the second transistor are turned off, the gate-source voltage of the second transistor is greater than 0.

[0007] In a possible implementation, the circuit further includes an inverter, an input end of the inverter is connected to the second input end of the first bootstrap module, an output end of the inverter is connected to the first input end of the first bootstrap module, and the second clock signal is generated by the inverter.

[0008] In a possible implementation, the circuit also includes a second bootstrap module, the second bootstrap module includes a fourth transistor, a fifth transistor, a sixth transistor, and a second capacitor, the first electrode of the fourth transistor is connected to the first electrode of the fifth transistor and serves as the first input end of the second bootstrap module, the second electrode of the fourth transistor is connected to the first end of the second capacitor and serves as the second input end of the second bootstrap module, the third electrode of the fourth transistor is connected to the third electrode of the fifth transistor and the first electrode of the sixth transistor and serves as the output end of the second bootstrap module, the second electrode of the fifth transistor is connected to the second electrode of the sixth transistor and the second end of the second capacitor, and the third electrode of the sixth transistor is connected to the power supply voltage; the first input end of the second bootstrap module is connected to the second input end of the first bootstrap module to receive the first clock signal, the second input end of the second bootstrap module is connected to the first input end of the first bootstrap module to receive the second clock signal, and the output end of the second bootstrap module outputs a fourth clock signal, and the third clock signal and the fourth clock signal are a pair of differential signals.

[0009] In a possible implementation, when the second clock signal is at a low level, the second and third electrodes of the fourth transistor are turned on, the second and third electrodes of the sixth transistor are turned on, the second and third electrodes of the fifth transistor are turned off and the gate-source voltage is greater than or equal to 0, the power supply voltage charges the second capacitor through the sixth transistor, and the fourth clock signal is at a low level; when the second clock signal is at a high level, the second and third electrodes of the fourth transistor are turned off and the gate-source voltage is less than 0, the second and third electrodes of the sixth transistor are turned off, the second and third electrodes of the fifth transistor are turned on, the second capacitor is discharged, the fourth clock signal is at a high level and the level of the fourth clock signal is greater than the level of the second clock signal; when the high level of the second clock signal is equal to the power supply voltage, when the second and third electrodes of the fifth transistor are turned off, the gate-source voltage of the fifth transistor is equal to 0; when the high level of the second clock signal is greater than the power supply voltage, when the second and third electrodes of the fifth transistor are turned off, the gate-source voltage of the fifth transistor is greater than 0.

[0010] In a possible implementation, the circuit also includes an inverter, an input end of the inverter is connected to the second input end of the first bootstrap module and the first input end of the second bootstrap module, an output end of the inverter is connected to the first input end of the first bootstrap module and the second input end of the second bootstrap module, and the second clock signal is generated by the inverter.

[0011] In a possible implementation manner, the level of the power supply voltage is lower than a first threshold.

[0012] According to another aspect of the present disclosure, a cascade circuit is provided, which includes at least one stage of clock signal bootstrap circuit, and each stage of the clock signal bootstrap circuit respectively includes the clock signal bootstrap circuit described above; wherein, the clock signal output by the previous stage clock signal bootstrap circuit is used as the clock signal input by the subsequent stage clock signal bootstrap circuit, the high level of the first clock signal received by the first stage clock signal bootstrap circuit is equal to the power supply voltage, and the high level of the first clock signal received by the second stage and subsequent clock signal bootstrap circuits is greater than the power supply voltage.

[0013] According to another aspect of the present disclosure, a chip is provided, comprising the above-mentioned cascade circuit.

[0014] According to another aspect of the present disclosure, an electronic device is provided, comprising the chip described above.

[0015] According to the clock signal bootstrap circuit of the embodiment of the present disclosure, it is only necessary to set a first bootstrap module including a first transistor, a second transistor, a third transistor, and a first capacitor, so that the first electrode of the first transistor is connected to the first electrode of the second transistor and serves as the first input end of the first bootstrap module, the second electrode of the first transistor is connected to the first end of the first capacitor and serves as the second input end of the first bootstrap module, the third electrode of the first transistor is connected to the third electrode of the second transistor and the first electrode of the third transistor and serves as the output end of the first bootstrap module, the second electrode of the second transistor is connected to the second electrode of the third transistor and the second end of the first capacitor, the third electrode of the third transistor is connected to the power supply voltage, and the second input end receives the first clock signal, the first input end receives the second clock signal, the first clock signal and the second clock signal are a pair of differential signals, and the third clock signal can be output at the output end of the first bootstrap module. The clock signal bootstrap circuit further reduces the number of transistors and capacitors, thereby reducing the cost of the circuit. When the first clock signal is at a low level, if the second and third electrodes of the first transistor are turned on, the second and third electrodes of the third transistor are turned on, and the second and third electrodes of the second transistor are turned off, and the power supply voltage charges the first capacitor through the third transistor, then the third clock signal may be at a low level, and the gate-source voltage of the third transistor may be greater than or equal to 0; when the first clock signal is at a high level, if the second and third electrodes of the first transistor are turned off, the second and third electrodes of the third transistor are turned off, the second and third electrodes of the second transistor are turned on, and the first capacitor is discharged, then the third clock signal may be at a high level and the level of the third clock signal is greater than the level of the first clock signal, and the gate-source voltage of the first transistor may be less than 0. The second and third electrodes of the second transistor are turned off and the gate-source voltage is greater than 0, which can reduce the leakage degree of the first transistor, and the second and third electrodes of the first transistor are turned off and the gate-source voltage is less than 0, which can reduce the leakage degree of the first transistor, so that the voltage value of the third clock signal is higher, thereby improving the bootstrap efficiency of the clock signal bootstrap circuit and reducing power consumption.

[0016] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0018] Figure 1 A schematic diagram showing the structure of a clock signal bootstrap circuit proposed in the prior art.

[0019] Figure 2 A schematic diagram showing the structure of a clock signal bootstrap circuit proposed in the second prior art.

[0020] Figure 3 A schematic diagram showing the structure of a clock signal bootstrap circuit proposed in prior art three.

[0021] Figure 4 An exemplary application scenario of the clock signal bootstrap circuit according to an embodiment of the present disclosure is shown.

[0022] Figure 5 A schematic diagram showing the structure of a clock signal bootstrap circuit according to an embodiment of the present disclosure.

[0023] Figure 6 A schematic diagram showing the structure of a clock signal bootstrap circuit according to an embodiment of the present disclosure.

[0024] Figure 7 A schematic diagram showing the structure of a clock signal bootstrap circuit according to an embodiment of the present disclosure.

[0025] Figure 8 A schematic diagram showing the structure of a clock signal bootstrap circuit according to an embodiment of the present disclosure.

[0026] Fig. 9 A schematic diagram showing the structure of a cascade circuit according to an embodiment of the present disclosure.

[0027] Fig.10 A schematic diagram showing the structure of an analog-to-digital conversion circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0029] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0030] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0031] Several clock signal bootstrap circuits proposed in the prior art are introduced below.

[0032] Figure 1 A schematic diagram showing the structure of a clock signal bootstrap circuit proposed in the prior art.

[0033] like Figure 1 As shown in the figure, CLK is the input clock signal, and its voltage value is 0~VDD. bst is the output clock signal. V in is the input voltage signal, whose voltage value is equal to VDD. CLKB is the clock signal opposite to CLK. Transistor T8 and transistor T9 form an inverter.

[0034] When CLK=0, transistor T8 is turned on, transistor T9 is turned off, and the inverter outputs a high-level signal to the gate of transistor T2, causing transistor T2 to turn off. When CLK=0, CLKB=VDD, and transistor T7 is turned on. Since transistor T6 is continuously turned on, the gate of transistor T1 is at a low level, causing transistor T1 to also turn on. When CLKB is at a high level, transistor T5 is also turned on, so the power supply voltage VDD, transistor T1, and capacitor C B , transistor T5, and ground form a path for capacitor C B Charge, so that the capacitor C B The upper voltage is VDD, and the lower voltage is 0. At this time, CLK bst =0, transistors T3 and T4 are both turned off.

[0035] When CLK=VDD, transistor T8 is turned off, transistor T9 is turned on, and the inverter outputs a low-level signal to the gate of transistor T2, turning on transistor T2. CLKB=0, transistors T5 and T7 are turned off. The gates of transistors T1, T3, and T4 are at a high level, turning off transistor T1 and turning on transistors T3 and T4. in Through transistor T4, it is accumulated to capacitor C B The lower end of the capacitor C B The upper end of the voltage level is raised to 2VDD. In this case, CLK bst =2VDD.

[0036] In the bootstrap circuit of the prior art, in addition to the inverter, 7 transistors are required. These transistors have parasitic capacitance. The parasitic capacitance and the capacitance C B Producing voltage division will reduce CLK bst The voltage (ie CLK bst The high level of the MOSFET cannot reach 2VDD), which reduces the efficiency of the bootstrap. In addition, 7 transistors means a larger chip area and higher chip cost.

[0037] Figure 2 A schematic diagram showing the structure of a clock signal bootstrap circuit proposed in the second prior art.

[0038] like Figure 2 As shown in the figure, CLK is the input clock signal, and its voltage value is 0~VDD. bstis the output clock signal.

[0039] When CLK = VDD, the inverter output is 0, V2 = VDD. At this time, the gate voltage of transistors Q3 and Q4 is VDD, so Q3 is not turned on, Q4 is turned on, and CLK bst It is pulled down to 0V by Q4.

[0040] When CLK = 0, the inverter output is VDD, V2 = 2VDD, at this time the gate voltage of transistors Q3 and Q4 is 0, so Q3 is turned on, and Q4 is not turned on, CLK bst Pull up to 2VDD through Q3.

[0041] Transistors Q1 and Q2 form a pair of positive feedback latches, which can make V2 latch to the voltage value of VDD and 2VDD more quickly. A , C B It plays the role of AC coupling.

[0042] Figure 2 The bootstrap circuit uses two capacitors, which usually occupy a large chip area, which increases the chip area cost. When CLK = VDD, theoretically CLK bst =2VDD, but from the output CLK bst There is a discharge (leakage) path through transistors Q3 and Q2 to the power supply voltage VDD. bst There is also a discharge (leakage) path to ground through transistor Q4. The gate-source voltage V GS are all 0. This will cause CLK bst Especially when VDD is low, for example, when VDD=0.3V, V GS = 0V, the on-resistance of transistors Q2 and Q4 may be as low as kilo-ohm (kΩ) level, and the impact of leakage current will be very serious, so Figure 2 The bootstrap circuit is actually not applicable in scenarios with low power supply voltage.

[0043] Figure 3 A schematic diagram showing the structure of a clock signal bootstrap circuit proposed in prior art three.

[0044] like Figure 3 As shown in the figure, CLK is the input clock signal, and its voltage value is 0~VDD. bst is the output clock signal. Transistors G4 and G5 form an inverter.

[0045] When CLK = VDD, the inverter output is 0. Transistor G1 is turned on, transistor G2 is turned off, and CLK bst=0. Transistor G3 is turned on, and the power supply voltage VDD is the capacitor C B Charge, making V CB =VDD.

[0046] When CLK = 0, the inverter output is VDD, V CB =2VDD. Transistor G1 is turned off, transistor G2 is turned on, transistor G3 is turned off, CLK bst =2VDD.

[0047] Figure 3 Although the bootstrap circuit only uses one capacitor, it still has leakage problems. The reason is that when CLK = VDD, the source voltage of G2 is VDD, the drain voltage is 0, the gate voltage is VDD, and the gate-source voltage V GS =0, there will be a leakage of about several hundred nanoamperes (nA). When CLK = 0V, the gate voltage of G1 is VDD, the source voltage is VDD, the drain voltage is 2VDD, and the gate-source voltage V GS =0, there will be a leakage of about several hundred nanoamperes (nA).

[0048] In summary, the clock signal bootstrap circuit proposed in the prior art has leakage problems or voltage division problems, resulting in low bootstrap efficiency and high power consumption.

[0049] In view of this, the present disclosure proposes a clock signal bootstrap circuit, a cascade circuit, a chip, and an electronic device. The clock signal bootstrap circuit of the embodiment of the present disclosure can reduce leakage, thereby improving the bootstrap efficiency of the clock signal bootstrap circuit and reducing power consumption.

[0050] Figure 4 An exemplary application scenario of the clock signal bootstrap circuit according to an embodiment of the present disclosure is shown.

[0051] like Figure 4 As shown, the clock signal bootstrap circuit of the embodiment of the present disclosure can be arranged on a chip. The chip can also include a clock signal generating circuit and a circuit that needs to be driven by a high-swing clock signal, such as an analog-to-digital conversion circuit.

[0052] The clock signal generating circuit can generate a clock signal with a low swing (such as the first clock signal described below) and input it to the clock signal bootstrap circuit. The clock signal bootstrap circuit can output a clock signal with a high swing (such as the third clock signal described below) for driving the analog-to-digital conversion circuit. The analog-to-digital conversion circuit converts the input analog signal into a digital signal.

[0053] The chip can be set in an electronic device (such as an Internet of Things device). The electronic device can support multiple power supply methods, such as battery power supply, solar power supply, cable power supply, wireless charging and energy harvesting (Energy Harvesting, EH), etc. Among them, energy harvesting refers to the use of surrounding environmental energy, such as solar energy, wind energy, mechanical vibration or temperature difference, to reduce dependence on batteries. The embodiments of the present disclosure do not limit the power supply method of the electronic device.

[0054] Figure 5 A schematic diagram showing the structure of a clock signal bootstrap circuit according to an embodiment of the present disclosure.

[0055] like Figure 5 As shown, in a possible implementation, the circuit includes a first bootstrap module 51, and the first bootstrap module 51 includes a first transistor M1, a second transistor M2, a third transistor M3, and a first capacitor C1.

[0056] The first electrode m11 of the first transistor is connected to the first electrode m21 of the second transistor and serves as the first input terminal w11 of the first bootstrap module, the second electrode m12 of the first transistor is connected to the first terminal c11 of the first capacitor and serves as the second input terminal w12 of the first bootstrap module, the third electrode m13 of the first transistor is connected to the third electrode m23 of the second transistor and the first electrode m31 of the third transistor and serves as the output terminal w13 of the first bootstrap module, the second electrode m22 of the second transistor is connected to the second electrode m32 of the third transistor and the second terminal c12 of the first capacitor, and the third electrode m33 of the third transistor is connected to the power supply voltage VDD;

[0057] The second input terminal w12 of the first bootstrap module receives the first clock signal CLK P The first input terminal w11 of the first bootstrap module receives the second clock signal CLK N , the first clock signal CLK P and the second clock signal CLK N is a pair of differential signals, the output terminal w13 of the first bootstrap module outputs the third clock signal CLK BSTP .

[0058] For example, the clock signal bootstrap circuit may include at least a first bootstrap module. The first bootstrap module may include three transistors and a capacitor. The first transistor may be an N-channel transistor, and the second transistor and the third transistor may be P-channel transistors. The first electrode of each transistor may be a gate, the second electrode may be a source, and the third electrode may be a drain. The first clock signal CLK P It can be a low-swing clock signal input from the clock signal bootstrap circuit, and its voltage value can be 0~V clk . V clkcan be greater than or equal to the power supply voltage VDD. clk There is no restriction on the specific value of .

[0059] The second clock signal CLK N The clock signal may be input from outside the clock signal bootstrap circuit, or may be generated inside the clock signal bootstrap circuit, which is not limited in the embodiments of the present disclosure.

[0060] Since the first clock signal CLK P and the second clock signal CLK N It is a pair of differential signals. The first clock signal CLK P The voltage value is 0~V clk , so CLK P = 0 when CLK N =V clk , that is, when the first clock signal is at a low level, the second clock signal is at a high level. Similarly, CLK P =V clk CLK N =0, that is, when the first clock signal is at a high level, the second clock signal is at a low level.

[0061] The third clock signal CLK is introduced below BSTP The level of the first clock signal CLK P and the second clock signal CLK N relationship.

[0062] In a possible implementation, the first clock signal CLK P When the voltage is low, the second electrode m12 and the third electrode m13 of the first transistor are turned on, the second electrode m32 and the third electrode m33 of the third transistor are turned on, the second electrode m22 and the third electrode m23 of the second transistor are turned off, and the gate-source voltage is greater than or equal to 0, the power supply voltage VDD charges the first capacitor C1 through the third transistor, and the third clock signal CLK BSTP is low level;

[0063] The first clock signal CLK P When the voltage is high, the second electrode m12 and the third electrode m13 of the first transistor are disconnected and the gate-source voltage is less than 0, the second electrode m32 and the third electrode m33 of the third transistor are disconnected, the second electrode m22 and the third electrode m23 of the second transistor are turned on, the first capacitor C1 is discharged, and the third clock signal CLK BSTP is high level and the third clock signal CLK BSTP The level is greater than the first clock signal CLK P The level of

[0064] The first clock signal CLK PWhen the high level of is equal to the power supply voltage, when the second electrode and the third electrode of the second transistor are disconnected, the gate-source voltage of the second transistor is equal to 0;

[0065] The first clock signal CLK P When the high level of is greater than the power supply voltage, when the second electrode and the third electrode of the second transistor are disconnected, the gate-source voltage of the second transistor is greater than 0.

[0066] See also Figure 5 Since the first terminal c11 of the first capacitor receives the first clock signal CLK P , so CLK P =0, the voltage at the first terminal c11 of the first capacitor is 0.

[0067] The first electrode m11 of the first transistor receives the second clock signal CLK N The second electrode m12 of the first transistor receives the first clock signal CLK P , so CLK P =0, the voltage of the first electrode m11 of the first transistor is V clk , the voltage of the second electrode m12 is 0. The first transistor is an N-channel transistor, so the second electrode m12 and the third electrode m13 of the first transistor are turned on. The third electrode m13 of the first transistor outputs the third clock signal CLK BSTP , so the third clock signal CLK BSTP The voltage value is also 0.

[0068] The first electrode m21 of the second transistor receives the second clock signal CLK N , so CLK P = 0, the voltage of the first electrode m21 of the second transistor is V clk The second transistor is a P-channel transistor, so the second electrode m22 and the third electrode m23 of the second transistor are disconnected.

[0069] The third transistor is a P-channel transistor and CLK BSTP =0, so the second terminal m32 and the third terminal m33 of the third transistor are turned on. At this time, the power supply voltage VDD charges the first capacitor C1 through the third transistor M3, so that the voltage at the second end c12 of the first capacitor C1 is VDD.

[0070] The second end c12 of the first capacitor C1 is connected to the second electrode m22 of the second transistor, so the voltage of the second electrode m22 of the second transistor is also VDD. clk is greater than or equal to the power supply voltage VDD, so the gate-source voltage of the second transistor (V clk -VDD) is greater than or equal to 0.

[0071] In this case, as long as V clk>VDD, the gate-source voltage of the second transistor will be greater than 0. When the second transistor is a P-channel transistor, the leakage level of the second transistor will be greatly reduced.

[0072] In this way, when the first clock signal is at a high level, the leakage level of the clock signal bootstrap circuit is reduced, thereby reducing the power consumption of the clock signal bootstrap circuit.

[0073] Similarly, CLK P =V clk When the voltage at the first terminal c11 of the first capacitor is VDD, the voltage at the second terminal c12 of the first capacitor reaches VDD+V clk .

[0074] CLK P =V clk CLK N =0, that is, the first clock signal CLK P When the second clock signal CLK is high, N is low level.

[0075] The first electrode m11 of the first transistor receives the second clock signal CLK N The second electrode m12 of the first transistor receives the first clock signal CLK P , so CLK P =V clk When the voltage of the first electrode m11 of the first transistor is 0, the voltage of the second electrode m12 is V clk The first transistor is an N-channel transistor, and thus the second electrode m12 and the third electrode m13 of the first transistor are disconnected.

[0076] The first electrode m21 of the second transistor receives the second clock signal CLK N , so CLK P =V clk When , the voltage of the first electrode m21 of the second transistor is 0. The second transistor is a P-channel transistor, so the second electrode m22 and the third electrode m23 of the second transistor are turned on.

[0077] The voltage at the second terminal c12 of the first capacitor is equal to VDD+V clk , when the second and third electrodes of the second transistor are turned on, if leakage is not considered, the voltage of the third electrode m23 of the second transistor and the first electrode m31 of the third transistor is also equal to VDD+V clk ,CLK BSTP =VDD+V clk The third transistor is a P-channel transistor, so the second electrode m32 and the third electrode m33 of the third transistor are disconnected.

[0078] At this time, the voltage difference between the second electrode m12 and the third electrode m13 of the first transistor is VDD, so the first transistor has leakage. However, since the voltage of the first electrode m11 of the first transistor is equal to 0, the voltage of the second electrode m12 is equal to V clk Therefore, the gate-source voltage of the first transistor is less than 0. When the first transistor is an N-channel transistor, the leakage level of the first transistor will be greatly reduced.

[0079] Those skilled in the art should understand that the embodiments of the present disclosure do not limit the type of each transistor, nor the type of each pole of each transistor, as long as the leakage level of at least one of the first transistor and the second transistor is reduced when not turned on.

[0080] According to the clock signal bootstrap circuit of the embodiment of the present disclosure, it is only necessary to set a first bootstrap module including a first transistor, a second transistor, a third transistor, and a first capacitor, so that the first electrode of the first transistor is connected to the first electrode of the second transistor and serves as the first input end of the first bootstrap module, the second electrode of the first transistor is connected to the first end of the first capacitor and serves as the second input end of the first bootstrap module, the third electrode of the first transistor is connected to the third electrode of the second transistor and the first electrode of the third transistor and serves as the output end of the first bootstrap module, the second electrode of the second transistor is connected to the second electrode of the third transistor and the second end of the first capacitor, the third electrode of the third transistor is connected to the power supply voltage, and the second input end receives the first clock signal, the first input end receives the second clock signal, the first clock signal and the second clock signal are a pair of differential signals, and the third clock signal can be output at the output end of the first bootstrap module. The clock signal bootstrap circuit further reduces the number of transistors and capacitors, thereby reducing the cost of the circuit. When the first clock signal is at a low level, if the second and third electrodes of the first transistor are turned on, the second and third electrodes of the third transistor are turned on, and the second and third electrodes of the second transistor are turned off, and the power supply voltage charges the first capacitor through the third transistor, then the third clock signal may be at a low level, and the gate-source voltage of the third transistor may be greater than or equal to 0; when the first clock signal is at a high level, if the second and third electrodes of the first transistor are turned off, the second and third electrodes of the third transistor are turned off, the second and third electrodes of the second transistor are turned on, and the first capacitor is discharged, then the third clock signal may be at a high level and the level of the third clock signal is greater than the level of the first clock signal, and the gate-source voltage of the first transistor may be less than 0. The second and third electrodes of the second transistor are turned off and the gate-source voltage is greater than 0, which can reduce the leakage degree of the first transistor, and the second and third electrodes of the first transistor are turned off and the gate-source voltage is less than 0, which can reduce the leakage degree of the first transistor, so that the voltage value of the third clock signal is higher, thereby improving the bootstrap efficiency of the clock signal bootstrap circuit and reducing power consumption.

[0081] In a possible implementation manner, the level of the power supply voltage is lower than a first threshold.

[0082] It is understandable that the lower the power supply voltage of the clock signal bootstrap circuit, the greater the impact of leakage on the clock signal bootstrap circuit. The clock signal bootstrap circuits shown in the second and third prior arts have more leakage and are difficult to be applied in scenarios with lower power supply voltage.

[0083] Since the clock signal bootstrap circuit of the embodiment of the present disclosure can significantly reduce leakage, it can be applied in a scenario where the power supply voltage of the clock signal is low (for example, lower than the first threshold). The power supply voltage is the power supply voltage of the clock signal bootstrap circuit, so the clock signal bootstrap circuit of the embodiment of the present disclosure can be applied in a scenario where the power supply voltage is less than the first threshold. The value of the first threshold can be set according to the application scenario requirements, for example, set to 0.3V. The embodiment of the present disclosure does not limit the specific value of the first threshold.

[0084] In this way, the adaptability of the clock signal bootstrap circuit to different scenarios can be improved.

[0085] Figure 6-Figure 8 A schematic diagram showing the structure of a clock signal bootstrap circuit according to an embodiment of the present disclosure.

[0086] If the clock signal generating circuit can directly generate a differential clock signal, and the circuit to be driven only requires a single-ended clock signal, then Figure 5 The clock signal bootstrap circuit shown can meet the requirements. At this time, the first input terminal and the second input terminal of the first bootstrap module can be used as two input terminals of the clock signal bootstrap circuit respectively, and the output terminal of the first bootstrap module can be used as the output terminal of the clock signal bootstrap circuit.

[0087] If the clock signal generating circuit can only generate a single-ended clock signal, and the circuit to be driven only requires a single-ended clock signal, you can use Figure 6 The clock signal bootstrap circuit shown.

[0088] If the clock signal generating circuit can directly generate a differential clock signal, and the circuit to be driven also requires a differential clock signal, then Figure 7 The clock signal bootstrap circuit shown.

[0089] If the clock signal generating circuit can only generate a single-ended clock signal, and the circuit to be driven requires a differential clock signal, you can use Figure 8 The clock signal bootstrap circuit shown.

[0090] The following will introduce Figure 6-Figure 8 The working principle of the clock signal bootstrap circuit is shown.

[0091] like Figure 6As shown, in a possible implementation, the circuit also includes an inverter, the input end of the inverter is connected to the second input end w12 of the first bootstrap module, the output end of the inverter is connected to the first input end w11 of the first bootstrap module, and the second clock signal is generated by the inverter.

[0092] At this time, the input end of the inverter and the second input end of the first bootstrap module can be used together as the input end of the clock signal bootstrap circuit, and the output end of the first bootstrap module can be used as the output end of the clock signal bootstrap circuit.

[0093] For example, in the case where the clock signal generating circuit can only generate a single-ended clock signal, Figure 5 Based on the circuit structure shown, an inverter is connected between the first input terminal and the second input terminal of the first bootstrap module. The input terminal of the inverter is connected to the second input terminal of the first bootstrap module, and the output terminal of the inverter is connected to the first input terminal of the first bootstrap module, that is, the input terminal of the inverter is connected to the first terminal c11 of the first capacitor and the second pole m12 of the first transistor, and the output terminal of the inverter is connected to the first pole m11 of the first transistor and the first pole m21 of the second transistor. In this case, when the first clock signal is input to the second input terminal of the first bootstrap module, it is also input to the inverter, and the inverter can directly invert the first clock signal to obtain the second clock signal and then input it to the first input terminal of the first bootstrap module.

[0094] In this way, the clock signal bootstrap circuit of the embodiment of the present disclosure can be applied in scenarios where the clock signal generating circuit can only generate a single-ended clock signal and the circuit to be driven only needs a single-ended clock signal, thereby improving the adaptability of the clock signal bootstrap circuit to different application scenarios.

[0095] like Figure 7 As shown, in a possible implementation, the circuit further includes a second bootstrap module 52, and the second bootstrap module 52 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a second capacitor C2.

[0096] The first electrode m41 of the fourth transistor is connected to the first electrode m51 of the fifth transistor and serves as the first input terminal w21 of the second bootstrap module, the second electrode m42 of the fourth transistor is connected to the first terminal c21 of the second capacitor and serves as the second input terminal w22 of the second bootstrap module, the third electrode m43 of the fourth transistor is connected to the third electrode m53 of the fifth transistor and the first electrode m61 of the sixth transistor and serves as the output terminal w23 of the second bootstrap module, the second electrode m52 of the fifth transistor is connected to the second electrode m62 of the sixth transistor and the second terminal c22 of the second capacitor, and the third electrode m63 of the sixth transistor is connected to the power supply voltage VDD;

[0097] The first input terminal w21 of the second bootstrap module is connected to the second input terminal w12 of the first bootstrap module and receives the first clock signal CLK P The second input terminal w22 of the second bootstrap module is connected to the first input terminal w11 of the first bootstrap module, and receives the second clock signal CLK N The output terminal w23 of the second bootstrap module outputs the fourth clock signal CLK BSTN , the third clock signal CLK BSTP and the fourth clock signal CLK BSTN It is a pair of differential signals.

[0098] For example, if the circuit to be driven requires a differential clock signal drive, Figure 5 On the basis of the circuit structure shown, a second bootstrap module is added, and the second bootstrap module may include a fourth transistor, a fifth transistor, a sixth transistor, and a second capacitor.

[0099] The fourth transistor may be an N-channel transistor, and the fifth and sixth transistors may be P-channel transistors. The first electrode of each transistor may be a gate electrode, the second electrode may be a source electrode, and the third electrode may be a drain electrode.

[0100] Since the signal received by the first input terminal of the first bootstrap module is the same as the signal received by the second input terminal of the second bootstrap module, the first input terminal of the first bootstrap module can be connected to the second input terminal of the second bootstrap module, and together serve as an input terminal of the clock signal bootstrap circuit. Since the signal received by the second input terminal of the first bootstrap module is the same as the signal received by the first input terminal of the second bootstrap module, the second input terminal of the first bootstrap module can be connected to the first input terminal of the second bootstrap module, and together serve as another input terminal of the clock signal bootstrap circuit. The output terminal of the first bootstrap module and the output terminal of the second bootstrap module can be respectively used as two output terminals of the clock signal bootstrap circuit.

[0101] The fourth clock signal CLK is introduced below BSTN The level of the first clock signal CLK P and the second clock signal CLK N relationship.

[0102] In a possible implementation, the second clock signal CLK N When the gate-source voltage is greater than or equal to 0, the power supply voltage charges the second capacitor C2 through the sixth transistor, and the fourth clock signal CLK BSTN is low level;

[0103] The second clock signal CLKN When the fourth transistor is at a high level, the second electrode m42 and the third electrode m43 are disconnected and the gate-source voltage is less than 0, the second electrode m62 and the third electrode m63 of the sixth transistor are disconnected, the second electrode m52 and the third electrode m53 of the fifth transistor are turned on, the second capacitor is discharged, and the fourth clock signal CLK BSTN is high level and the fourth clock signal CLK BSTN The level of the second clock signal CLK N The level of

[0104] The second clock signal CLK N When the high level of is equal to the power supply voltage, when the second electrode and the third electrode of the fifth transistor are disconnected, the gate-source voltage of the fifth transistor is equal to 0;

[0105] The second clock signal CLK N In the case where the high level is greater than the power supply voltage, when the second electrode and the third electrode of the fifth transistor are disconnected, the gate-source voltage of the fifth transistor is less than 0.

[0106] See also Figure 7 Since the first terminal c21 of the second capacitor receives the second clock signal CLK N , and the first clock signal CLK P and the second clock signal CLK N It is a pair of differential signals, so CLK N =0, CLK P =V clk When the voltage at the first terminal c21 of the second capacitor is 0, the first electrode m41 of the fourth transistor receives the first clock signal CLK P The second electrode m42 of the fourth transistor receives the second clock signal CLK N , so CLK P =V clk When the voltage of the first electrode m41 of the fourth transistor is V clk , the voltage of the second electrode m42 is 0. The fourth transistor is an N-channel transistor, so the second electrode m42 and the third electrode m43 of the fourth transistor are turned on. The third electrode m43 of the fourth transistor outputs the fourth clock signal CLK BSTN , so the fourth clock signal CLK BSTN The voltage value is also 0.

[0107] The first electrode m51 of the fifth transistor receives the first clock signal CLK P , so CLK P =V clk When the voltage of the first electrode m51 of the fifth transistor is V clk The fifth transistor is a P-channel transistor, and thus the second electrode m52 and the third electrode m53 of the fifth transistor are disconnected.

[0108] The sixth transistor is a P-channel transistor and CLK BSTP =0, so the second electrode m62 and the third electrode m63 of the sixth transistor are turned on. At this time, the power supply voltage VDD charges the second capacitor C2 through the sixth transistor, so that the voltage at the second end c22 of the second capacitor is VDD.

[0109] The second end c22 of the second capacitor is connected to the second electrode m52 of the fifth transistor, so the voltage of the second electrode m52 of the fifth transistor is also VDD. clk is greater than or equal to the power supply voltage VDD, so the gate-source voltage (V clk -VDD) is greater than or equal to 0.

[0110] In this case, as long as V clk >VDD, the gate-source voltage of the fifth transistor (V clk -VDD) will be greater than 0. When the fifth transistor is a P-channel transistor, the leakage level of the fifth transistor can be reduced.

[0111] See also Figure 5 According to the relevant description, at this time, the second electrode and the third electrode of the first transistor are turned on, and the gate-source voltage of the first transistor is less than 0. When the first transistor is an N-channel transistor, the leakage level of the first transistor can be reduced.

[0112] Similarly, CLK P =0, the voltage at the first terminal c21 of the second capacitor is VDD. The second capacitor discharges so that the voltage at the second terminal c22 of the second capacitor reaches VDD+V clk .

[0113] CLK P = 0 when CLK N =V clk The first electrode m41 of the fourth transistor receives the first clock signal CLK P The second electrode m42 of the fourth transistor receives the second clock signal CLK N , so CLK P =0, the voltage of the first electrode m41 of the fourth transistor is 0, and the voltage of the second electrode m42 is V clk The fourth transistor is an N-channel transistor, and thus the second electrode m42 and the third electrode m43 of the fourth transistor are disconnected.

[0114] The first electrode m51 of the fifth transistor receives the first clock signal CLK P , so CLK P= 0, the voltage of the first electrode m51 of the fifth transistor is 0. The fifth transistor is a P-channel transistor, so the second electrode m52 and the third electrode m53 of the fifth transistor are turned on.

[0115] The voltage at the second terminal c22 of the second capacitor is equal to VDD+V clk , when the second electrode m52 and the third electrode m53 of the fifth transistor are turned on, if leakage is not considered, the voltage of the third electrode m53 of the fifth transistor and the first electrode m61 of the sixth transistor is also equal to VDD+V clk ,CLK BSTN =VDD+V clk The sixth transistor is a P-channel transistor, and thus the second electrode m62 and the third electrode m63 of the sixth transistor are disconnected.

[0116] At this time, the voltage difference between the second electrode m42 and the third electrode m43 of the fourth transistor is VDD, so the fourth transistor has leakage. However, since the voltage of the first electrode of the fourth transistor is equal to 0, the voltage of the second electrode is equal to V clk Therefore, the gate-source voltage of the fourth transistor is less than 0. When the fourth transistor is an N-channel transistor, the leakage level of the fourth transistor will be greatly reduced.

[0117] See also Figure 5 , at this time, the second electrode and the third electrode of the second transistor are disconnected, and the gate-source voltage of the second transistor is equal to V clk -VDD, in this case, as long as V clk >VDD, the gate-source voltage of the second transistor (V clk -VDD)0 will be greater than 0. When the second transistor is a P-channel transistor, the leakage level of the second transistor can be reduced.

[0118] In this way, no matter when the first clock signal is at a high level or a low level, the leakage level of the clock signal bootstrap circuit is reduced, thereby further reducing the power consumption of the clock signal bootstrap circuit.

[0119] Since the clock signal bootstrap circuit can output a differential clock signal, the differential clock signal can drive a device with higher linearity, and thus can support the arrangement of a device with higher linearity in the circuit to be driven, thereby improving the performance of the circuit to be driven.

[0120] In this way, the clock signal bootstrap circuit of the embodiment of the present disclosure can be applied to the scenario where the circuit to be driven requires a differential clock signal, thereby improving the adaptability of the clock signal bootstrap circuit to different application scenarios.

[0121] like Figure 8As shown, in a possible implementation, the circuit also includes an inverter, an input end of the inverter is connected to the second input end w12 of the first bootstrap module and the first input end w21 of the second bootstrap module, an output end of the inverter is connected to the first input end w11 of the first bootstrap module and the second input end w22 of the second bootstrap module, and the second clock signal is generated by the inverter.

[0122] At this time, the input end of the inverter, the second input end of the first bootstrap module and the first input end of the second bootstrap module can be used as the input end of the clock signal bootstrap circuit, and the output end of the first bootstrap module and the output end of the second bootstrap module can be used as the two output ends of the clock signal bootstrap circuit respectively.

[0123] For example, in the case where the clock signal generating circuit can only generate a single-ended clock signal, Figure 7 Based on the circuit structure shown, an inverter is added, so that the input end of the inverter is connected to the second input end of the first bootstrap module and the first input end of the second bootstrap module, and the output end of the inverter is connected to the first input end of the first bootstrap module and the second input end of the second bootstrap module. That is, the input end of the inverter is connected to the first end c11 of the first capacitor, the second pole m12 of the first transistor, the first pole m41 of the fourth transistor, and the first pole m51 of the fifth transistor, and the output end of the inverter is connected to the first end c21 of the second capacitor, the second pole m42 of the fourth transistor, the first pole m11 of the first transistor, and the first pole m21 of the second transistor.

[0124] In this case, the first clock signal is simultaneously input to the second input terminal of the first bootstrap module, the first input terminal of the second bootstrap module and the input terminal of the inverter. The inverter can directly invert the first clock signal to obtain the second clock signal which is then input to the first input terminal of the first bootstrap module and the second input terminal of the second bootstrap module.

[0125] In this way, the clock signal bootstrap circuit of the embodiment of the present disclosure can be applied in scenarios where the clock signal generating circuit can only generate a single-ended clock signal and the circuit to be driven requires a differential clock signal, thereby improving the adaptability of the clock signal bootstrap circuit to different application scenarios.

[0126] Furthermore, since the power supply voltage of the clock signal bootstrap circuit may be relatively low, the swing amplitude of the clock signal output by the clock signal bootstrap circuit may still not meet the requirements of the circuit to be driven. In this case, the embodiment of the present disclosure further proposes a cascade circuit.

[0127] Fig. 9 A schematic diagram showing the structure of a cascade circuit according to an embodiment of the present disclosure.

[0128] like Fig. 9As shown, in a possible implementation, the cascade circuit includes at least one stage of clock signal bootstrap circuit, and each stage of the clock signal bootstrap circuit includes the clock signal bootstrap circuit described above respectively;

[0129] Among them, the clock signal output by the previous stage clock signal bootstrap circuit is used as the clock signal input by the subsequent stage clock signal bootstrap circuit, the high level of the first clock signal received by the first stage clock signal bootstrap circuit is equal to the power supply voltage, and the high level of the first clock signal received by the second stage and subsequent clock signal bootstrap circuits is greater than the power supply voltage.

[0130] For example, multiple stages of clock signal bootstrap circuits may be cascaded to obtain a cascade circuit, wherein the clock signal output by the preceding stage clock signal bootstrap circuit serves as the clock signal input by the succeeding stage clock signal bootstrap circuit.

[0131] Among them, each level of clock signal bootstrap circuit can be used Figure 5-Figure 8 The disclosed embodiment does not limit the specific structure of each stage of the clock signal bootstrap circuit, as long as the number of clock signals output by the previous stage clock signal bootstrap circuit is consistent with the number of clock signals input by the next stage clock signal bootstrap circuit.

[0132] The high level of the first clock signal received by the first-stage clock signal bootstrap circuit may be equal to the power supply voltage, and the high level of the first clock signal received by the second-stage and subsequent clock signal bootstrap circuits may be greater than the power supply voltage. Ideally, the high level of the clock signal output by the k-th stage (k is a positive integer) clock signal bootstrap circuit may be equal to k+1 times the power supply voltage VDD.

[0133] The present disclosure also provides a chip, including the cascade circuit described above. The schematic diagram of the chip structure can be found in Figure 4 .

[0134] In a possible implementation, the chip further includes an analog-to-digital conversion circuit, a power supply voltage of the chip is less than a first threshold, and the cascade circuit is used to provide a clock signal for the analog-to-digital conversion circuit.

[0135] Among them, the high-swing clock signal generated by the cascade circuit can be provided only to a small number of devices in the analog-to-digital conversion circuit, and most of the devices in the analog-to-digital conversion circuit can still be powered by the chip's power supply voltage to reduce the power consumption required for the chip to achieve analog-to-digital conversion.

[0136] The following describes an exemplary structure of an analog-to-digital conversion circuit and an exemplary manner in which a clock signal bootstrap circuit drives the analog-to-digital conversion circuit.

[0137] Fig.10 A schematic diagram showing the structure of an analog-to-digital conversion circuit according to an embodiment of the present disclosure.

[0138] like Fig.10 As shown, the analog-to-digital conversion circuit may include a conversion module and a feedback module.

[0139] The conversion module includes a first chopping unit 10, a capacitor filtering unit 20, a dead zone control unit 30, a voltage-current conversion unit 40, a second chopping unit 50, an integration unit 60, a quantization unit 70, and an output unit 80.

[0140] The analog input signal includes a differential first input signal VINP and a second input signal VINN, and the feedback signal includes a differential first feedback signal VFP and a second feedback signal VFN.

[0141] The first end a1 of the first chopping unit receives the first input signal VINP, the second end a2 of the first chopping unit receives the second input signal VINN, the third end a3 of the first chopping unit is connected to the first end b1 of the capacitor filter unit, and the fourth end a4 of the first chopping unit is connected to the second end b2 of the capacitor filter unit;

[0142] The third terminal b3 of the capacitor filter unit is connected to the first terminal d1 of the dead zone control unit and the fourth terminal n4 of the feedback module, the fourth terminal b4 of the capacitor filter unit is connected to the second terminal d2 of the dead zone control unit and the third terminal n3 of the feedback module, the fourth terminal n4 of the feedback module outputs the first feedback signal VFP, and the third terminal n3 of the feedback module outputs the second feedback signal VFN;

[0143] The third terminal d3 of the dead zone control unit is connected to the first terminal e1 of the voltage-current conversion unit, and the fourth terminal d4 of the dead zone control unit is connected to the second terminal e2 of the voltage-current conversion unit;

[0144] The third terminal e3 of the voltage-current conversion unit is connected to the first terminal f1 of the second chopping unit, and the fourth terminal e4 of the voltage-current conversion unit is connected to the second terminal f2 of the second chopping unit;

[0145] The third end f3 of the second chopping unit is connected to the first end g1 of the integration unit, and the fourth end f4 of the second chopping unit is connected to the second end g2 of the integration unit;

[0146] The third terminal g3 of the integration unit is connected to the first terminal h1 of the quantization unit, the fourth terminal g4 of the integration unit is connected to the second terminal h2 of the quantization unit, the third terminal h3 of the quantization unit is connected to the first terminal j1 of the output unit and the first terminal n1 of the feedback unit, and the fourth terminal h4 of the quantization unit is connected to the second terminal j2 of the output unit and the second terminal n2 of the feedback unit;

[0147] The third terminal j3 of the output unit outputs the digital output signal DOUT.

[0148] For example, the conversion module may include a first chopping unit, a capacitor filtering unit, a dead zone control unit, a voltage-current conversion unit, a second chopping unit, an integration unit, a quantization unit, and an output unit. The unit driven by the clock signal output by the clock signal bootstrap circuit may include a first chopping unit, a dead zone control unit, and a second chopping unit.

[0149] The first chopping unit may receive an analog input signal input from the outside. The analog input signal may be a differential signal, including a first input signal and a second input signal. In this case, the first chopping unit, the capacitor filter unit, the dead zone control unit, the voltage-current conversion unit, the second chopping unit, the integration unit, and the quantization unit may include two input terminals and two output terminals respectively; the output unit may include two input terminals and one output terminal.

[0150] The first end of the first chopping unit receives a first input signal, the second end receives a second input signal, the third end outputs a signal VAP obtained by chopping the first input signal, and the fourth end outputs a signal VAN obtained by chopping the second input signal.

[0151] The first chopping unit may include switches S1-S4. The first end s11 of S1 is connected to the first end s31 of S3 and serves as the first end of the first chopping unit. The second end s12 of S1 is connected to the first end s41 of S4 and serves as the third end of the first chopping unit. The first end s21 of S2 is connected to the second end s42 of S4 and serves as the second end of the first chopping unit. The second end s22 of S2 is connected to the second end s32 of S3 and serves as the fourth end of the first chopping unit.

[0152] Those skilled in the art should understand that the first chopping unit may also be implemented using other structures, as long as it has a chopping function and can chop the differential input signal to obtain a differential output signal. The embodiments of the present disclosure do not limit the specific structure of the first chopping unit.

[0153] After the signal VAP and the signal VAN are outputted by the first chopping unit respectively, they are inputted into the first end and the second end of the capacitor filter unit. The capacitor filter unit may include a capacitor C3 and a capacitor C4. One end of the capacitor C3 serves as the first end of the capacitor filter unit, and the other end of the capacitor C3 serves as the third end of the capacitor filter unit; one end of the capacitor C4 serves as the first end of the capacitor filter unit, and the other end of the capacitor C4 serves as the fourth end of the capacitor filter unit.

[0154] Capacitor C3 can be used to filter out interference components in signal VAP. Capacitor C4 can be used to filter out interference components in signal VAN. Since the third end of the capacitor filter unit is also connected to the third end of the feedback module, and the fourth end of the capacitor filter unit is also connected to the fourth end of the feedback module, the feedback signal output by the feedback module is a differential signal and includes a first feedback signal VFP and a second feedback signal VFN. The fourth end and the third end of the feedback module output the first feedback signal VFP and the second feedback signal VFN respectively. Therefore, after the interference components in signal VAP are filtered out, the swing amplitude is adjusted by the first feedback signal VFP to obtain signal VBP and output to the first end of the dead zone control unit. After the interference components in signal VAN are filtered out, the swing amplitude is adjusted by the second feedback signal VFN to obtain signal VBN and output to the second end of the dead zone control unit.

[0155] The dead zone control unit may include a switch S5 and a switch S6. One end of the switch S5 serves as the first end of the dead zone control unit, and the other end serves as the third end of the dead zone control unit; one end of the switch S6 serves as the second end of the dead zone control unit, and the other end serves as the fourth end of the dead zone control unit. The third end of the dead zone control unit is connected to the first end of the voltage-current conversion unit, and the fourth end is connected to the second end of the voltage-current conversion unit. After the signal VBP and the signal VBN enter the voltage-current conversion unit, they enter the voltage-current conversion stage described above. Therefore, the switch S5 and the switch S6 can be controlled to be disconnected within a short period of time in each cycle (the cycle frequency can be the sampling frequency of the analog-to-digital conversion circuit) to prevent the signal VBP and the signal VBN from entering the voltage-current conversion unit, so as to optimize the quality of the signal output by the voltage-current conversion unit (for example, to remove the burrs in the signal output by the voltage-current conversion unit). The time period for controlling the switch S5 and the switch S6 to be disconnected can be set according to the application scenario requirements, and the embodiments of the present disclosure are not limited to this.

[0156] The voltage-to-current conversion unit can convert the input signal VBP into a current signal IEP and the input signal VBN into a current signal IEN. The function of the voltage-to-current conversion unit can be realized by a transconductance amplifier in the prior art, which will not be described in detail here.

[0157] The current signal IEP can be input to the first end of the second chopping unit, and the current signal IEN can be input to the second end of the second chopping unit. The structure and function of the second chopping unit can be the same as those of the first chopping unit, and will not be repeated here. The third end of the second chopping unit outputs the signal IEP after chopping to obtain the signal IFP, and the fourth end outputs the signal IEN after chopping to obtain the signal IFN.

[0158] The integration unit may include a first integrator and a second integrator. The signal IFP may be input to one end of the first integrator (the first end of the integration unit), the first integrator integrates the signal IFP, and outputs the signal IGP through the other end (the third end of the integration unit). The signal IFN may be input to one end of the second integrator (the second end of the integration unit), the second integrator integrates the signal IFN, and outputs the signal IGN through the other end (the fourth end of the integration unit). The first integrator and the second integrator may be implemented based on the prior art, and the structures of the first integrator and the second integrator will not be described in detail herein.

[0159] The signal IGP can be input to the first terminal of the quantization unit, and the signal IGN can be input to the second terminal of the quantization unit. The quantization unit can quantize the signal IGP into a value A and quantize the signal IGN into a value B. The value A can be output through the third terminal of the quantization unit, and the value B can be output through the fourth terminal of the quantization unit. The quantization unit can be implemented based on the existing technology, and the structure of the quantization unit will not be described in detail here.

[0160] The value A can be input to the first terminal of the output unit, and the value B can be input to the second terminal of the output unit. The output unit can perform a subtraction operation on the value A and the value B, and use the operation result as a digital output signal DOUT. The digital output signal DOUT can be output from the third terminal of the output unit. The output unit can be implemented based on the existing technology, and the specific structure of the output unit will not be described in detail here.

[0161] The value A and the value B are also input to the feedback module. The feedback module can output a first feedback signal VFP and a second feedback signal VFN according to the value A and the value B.

[0162] The quantization unit is a time domain quantization unit, the integration unit is a time domain integration unit, and the quantization unit and the integration unit are implemented by digital circuits.

[0163] For example, since the characteristics of the time domain integration unit and the time domain quantization unit are to process signals in the time domain instead of in the analog domain, the time domain integration unit and the time domain quantization unit can be implemented by digital circuits. Digital circuits can work at low voltages (especially digital circuits under advanced processes, the more advanced the process, the lower the voltage at which they can work), so the time domain integration unit and the time domain quantization unit can maintain high performance at a power supply voltage lower than the first threshold. Since this further increases the proportion of digital circuits in the analog-to-digital converter circuit, the power consumption of the analog-to-digital conversion circuit is further reduced.

[0164] In a possible implementation, the swing of the clock signal used to drive the dead zone control unit is greater than or equal to the second threshold, the swing of the clock signal used to drive the first chopping unit and the second chopping unit is greater than or equal to the third threshold, and the second threshold is greater than the third threshold.

[0165] For example, the higher the swing of the clock signal, the better the effect of driving the first chopping unit, the dead zone control unit, and the second chopping unit, but the greater the power consumption. Therefore, the clock signal driving the first chopping unit, the dead zone control unit, and the second chopping unit can be determined according to the requirements of the first chopping unit, the dead zone control unit, and the second chopping unit for the swing of the clock signal.

[0166] The first chopping unit and the second chopping unit may have a clock signal swing requirement equal to a third threshold value (e.g., 0.9V). The dead zone control unit may have a higher clock signal swing requirement, which may be equal to a second threshold value (e.g., 1.1V). The swing of the first pair of clock signals output by the clock signal bootstrap unit may be 0.9V, the swing of the second pair of clock signals may be 1V, and the swing of the third pair of clock signals may be 1.1V. In this case, the first pair of clock signals may be used to drive the first chopping unit and the second chopping unit, and the third pair of clock signals may be used to drive the dead zone control unit.

[0167] If the swing of the pair of clock signals with the lowest swing output by the clock signal bootstrap module exceeds the second threshold, the pair of clock signals with the lowest swing can be used to drive the first chopping unit, the dead zone control unit and the second chopping unit.

[0168] That is, the swing of the clock signal used to drive the dead zone control unit is greater than or equal to the second threshold, the swing of the clock signal used to drive the first chopping unit and the second chopping unit is greater than or equal to the third threshold, and the second threshold is greater than the third threshold.

[0169] In this way, the power consumption of the analog-to-digital conversion circuit can be reduced while ensuring the quality of the analog-to-digital conversion.

[0170] The feedback module may include a logic control unit, a third chopping unit, and a capacitive digital-to-analog conversion unit.

[0171] The first end of the logic control unit serves as the first end of the feedback module, the second end of the logic control unit serves as the second end of the feedback module, the third end of the logic control unit is connected to the first end of the third chopping unit, and the fourth end of the logic control unit is connected to the second end of the third chopping unit;

[0172] The third end of the third chopping unit is connected to the first end of the capacitive digital-to-analog conversion unit, and the fourth end of the third chopping unit is connected to the second end of the capacitive digital-to-analog conversion unit;

[0173] The third terminal of the capacitive digital-to-analog conversion unit serves as the third terminal of the feedback module, and the fourth terminal of the capacitive digital-to-analog conversion unit serves as the fourth terminal of the feedback module.

[0174] For example, if Fig.10 As shown, the feedback module as a whole can be implemented by a digital circuit, and may include a logic control unit 11 , a third chopping unit 21 , and a capacitive digital-to-analog conversion unit 31 .

[0175] The first terminal n1 of the logic control unit serves as the first terminal of the feedback module to receive the value A, and the second terminal n2 of the logic control unit serves as the second terminal of the feedback module to receive the value B. According to the values ​​A and B, the logic control unit can obtain a digital control signal, which can be a differential signal, including a signal ctrl1 and a signal ctrl2. The digital control signal is used to control the degree of regulation of the analog input signal by the feedback module. The logic control unit can be implemented based on the prior art, and the specific implementation method of the logic control unit will not be repeated here.

[0176] The third terminal p3 of the logic control unit can be connected to the first terminal q1 of the third chopping unit, and the fourth terminal p4 of the logic control unit can be connected to the second terminal q2 of the third chopping unit, and the signal ctrl1 and the signal ctrl2 are input to the third chopping unit for chopping. The signal ctrl1 is chopped to obtain the signal ctrl11, and the signal ctrl2 is chopped to obtain the signal ctrl22. The third chopping unit can be implemented based on the prior art, and the specific implementation method of the third chopping unit will not be repeated here.

[0177] The third terminal q3 of the third chopping unit can input the signal ctrl11 to the first terminal p1 of the capacitive digital-to-analog conversion unit, and the fourth terminal q4 of the third chopping unit can input the signal ctrl22 to the second terminal p2 of the capacitive digital-to-analog conversion unit. The capacitive digital-to-analog conversion unit can perform digital-to-analog conversion on the signal ctrl11 to obtain the signal VFN, and perform digital-to-analog conversion on the signal ctrl22 to obtain the signal VFP, and the signal VFP and the signal VFN can be analog signals. In this case, the signal VFP can be operated with the signal VAP, and the signal VFN can be operated with the signal VAN. The third terminal n3 of the capacitive digital-to-analog conversion unit can output the signal VFN, and the fourth terminal n4 can output the signal VFP. The capacitive digital-to-analog conversion unit can be implemented based on the prior art, and the specific implementation method of the capacitive digital-to-analog conversion unit will not be repeated here.

[0178] The embodiment of the present disclosure also provides a chip, including the above-mentioned cascade circuit. The chip may further include a clock signal generating circuit and an analog-to-digital conversion circuit, etc. The embodiment of the present disclosure does not limit the specific structure of the chip.

[0179] The embodiment of the present disclosure also provides an electronic device, including the chip described above. The electronic device may be a terminal device or a server, etc. The embodiment of the present disclosure does not limit the specific type of the electronic device.

[0180] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0181] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A clock signal bootstrap circuit, characterized in that: The circuit includes a first bootstrap module, wherein the first bootstrap module includes a first transistor, a second transistor, a third transistor, and a first capacitor. The first electrode of the first transistor is connected to the first electrode of the second transistor and serves as the first input terminal of the first bootstrap module, the second electrode of the first transistor is connected to the first terminal of the first capacitor and serves as the second input terminal of the first bootstrap module, the third electrode of the first transistor is connected to the third electrode of the second transistor and the first electrode of the third transistor and serves as the output terminal of the first bootstrap module, the second electrode of the second transistor is connected to the second electrode of the third transistor and the second terminal of the first capacitor, and the third electrode of the third transistor is connected to a power supply voltage; The second input terminal of the first bootstrap module receives a first clock signal, the first input terminal of the first bootstrap module receives a second clock signal, the first clock signal and the second clock signal are a pair of differential signals, and the output terminal of the first bootstrap module outputs a third clock signal.

2. The circuit according to claim 1, characterized in that When the first clock signal is at a low level, the second electrode and the third electrode of the first transistor are turned on, the second electrode and the third electrode of the third transistor are turned on, the second electrode and the third electrode of the second transistor are turned off and the gate-source voltage is greater than or equal to 0, the power supply voltage charges the first capacitor through the third transistor, and the third clock signal is at a low level; When the first clock signal is at a high level, the second electrode and the third electrode of the first transistor are disconnected and the gate-source voltage is less than 0, the second electrode and the third electrode of the third transistor are disconnected, the second electrode and the third electrode of the second transistor are turned on, the first capacitor is discharged, the third clock signal is at a high level and the level of the third clock signal is greater than the level of the first clock signal; When the high level of the first clock signal is equal to the power supply voltage, when the second electrode and the third electrode of the second transistor are disconnected, the gate-source voltage of the second transistor is equal to 0; When the high level of the first clock signal is greater than the power supply voltage, when the second electrode and the third electrode of the second transistor are disconnected, the gate-source voltage of the second transistor is greater than 0.

3. The circuit according to claim 1, characterized in that The circuit further includes an inverter, an input end of the inverter is connected to the second input end of the first bootstrap module, an output end of the inverter is connected to the first input end of the first bootstrap module, and the second clock signal is generated by the inverter.

4. The circuit according to claim 1, characterized in that The circuit further includes a second bootstrap module, wherein the second bootstrap module includes a fourth transistor, a fifth transistor, a sixth transistor, and a second capacitor. The first electrode of the fourth transistor is connected to the first electrode of the fifth transistor and serves as the first input terminal of the second bootstrap module, the second electrode of the fourth transistor is connected to the first terminal of the second capacitor and serves as the second input terminal of the second bootstrap module, the third electrode of the fourth transistor is connected to the third electrode of the fifth transistor and the first electrode of the sixth transistor and serves as the output terminal of the second bootstrap module, the second electrode of the fifth transistor is connected to the second electrode of the sixth transistor and the second terminal of the second capacitor, and the third electrode of the sixth transistor is connected to the power supply voltage; The first input end of the second bootstrap module is connected to the second input end of the first bootstrap module to receive the first clock signal, the second input end of the second bootstrap module is connected to the first input end of the first bootstrap module to receive the second clock signal, and the output end of the second bootstrap module outputs a fourth clock signal, and the third clock signal and the fourth clock signal are a pair of differential signals.

5. The circuit according to claim 4, characterized in that When the second clock signal is at a low level, the second electrode and the third electrode of the fourth transistor are turned on, the second electrode and the third electrode of the sixth transistor are turned on, the second electrode and the third electrode of the fifth transistor are turned off and the gate-source voltage is greater than or equal to 0, the power supply voltage charges the second capacitor through the sixth transistor, and the fourth clock signal is at a low level; When the second clock signal is at a high level, the second electrode and the third electrode of the fourth transistor are disconnected and the gate-source voltage is less than 0, the second electrode and the third electrode of the sixth transistor are disconnected, the second electrode and the third electrode of the fifth transistor are turned on, the second capacitor is discharged, the fourth clock signal is at a high level and the level of the fourth clock signal is greater than the level of the second clock signal; When the high level of the second clock signal is equal to the power supply voltage, when the second electrode and the third electrode of the fifth transistor are disconnected, the gate-source voltage of the fifth transistor is equal to 0; When the high level of the second clock signal is greater than the power supply voltage, when the second electrode and the third electrode of the fifth transistor are disconnected, the gate-source voltage of the fifth transistor is greater than 0.

6. The circuit according to claim 4, characterized in that The circuit also includes an inverter, an input end of the inverter is connected to the second input end of the first bootstrap module and the first input end of the second bootstrap module, an output end of the inverter is connected to the first input end of the first bootstrap module and the second input end of the second bootstrap module, and the second clock signal is generated by the inverter.

7. The circuit according to any one of claims 1 to 6, characterized in that: The level of the power supply voltage is lower than a first threshold.

8. A cascade circuit, characterized in that: The cascade circuit comprises at least one stage of clock signal bootstrap circuit, and each stage of the clock signal bootstrap circuit comprises the clock signal bootstrap circuit according to any one of claims 1 to 7; Among them, the clock signal output by the previous stage clock signal bootstrap circuit is used as the clock signal input by the subsequent stage clock signal bootstrap circuit, the high level of the first clock signal received by the first stage clock signal bootstrap circuit is equal to the power supply voltage, and the high level of the first clock signal received by the second stage and subsequent clock signal bootstrap circuits is greater than the power supply voltage.

9. A chip, characterized in that: Comprising the cascade circuit as claimed in claim 8.

10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.

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