Phase-Adjusted Sampling Circuit, Sampling Control Method, and Electronic Device

Abstract

The present application discloses a phase-adjusted sampling circuit, a sampling control method, and an electronic device. The sampling circuit includes: a first differential branch connected between a first port and a first input end of a sub-analog-to-digital converter; a second differential branch connected between a second port and a second input end of the sub-analog-to-digital converter; a first correction circuit connected between the second port and the first differential branch; a second correction circuit connected between the first port and the second differential branch; a third correction circuit coupled to an output end of the sub-analog-to-digital converter, and a first output end is coupled to the first correction circuit, and a second output end is coupled to the second correction circuit, and is configured to adjust capacitance parameters of at least one of the first correction circuit and the second correction circuit based on an output result of the sub-analog-to-digital converter to correct even harmonics in a sampling result of the sampling circuit. The present application has the technical effects of reducing mismatch of differential input signals and reducing even harmonic energy of an analog-to-digital conversion chip.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of circuit technologies, and in particular, to a sampling circuit with phase adjustment, a sampling control method, and an electronic device. Background Art

[0002] The development of wireless communication technologies has continuously increased the signal frequency requirements for high-speed and high-precision analog-to-digital converters. In high-sampling-rate analog-to-digital converters, time-domain interleaved sampling is usually adopted to improve the sampling rate. The spectrum finally output by the analog-to-digital converter includes the high-order harmonics of each sub-channel analog-to-digital converter itself, and also includes the inter-channel spurs generated due to mismatches such as amplitude and phase between multiple channels. Moreover, due to non-ideal factors such as asymmetric traces and device mismatches, the influence of the even-order linearity of the differential signal becomes worse with frequency. Therefore, the harmonic problem of the differential signal input to the analog-to-digital converter deserves attention. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a sampling circuit with phase adjustment, a sampling control method, and an electronic device, in order to reduce the harmonic influence in the differential signal input to the analog-to-digital converter. In a first aspect, a sampling circuit is provided, including: a first differential branch, a second differential branch, a first correction circuit, a second correction circuit, a sub-analog-to-digital converter, and a third correction circuit; the first differential branch is connected between a first port and a first input end of the sub-analog-to-digital converter; the second differential branch is connected between a second port and a second input end of the sub-analog-to-digital converter; the first correction circuit is connected between the second port and the first differential branch; the second correction circuit is connected between the first port and the second differential branch; the third correction circuit is coupled to the output end of the sub-analog-to-digital converter, and its first output end is coupled to the first correction circuit, and its second output end is coupled to the second correction circuit, and is configured to adjust the capacitance parameters of at least one of the first correction circuit and the second correction circuit based on the output result of the sub-analog-to-digital converter, so as to correct the even-order harmonics in the sampling result of the sampling circuit.

[0004] The above sampling circuit with phase adjustment can adjust the sampling capacitance sizes of the two input ends of the differential signal respectively through the correction capacitors provided by the first correction circuit and the second correction circuit, so as to reduce the mismatch of the differential input signal, thereby reducing the even-order harmonic energy of the entire analog-to-digital conversion chip.

[0005] Optionally, the first differential branch includes: a first sampling switch and a first sampling capacitor, and the first sampling switch is connected between the first port and the first end of the first sampling capacitor; the second differential branch includes: a second sampling switch and a second sampling capacitor, and the second sampling switch is connected between the second port and the first end of the second sampling capacitor.

[0006] Optionally, the first correction circuit includes a plurality of first correction branches, which are connected in parallel with each other. Among them, the first correction branch includes a first switch and a first correction capacitor; the second correction circuit includes a plurality of second correction branches, which are connected in parallel with each other. Among them, the second correction branch includes a second switch and a second correction capacitor.

[0007] Optionally, the second end of the first sampling capacitor is grounded, and the second end of the second sampling capacitor is grounded; one end of the first switch is coupled to the second port, and the other end is coupled to the first end of the first correction capacitor, and the second end of the first correction capacitor is grounded; one end of the second switch is coupled to the first port, and the other end is coupled to the first end of the second correction capacitor, and the second end of the second correction capacitor is grounded.

[0008] Optionally, the second end of the first sampling capacitor is coupled to the first input terminal, and the second end of the second sampling capacitor is coupled to the second input terminal; the first correction branch includes a first switch and a first correction capacitor connected in series between the second port and the first input terminal; the second correction branch includes a second switch and a second correction capacitor connected in series between the first port and the second input terminal.

[0009] Optionally, it further includes: a common-mode voltage source, a first access switch, and a second access switch connected in series between the first input terminal and the second input terminal; the common-mode voltage source is configured to provide a common-mode voltage to the first input terminal or the second input terminal based on the control of the first access switch or the second access switch.

[0010] Optionally, the capacitance values of the first correction capacitors in the plurality of first correction branches are the same or different; the capacitance values of the second correction capacitors in the plurality of second correction branches are the same or different.

[0011] In a second aspect, a sampling control method is provided for controlling the sampling circuit in the first aspect, including: configuring the first correction capacitor parameters of the first correction circuit and the second correction capacitor parameters of the second correction circuit to a first preset correction capacitor value; adjusting the first preset correction capacitor value to a second preset correction capacitor value, where the first preset correction capacitor value is less than the second preset correction capacitor value; obtaining a first output result of the sub-analog-to-digital converter; when the first output result meets the first preset parameter, adjusting one or more of the first correction capacitor value and the second correction capacitor value respectively; obtaining a second output result of the sub-analog-to-digital converter; when the second output result meets the second preset parameter, causing the sub-analog-to-digital converter to output the second output result.

[0012] Optionally, the first preset parameter includes an even harmonic parameter; the second preset parameter includes one or more of a phase error parameter and an amplitude error parameter.

[0013] In a third aspect, an electronic device is provided, including the sampling circuit in the first aspect. Description of the Drawings

[0014] The following is a brief introduction to the drawings used in the description of the embodiments of the present disclosure:

[0015] Figure 1 It shows a schematic diagram of a conventional test scenario provided in some embodiments of the present application;

[0016] Figure 2 It shows a schematic circuit diagram of a phase-adjusted sampling circuit provided in some embodiments of the present application;

[0017] Figure 3 It shows a schematic circuit diagram of another phase-adjusted sampling circuit provided in some embodiments of the present application;

[0018] Figure 4 It shows a schematic circuit diagram of yet another phase-adjusted sampling circuit provided in some embodiments of the present application;

[0019] Figure 5 It shows a schematic flowchart of a sampling control method provided in some embodiments of the present application;

[0020] Figure 6 It shows a relationship diagram between the first preset correction capacitance value and the phase difference provided in some embodiments of the present application;

[0021] Figure 7 It shows a proportional relationship diagram between the first preset correction capacitance value and the phase difference provided in some embodiments of the present application;

[0022] Figure 8 It shows a relationship diagram between the first correction capacitance parameter and the second correction capacitance parameter when the phase difference is 160 degrees provided in some embodiments of the present application;

[0023] Figure 9 It shows a relationship diagram between the first correction capacitance parameter and the second correction capacitance parameter when the phase difference is 180 degrees provided in some embodiments of the present application;

[0024] Figure 10 It shows a schematic structural diagram of a sampling control device provided in some embodiments of the present application. Detailed implementation manners

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will describe the example embodiments of the present disclosure with reference to the accompanying drawings. The accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings, and other embodiments can be obtained. Adjustments and improvements made without departing from the concept of the present disclosure all fall within the protection scope of the present disclosure.

[0026] To simplify the drawings, each drawing only schematically shows the parts related to the embodiments, and they do not represent the actual structure of the product. In addition, to simplify the drawings for better understanding, in some drawings, only some of the components with the same structure or function are schematically shown, and there may actually be more or fewer components with the same structure or function.

[0027] In the present disclosure, unless otherwise clearly specified and limited, ordinal numbers, such as "first", "second", etc., are only used to distinguish and describe related objects, and cannot be understood as indicating or implying the relative importance or order between related objects; in addition, they do not represent the quantity of related objects. "A plurality" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between related objects, which represents the "or" relationship between related objects. "And / or" is used to describe the relationship between related objects, which includes any combination relationship between related objects. For example, "a and / or b" includes: "a alone", "b alone", or "a and b". "One or more" or "at least one" of multiple objects refers to any object or any combination of multiple objects. For example, "one or more of a1, a2, a3" or "at least one of a1, a2, a3" includes: "a1 alone", "a2 alone", "a3 alone", "a1 and a2", "a1 and a3", "a2 and a3", or "a1, a2 and a3".

[0028] The development of wireless communication technology has continuously increased the signal frequency requirements for high-speed and high-precision analog-to-digital converters. In analog-to-digital converters with high sampling rates, time-domain interleaved sampling is usually adopted to improve the sampling rate. The spectrum finally output by the analog-to-digital converter contains the high-order harmonics of each sub-channel analog-to-digital converter itself, and also contains inter-channel spurs generated due to mismatches such as amplitude and phase between multiple channels. Moreover, due to non-ideal factors such as asymmetric traces and device mismatches, the even-order linearity influence of differential signals becomes worse with frequency. In the actual chip testing process, the phenomenon that the even-order harmonic energy is much higher than other harmonic energies often occurs, and this problem is unacceptable in some special scenarios such as radar detection applications. Figure 1FIG. 0 shows a schematic diagram of a conventional test scenario provided in some embodiments of the present application. The high-frequency signal is provided by a signal source 10, converted into a differential signal through an external balun 20, and the differential signal is respectively connected to a PCB board through two equal-length transmission lines, and then sent to a chip under test 30 through a series of RC matching network devices. However, the differential signal generated by the balun 20 cannot completely achieve a 180-degree phase difference, and it is difficult for the two transmission lines of the differential signal to be completely symmetric. Therefore, a phase or amplitude difference will be generated in the differential signal sent into the chip under test 30. Inside the chip under test 30, the differential input is sent to the input port of the analog front-end circuit through symmetric traces, and then provided to each sub-analog-to-digital converter through tree-shaped traces. In the actual layout, due to physical trace limitations, there are also mismatches in the differential input traces and the tree-shaped traces, and there may also be device mismatches in the analog front-end circuit. Therefore, the signals actually sent to the sampling input ends of the sub-analog-to-digital converters must have phase and amplitude mismatches, which affect the final test results or cause unexpected failures. Therefore, a sampling circuit provided in the present application can separately adjust the sampling capacitance sizes of the two input ends of the differential signal on the chip to reduce the mismatch of the differential input signal, thereby reducing the even harmonic energy of the entire analog-to-digital conversion chip.

[0029] Figure 2 FIG. 4 shows a schematic diagram of the circuit structure of a phase-adjusting sampling circuit provided in some embodiments of the present application. The sampling circuit 200 includes: a first differential branch 210, a second differential branch 220, a first correction circuit 230, a second correction circuit 240, a sub-analog-to-digital converter 250, and a third correction circuit 260; the first differential branch is connected between a first port and a first input end of the sub-analog-to-digital converter; the second differential branch is connected between a second port and a second input end of the sub-analog-to-digital converter; the first correction circuit is connected between the second port and the first differential branch; the second correction circuit is connected between the first port and the second differential branch; the third correction circuit is coupled to the output end of the sub-analog-to-digital converter, and its first output end is coupled to the first correction circuit, and the second output end is coupled to the second correction circuit, and is configured to adjust the capacitance parameters of at least one of the first correction circuit and the second correction circuit based on the output result of the sub-analog-to-digital converter to correct the even harmonics in the sampling result of the sampling circuit.

[0030] In an embodiment of the present application, the first differential branch 210 and the second differential branch 220 may include a sampling switch and a sampling capacitor. The sampling switch samples the input signal through the sampling capacitor under the control of a preset switching frequency to help the subsequent sub-analog-to-digital conversion circuit realize the function of analog-to-digital conversion. The sampling method can be top plate sampling or bottom plate sampling, which is not specifically limited here. The first correction circuit and the second correction circuit may include a correction capacitor and a switch. The first correction circuit and the second correction circuit are respectively controlled by a third correction circuit so that the correction capacitor cooperates with the sampling capacitor. Based on the output result of the sub-analog-to-digital converter, the size of the capacitor connected to the differential circuit is adjusted to realize even harmonic correction. Taking the sampling method as top plate sampling as an example, for example, the input signal entering the sampling circuit from the first port IN1 and the second port IN2 can be expressed by formula 1:

[0031]

[0032] The capacitance value provided by the second correction circuit can be set to a1, the capacitance value provided by the first correction circuit can be set to a2, and the sampling capacitance value of the first differential branch (or the second differential branch) can be set to 1. Therefore, the sampling and holding node VSP can be expressed as follows with reference to Formula 2:

[0033]

[0034] make , then A1 and θ1 can be expressed by referring to Formula 3:

[0035]

[0036] Similarly, the sample-and-hold node VSN can be expressed as follows with reference to Formula 4:

[0037]

[0038] make , then A2 and θ2 can be expressed by referring to Formula 5:

[0039]

[0040] If there is no phase difference between the final differential signals, that is, θ1=θ2+180°, combining equations 3 and 5 gives equation 6:

[0041]

[0042] Therefore, the phase difference between the two differential signals input to the sub-analog-to-digital converter can be made close to or equal to 180° by adjusting the correction capacitance values provided by the first correction circuit and the second correction circuit, thereby achieving the correction of the phase error. On the other hand, to ensure that the amplitudes between the differential signals (i.e., between VSP and VSN) remain the same, combining Equation 3 and Equation 5, referring to Equation 7:

[0043]

[0044] According to Equation 7, by adjusting the capacitance value a1 provided by the second correction circuit and the capacitance value a2 provided by the first correction circuit, the errors in amplitude and phase at both ends of the differential sampling are minimized, thereby reducing the even harmonic energy.

[0045] Figure 3 FIG. shows a schematic circuit diagram of another phase adjustment sampling circuit provided in some embodiments of the present application. The sampling circuit 300 includes: a first differential branch, including: a first sampling switch Sc1 and a first sampling capacitor Cc1, the first sampling switch Sc1 being connected between the first port IN1 and the first end of the first sampling capacitor Cc1; a second differential branch including: a second sampling switch Sc2 and a second sampling capacitor Cc2, the second sampling switch Sc2 being connected between the second port IN2 and the first end of the second sampling capacitor Cc2. The above circuit forms a top plate sampling structure. The first sampling switch Sc1 and the second sampling switch Sc2 can be turned on and off according to the preset switch control requirements at a certain sampling period, so that the first sampling capacitor Cc1 or the second sampling capacitor Cc2 can collect the signals input through the first port IN1 or the second port IN2, and input the sampled differential signals into the sub-analog-to-digital converter 350 for analog-to-digital conversion. Among them, the capacitance specifications of the first sampling capacitor Cc1 and the second sampling capacitor Cc2 can be the same or different, and the sampling periods of the first sampling switch and the second sampling switch can be the same or different. For example, when there are phase and amplitude errors between the differential signals, the even harmonic energy can be reduced by adjusting the sampling period or the parameters of the sampling capacitor.

[0046] Continue to refer to Figure 3, the first correction circuit 330 includes a plurality of first correction branches, which are connected in parallel with each other. Among them, each first correction branch includes a first switch S1 and a first correction capacitor Cj1; the second correction circuit includes a plurality of second correction branches, which are connected in parallel with each other. Among them, each second correction branch includes a second switch S2 and a second correction capacitor Cj2. That is, the plurality of first correction branches include a plurality of first switches S1 and a plurality of first correction capacitors Cj1. The plurality of second correction branches are similar to the first correction branches. Among them, the number of the first correction branches and the second correction branches may be the same or different. The capacitance parameters of the plurality of first correction capacitors Cj1 may be the same or different, and the capacitance parameters of the plurality of second correction capacitors Cj2 may be the same or different, and can be set according to actual requirements and adjustment requirements. The correction capacitors in the first correction circuit 330 and the second correction circuit 340 may be composed of the same unit capacitor or sub-capacitors with binary ratios. When adjusting the capacitance value provided in the first correction circuit 330 or the second correction circuit 340, the first correction capacitor Cj1 or the second correction capacitor Cj2 can be connected to the circuit by controlling the corresponding first switch S1 or second switch S2, so as to adjust the phase and amplitude of the differential signal, eliminate errors, and reduce the energy of even harmonics.

[0047] In some embodiments, continue to refer to Figure 3 , the second end of the first sampling capacitor Cc1 is grounded, and the second end of the second sampling capacitor Cc2 is grounded; one end of the first switch S1 is coupled to the second port IN2, and the other end is coupled to the first end of the first correction capacitor Cj1. The second end of the first correction capacitor Cj1 is grounded; one end of the second switch S2 is coupled to the first port IN1, and the other end is coupled to the first end of the second correction capacitor Cj2. The second end of the second correction capacitor Cj2 is grounded.

[0048] Figure 4The schematic circuit diagram of another phase - adjusted sampling circuit provided in some embodiments of the present application is shown. In the sampling circuit 400, the second end of the first sampling capacitor Cc1 is coupled to the first input terminal, and the second end of the second sampling capacitor Cc2 is coupled to the second input terminal; the first correction branch includes a first switch S1 and a first correction capacitor Cj1 connected in series between the second port IN2 and the first input terminal; the second correction branch includes a second switch S2 and a second correction capacitor Cj2 connected in series between the first port IN1 and the second input terminal. The above - mentioned embodiments form a bottom - plate sampling structure. Among them, in top - plate sampling during the sampling phase, the top plate of the capacitor is connected to the input signal through a switch, and the bottom plate is equivalent to being grounded. After the sampling is completed, the switch is disconnected, and the charge is stored on the top plate. During bottom - plate sampling, the input signal is connected to the bottom plate, and the top plate is usually grounded. After the sampling is completed, the charge is transferred to other electrodes through a series of switch operations to complete the sampling. Top - plate sampling is suitable for scenarios with relatively high requirements for sampling speed but relatively low requirements for accuracy; bottom - plate sampling is suitable for scenarios with relatively high requirements for sampling accuracy and can accept a more complex circuit design. The circuit structure selection of the above - mentioned embodiments can be designed based on actual application requirements.

[0049] Continuing to refer to Figure 4 , it further includes: a common - mode voltage source VCM, a first access switch K1, and a second access switch K2 connected in series between the first input terminal and the second input terminal; the common - mode voltage source VCM is configured to provide a common - mode voltage to the first input terminal or the second input terminal based on the control of the first access switch or the second access switch. During the bottom - plate sampling process, the bottom plate of the capacitor is connected to the input signal, and the top plate is usually grounded. For differential input signals, the common - mode part of the input signal (i.e., the average value of the two input signals) needs to be properly processed to avoid affecting the performance of the circuit. By introducing the common - mode voltage, the common - mode level of the circuit can be ensured to remain stable. And during the sampling process of the sampling switch, as well as the opening and closing processes of the switches in the correction branch, switch switching will generate noise, such as channel charge injection or clock feed - through noise, which will affect the sampling accuracy. Connecting the common - mode voltage can help suppress the influence of these noises on the circuit performance, thereby improving the sampling accuracy.

[0050] Based on the same technical concept, referring to Figure 5 , the schematic flow diagram of a sampling control method provided in some embodiments of the present application is shown. This method is used to control the sampling circuit with phase adjustment in the first aspect, and at least includes the steps:

[0051] S510: Configure the first correction capacitor parameter of the first correction circuit and the second correction capacitor parameter of the second correction circuit to a first preset correction capacitor value;

[0052] S520: Adjust the first preset correction capacitance value to a second preset correction capacitance value, where the first preset correction capacitance value is less than the second preset correction capacitance value;

[0053] S530: Obtain the first output result of the sub - analog - to - digital converter;

[0054] S540: When the first output result meets the first preset parameter, adjust one or more of the first correction capacitance value and the second correction capacitance value;

[0055] S550: Obtain the second output result of the sub - analog - to - digital converter;

[0056] S560: When the second output result meets the second preset parameter, make the sub - analog - to - digital converter output the second output result.

[0057] In the method of the above embodiments, the first preset parameter includes an even - harmonic parameter; the second preset parameter includes one or more of a phase - error parameter and an amplitude - error parameter. For example, when controlling using the Figure 3 shown sampling circuit, the first correction capacitance parameter provided by the second correction circuit 340 can be set to a1, and the second correction capacitance parameter provided by the first correction circuit 330 can be set to a2, and they are respectively equal to the first preset correction capacitance value a. Through experimental testing, it can be determined that Figure 6 shows the relationship diagram between the first preset correction capacitance value and the phase difference in some embodiments of the present application. It can be seen from the figure that if there is a 20 - degree phase difference between the differential input signals VIP and VIN, there is an a that can make the phase difference of the sampling terminals VSP / VSN be 180 degrees, that is, the phase - error correction is achieved. For the same phase error, there are multiple solutions of a that can make the equation hold, and the smaller a is, the smaller the capacitance connected to the circuit. Therefore, the solution with a smaller a is preferably selected. From Figure 6 and the experimental results, it can be known that when the phase at both ends of the differential input is about 168 degrees and 192 degrees, a takes the maximum value, which can be used as the maximum value of the sum of the capacitance values provided by the first correction circuit 330 and the second correction circuit 340, about 0.7 times the capacitance value provided by the first sampling capacitor. On the other hand, in order to keep the amplitudes of the sampling terminals VSP / VSN the same and satisfy formula 7 in the above embodiments, when a1 = a2 = a, the relationship between the phase difference of the differential input signals VIP / VIN and the correction - capacitance ratio a is as Figure 7 shown, Figure 7The diagram showing the proportional relationship between the first preset correction capacitance value and the phase difference provided in some embodiments of the present application. Similar to the curve with a phase difference of 180 degrees at the sampling end, there are multiple different solutions for the same input phase difference that can satisfy the same amplitude at both ends of the differential sampling. It should be noted that since there may not exist a value of a1 = a2 = a that can simultaneously satisfy the same amplitude at both ends of the differential sampling and a phase difference of 180 degrees. Therefore, it is necessary to find the relationship between a1 and a2 to ensure that the amplitude equality and the phase difference of 180 degrees are satisfied simultaneously. For example, when the input phase difference is 160 degrees, Figure 8 The diagram showing the relationship between the first correction capacitance parameter and the second correction capacitance parameter when the phase difference is 160 degrees provided in some embodiments of the present application. To satisfy the same amplitude at both ends of the differential sampling and a phase difference of 180 degrees, the relationship between a1 and a2 is adjusted to Figure 9 The shown diagram. From Figure 8 and Figure 9 The values of a1 and a2 that hold simultaneously can be obtained. Through the above method, the curves of a1 and a2 corresponding to each differential input phase difference can be obtained. Therefore, based on the above, first let a1 = a2 = a, and then roughly adjust the value of a. The value of a can be taken one by one from the minimum value to the maximum value, and observe the magnitude of the even harmonics in the quantization result of the sub-analog-to-digital converter. When the even harmonics drop to the lowest value, then finely adjust a1 or a2 to minimize the phase error and amplitude error at the sampling end, thereby further reducing the even harmonic energy.

[0058] Based on the same technical concept, the present application also provides an electronic device including the sampling circuit provided in the above embodiments.

[0059] Based on the same technical concept, Figure 10 The structural schematic diagram of a sampling control device provided in some embodiments of the present application is shown. The sampling control device 1000 includes: a configuration unit 1010 for configuring the first correction capacitance parameter of the first correction circuit and the second correction capacitance parameter of the second correction circuit as the first preset correction capacitance value; an adjustment unit 1020 for adjusting the first preset correction capacitance value to the second preset correction capacitance value, where the first preset correction capacitance value is less than the second preset correction capacitance value; an acquisition unit 1030 for acquiring the first output result of the sub-analog-to-digital converter; the adjustment unit 1020 is further configured to, when the first output result meets the first preset parameter, adjust one or more of the first correction capacitance value and the second correction capacitance value respectively; the acquisition unit 1030 is further configured to acquire the second output result of the sub-analog-to-digital converter; an output unit 1040 for enabling the sub-analog-to-digital converter to output the second output result when the second output result meets the second preset parameter.

[0060] The division of each of the above units is only a division of logical functions. In actual implementation, they can be fully or partially integrated into a physical entity, or physically separated. In addition, each of the above units can be implemented in the form of a processor invoking software. For example, the photovoltaic module roller brush cleaning control device includes a processor, the processor is connected to a memory, and instructions are stored in the memory. The processor invokes the instructions stored in the memory to implement any of the above methods or the functions of each unit. The processor is, for example, a general-purpose processor, such as a central processing unit (CPU), and the memory is a memory inside or outside the device. Alternatively, each of the above units can be implemented in the form of a hardware circuit, and the functions of some or all of the units can be implemented by designing the hardware circuit. The hardware circuit can be understood as one or more processors. For example, in some embodiments, the hardware circuit is an application specific integrated circuit (ASIC), and the functions of some or all of the above units are implemented by designing the logical relationship between the components in the circuit. Again, in another implementation, the hardware circuit can be implemented by a programmable logic device (PLD), which can include a large number of logic gate circuits, and the logical relationship between the logic gate circuits is configured through a configuration file to implement the functions of some or all of the above units. All units of the above device can be fully implemented in the form of a processor invoking a program, or fully implemented in the form of a hardware circuit, or partially implemented in the form of a processor invoking a program, and the remaining part is implemented in the form of a hardware circuit.

[0061] In some embodiments of the present disclosure, a processor is a circuit with signal processing capabilities. In some embodiments, a processor can be a circuit with instruction reading and running capabilities, such as a CPU, a microprocessor, a graphics processing unit (GPU), or a digital signal processor (DSP), etc. In another implementation, a processor can achieve certain functions through the logical relationship of a hardware circuit, and the logical relationship of this hardware circuit is fixed or can be reconfigured. For example, the processor is a hardware circuit implemented by an ASIC or a PLD, such as a field programmable gate array (FPGA). In a reconfigurable hardware circuit, the process of a processor loading a configuration document to implement the configuration of the hardware circuit can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. In addition, it can also be a hardware circuit designed for artificial intelligence, which can be understood as a type of ASIC, such as a neural network processing unit (NPU), a tensor processing unit (TPU), a deep learning processing unit (DPU), etc. It can be seen that each unit in the above device can be one or more processors (or processing circuits) configured to implement the above method. For example: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor forms. In addition, each unit in the above device can be integrated in whole or in part, or can be independently implemented. In some embodiments, these units are integrated together and implemented in the form of a system on chip (SOC). The SOC can include at least one processor for implementing any of the above methods or implementing the functions of each unit of the above device.

[0062] In the above embodiments, the descriptions of each embodiment have their own emphases. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. A phase-adjustable sampling circuit, characterized in that: include: A first differential branch, a second differential branch, a first correction circuit, a second correction circuit, a sub-analog-to-digital converter, and a third correction circuit; The first differential branch is connected between the first port and the first input terminal of the sub-ADC, and the first differential branch is configured to input a first differential signal from the first port; The second differential branch is connected between the second port and the second input terminal of the sub-ADC, the second differential branch is configured to input a second differential signal from the second port, the first differential signal and the second differential signal are a pair of differential signals having a first phase difference; The first correction circuit is connected between the second port and the first differential branch; the first correction circuit includes a plurality of first correction branches, the plurality of first correction branches are connected in parallel, wherein the first correction branch includes a first switch and a first correction capacitor; The second correction circuit is connected between the first port and the second differential branch; the second correction circuit includes a plurality of second correction branches, the plurality of second correction branches are connected in parallel, wherein the second correction branch includes a second switch and a second correction capacitor; The third correction circuit is coupled to the output end of the sub-analog-to-digital converter, and its first output end is coupled to the first correction circuit, and its second output end is coupled to the second correction circuit. It is configured to adjust the capacitance parameters of at least one of the first correction circuit and the second correction circuit based on the output result of the sub-analog-to-digital converter so that the first phase difference is close to or equal to 180°, thereby correcting the even harmonics in the sampling result of the sampling circuit.

2. The sampling circuit according to claim 1, characterized in that: The first differential branch includes: a first sampling switch and a first sampling capacitor, wherein the first sampling switch is connected between the first port and a first end of the first sampling capacitor; The second differential branch includes: a second sampling switch and a second sampling capacitor, wherein the second sampling switch is connected between the second port and a first end of the second sampling capacitor.

3. The sampling circuit according to claim 2, characterized in that: The second end of the first sampling capacitor is grounded, and the second end of the second sampling capacitor is grounded; One end of the first switch is coupled to the second port, and the other end is coupled to the first end of the first correction capacitor, and the second end of the first correction capacitor is grounded; One end of the second switch is coupled to the first port, and the other end of the second switch is coupled to the first end of the second correction capacitor. The second end of the second correction capacitor is grounded.

4. The sampling circuit according to claim 2, characterized in that: The second end of the first sampling capacitor is coupled to the first input end, and the second end of the second sampling capacitor is coupled to the second input end; The first correction branch includes a first switch and a first correction capacitor connected in series between the second port and the first input terminal; The second correction branch includes a second switch and a second correction capacitor connected in series between the first port and the second input terminal.

5. The sampling circuit according to claim 4, characterized in that: Also includes: A common mode voltage source, a first access switch and a second access switch connected in series between the first input terminal and the second input terminal; The common mode voltage source is configured to provide a common mode voltage to the first input terminal or the second input terminal based on control of the first access switch or the second access switch.

6. The sampling circuit according to any one of claims 1 to 5, characterized in that: The capacitance values ​​of the first correction capacitors in the plurality of first correction branches are the same or different; The capacitance values ​​of the second correction capacitors in the plurality of second correction branches are the same or different.

7. A sampling control method, characterized in that: Used to control the sampling circuit according to any one of claims 1 to 6, comprising: configuring a first correction capacitor parameter of the first correction circuit and a second correction capacitor parameter of the second correction circuit to be a first preset correction capacitor value; Adjusting the first preset correction capacitance value to a second preset correction capacitance value, wherein the first preset correction capacitance value is smaller than the second preset correction capacitance value; Obtaining a first output result of the sub-analog-to-digital converter; When the first output result satisfies a first preset parameter, adjusting one or more of the first correction capacitance value and the second correction capacitance value respectively; Obtaining a second output result of the sub-analog-to-digital converter; When the second output result satisfies a second preset parameter, the sub-ADC outputs the second output result, wherein the second output result includes a phase difference between the first differential signal and the second differential signal that is close to or equal to 180°.

8. The sampling control method according to claim 7, characterized in that: The first preset parameters include even harmonic parameters; The second preset parameter includes one or more of a phase error parameter and an amplitude error parameter.

9. An electronic device, characterized in that: The sampling circuit comprises the sampling circuit described in any one of claims 1 to 6.

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