Encryption and decryption method, device and system for PHY (Physical Layer)

Abstract

The invention provides an encryption and decryption method, device and system for a PHY (Physical Layer), and belongs to the technical field of communication. The PHY comprises an encryption module, the encryption module is used for receiving a first code stream, the encryption module is further used for encrypting the first code stream to obtain a second code stream, the encoding format of the first code stream is the same as that of the second code stream, the second code stream comprises a plurality of ciphertext segments, each ciphertext segment comprises a plurality of second code blocks, and the second code blocks are used for encoding the first code stream and the second code stream. The plurality of second code blocks correspond to a plurality of first code blocks in the first code stream, and outputting the second code stream. The encryption function is achieved in the PHY, user data are encrypted, information such as flow characteristics of the user data can also be encrypted, and the data transmission safety is improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an encryption and decryption method, device and system for a physical layer (PHY). Background Art

[0002] With the development of computing technology and networks, more and more data needs to be transmitted between devices. For example, the intelligent computing center uses a large amount of data as resources and uses powerful computing power to drive AI models to deeply process data, thereby generating various intelligent computing capabilities and providing them to users in the form of cloud services. In this process, a large amount of data is involved in the processing and transmission of network scenarios entering the intelligent computing center, within the intelligent computing center, and between intelligent computing centers.

[0003] In the process of data transmission, in order to prevent important data from being leaked, the data is encrypted during transmission. At present, the media access control security (MACsec) protocol is a commonly used security encryption technology in data networks. This encryption technology is implemented in the data link layer of the open system interconnection (OSI) reference model and is a standardized layer 2 encryption technology. The sender uses this encryption technology to encrypt user data, obtain encrypted data, and send the encrypted data to the receiver. The receiver decrypts the encrypted data and obtains the data sent by the sender.

[0004] Since the encryption technology of the MACsec protocol only protects user data, it may lead to poor security. Summary of the invention

[0005] The present application provides an encryption and decryption method, device and system for PHY, which can improve the security of data transmission. The technical solution is as follows:

[0006] In a first aspect, the present application provides a PHY, which includes an encryption module, which is used to receive a first code stream; the encryption module is also used to encrypt the first code stream to obtain a second code stream, the first code stream and the second code stream have the same encoding format, the second code stream includes multiple ciphertext segments, each of the multiple ciphertext segments includes multiple second code blocks, and the multiple second code blocks correspond to the multiple first code blocks in the first code stream; the encryption module is also used to output the second code stream.

[0007] In the solution shown in the present application, in the PHY below the media access control (MAC) layer, encrypting the code stream is equivalent to encrypting all upper layer information of the PHY, which can improve the security of data transmission.

[0008] In an optional manner, the PHY also includes an encoding module and a transcoding module, the encryption module is located between the encoding module and the transcoding module, and the encoding format is 64-bit (bit, B) / 66B encoding; the encoding module is used to send a first code stream to the encryption module, and the transcoding module is used to receive a second code stream sent by the encryption module.

[0009] In an optional manner, the first code stream includes a plurality of idle code blocks, and the encryption module is further used to delete at least one idle code block from the plurality of idle code blocks. In this way, deleting the idle code blocks in the first code stream can also reduce the amount of encrypted data.

[0010] In an optional manner, each of the multiple first code blocks includes a first synchronization header, and the encryption module is also used to compress the first synchronization header of each first code block to obtain a second synchronization header, and the second code block in the second code stream includes the encrypted second synchronization header.

[0011] In the solution shown in the present application, compressing the synchronization header in the first code block can reduce the amount of encrypted data.

[0012] In an optional manner, the length of the first synchronization header is 2 bits, and the length of the second synchronization header is 1 bit.

[0013] In an optional manner, the first code stream includes a third code block, the second code stream includes a fourth code block and a fifth code block, and the encryption module is also used to load part of the encrypted content of the third code block into the payload of the fourth code block and load the remaining content of the encrypted third code block into the payload of the fifth code block.

[0014] In an optional manner, each ciphertext segment in the multiple ciphertext segments includes N second code blocks, and the encryption module is also used to load the M first code blocks in the encrypted first code stream into the payload of the N second code blocks, and the M and N satisfy the following relationship: M*K=N*64, where K is the number of bits of each first code block in the M first code blocks during encryption.

[0015] In an optional manner, a start (S) code block and a termination (T) code block are respectively inserted into the head and tail of the N second code blocks to encapsulate into a ciphertext segment in the second code stream, the S code block is a start mark of the ciphertext segment in the second code stream, and the T code block is an end mark of the ciphertext segment in the second code stream. In this way, the ciphertext segment is defined by using the S code block and T, so that the receiving end can find the ciphertext segment.

[0016] In an optional manner, the encryption module is further used to insert a code block carrying integrity check information between the N second code blocks and the T code block.

[0017] In an optional manner, the encryption module is further used to insert an idle code block between two adjacent ciphertext segments in the multiple ciphertext segments.

[0018] In an optional manner, the PHY further includes an alignment marker (AM) insertion module and a physical medium attachment (PMA) sublayer; the encryption module is located between the AM insertion module and the PMA, and the first code stream is the code stream output by the AM insertion module.

[0019] In an optional manner, the PHY also includes a distribution module, the encryption module includes a first encryption unit and a second encryption unit, the first encryption unit is located between the AM insertion module and the distribution module, and the second encryption unit is located between the distribution module and the PMA; the first encryption unit is used to determine the AM fields of multiple logical channels in the first code stream, add ciphertext segment information to the AM field of each logical channel in the multiple logical channels according to the AM cycle, obtain a third code stream, and send the third code stream to the distribution module, each AM cycle includes multiple AM ​​fields, and the adjacent code streams after the AM fields included in each AM cycle are used to form a ciphertext segment, in each logical channel, the ciphertext segment information of the xth ciphertext segment includes the starting identifier and decryption parameters of the xth ciphertext segment, or the starting identifier of the xth ciphertext segment and the decryption parameters of the x+nth ciphertext segment, x is a positive integer, and n is a non-negative integer; the distribution module is used to distribute the received code stream to the multiple logical channels; the second encryption unit is used to encrypt the code stream between the AMs in each logical channel to obtain the second code stream.

[0020] In the scheme shown in this application, an AM cycle is defined, and the AM field within the AM cycle is used to define the ciphertext segment and carry information such as decryption parameters. There is no need to add additional fields, the encryption overhead is small, and it does not occupy user service bandwidth.

[0021] In an optional manner, the PHY also includes a first encryption module, an encoding module, a transcoding module, an AM insertion module and a PMA sublayer, the encryption module is located between the encoding module and the transcoding module, and the first encryption module is located between the AM insertion module and the PMA sublayer; the encryption module is also used to receive the first code stream sent by the encoding module and send the second code stream to the transcoding module; the first encryption module is used to encrypt the fourth code stream to obtain the fifth code stream, and send the fifth code stream to the PMA sublayer, the fourth code stream is the code stream after the second code stream is processed by the transcoding module and the AM insertion module, and the encoding format of the fourth code stream is the same as that of the fifth code stream.

[0022] In the solution shown in the present application, in PHY, the code stream is encrypted twice, which is equivalent to performing secondary protection on the code stream, thereby improving the security of data transmission.

[0023] In an optional manner, the encryption module is located in a physical coding sublayer (PCS).

[0024] In a second aspect, the present application provides a PHY, which includes a decryption module; the decryption module is used to receive a first encryption code stream, the first encryption code stream includes multiple ciphertext segments, each of the multiple ciphertext segments includes multiple first encryption code blocks; the decryption module is also used to decrypt the first encryption code stream to obtain a decrypted code stream, the decrypted code stream has the same encoding format as the first encryption code stream, and the multiple first encryption code blocks correspond to the multiple first decrypted code blocks in the decrypted code stream; the decryption module is also used to output the decrypted code stream.

[0025] In the solution shown in the present application, in the PHY below the MAC layer, the encrypted code stream is equivalent to encrypting all upper layer information of the PHY, which can improve the security of data transmission, and the encrypted code stream is decrypted accordingly in the PHY.

[0026] In an optional manner, the PHY also includes a reverse transcoding module and a decoding module; the decryption module is located between the reverse transcoding module and the decoding module, and the encoding format is 64B / 66B encoding; the reverse transcoding module is used to send a first encrypted code stream to the decryption module; the decoding module is used to receive the decrypted code stream sent by the decryption module.

[0027] In an optional manner, each of the multiple first decryption code blocks includes a second synchronization header; the decryption module is further used to recover the second synchronization header of each first decryption code block to obtain the first synchronization header.

[0028] In the solution shown in the present application, the second synchronization header in the first decrypted code block is restored to the first synchronization header, so that the synchronization header can be used to distinguish the data loaded in the payload in the first decrypted code block.

[0029] In an optional manner, the length of the first synchronization header is 2 bits, and the length of the second synchronization header is 1 bit.

[0030] In an optional manner, the first encryption code stream includes a second encryption code block and a third encryption code block, and the decryption code stream includes the second decryption code block; the decryption module is also used to unload the content belonging to the second decryption code block in the decrypted second encryption code block into the second decryption code block, and unload the content belonging to the second decryption code block in the decrypted third encryption code block into the second decryption code block.

[0031] In an optional manner, each ciphertext segment in the multiple ciphertext segments includes N first encryption code blocks; the decryption module is also used to unload the N first encryption code blocks in the decrypted ciphertext segment into M first decryption code blocks, and the M and N satisfy the following relationship: M*K=N*64, K is the number of bits of each first decryption code block in the M first decryption code blocks.

[0032] In an optional manner, the decryption module is also used to determine an S code block and a T code block in the first encryption code stream, the S code block being the start mark of the ciphertext segment in the first encryption code stream, and the T code block being the end mark of the ciphertext segment in the first encryption code stream; and unloading the N first encryption code blocks decrypted between the S code block and the T code block into the M first decryption code blocks.

[0033] In the scheme shown in the present application, each ciphertext segment starts and ends with an S code block and a T code block respectively. The use of S code blocks and T code blocks can quickly define the ciphertext segment.

[0034] In an optional manner, the code block adjacent to the S code block is a code block loaded with a first decryption parameter; the decryption module is also used to obtain the first decryption parameter from the code block adjacent to the S code block, use the first decryption parameter to decrypt the N first encryption code blocks, and unload them into the M first decryption code blocks.

[0035] In the scheme shown in the present application, the code block loaded with the first decryption parameter is immediately followed by the S code block, so that the first decryption parameter can be obtained at the beginning of the ciphertext segment, and the first encrypted code block in the ciphertext segment can be directly decrypted without waiting for the first decryption parameter, thereby reducing the code stream decryption delay.

[0036] In an optional manner, the code block adjacent to the T code block is a code block carrying integrity check information; the decryption module is also used to use the integrity check information to perform integrity check on the ciphertext segment to which it belongs.

[0037] In the solution shown in the present application, when decrypting a ciphertext segment, the integrity of the ciphertext segment can also be checked to confirm whether the ciphertext segment has been tampered with.

[0038] In an optional manner, the PHY further includes an AM deletion module and an AM locking module; the decryption module is located between the AM deletion module and the AM locking module; and the first encrypted code stream is a code stream output by the AM locking module.

[0039] In an optional manner, the first encrypted code stream is a code stream composed of code streams of multiple logical channels, the code stream of each logical channel in the multiple logical channels includes multiple AM ​​fields, the AM fields in the code stream of each logical channel are divided into multiple AM ​​cycles, and the adjacent code streams after the AM fields included in each AM cycle constitute a ciphertext segment; the PHY also includes a rearrangement module, the decryption module includes a first decryption unit and a second decryption unit; the first decryption unit is located between the AM locking module and the rearrangement module; the second decryption unit is located between the rearrangement module and the AM deletion module; the first decryption unit is used to, Based on the AM field in the code stream of each logical channel, the ciphertext segment of each logical channel is determined, and based on the cached second decryption parameters of the ciphertext segment of each logical channel, the ciphertext segment of each logical channel is decrypted to obtain a second decryption code stream, and the second decryption code stream is sent to a second decryption unit; the second decryption unit is used to obtain the second decryption parameters of each ciphertext segment in each logical channel from the AM field of the received decryption code stream according to the AM period, and for each logical channel, the second decryption parameter carried by the xth ciphertext segment is used to decrypt the x+kth ciphertext segment, where x and k are positive integers.

[0040] In the scheme shown in the present application, the second decryption parameter carried by the xth ciphertext segment is used to decrypt the x+kth ciphertext segment. The xth ciphertext segment is received earlier than the x+kth ciphertext segment, and the decryption parameter of the x+kth ciphertext segment can be obtained before decrypting the x+kth ciphertext segment. Therefore, after receiving the x+kth ciphertext segment, the x+kth ciphertext segment can be decrypted without waiting, thereby reducing the code stream decryption delay.

[0041] In an optional manner, the PHY also includes a first decryption module, an AM deletion module, an AM locking module, a reverse transcoding module and a decoding module; the first decryption module is located between the AM deletion module and the AM locking module, and the decryption module is located between the reverse transcoding module and the decoding module; the first decryption module is used to receive the second encrypted code stream sent by the AM locking module, decrypt the second encrypted code stream to obtain a third encrypted code stream, and send the third encrypted code stream to the AM deletion module, and the encoding format of the second encrypted code stream is the same as that of the third encrypted code stream; the decryption module is also used to receive the first encrypted code stream sent by the reverse transcoding module, and output the decrypted code stream to the decoding module, and the first encrypted code stream is the code stream after the third encrypted code stream is processed by the AM deletion module and the reverse transcoding module.

[0042] In the solution shown in the present application, when sending a code stream, the code stream is encrypted twice at the PHY, and when receiving the code stream, the code stream is decrypted twice at the PHY to obtain a decrypted code stream.

[0043] In an optional manner, the decryption module is located in the PCS.

[0044] In a third aspect, the present application provides a PHY system, the PHY system comprising a first PHY device and a second PHY device, the first PHY device having a function of implementing the PHY behavior in the first aspect, and the second PHY device having a function of implementing the PHY behavior in the second aspect. The functions are implemented based on hardware, or corresponding software implementations can be performed based on hardware. The hardware or software includes one or more modules corresponding to the above functions.

[0045] In a fourth aspect, the present application provides a PHY encryption method, which is applied to the PHY as described in the first aspect and possible implementations.

[0046] In an optional manner, the PHY belongs to a first PHY device.

[0047] In a fifth aspect, the present application provides a PHY decryption method, which is applied to the PHY as described in the first aspect and possible implementations.

[0048] In an optional manner, the PHY belongs to a second PHY device.

[0049] In a sixth aspect, the present application provides a first PHY device, wherein the structure of the first PHY device includes a processor and an interface, and the processor is configured to support the first PHY device to perform the corresponding functions in the above-mentioned corresponding method. The interface is used to support communication between the first PHY device and another PHY device, and receive information or instructions involved in the above-mentioned corresponding method from the other PHY device. The interface is also used to support communication between the first PHY device and a user equipment. The first PHY device may also include a memory, which is used to couple with the processor and store program instructions and data necessary for the first PHY device.

[0050] Alternatively, the first PHY device includes a main control board and an interface board, and further, may include a switching network board. The first PHY device is used to execute the method of the fourth aspect. Specifically, the first PHY device includes a module for executing the method of the fourth aspect.

[0051] Alternatively, the first PHY device includes a controller and a first forwarding sub-device. The first forwarding sub-device includes: an interface board, and further, may also include a switching network board. The first forwarding sub-device is used to perform the functions of the aforementioned interface board, and further, may also perform the functions of the aforementioned switching network board. The controller includes a receiver, a processor, a transmitter, a random access memory, a read-only memory, and a bus. Among them, the processor is respectively coupled to the receiver, the transmitter, the random access memory, and the read-only memory through the bus. Among them, when it is necessary to run the controller, the basic input / output system solidified in the read-only memory or the boot loader (bootloader) in the embedded system is used to boot the system to start, and the controller is guided to enter a normal operating state. After the controller enters the normal operating state, the application program and the action system are run in the random access memory, so that the processor performs the functions of the aforementioned main control board.

[0052] In a seventh aspect, the present application provides a second PHY device, wherein the structure of the second PHY device includes a processor and an interface, and the processor is configured to support the second PHY device to perform the corresponding functions in the above-mentioned corresponding method. The interface is used to support communication between the second PHY device and another PHY device, and receive information or instructions involved in the above-mentioned corresponding method from the other PHY device. The interface is also used to support communication between the second PHY device and a user equipment. The second PHY device may also include a memory, which is used to couple with the processor and store program instructions and data necessary for the second PHY device.

[0053] Alternatively, the second PHY device includes a main control board and an interface board, and further, may include a switching network board. The second PHY device is used to execute the method of the fifth aspect. Specifically, the second PHY device includes a module for executing the method of the fifth aspect.

[0054] Alternatively, the second PHY device includes a controller and a first forwarding sub-device. The first forwarding sub-device includes: an interface board, and further, may also include a switching network board. The first forwarding sub-device is used to perform the functions of the aforementioned interface board, and further, may also perform the functions of the aforementioned switching network board. The controller includes a receiver, a processor, a transmitter, a random access memory, a read-only memory and a bus. Among them, the processor is respectively coupled to the receiver, the transmitter, the random access memory and the read-only memory through the bus. Among them, when it is necessary to run the controller, it is started by the basic input / output system solidified in the read-only memory or the bootloader boot system in the embedded system, and the controller is guided to enter a normal operating state. After the controller enters the normal operating state, the application program and the action system are run in the random access memory, so that the processor performs the functions of the aforementioned main control board.

[0055] In an eighth aspect, the present application provides a computer storage medium for storing programs, codes or instructions used for the above-mentioned first PHY device, which can complete the functions of the above-mentioned first PHY device when the processor or hardware device executes these programs, codes or instructions; or, for storing programs, codes or instructions used for the above-mentioned second PHY device, which can complete the functions of the above-mentioned second PHY device when the processor or hardware device executes these programs, codes or instructions.

[0056] In a ninth aspect, the present application provides a chip, comprising a processor and an interface, wherein the chip has the function of implementing the PHY behavior in the first aspect and the function of the PHY behavior in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 is a schematic diagram of an AM field provided by an exemplary embodiment of the present application;

[0058] Figure 2 This is a schematic diagram of an encrypted transmission scenario provided by an exemplary embodiment of the present application;

[0059] Figure 3 It is a schematic diagram of an application scenario provided by an exemplary embodiment of the present application;

[0060] Figure 4 is a schematic diagram of an application scenario provided by another exemplary embodiment of the present application;

[0061] Figure 5 is a schematic diagram of an application scenario provided by another exemplary embodiment of the present application;

[0062] Figure 6 is a schematic diagram of a system architecture provided by an exemplary embodiment of the present application;

[0063] Figure 7 is a schematic diagram of a PHY with encryption function provided by an exemplary embodiment of the present application;

[0064] Figure 8 is a schematic diagram of a PHY with a decryption function provided by an exemplary embodiment of the present application;

[0065] Fig. 9 is a schematic diagram of a code stream transmission framework provided by an exemplary embodiment of the present application;

[0066] Fig.10 is a schematic diagram of a PHY with encryption function provided by another exemplary embodiment of the present application;

[0067] Fig.11 is a schematic diagram of a PHY with encryption function provided by another exemplary embodiment of the present application;

[0068] Fig.12 is a schematic diagram of an encryption process provided by yet another exemplary embodiment of the present application;

[0069] Fig.13 is a schematic diagram of a ciphertext segment provided by yet another exemplary embodiment of the present application;

[0070] Fig.14 is a schematic diagram of a PHY with a decryption function provided by another exemplary embodiment of the present application;

[0071] Fig.15 is a schematic diagram of a PHY with a decryption function provided by another exemplary embodiment of the present application;

[0072] Fig.16 is a schematic diagram of an encryption and decryption system provided by an exemplary embodiment of the present application;

[0073] Fig.17 is a schematic diagram of additional overhead comparison provided by an exemplary embodiment of the present application;

[0074] Fig.18 is a schematic diagram of data encryption transmission provided by an exemplary embodiment of the present application;

[0075] Fig.19 is a schematic diagram of a PHY with encryption function provided by another exemplary embodiment of the present application;

[0076] Fig. 20 is a schematic diagram of a PHY with encryption function provided by another exemplary embodiment of the present application;

[0077] Fig.21 is a schematic diagram of a ciphertext segment provided by yet another exemplary embodiment of the present application;

[0078] Fig. 22 is a schematic diagram of an AM field in an AM cycle provided by yet another exemplary embodiment of the present application;

[0079] Fig.23 is a schematic diagram of a PHY with a decryption function provided by another exemplary embodiment of the present application;

[0080] Fig.24 is a schematic diagram of a PHY with a decryption function provided by another exemplary embodiment of the present application;

[0081] Fig.25 is a schematic diagram of an encryption and decryption system provided by another exemplary embodiment of the present application;

[0082] Fig.26 is a schematic diagram of additional overhead comparison provided by an exemplary embodiment of the present application;

[0083] Fig. 27 is a schematic diagram of data encryption transmission provided by another exemplary embodiment of the present application;

[0084] Fig.28 is a schematic diagram of a PHY with encryption and decryption functions provided by an exemplary embodiment of the present application;

[0085] Fig.29 is a schematic diagram of a PHY with encryption and decryption functions provided by another exemplary embodiment of the present application;

[0086] Fig.30 is a flowchart of an encryption method provided by an exemplary embodiment of the present application;

[0087] Fig.31 is a flowchart of a decryption method provided by an exemplary embodiment of the present application;

[0088] Fig.32 is a schematic diagram of the structure of a device provided by an exemplary embodiment of the present application;

[0089] Fig.33 It is a structural schematic diagram of a device provided by another exemplary embodiment of the present application. DETAILED DESCRIPTION

[0090] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0091] With the development of network technology, a large amount of data will be transmitted in the network. For example, in the artificial intelligence (AI) scenario, as the iteration speed of AI models grows exponentially, as the infrastructure foundation for the development of AI technology, intelligent computing centers are gradually built and deployed on a large scale. Intelligent computing centers use a large amount of data as resources, and use powerful computing power to drive AI models to deeply process data, generate various intelligent computing capabilities, and provide them to users in the form of cloud services. In this process, a large amount of data is involved in the processing and transmission of network scenarios, and when entering the intelligent computing center, it is inside the intelligent computing center or between intelligent computing centers. This data is important data, and once leaked, it will have serious consequences. Therefore, how to ensure data security is the core issue of the development of intelligent computing centers. For scenarios entering the intelligent computing center, data uploaded in real time by the Internet or user devices must enter the intelligent computing center through a wide area network or a metropolitan area network. This data is used for AI training in the intelligent computing center, and there is a risk of leakage during transmission. For scenarios within the intelligent computing center, the models and parameters used in AI training or reasoning, as well as user data, need to be frequently transmitted between computing nodes, and there is also a risk of leakage. For scenarios between intelligent computing centers, the high-speed interconnected optical fiber links and related facilities used to transmit the computing resources of the intelligent computing centers are also exposed to the physical environment and are also subject to the risk of leakage. Therefore, user data needs to be securely encrypted when entering the intelligent computing center, when being transmitted within the intelligent computing center, and between intelligent computing centers.

[0092] The underlying network DC technology of the three network scenarios of the above-mentioned intelligent computing center is Ethernet, so it is necessary to provide Ethernet with security authentication, key management, and data encryption and decryption scenarios. Considering the pursuit of network performance such as latency and bandwidth by AI and high performance computing (HPC) carried by the intelligent computing center scenario, the Ethernet security technology of the intelligent computing center has the following capabilities.

[0093] 1. Low-latency and low-overhead data encryption and decryption capabilities. With the development of AI applications, the demand for high-throughput and low-latency data transmission between massive computing chips has become more urgent. Therefore, while providing secure encryption for Ethernet, it is also necessary to pay attention to the latency and overhead caused by data encryption.

[0094] 2. Full encryption capability of Ethernet frames and control protocols. Ethernet continuously sends some special protocol frames, such as priority-based flow control frames. These special protocol frames cannot be protected by traditional network security mechanisms. For application scenarios with high privacy protection requirements, Ethernet frames also need to be fully encrypted, including encrypting frame headers and hiding traffic features such as frame transmission frequency and frame length to prevent traffic analysis attacks.

[0095] 3. Simple and efficient authentication and key management mechanism. Authentication and key management involve a large number of security sessions, which consume the central processing unit (CPU) and network card memory resources of the computing node, affecting the computing efficiency of the computing node. Therefore, a simple and efficient authentication and key management mechanism is needed to reduce the number of security sessions.

[0096] The current security encryption mechanism can provide data security protection at different network levels, but it cannot meet the above-mentioned key capability requirements at the same time. For example, the media access control security protocol based on the Institute of Electrical and Electronics Engineers (IEEE) 802.1AE standard can provide secure encrypted communication frame by frame at the data link layer between Ethernet devices. Since the media access control security protocol encrypts user data, it will expose the Ethernet frame header information, and it cannot completely hide traffic characteristics such as message length and packet transmission frequency, which can be easily used for traffic analysis attacks. And it is difficult to be compatible with all existing devices. For example, it is necessary to perform back-to-back conversion from bit stream to packet and frame in the PHY chip, which will introduce additional implementation complexity and conversion delay, and also require the replacement of device hardware. In addition, the user's on-site application requirements for port encryption often change dynamically and are difficult to predict. For example, at present, only 8 ports support the media access control security protocol, which can basically meet the needs at the time. If more ports are needed in the future, only additional ports can be added.

[0097] Based on this, the embodiments of the present application provide physical layer (PHY) encryption and decryption technology, which protects all upper layer protocols by encrypting and decrypting data packets in Ethernet PHY, solves the security threats brought by traffic analysis attacks by hiding traffic characteristics, and realizes low-latency, low-overhead and protocol-transparent data encryption and decryption.

[0098] In order to better understand the embodiments of the present application, some terminology concepts involved in the embodiments of the present application are first explained.

[0099] 1. Ethernet media access control (MAC) / physical layer architecture: This is an architecture that receives messages from the user side and distributes them to multiple physical channels after processing. In this architecture, the messages received from the user side are assembled into Ethernet frames through MAC, and the code blocks are encoded in the physical coding sublayer (PCS) and distributed to multiple logical channels. Then, they are converted by bit multiplexing in the physical medium attachment (PMA) sublayer and distributed to multiple physical channels. Among them, bit multiplexing is deployed in PHY, mainly to complete the conversion of signal streams from m input channels to n output channels in a bit-interleaved manner. For example, when m:n=4:2, every two input channels are bit-interleaved into a bit stream of one output channel.

[0100] 2. MAC / PHY interface: It is a standard Ethernet interface defined by Ethernet IEEE802.3. The range of MAC / PHY interface is from MAC to PMA from top to bottom. MAC / PHY interface can be implemented by an independent chip, for example, in high-speed communication scenarios; or MAC / PHY interface can be implemented by multiple chips, for example, in low-speed communication scenarios, MAC is integrated on the central processing unit (CPU) side, and PHY is implemented by an independent chip. Therefore, MAC / PHY interface can also be called MAC / PHY chip.

[0101] 3. 64B / 66B encoding is a method of encoding input data into a 66-bit code block. The code block includes a 2-bit synchronization header and 64 bits of data. The 2-bit synchronization header is used to indicate whether the following 64 bits are data. When the 2 bits in the synchronization header indicate that it is not data, the first 8 bits of the 64 bits also indicate the code block type area, which is used to indicate the function of the code block. For example, if the 2 bits of the synchronization header are 01, it means that the following 64 bits are all data. If the 2 bits of the synchronization header are 10, it means that the following 64 bits are control information, or a mixture of data and control information.

[0102] 4. Logical channel, also known as virtual lane, for example, PCS lane or forward error correction (FEC lane) are virtual lanes, among which, in the 100Gbps (where Gb means gigabit and ps means per second) standard, it is FEC lane, and in the 200Gbps / 400Gbps standard, it is PCSlane. PCS distributes the serial bit stream to multiple channels, which are distributed inside the physical layer chip. These multiple channels are generally called virtual channels or logical channels. For example, in the 100Gbps standard Ethernet specification, the number of logical channels is 4, in the 200Gbps standard Ethernet specification, the number of logical channels is 8, and in the 400Gbps standard Ethernet specification, the number of logical channels is 16. PCS lane or FEC lane is called a logical channel to distinguish it from PMA lane. PMA Lane is a physical channel that can carry data from one or more logical channels. In 100Gbps, 200Gbps and 400Gbps high-speed Ethernet, the number of physical channels will vary depending on the implementation. 100Gbps can also be expressed as 100G / s, 200Gbps can also be expressed as 200G / s, and 400Gbps can also be expressed as 400G / s.

[0103] 5. AM field is the AM field of each logical channel in the IEEE802.3 specification. The AM field is 120 bits long and is used to merge multiple signals into one serial signal. For example, when a serial signal sent by the transmitter is sent to multiple logical channels, the AM field is periodically inserted into each logical channel. The receiver locks according to the AM field of each logical channel so as to merge the multiple signals of multiple logical channels into one serial signal. For the format of the AM field of 200G and 400G, see Figure 1 , the common marker (CM) 0, CM1, CM2, CM3, CM4 and CM5 fields are common identifiers of each logical channel, the unique marker (UM) 0, UM1, UM2, UM3, UM4 and UM5 fields uniquely identify a logical channel, and the unique pad (UP) 0, UP1 and UP2 fields are user-defined fields. For example, there are 8 logical channels in 200G, and each logical channel has a specified AM field. The receiving end can only lock a logical channel and correctly identify the logical channel when all the fields except UP0~UP2 fields are matched with the AM fields specified by the logical channel.

[0104] 6. Advanced Encryption Standard-Counter (AES-CTR) mode is a group symmetric key encryption algorithm. Grouping here means dividing the data to be encrypted into multiple groups, each with the same data length, and encrypting one group of data at a time until the entire data to be encrypted is encrypted. For example, in the AES standard specification, the group length is 128 bits.

[0105] The application scenarios of the embodiments of the present application are described below.

[0106] The encryption and decryption scheme in the embodiment of the present application is applied to data transmission between two Ethernet devices, where the Ethernet device is a switch, a router or a network card of a server in an Ethernet network. Figure 2 , two Ethernet devices include device A and device B, device A encrypts data to obtain encrypted data, sends the encrypted data to device B, device B receives the encrypted data, decrypts the encrypted data, and obtains decrypted data. Optionally, device A encrypts data through an Ethernet interface chip, and device B decrypts the encrypted data through an Ethernet interface chip.

[0107] In application scenario 1, device A and device B are directly connected via Ethernet optical fiber or cable. Figure 3 , device A is located in data center A and is the egress switch of data center A, device B is located in data center B and is the ingress switch of data center B, device A and device B are directly connected based on optical modules, and the distance between device A and device B is less than the distance threshold, such as the distance threshold is 80km.

[0108] In application scenario 2, the distance between device A and device B is relatively large, and device A and device B are connected over a long distance based on an optical transport network (OTN) or wavelength division multiplexing (WDM). Figure 4 , device A is located in data center A and is the egress switch of data center A, device B is located in data center B and is the ingress switch of data center B, data center A and data center B are connected through OTN, OTN is a network provided by the operator, OTN includes OTN device A and OTN device B, device A is connected to OTN device A in OTN, device B is connected to OTN device B in OTN, data is transmitted between device A and OTN device A through gray light, data is transmitted between OTN device A and OTN device B through color light, and data is transmitted between OTN device B and device B through gray light. Among them, data center A and data center B may belong to the same content provider or not.

[0109] In application scenario 3, device A and device B are connected based on a flexible dedicated line. For example, see Figure 5 Device A is the enterprise's egress network device, such as a switch or router, and device B is a switch in a data center. Device A passes through the OTN or packet transport network (PTN) of the operator's network. Specifically, device A is connected to device B through the OTN device in the OTN, or device A is connected to device B through the PTN device in the PTN.

[0110] Among them, in the three application scenarios, the data center can be an intelligent computing center.

[0111] The PHY in the embodiment of the present application is described below.

[0112] PHY has an encryption function, or has a decryption function, or has an encryption and decryption function. PHY is a PHY chip, and the PHY chip does not have the function of the MAC layer, or PHY is a combination of a PHY chip and a MAC chip. In the following, PHY is taken as an example of a combination of a PHY chip and a MAC chip.

[0113] Figure 6 Provides the system architecture of the encryption and decryption system. Figure 6 , the sending end has an encryption function, the receiving end has a decryption function, the physical layer in the sending end includes an encryption module, the physical layer in the receiving end includes a decryption module, or the sending end has encryption and decryption functions, the receiving end also has encryption and decryption functions, the physical layer in the sending end includes an encryption module and a decryption module, and the physical layer in the receiving end includes an encryption module and a decryption module. The physical layer of the sending end receives data from the upper layer, passes through the MAC / reconciliation sublayer (RS) chip, and reaches the PHY chip through the media independent interface (MII) interface. The encryption module in the PHY chip encrypts the data to obtain encrypted data. The encrypted data is sent to the PMA sublayer in the media module through the PMA sublayer of the PHY chip and the interface with the medium (some kind of attachment unit interface, xAUI), and is transmitted to the receiving end through the optical fiber or cable after passing through the PMA sublayer and the physical medium dependent (PMD) sublayer. The media module in the receiving end receives the encrypted data, and transmits the encrypted data to the physical layer of the receiving end through xAUI. The PHY chip in the physical layer of the receiving end decrypts the encrypted data, obtains the decrypted data, and transmits it to the MAC / RS chip through the MII interface. The above is sent to the upper layer to perform the corresponding function.

[0114] In the initialization phase, the processor at the transmitting end (such as a single-board processor) configures the PHY chip through the management data input / output (MDIO) interface to enable the encryption function of the PHY chip. The processor at the receiving end (such as a single-board processor) configures the PHY chip through the MDIO interface to enable the decryption function of the PHY chip. Alternatively, the processors at the transmitting end and the receiving end configure the PHY chip through the MDIO interface to enable the encryption and decryption functions of the PHY chip.

[0115] The encryption module of the physical layer of the sending end and the decryption module of the physical layer of the receiving end negotiate through the protocol to achieve handshake coordination between the sending end and the receiving end, including the definition of the ciphertext segment and the ciphertext segment at the beginning of encryption and decryption.

[0116] 1. The encryption function of the PHY at the transmitter.

[0117] See also Figure 7 The PHY includes an encryption module, which receives a first code stream, encrypts the first code stream, and obtains a second code stream. The first code stream and the second code stream have the same encoding format. The second code stream includes multiple ciphertext segments, each of which includes multiple second code blocks. The multiple second code blocks correspond to the multiple first code blocks in the first code stream. Here, "corresponding" means that the multiple second code blocks have the same data information as the multiple first code blocks, but the code blocks are divided differently and are encrypted. The encryption module outputs the second code stream.

[0118] Among them, the encryption module encrypts the first code stream to obtain the second code stream. Generally speaking, there are two encryption schemes. The first encryption scheme: encrypt the first code stream in 64B / 66B format between the encoding module and the transcoding module to obtain the second code stream; the second encryption scheme: encrypt the first code stream between the AM insertion module and the PMA sublayer to obtain the second code stream;

[0119] In addition, after obtaining the second code stream, the second code stream can also be encrypted using the encryption method of the second scheme to obtain the encrypted second code stream, that is: the first code stream in 64B / 66B format is encrypted between the encoding module and the transcoding module to obtain the second code stream, and the second code stream is encrypted again between the AM insertion module and the PMA sublayer to obtain the fourth code stream. This encryption scheme is called the third encryption scheme.

[0120] In an optional manner, the encryption module is located in a physical coding sublayer (PCS), a data terminal equipment extender sublayer (DTE XS), or a PHY extender sublayer (XS).

[0121] 2. Decryption function of PHY at the receiving end.

[0122] See also Figure 8 The PHY includes a decryption module, which receives the second code stream, decrypts the second code stream, and obtains the first code stream.

[0123] Among them, corresponding to the two encryption schemes of the encryption module, the decryption module decrypts the second code stream to obtain the first code stream. Generally speaking, there are two decryption schemes. The first decryption scheme: decrypt the second code stream in 64B / 66B format between the decoding module and the reverse transcoding module to obtain the first code stream; the second decryption scheme: decrypt the second code stream between the AM insertion module and the AM locking module to obtain the first code stream.

[0124] In addition, at the sending end, the encryption module encrypts the first code stream twice. When decrypting the twice encrypted first code stream, decryption is performed once between the AM insertion module and the AM locking module, and the decrypted code stream is decrypted again between the decoding module and the reverse transcoding module. This decryption scheme is called the third decryption scheme.

[0125] In an optional manner, the decryption module is located in the PCS, DTE XS or PHY XS.

[0126] In an optional manner, in the first encryption scheme, the handshake collaboration process between the sender and the receiver is:

[0127] The sender sends an unencrypted ciphertext segment to the receiver, notifying the receiver that the ciphertext segment is defined by the S code block and the T code block, the encryption start position, and the code block where the decryption parameters are located. After receiving the ciphertext segment, the receiver returns a confirmation message to the sender. After receiving the confirmation message, the sender starts encrypting the ciphertext segment from the encryption start position. In addition, the sender also notifies the receiver of the code block where the integrity check information is located.

[0128] The receiving end is notified of the encryption start position at the first moment after sending the unencrypted ciphertext segment, or L ciphertext segments after sending the unencrypted ciphertext segment, or the receiving end is notified that the specified bit position in the S code block is modified to the specified field, indicating the start of encryption.

[0129] In an optional manner, in the second encryption scheme, the handshake collaboration process between the sender and the receiver is:

[0130] The sender sends an unencrypted ciphertext segment to the receiver, notifying the receiver that the ciphertext segment is defined by the multiframe header, the encryption start position, and the location of the decryption parameters. After receiving the ciphertext segment, the receiver returns a confirmation message to the sender. After receiving the confirmation message, the sender starts encrypting the ciphertext segment from the encryption start position.

[0131] The receiving end is notified of the encryption start position at the first moment after sending the unencrypted ciphertext segment, or L ciphertext segments after sending the unencrypted ciphertext segment, or the receiving end is notified of the modification of the specified bit in the multi-frame header to the specified field, indicating the start of encryption.

[0132] In an optional manner, in the third encryption scheme, the handshake collaboration process between the sender and the receiver is a combination of the first scheme and the second scheme, which will not be repeated here.

[0133] a. Based on application scenario 2, describe the first encryption scheme and the first decryption scheme.

[0134] See also Fig. 9 , 100Gbps gray light is used for transmission between device A and OTN device A, 100Gbps color light is used for transmission between OTN device A and OTN device B, and 100Gbps gray light is used for transmission between device B and OTN device B. Device A needs to transmit important data to device B, such as AI training models, parameters, and data, which need to be encrypted. Device A includes Figure 7 As shown in the PHY, device B includes Figure 8 As a whole, the PHY of device A encrypts the first code stream in 64B / 66B format to encrypt all data frames, protocol frames, and inter-frame idle frames. At OTN device A, OTN device A maps the encrypted 64B / 66B code stream to the OTN pipe through the generic mapping procedure (GMP) or GFP-T mapping procedure and transmits it to the remote OTN device B.

[0135] OTN device B recovers the 64B / 66B format code stream and transmits it to device B. The PHY of device B decrypts the encrypted 64B / 66B format code stream, restores the 64B / 66B format code stream corresponding to the original data frame, protocol frame and inter-frame idle, and sends it to the upper-layer functional module for processing.

[0136] a1. Encrypt the code stream in 64B / 66B format between the encoding module and the transcoding module.

[0137] PHY also includes an encoding module and a transcoding module. The encoding module is an encoding module in 64B / 66B format, and the transcoding module is a transcoding module in 256B / 257B format. The encryption module is located between the encoding module and the transcoding module. The encoding module receives a code stream from the MAC layer through the MII interface, encodes the code stream into a first code stream, the encoding format of the first code block in the first code stream is 64B / 66B, and sends the first code stream to the encryption module. The encryption module receives the first code stream, encrypts the first code stream, and obtains a second code stream. The encoding format of the second code block in the second code stream is still 64B / 66B. The encryption module sends the second code stream to the transcoding module. The transcoding module receives the second code stream and transcodes the second code stream into a code stream in 256B / 257B format.

[0138] When PHY is used at 100 Gbps or less, see Fig.10 , PHY also includes a scrambling module, an AM insertion module, a Reed-Solomon forward error correction (RS-FEC) module, a distribution module and a PMA sublayer.

[0139] Among them, the transcoding module sends a code stream in 256B / 257B format to the scrambling module, the scrambling module scrambles the code stream in 256B / 257B format to obtain a scrambled code stream in 256B / 257B format, and sends the scrambled code stream in 256B / 257B format to the AM insertion module. The AM insertion module adds an AM field to the scrambled code stream in 256B / 257B format to obtain a code stream with an AM field added. The AM insertion module sends the code stream with the AM field added to the RS-FEC module. The RS-FEC module adds check bits to the code stream with the AM field added (such as adding 300 check bits to a 5140-bit code stream), obtains a FEC-protected code stream, and sends the FEC-protected code stream to the distribution module. The distribution module distributes the FEC-protected code stream to multiple logical channels. The PMA sublayer distributes the code streams of multiple logical channels to physical channels for transmission.

[0140] In the case of PHY applications above 100 Gbps, see Fig.11 , PHY also includes a scrambling module, an AM insertion module, a pre-FEC distribution module, an RS-FEC module, a distribution module and a PMA sublayer. The RS-FEC module includes multiple RS-FEC submodules, and the number of multiple RS-FEC submodules is set according to the network to which they are applied. For example, if the PHY is applied to 200Gbps or 400Gbps, the number of RS-FEC submodules is 2, and if the PHY is applied to 800Gbps, the number of RS-FEC submodules is 4.

[0141] Among them, the transcoding module sends a code stream in 256B / 257B format to the scrambling module, the scrambling module scrambles the code stream in 256B / 257B format to obtain a scrambled code stream in 256B / 257B format, and sends the scrambled code stream in 256B / 257B format to the AM insertion module. The AM insertion module adds an AM field to the received code stream to obtain a code stream with an AM field added. The AM insertion module sends the code stream with the AM field added to the FEC pre-distribution module. The FEC pre-distribution module distributes the code stream with the AM field added to multiple RS-FEC sub-modules. Multiple RS-FEC sub-modules add check bits to the received code stream to obtain a FEC-protected code stream, and send the FEC-protected code stream to the distribution module. The distribution module distributes the FEC-protected code stream to multiple logical channels. The PMA sublayer maps the code streams of multiple logical channels to multiple physical channels for transmission. Fig.11 The case where the PHY is applied to 200 Gbps or 400 Gbps is shown.

[0142] In an optional manner, the first code stream includes a plurality of idle code blocks, and the plurality of idle code blocks are used for rate adaptation between the receiving end and the transmitting end, etc. In order to reduce the amount of data to be encrypted, the encryption module deletes at least one idle code block from the plurality of idle code blocks, and then the encryption module encrypts the first code stream to obtain a second code stream.

[0143] In an optional manner, each of the plurality of first code blocks includes a first synchronization header, and the first synchronization header is used to identify whether the payload in the first code block is data or control information. In order to reduce the amount of data to be encrypted, the first synchronization header of each first code block is compressed to obtain a second synchronization header.

[0144] Optionally, the length of the first synchronization header is 2 bits, and the length of the second synchronization header is 1 bit. The first synchronization header is 01, indicating that the payload of the first code block is all data, and the first synchronization header is 10, indicating that the payload of the first code block is not all data. When the first synchronization header is 01, the second synchronization header is 1, and when the first synchronization header is 10, the second synchronization header is 0, or when the first synchronization header is 01, the second synchronization header is 0, and when the first synchronization header is 10, the second synchronization header is 1.

[0145] In an optional manner, in order to better understand the encryption process, the encryption of the third code block in the first code stream is used as an example for explanation, and the third code block is one of the multiple first code blocks. The encryption module encrypts the third code block to obtain the encrypted third code block. The encryption module loads part of the content in the encrypted third code block into the payload of the fourth code block, and loads the remaining content of the encrypted third code block into the payload of the fifth code block. The fourth code block and the fifth code block are two adjacent second code blocks in the second code stream. In this way, it is equivalent to that the internal content of the encrypted third code block is loaded into the two second code blocks in the second code stream.

[0146] In an optional manner, a ciphertext segment includes N second code blocks. The encryption module obtains M first code blocks in the encrypted first code stream and loads them into the payload of N second code blocks. The relationship between M and N is: M*K=N*64, K is the number of bits of each first code block in the M first code blocks during encryption. Since the payloads of the N second code blocks are all encrypted data, the synchronization header of each second code block in the N second code blocks is used to indicate that the payload of the second code block is data. Among them, the values ​​of M and N can be set according to actual needs. For example, when the value of K is 65, the values ​​of M and N are 512 and 520 respectively.

[0147] Optionally, the encryption module receives a first code stream in 64B / 66B format from the encoding module. The encryption module encrypts the 66-bit first code block. For example, the encryption module uses the AES-CTR encryption algorithm for encryption, takes M consecutive 66-bit first code blocks, and then divides them into 128-bit bit units, inputs the 128-bit bit unit, the key, and the initialize variable (IV) into the encryption algorithm (the encryption algorithm is also called a security algorithm), and outputs a 128-bit ciphertext unit. In the 128-bit ciphertext unit, every 64 bits are loaded into the payload area of ​​a 66-bit second code block, so that the 128-bit ciphertext requires 2 66-bit second code blocks to load. The number of 128-bit ciphertext units generated by the M 66-bit code blocks is M*66 / 128, and the number of second code blocks required is N=2*M*66 / 128. In this way, after encrypting the M first code blocks, a ciphertext segment including N second code blocks is obtained.

[0148] Optional, see Fig.12 The encryption process shown in FIG. 1 is as follows: The encryption module receives a first code stream in 64B / 66B format from the encoding module, compresses a first synchronization header of a first code block into 1 bit, and obtains a 65-bit first code block. Optionally, at least one idle code block in the first code stream is deleted.

[0149] The encryption module encrypts the 65-bit first code block. For example, the encryption module uses the AES-CTR encryption algorithm for encryption, takes M consecutive 65-bit first code blocks, and then divides them into 128-bit bit units, inputs the 128-bit bit units, the secret key and the initialization variable into the encryption algorithm, and outputs a 128-bit ciphertext unit. In the 128-bit ciphertext unit, every 64 bits are loaded into the payload area of ​​a 66-bit second code block, so that the 128-bit ciphertext requires 2 66-bit second code blocks to load. The number of 128-bit ciphertext units generated by the M 65-bit code blocks is M*65 / 128, and the number of second code blocks required is N=2*M*65 / 128. In this way, after encrypting the M first code blocks, a ciphertext segment including N second code blocks is obtained. In this way, since the first synchronization header is compressed, the amount of data to be encrypted can be reduced.

[0150] It should be noted that when using AES-CTR for encryption, the key length supports 128 bits, 192 bits or 256 bits. In the embodiments of the present application, the encryption algorithm is not limited. Any algorithm that can be used to encrypt the first code block can be applied to the embodiments of the present application. For example, the commercial secret algorithm (shang mi 4, SM4) can also be used.

[0151] Alternatively, see Fig.12 and Fig.13 In the ciphertext segment shown in FIG. 1 , after obtaining N second code blocks, the encryption module inserts an S code block at the head of the N second code blocks and inserts a T code block at the tail of the N second code blocks to encapsulate the ciphertext segment in the second code stream. The S code block is the start mark of the ciphertext segment in the second code stream, and the T code block is the end mark of the ciphertext segment in the second code stream. The S code block and the T code block are used to define the start and end of the ciphertext segment.

[0152] Alternatively, see Fig.12 and Fig.13The ciphertext segment shown in the figure has a code block carrying a first decryption parameter inserted after the S code block, and the first decryption parameter is used to decrypt the ciphertext segment to which it belongs. For example, the code block carrying the first decryption parameter is located between the S code block and the N second code blocks. The first decryption parameter includes a private key index (key index), an encryption version (version), encryption (encryption, En) indication information, authenticity (authenticity, Au) indication information, a secure channel number (secure channel number, SC No.) and a ciphertext segment number (segment number, SN), etc., wherein the private key index is used to search for a private key, the encryption version is used to indicate the encryption algorithm version used for encryption, En is used to indicate whether encryption is performed, Au is used to indicate whether integrity verification is implemented, SC No. indicates the number of the secure channel used, and one secure channel corresponds to one or more logical channels, and SN is used to indicate the number of the ciphertext segment.

[0153] Alternatively, see Fig.12 and Fig.13 In the ciphertext segment shown, in order for the receiving end to perform integrity check on the ciphertext segment, the encryption module calculates and generates integrity check information for the ciphertext segment, and inserts a code block carrying the integrity check information between the T code block and the N second code blocks, and the integrity check information includes an integrity check value. The code block carrying the integrity check information may be one or more. For example, 1.

[0154] Optionally, in order to adapt the transmitting and receiving end rates and frequency deviation, at least one idle code block is inserted between adjacent ciphertext segments.

[0155] It should be noted that the ciphertext segment is a fixed-length field. During encryption, in order to optimize latency, the second code block is sent to the transcoding module while encryption is in progress. That is, the S code blocks of a ciphertext segment and the code block carrying the first decryption parameter are sent first, and then the N second code blocks are sent in sequence.

[0156] In the ciphertext segment, the code block carrying the first decryption parameter and the code block carrying the integrity check information are both data code blocks, and the synchronization header is 01.

[0157] a2. Decrypt the 64B / 66B code stream between the decoding module and the reverse transcoding module.

[0158] PHY also includes a decoding module and a reverse transcoding module. The decoding module is a decoding module in 64B / 66B format, and the reverse transcoding module is a reverse transcoding module in 256B / 257B format. The decryption module is located between the decoding module and the reverse transcoding module. The reverse transcoding module receives the second code stream from the lower layer, sends the second code stream to the decryption module, and the decryption module receives the second code stream, decrypts the second code stream, and obtains the first code stream. The decryption module sends the first code stream to the decoding module. The decoding module receives the first code stream, decodes the first code stream into a code stream that can be transmitted by the MII interface, and sends the code stream to the MAC layer through the MII interface.

[0159] When PHY is used at 100 Gbps or less, see Fig.14 , PHY also includes a descrambling module, an AM delete module, an RS-FEC module, a reorder module, a deskew module, an AM lock module and a PMA sublayer.

[0160] Among them, the PMA sublayer sends the code streams of multiple logical channels to the AM locking module, the AM locking module performs locking processing on the code streams of multiple logical channels, and then sends the code streams to the jitter elimination module. The jitter elimination module performs jitter elimination on the code streams received from each logical channel, and sends the code streams of multiple logical channels after jitter elimination to the rearrangement module. The rearrangement module rearranges and interweaves the code streams of multiple logical channels into one code stream, and sends the one code stream to the RS-FEC module. The RS-FEC module performs error correction processing on the one code stream, and sends the one code stream after error correction processing to the AM deletion module. The AM deletion module deletes the AM field in the one code stream after error correction processing, and sends the code stream after the AM field is deleted to the descrambling module. The descrambling module performs descrambling processing on the code stream after the AM field is deleted, and sends the descrambled code stream to the reverse transcoding module. The reverse transcoding module converts the descrambled code stream into a second code stream in 64B / 66B format, and sends the second code stream to the decryption module. The decryption module decrypts the second code stream to obtain the first code stream.

[0161] In the case of PHY applications above 100 Gbps, see Fig.15, PHY also includes a descrambling module, an AM deletion module, a post FEC interleave module (also called an interleaving module), an RS-FEC module, a rearrangement module, a jitter elimination module, an AM locking module and a PMA sublayer. Among them, the RS-FEC module includes multiple RS-FEC submodules, and the number of multiple RS-FEC submodules is set according to the network to which they are applied. For example, if the PHY is applied to 200Gbps or 400Gbps, the number of RS-FEC submodules is 2, and if the PHY is applied to 800Gbps, the number of RS-FEC submodules is 4. Fig.14 The difference is that after multiple RS-FEC submodules perform error correction on the received code stream, they send the error-corrected code stream to the interleaving module. The interleaving module interleaves the code streams sent by multiple RS-FEC submodules into one code stream, sends the code stream to the AM deletion module, and the rest of the processing is the same as Fig.14 The process is the same as shown in , and will not be repeated here. Fig.15 The case where the PHY is applied to 200 Gbps or 400 Gbps is shown.

[0162] In an alternative approach, Fig.16 It shows the data transmission process from the sending end to the receiving end.

[0163] In an optional manner, the process of the decryption module decrypting the second code stream is as follows: the decryption module receives the second code stream, finds the S code block in the second code stream, extracts the first decryption parameter from the first adjacent code block after the S code block, and uses the first decryption parameter to decrypt the ciphertext segment to which the S code block belongs to obtain the decrypted code stream of the ciphertext segment.

[0164] In an optional manner, a ciphertext segment includes N second code blocks. The decryption module obtains the N second code blocks in the decrypted second code stream and places them into the N first code blocks, where the relationship between M and N is: M*K=N*64, where K is the number of bits of each second code block in the M second code blocks during decryption.

[0165] In an optional manner, in order to better understand the decryption process, the decryption of the fourth code block and the fifth code block in the second code stream is taken as an example for explanation, the fourth code block and the fifth code block are two adjacent code blocks in the plurality of second code blocks, and the decryption code block decrypts the fourth code block and the fifth code block to obtain the decrypted fourth code block and the fifth code block. The decryption module places the content belonging to the third code block in the decrypted fourth code block in the third code block, and places the content belonging to the third code block in the decrypted fifth code block in the third code block, and the third code block is a first code block in the plurality of first code blocks in the first code stream.

[0166] Optionally, the encryption algorithm is AES-CTR, the decryption module finds the S code block, extracts the first decryption parameter from the first code block adjacent to the S code block, extracts 128-bit ciphertext from the second and third code blocks, and the decryption module inputs the extracted ciphertext and the first decryption parameter into the decryption algorithm for decryption to obtain the plaintext of the second and third code blocks. In this way, the code blocks in the ciphertext segment are decrypted in turn to obtain a 128-bit plaintext stream. The 128-bit plaintext stream is then divided into 66 bits to obtain multiple 66-bit groups, each of which is a 66-bit code block, so that the standard 64B / 66B format code stream is restored to obtain the first code stream.

[0167] Optionally, the encryption algorithm is AES-CTR, and the synchronization header is also compressed during encryption. The decryption module finds the S code block, extracts the first decryption parameter from the first code block adjacent to the S code block, and extracts 128-bit ciphertext from the second and third code blocks. The decryption module inputs the extracted ciphertext and the first decryption parameter into the decryption algorithm for decryption to obtain the plaintext of the second and third code blocks. In this way, the code blocks in the ciphertext segment are decrypted in turn to obtain a 128-bit plaintext stream. The 128-bit plaintext stream is then grouped according to 65 bits to obtain multiple 65-bit groups, and the second synchronization header in each group is expanded to the first synchronization header so that each group includes 66 bits, thereby restoring the standard 64B / 66B format code stream to obtain the first code stream.

[0168] Optionally, the T code block, the S module and the code block carrying the first decryption parameter are deleted in the ciphertext segment.

[0169] Optionally, in the case where the ciphertext segment also includes a code block carrying integrity check information, for each ciphertext segment, the integrity check information is extracted from a code block before the T code block, the integrity check information includes an integrity check value, and the integrity check value of the ciphertext segment is calculated using an integrity check algorithm. If the calculated integrity check value is the same as the carried integrity check value, it is determined that the integrity check passes; if the calculated integrity check value is different from the carried integrity check value, it is determined that the ciphertext segment has been tampered with during transmission, and the decryption module can discard the ciphertext segment or continue to send it to the decoding module, and issue an alarm prompt.

[0170] After the integrity check is performed, the code block carrying the integrity check information is deleted.

[0171] It should be noted that when the decryption module is decrypting, in order to optimize the delay, it forms a 64B / 66B format code stream and sends it to the decoding module while decrypting, that is, starting from the decryption of N in the ciphertext segment and the first code block in the second code block, it decrypts and sends it at the same time.

[0172] In the embodiment of the present application, all information is encrypted, so the traffic feature information is hidden, and all protocols and data are encrypted. The embodiment of the present application also provides an encryption comparison table of the first encryption scheme and some other current schemes, which currently include transport layer security (TLS) / datagram transport layer security (DTLS), Internet security protocol and MAC security protocol, see Table 1.

[0173] Table 1

[0174]

[0175]

[0176] In addition, when the values ​​of M and N are 520 and 512 respectively, the solution of the embodiment of the present application is adopted, even if the idle code block is not deleted, The first "2" in the denominator indicates that there are two code blocks, the S code block and the T code block. The second "2" indicates that there is a code block carrying integrity check information and a code block carrying the first decryption parameter. The "1" in the denominator indicates that an idle code block is inserted. Since the utilization rate is greater than or equal to 97%, the additional overhead is close to 0, see Fig.17 , the dotted line represents the change of the additional overhead of MAC layer encryption with the frame length of Ethernet frame, and the solid line represents the change of the additional overhead of physical layer encryption with the frame length of Ethernet frame in the embodiment of the present application. The additional overhead of MAC layer encryption is greater than the solution shown in the embodiment of the present application.

[0177] b. Based on application scenario 1, describe the second encryption scheme and the second decryption scheme.

[0178] See also Fig.18 , the data transmitted between device A and device B is relatively important and needs to be encrypted. Device A includes Figure 7 As shown in the PHY, device B includes Figure 8 The PHY shown. Generally speaking, the PHY of device A encrypts the code stream of each logical channel to encrypt all data frames, protocol frames, and interframe idle. The PHY of device B uses the AM field to decrypt the code stream of each logical channel, restore the code stream corresponding to the original data frame, protocol frame, and interframe idle, and send it to the upper-layer functional module for processing.

[0179] b1. Encrypt the code stream between the AM insertion module and the PMA sublayer.

[0180] The PHY further includes an AM insertion module and a PMA sublayer. The encryption module is located between the AM insertion module and the PMA sublayer. The encryption module includes a first encryption unit and a second encryption unit.

[0181] When PHY is used at 100 Gbps or less, see Fig.19 The PHY further includes a scrambling module, an AM insertion module, an RS-FEC module, a distribution module and a PMA sublayer. The first encryption unit is located between the AM insertion module and the RS-FEC module, and the second encryption unit is located between the distribution module and the PMA sublayer.

[0182] Among them, the encoding module sends a code stream in 64B / 66B format to the transcoding module. The transcoding module transcodes the code stream in 64B / 66B format into a code stream in 256B / 257B format, and sends the code stream in 256B / 257B format to the scrambling module. The scrambling module scrambles the code stream in 256B / 257B format to obtain a scrambled code stream in 256B / 257B format, and sends the scrambled code stream in 256B / 257B format to the AM insertion module. The AM insertion module adds an AM field to the scrambled code stream in 256B / 257B format to obtain a code stream with an AM field added, which is called the first code stream. The AM insertion module sends the first code stream to the first encryption unit. The first encryption unit determines the AM fields of multiple logical channels in the first code stream, divides the AM field of each logical channel into periods according to the AM period, and multiple AM ​​fields are continuous in each divided AM period, and the adjacent code streams after multiple AMs are used to form a ciphertext segment. The first encryption unit adds ciphertext segment information to the AM field in each cycle to obtain a third code stream. In each logical channel, the ciphertext segment information of the xth ciphertext segment includes the starting identifier and decryption parameters of the xth ciphertext segment, or the starting identifier of the xth ciphertext segment and the decryption parameters of the x+nth ciphertext segment, where x is a positive integer and n is a non-negative integer. The first encryption unit sends the third code stream to the RS-FEC module. The RS-FEC module adds check bits to the third code stream to obtain a code stream protected by FEC, and sends the FEC-protected code stream to the distribution module. The distribution module distributes the FEC-protected code stream to multiple logical channels. The second encryption unit encrypts the code stream between AMs in each logical channel to obtain a second code stream, the second code stream includes code streams of multiple logical channels, and the code stream of each logical channel includes multiple ciphertext segments. The second encryption unit sends the second code stream to the PMA sublayer. The PMA sublayer distributes the code streams of multiple logical channels to the physical channel for transmission.

[0183] In the case of PHY applications above 100 Gbps, see Fig. 20, the PHY also includes a scrambling module, an AM insertion module, a FEC pre-distribution module, an RS-FEC module, a distribution module and a PMA sublayer. The first encryption unit is located between the AM insertion module and the FEC pre-distribution module, and the second encryption unit is located between the distribution module and the PMA sublayer. The RS-FEC module includes multiple RS-FEC submodules, and the number of the multiple RS-FEC submodules is set according to the network to which they are applied. For example, if the PHY is applied to 200Gbps or 400Gbps, the number of RS-FEC submodules is 2, and if the PHY is applied to 800Gbps, the number of RS-FEC submodules is 4. Fig. 20 The case where the PHY is applied to 200 Gbps or 400 Gbps Ethernet is shown. Fig. 20 The encryption process shown in Fig.19 The encryption process shown is not repeated here.

[0184] It should be noted that the encoding format of the first code stream is 256B / 257B, and the encoding format of the second code stream is also 256B / 257B. When the second encryption scheme is used for encryption, the encoding format does not change.

[0185] In an optional manner, the user-definable domain in the AM field can be used to carry information related to the ciphertext segment. An AM field includes UP0+UP1+UP2, a total of 24 bits, with 2 bits taking the value of "10" to indicate the start of the ciphertext segment, repeated 12 times, that is, the 8-bit binary value of UP0 is "10101010", the 8-bit binary value of UP1 is "10101010" and the 8-bit binary value of UP2 is "10101010", and these 24 bits are the start identifier. "10" here is an example, and it can also be other values, such as "01" or "11", or "00", etc. For another example, of the 24 bits of the start identifier, the first 12 bits can be repeated "10", and the last 12 bits can be repeated "01". For another example, the start identifier occupies part of the 24 bits, such as the first 12 bits.

[0186] Select the second AM field in the AM cycle, which contains UP0+UP1+UP2, a total of 24 bits. Use 2 bits with values ​​of "10" and "01" to represent the key index. "10" changes to "01" or "01" changes to "10", indicating that the next ciphertext segment will use a new encryption key. "10" or "01" is repeated 12 times. When encryption starts for the first time, "10" is taken, that is, the 8-bit binary value of UP0 is "10101010", the 8-bit binary value of UP1 is "10101010", and the 8-bit binary value of UP2 is "10101010".

[0187] Select UP0+UP1+UP2 of the subsequent Y AM fields of the AM field of the logical channel identifier key index to carry IV. In the embodiment of the present application, the length of IV is 12 bytes, and some other information is added, requiring a total of 11 AM fields, see Fig.21 The ciphertext segment shown in the figure. The data between AM in the ciphertext segment constitutes an encrypted object, and AM does not participate in encryption and decryption.

[0188] Optionally, the key index can be configured and modified by a microcontroller unit (MCU) at the sending end. When encryption is started for the first time, the IV can be configured by the MCU, and subsequent IVs can be automatically generated according to certain rules, for example, automatically generated by the first encryption unit and inserted into the AM field.

[0189] In an optional method, in order to achieve a balance between 0 and 1, the encoding method of UP0, UP1 and UP2 is: use [0~3] in UP0 and [0~7] in UP1 to carry the ciphertext segment information, and UP0[4~7] is the inverse of UP0[0~3], and UP2[0~7] is the inverse of UP1[0~7].

[0190] Fig. 22 The information stored in UP0+UP1+UP2 in the AM field of an AM cycle is given. Fig. 22 , each value in the horizontal direction 0-35 represents 1 bit. The first AM field (0AM field) stores the start identifier of the ciphertext segment (also called the multi-frame header), which occupies 24 bits. The second AM field (1AM field) stores the status (status), which is used to identify the current state of the ciphertext segment. Among them, 0b00 indicates that the local ciphertext segment is not locked, 0b01 indicates that the local ciphertext segment is locked and waiting for the remote ciphertext segment to be locked, 0b01 indicates that the local ciphertext segment is locked and the remote ciphertext segment is also locked, and 0b11 indicates reserved. The sender sends an unencrypted ciphertext segment to the receiver, and the receiver replies with a ciphertext segment to the sender. After mutual negotiation and confirmation that both parties have locked the ciphertext segment, the ciphertext segment is encrypted for transmission.

[0191] key index indicates the key index and is valid during the ciphertext segment lock time. 0b00 indicates that the local and remote ends have successfully completed the handshake and encryption has not yet started. 0b01 or 0b10 indicates that if the value is flipped, a new encryption key will be used for the next ciphertext segment. 0b11 indicates reserved.

[0192] IV includes: version, En, Au, number of ciphertext segment cycles, SC No., lane No. and ciphertext segment number. Version is a 4-bit protocol version number, and the default is 0001b. En uses 2 bits to indicate whether encryption is implemented, "0b00" means non-encryption, and "0b01" means encryption. Au uses 2 bits to indicate whether integrity verification is implemented, "0b00" means integrity verification is not implemented, and "0b01" means integrity verification is implemented. The number of ciphertext segment cycles uses 8 bits to indicate which ciphertext segment is in the current cycle, and the value ranges from 0 to 255. SC No. uses 6 bits to indicate the number of the security channel used. Lane No. indicates the number of the logical channel to which the ciphertext segment belongs. The number of the ciphertext segment uses 64 bits to indicate, the upper 32 bits are valid values, and the lower 32 bits are inverted.

[0193] In addition, the AM field also includes a reserve (Rsv) field.

[0194] Fig. 22 This is an example. The number of AM fields included in the AM cycle is set according to actual needs, and the embodiments of the present application do not limit this.

[0195] In an alternative approach, Fig.19 and Fig. 20 In the encryption, AES-CTR is also used. The second decryption unit inputs the code stream between the AM fields into the decryption algorithm together with the secret key and IV in units of 128 bits, outputs 128-bit ciphertext, and transmits it to PAM.

[0196] b2. Decrypt the code stream between the AM insertion module and the PMA sublayer.

[0197] The PHY further includes an AM deletion module and an AM locking module. The decryption module is located between the AM deletion module and the AM locking module. The decryption module includes a first decryption unit and a second decryption unit.

[0198] When PHY is used at 100 Gbps or less, see Fig.23 , the PHY also includes a decoding module, a reverse transcoding module, a descrambling module, an AM removal module, an RS-FEC module, a rearrangement module, a jitter elimination module, an AM locking module and a PMA sublayer. The first decryption unit is located between the jitter elimination module and the AM locking module, and the second decryption unit is located between the AM removal module and the RS-FEC module.

[0199] Among them, the PMA sublayer sends the code streams of multiple logical channels to the AM locking module, the AM locking module performs locking processing on the code streams of multiple logical channels, sends the code streams of multiple logical channels to the first decryption unit, and the code streams of the multiple logical channels constitute the second code stream. The first decryption unit uses the AM field in the code stream of each logical channel to determine the ciphertext segment of each logical channel. For any ciphertext segment, the cached second decryption parameter of the ciphertext segment is obtained. The second decryption parameter includes keyindex and IV information, and the key index is used to determine the secret key. The secret key, IV and the code stream in the ciphertext segment are input into the decryption algorithm to obtain the plaintext of the code stream. In this way, the ciphertext segment of each logical channel can be decrypted to obtain the decrypted code stream. The first decryption unit sends the code stream to the jitter elimination module. The jitter elimination module performs jitter elimination on the code streams received from each channel, and sends the code streams of multiple logical channels after jitter elimination to the rearrangement module. The rearrangement module rearranges the code streams of multiple logical channels into one code stream, and sends the one code stream to the RS-FEC module. The RS-FEC module performs error correction processing on the code stream and sends the error-corrected code stream to the second decryption unit. The second decryption unit obtains the second decryption parameters of each ciphertext segment of each logical channel from the AM field of the received code stream according to the AM cycle, and caches the second decryption parameters for subsequent ciphertext segment decryption. The second decryption unit sends the code stream after reading the second decryption parameter to the AM deletion module, and the code stream is the first code stream. The AM deletion module deletes the AM field in the code stream and sends the code stream after deleting the AM field to the descrambling module. The descrambling module performs descrambling processing on the code stream after deleting the AM field, and sends the descrambled code stream to the reverse transcoding module. The reverse transcoding module converts the descrambled code stream into a code stream in 64B / 66B format, and sends the code stream in 64B / 66B format to the decoding module. The decoding module decodes the code stream in 64B / 66B format and sends it to the upper-layer functional module.

[0200] In the case of PHY applications above 100 Gbps, see Fig.24 , the PHY also includes a decoding module, a reverse transcoding module, a descrambling module, an AM removal module, an interleaving module, an RS-FEC module, a rearrangement module, a jitter elimination module, an AM locking module and a PMA sublayer. The first decryption unit is located between the jitter elimination module and the AM locking module, and the second decryption unit is located between the AM removal module and the interleaving module.

[0201] The RS-FEC module includes multiple RS-FEC sub-modules, and the number of the multiple RS-FEC sub-modules is set according to the network to which they are applied. For example, if the PHY is applied to 200Gbps or 400Gbps, the number of RS-FEC sub-modules is 2, and if the PHY is applied to 800Gbps, the number of RS-FEC sub-modules is 4. Fig.23 The difference is that after multiple RS-FEC submodules perform error correction on the received code stream, they send the error-corrected code stream to the interleaving module. The interleaving module interleaves the code streams sent by multiple RS-FEC submodules into one code stream, sends the code stream to the second decryption unit, and the rest of the processing is the same as Fig.23 The process is the same as shown in , and will not be repeated here. Fig.24 The case where the PHY is applied to 200 Gbps or 400 Gbps is shown.

[0202] In an alternative approach, Fig.25 It shows the data transmission process from the sending end to the receiving end.

[0203] In an optional manner, if the ciphertext segment carries its own second decryption parameter, the first decryption unit caches the ciphertext segment after determining the ciphertext segment, and returns it to the first decryption unit after the second decryption unit reads the second decryption parameter, which then decrypts the ciphertext segment.

[0204] If the ciphertext segment carries the second decryption parameter of the subsequent ciphertext segment, the second decryption parameter is cached. After the subsequent first decryption unit determines the ciphertext segment, the cached second decryption parameter is used for decryption without waiting, which can reduce transmission delay.

[0205] In an optional manner, the first decryption unit uses the start identifier in the AM field to determine the start of the ciphertext segment, and uses the number of AM fields included in the AM cycle to determine the end of the ciphertext segment.

[0206] In an optional manner, when using AES-CTR for encryption, the first decryption unit inputs the code stream between the AM fields into the decryption algorithm together with the secret key and IV in units of 128 bits, outputs a 128-bit ciphertext, and transmits it to the jitter elimination module.

[0207] In an optional manner, the first decryption unit may use the Lane No. to determine the logical channel, or may use the identifier originally added in the AM field to determine the logical channel.

[0208] It should be noted that each logical channel independently completes locking the AM field, encryption and decryption, and insertion and extraction of encryption parameters, and is unrelated to each other.

[0209] In the embodiment of the present application, the code stream between the AM fields is encrypted, which is also full information encryption, so the traffic feature information is hidden and all protocols and data are encrypted. The embodiment of the present application also provides an encryption comparison table of the second encryption scheme and some other current schemes, see Table 2.

[0210] Table 2

[0211]

[0212]

[0213] In the embodiment of the present application, the code stream between the AM fields is encrypted, and the user service bandwidth does not need to be occupied, the utilization rate is 100%, and the additional overhead is 0. Fig.26 In the figure, the dotted line indicates the change of the additional overhead of MAC layer encryption with the frame length of Ethernet frame, and the solid line indicates the change of the additional overhead of PHY encryption with the frame length of Ethernet frame in the embodiment of the present application. The additional overhead of MAC layer encryption is greater than the scheme shown in the embodiment of the present application.

[0214] In the embodiment of the present application, the code stream is encrypted at the PCS bottom layer of the PHY, which can hide the user traffic characteristics and protect all network protocols. At the same time, encryption and decryption parameters are transmitted based on the AM native mechanism with zero overhead.

[0215] c. Based on application scenario 2, describe the third encryption scheme and the third decryption scheme.

[0216] See also Fig. 27 , 100Gbps gray light is used for transmission between device A and OTN device A, 100Gbps color light is used for transmission between OTN device A and OTN device B, and 100Gbps gray light is used for transmission between device B and OTN device B. Device A needs to transmit important data to device B, such as AI training models, parameters, and data, which need to be encrypted. Overall, the PHY of device A encrypts the first bitstream in 64B / 66B format to encrypt all data frames, protocol frames, and idle frames between frames. After the first bitstream is transmitted to the logical channel, the PHY of device A encrypts the bitstream between the AM fields in each logical channel to achieve secondary encryption. At OTN device A, OTN device A decrypts the second encryption and maps the encrypted bitstream to the OTN pipe through the generic mapping procedure (GMP) procedure or the GFP-T mapping procedure to transmit it to the remote OTN device B.

[0217] OTN device B recovers the 64B / 66B code stream, and then re-encrypts the code stream between the AM fields in each logical channel and transmits it to device B. The PHY of device B decrypts the twice encrypted 64B / 66B code stream, restores the original data frame, protocol frame and the 64B / 66B code stream corresponding to the inter-frame idle, and sends it to the upper-layer functional module for processing.

[0218] In this way, during the 100Gbps gray light transmission stage, there can be double-layer encryption protection, which is more secure.

[0219] The second encrypted data is decrypted on the OTN device because the data that cannot be encrypted for the second time cannot be transmitted in the OTN at present. In the subsequent development, if the second encrypted data can also be transmitted in the OTN, then the entire communication link will be encrypted twice, which will be more secure.

[0220] When performing secondary encryption, PHY also includes a first encryption module. The encryption module in the previous article is used to encrypt the 64B / 66B code stream. The first encryption module is located between the AM insertion module and the PMA sublayer, and is used to encrypt the code stream output by the AM insertion module. The specific encryption process is described in the previous article and will not be repeated here.

[0221] When there is secondary encryption, the PHY further includes a first decryption module, which is used to decrypt the code stream sent by the AM locking module and send the decrypted code stream to the AM insertion module. The decryption module is used to decrypt the decrypted code stream again to obtain the first code stream. The specific process is described in the previous text and will not be repeated here.

[0222] In the embodiment of the present application, the same device can not only realize encryption, but also realize decryption, support receiving and sending at the same time, and also support encryption and decryption at the same time. Therefore, it is equivalent to that there is a PHY system in the device, including an encryption module and a decryption module, see Fig.28 and Fig.29 , Fig.28 It is for 64B / 66B format code stream encryption. Fig.29 It is the encryption of the code stream between AM fields. Fig.28 and Fig.29 The decryption process of the decryption module in can be found in the code stream decryption process in the previous article, which will not be repeated here. Fig.28 and Fig.29 In FIG. 1 , two logical PHYs are shown, one for transmitting and the other for receiving. Fig.28 and Fig.29 The description is given below the example of PHY being applied to 100 Gbps and below. When applied to above 100 Gbps, the description is similar and will not be repeated here.

[0223] In the embodiment of the present application, the PHY deployed below the MAC layer is designed based on the Ethernet native mechanism for encryption and decryption, encrypting all upper layer information, with high security, low overhead, and no occupation of user service bandwidth. It also has no impact on the functional modules above or below the PHY.

[0224] It should be noted that in the embodiments of the present application, the encryption algorithm and the decryption algorithm mentioned above are the same, that is, a set of algorithms, except that the input and output of the algorithms are different during encryption and decryption.

[0225] In an embodiment of the present application, a chip is also provided, which includes the PHY that performs encryption, the PHY that performs decryption, or the PHY that performs encryption and decryption as described above.

[0226] Optionally, the chip may be an Ethernet interface chip.

[0227] The present application also provides an encryption method, which is applied to PHY. Fig.30 In step 3001 to step 3003, the PHY includes an encryption module.

[0228] Step 3001: The encryption module receives a first code stream.

[0229] Step 3002: The encryption module encrypts the first code stream to obtain a second code stream. The encoding format of the first code stream and the second code stream is the same. The second code stream includes multiple ciphertext segments. Each ciphertext segment in the multiple ciphertext segments includes multiple second code blocks. The multiple second code blocks correspond to the multiple first code blocks in the first code stream.

[0230] Step 3003: The encryption module outputs a second code stream.

[0231] In a possible implementation, the PHY further includes a coding module and a transcoding module, the encryption module is located between the coding module and the transcoding module, and the coding format is 64B / 66B coding;

[0232] The encoding module sends a first code stream to the encryption module;

[0233] The transcoding module receives the second code stream sent by the encryption module.

[0234] In a possible implementation, the first code stream includes a plurality of idle code blocks;

[0235] The encryption module deletes at least one idle code block among the plurality of idle code blocks.

[0236] In a possible implementation manner, each of the plurality of first code blocks includes a first synchronization header;

[0237] The encryption module compresses the first synchronization header of each first code block to obtain a second synchronization header, and the second code block in the second code stream includes the encrypted second synchronization header.

[0238] In a possible implementation, the length of the first synchronization header is 2 bits, and the length of the second synchronization header is 1 bit.

[0239] In a possible implementation, the first code stream includes a third code block, and the second code stream includes a fourth code block and a fifth code block;

[0240] The encryption module loads part of the encrypted content of the third code block into the payload of the fourth code block and loads the remaining content of the encrypted third code block into the payload of the fifth code block.

[0241] In a possible implementation, each ciphertext segment of the plurality of ciphertext segments includes N second code blocks;

[0242] The encryption module loads the M first code blocks in the encrypted first code stream into the payload of the N second code blocks, where M and N satisfy the following relationship: M*K=N*64, where K is the number of bits of each first code block in the M first code blocks during encryption.

[0243] In a possible implementation, an S code block and a T code block are respectively inserted into the head and tail of the N second code blocks to encapsulate them into a ciphertext segment in the second code stream, the S code block is the start mark of the ciphertext segment in the second code stream, and the T code block is the end mark of the ciphertext segment in the second code stream.

[0244] In a possible implementation manner, a code block carrying integrity check information is inserted between the N second code blocks and the T code block.

[0245] In a possible implementation, the encryption module inserts an idle code block between two adjacent ciphertext segments in the multiple ciphertext segments.

[0246] In a possible implementation, the PHY further includes an AM insertion module and a PMA sublayer;

[0247] The encryption module is located between the AM insertion module and the PMA sublayer, and the first code stream is the code stream output by the AM insertion module.

[0248] In a possible implementation, the PHY further includes a distribution module, the encryption module includes a first encryption unit and a second encryption unit, the first encryption unit is located between the AM insertion module and the distribution module, and the second encryption unit is located between the distribution module and the PMA sublayer;

[0249] The first encryption unit determines the AM fields of the multiple logical channels in the first code stream, adds ciphertext segment information to the AM field of each logical channel in the multiple logical channels according to the AM cycle, obtains a third code stream, and sends the third code stream to the distribution module, each AM cycle includes multiple AM ​​fields, and the adjacent code streams after the AM fields included in each AM cycle are used to form a ciphertext segment, and in each logical channel, the ciphertext segment information of the xth ciphertext segment includes the start identifier and decryption parameters of the xth ciphertext segment, or the start identifier of the xth ciphertext segment and the decryption parameters of the x+nth ciphertext segment, where x is a positive integer and n is a non-negative integer;

[0250] The distribution module distributes the received code stream to the multiple logical channels;

[0251] The second encryption unit encrypts the code stream between AMs in each logical channel to obtain a second code stream.

[0252] In a possible implementation, the PHY also includes a first encryption module, an encoding module, a transcoding module, an AM insertion module and a PMA sublayer, the encryption module is located between the encoding module and the transcoding module, and the first encryption module is located between the AM insertion module and the PMA sublayer; the encryption module receives the first code stream sent by the encoding module, and sends the second code stream to the transcoding module; the first encryption module encrypts the fourth code stream to obtain the fifth code stream, and sends the fifth code stream to the PMA sublayer, the fourth code stream is the code stream after the second code stream is processed by the transcoding module and the AM insertion module, and the encoding format of the fourth code stream is the same as that of the fifth code stream.

[0253] In a possible implementation, the encryption module is located in the PCS.

[0254] The present application also provides a decryption method for PHY. Fig.31 In step 3101 to step 3103, the PHY includes a decryption module.

[0255] Step 3101: The decryption module receives a first decryption code stream, wherein the first decryption code stream includes a plurality of ciphertext segments, and each of the plurality of ciphertext segments includes a plurality of first decryption code blocks.

[0256] Step 3102: The decryption module decrypts the first decryption code stream to obtain a decryption code stream, wherein the decryption code stream has the same encoding format as the first decryption code stream, and the multiple first decryption code blocks correspond to the multiple first decryption code blocks in the decryption code stream.

[0257] Step 3103: the decryption module outputs the decrypted code stream.

[0258] In a possible implementation, the PHY further includes a reverse transcoding module and a decoding module;

[0259] The decryption module is located between the reverse transcoding module and the decoding module, and the encoding format is 64B / 66B encoding;

[0260] The reverse transcoding module sends the first encrypted code stream to the decryption module;

[0261] The decoding module receives the decrypted code stream sent by the decryption module.

[0262] In a possible implementation, each of the plurality of first decryption code blocks includes a second synchronization header;

[0263] The decryption module recovers the second synchronization header of each first decrypted code block to obtain a first synchronization header.

[0264] In a possible implementation manner, the length of the first synchronization header is 2 bits, and the length of the second synchronization header is 1 bit.

[0265] In a possible implementation, the first encryption code stream includes a second encryption code block and a third encryption code block, and the decryption code stream includes the second decryption code block;

[0266] The decryption module unloads the content of the decrypted second encryption code block belonging to the second decryption code block into the payload of the second decryption code block, and unloads the content of the decrypted third encryption code block belonging to the second decryption code block into the payload of the second decryption code block.

[0267] In a possible implementation, each ciphertext segment of the multiple ciphertext segments includes N first encryption code blocks;

[0268] The decryption module unloads N first encryption code blocks in the decrypted ciphertext segment into M first decryption code blocks, where M and N satisfy the following relationship: M*K=N*64, where K is the number of bits of each first decryption code block in the M first decryption code blocks.

[0269] In a possible implementation, the decryption module determines an S code block and a T code block in the first encryption code stream, the S code block being a start mark of a ciphertext segment in the first encryption code stream, and the T code block being an end mark of a ciphertext segment in the first encryption code stream;

[0270] The N first encryption code blocks decrypted between the S code blocks and the T code blocks are unloaded into the M first decryption code blocks.

[0271] In a possible implementation, the code block adjacent to the S code block is a code block carrying the first decryption parameter;

[0272] The decryption module obtains the first decryption parameter from the adjacent code block after the S code block, uses the first decryption parameter to decrypt the N first encrypted code blocks, and unloads them into the M first decrypted code blocks.

[0273] In a possible implementation, the code block adjacent to the T code block is a code block carrying integrity check information;

[0274] The decryption module uses the integrity check information to perform integrity check on the ciphertext segment.

[0275] In a possible implementation, the PHY further includes an AM deletion module and an AM locking module;

[0276] The decryption module is located between the AM deletion module and the AM locking module;

[0277] The first encrypted code stream is the code stream output by the AM locking module.

[0278] In a possible implementation, the first encrypted code stream is a code stream composed of code streams of multiple logical channels, the code stream of each logical channel in the multiple logical channels includes multiple AM ​​fields, the AM fields in the code stream of each logical channel are divided into multiple AM ​​periods, and the code streams adjacent to the AM fields included in each AM period constitute a ciphertext segment;

[0279] The PHY further includes a reordering module, and the decryption module includes a first decryption unit and a second decryption unit;

[0280] The first decryption unit is located between the AM locking module and the rearrangement module;

[0281] The second decryption unit is located between the rearrangement module and the AM deletion module;

[0282] The first decryption unit determines the ciphertext segment of each logical channel based on the AM field in the code stream of each logical channel, decrypts the ciphertext segment of each logical channel based on the cached second decryption parameter of the ciphertext segment of each logical channel, obtains a second decryption code stream, and sends the second decryption code stream to the second decryption unit;

[0283] The second decryption unit obtains the second decryption parameter of each ciphertext segment in each logical channel from the AM field of the received decryption code stream according to the AM period. For each logical channel, the second decryption parameter carried by the xth ciphertext segment is used to decrypt the x+kth ciphertext segment, where x and k are positive integers.

[0284] In a possible implementation, the PHY also includes a first decryption module, an AM deletion module, an AM locking module, a reverse transcoding module and a decoding module; the first decryption module is located between the AM deletion module and the AM locking module, and the decryption module is located between the reverse transcoding module and the decoding module; the first decryption module receives the second encrypted code stream sent by the AM locking module, decrypts the second encrypted code stream to obtain a third encrypted code stream, and sends the third encrypted code stream to the AM deletion module, and the encoding format of the second encrypted code stream is the same as that of the third encrypted code stream; the decryption module receives the first encrypted code stream sent by the reverse transcoding module, and outputs the decrypted code stream to the decoding module, and the first encrypted code stream is the code stream after the third encrypted code stream is processed by the AM deletion module and the reverse transcoding module.

[0285] In a possible implementation manner, the decryption module is located in a physical coding sublayer PCS.

[0286] Fig.30 and Fig.31 The process is described in the previous article and will not be repeated here.

[0287] See also Fig.32 , Fig.32 A schematic diagram of the structure of a device 3000 in which the PHY is located is shown. The device 3000 may be implemented by a bus architecture.

[0288] like Fig.32 As shown, the device 3000 includes: a main control board 3110 and an interface board 3130, and the interface board 3130 includes the above-mentioned Ethernet interface.

[0289] The main control board is also called the main processing unit (MPU) or route processor card. The main control board 3110 is used to control and manage various components in the device 3000, including routing calculation, device management, device maintenance, and protocol processing functions. The main control board 3110 includes: a central processing unit 3111 and a memory 3112.

[0290] The interface board 3130 is also called a line processing unit (LPU), a line card or a service board. The interface board 3130 is used to provide various service interfaces and realize the forwarding of data packets. The service interface includes but is not limited to an Ethernet interface, a POS (Packet over SONET / SDH) interface, etc., and the Ethernet interface is, for example, a Flexible Ethernet Client (FlexE Client). The interface board 3130 includes: a central processing unit 3131, a network processor 3132, a forwarding table entry memory 3134 and a physical interface card (physical interface card, PIC) 3133.

[0291] The central processing unit 3131 on the interface board 3130 is used to control and manage the interface board 3130 and communicate with the central processing unit 3111 on the main control board 3110 .

[0292] The network processor 3132 is used to implement the forwarding processing of the message. The network processor 3132 can be in the form of a forwarding chip. The forwarding chip can be a network processor (NP). In some embodiments, the forwarding chip can be implemented by an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Specifically, the network processor 3132 is used to forward the received message based on the forwarding table stored in the forwarding table entry memory 3134. If the destination address of the message is the address of the device 3000, the message is sent to the CPU (such as the central processor 3131) for processing; if the destination address of the message is not the address of the device 3000, the next hop and the output interface corresponding to the destination address are found from the forwarding table according to the destination address, and the message is forwarded to the output interface corresponding to the destination address. Among them, the processing of the uplink message may include: processing of the message input interface, forwarding table search; the processing of the downlink message may include: forwarding table search, etc. In some embodiments, the central processor can also perform the function of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, so that the forwarding chip is not required in the interface board.

[0293] The physical interface card 3133 is used to implement the docking function of the physical layer, and the original traffic enters the interface board 3130 from it, and the processed message is sent from the physical interface card 3133. The physical interface card 3133 is also called a daughter card, which can be installed on the interface board 3130, and is responsible for converting the optical signal into a message and forwarding the message to the network processor 3132 for processing after checking the legitimacy of the message. In some embodiments, the central processor 3131 can also perform the functions of the network processor 3132, such as realizing software forwarding based on a general-purpose CPU, so that the network processor 3132 is not required in the physical interface card 3133.

[0294] Optionally, the device 3000 includes multiple interface boards, for example, the device 3000 also includes an interface board 3140, and the interface board 3140 includes: a central processor 3141, a network processor 3142, a forwarding table entry memory 3144, and a physical interface card 3143. The functions and implementation methods of the components in the interface board 3140 are the same or similar to those of the interface board 3130, and are not described in detail here.

[0295] Optionally, the device 3000 further includes a switching fabric board 3120. The switching fabric board 3120 may also be referred to as a switch fabric unit (SFU). When the device has multiple interface boards, the switching fabric board 3120 is used to complete data exchange between the interface boards. For example, the interface board 3130 and the interface board 3140 may communicate through the switching fabric board 3120.

[0296] The main control board 3110 is coupled to the interface board. For example, the main control board 3110, the interface board 3130, the interface board 3140, and the switching network board 3120 are connected to the system backplane through the system bus to achieve intercommunication. In a possible implementation, an inter-process communication (IPC) channel is established between the main control board 3110 and the interface board 3130 and the interface board 3140, and the main control board 3110 and the interface board 3130 and the interface board 3140 communicate through the IPC channel.

[0297] Logically, the device 3000 includes a control plane and a forwarding plane. The control plane includes a main control board 3110 and a central processing unit 3111. The forwarding plane includes various components for performing forwarding, such as a forwarding table entry memory 3134, a physical interface card 3133, and a network processor 3132. The control plane performs functions such as a router, generating a forwarding table, processing signaling and protocol messages, and configuring and maintaining the status of the device. The control plane sends the generated forwarding table to the forwarding plane. On the forwarding plane, the network processor 3132 forwards the message received by the physical interface card 3133 based on the forwarding table sent by the control plane. The forwarding table sent by the control plane can be stored in the forwarding table entry memory 3134. In some embodiments, the control plane and the forwarding plane can be completely separated and not on the same device.

[0298] See also Fig.33 , Fig.33 A schematic diagram of the structure of a device 4000 provided by an exemplary embodiment of the present application is shown. Fig.33 The device 4000 shown is used to perform the operations involved in the above-mentioned PHY. The device 4000 is, for example, a switch, a router or a controller, etc., and can also be a server, a storage device and a network device, etc. The device 4000 can be implemented by a bus architecture.

[0299] like Fig.33 As shown, the device 4000 includes at least one processor 4001 and at least one communication interface 4004. In some embodiments, the processor 4001 is coupled to the memory 4003.

[0300] Processor 4001 is, for example, a general-purpose CPU, a digital signal processor (DSP), an NP, a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solution of the present application. For example, processor 4001 includes an ASIC, a programmable logic device (PLD) or other programmable logic devices, a transistor logic device, a hardware component, or any combination thereof. PLD is, for example, a complex programmable logic device (CPLD), an FPGA, a generic array logic (GAL), or any combination thereof. It can implement or execute various logic blocks, modules, and circuits described in conjunction with the disclosure of the embodiments of the present application. The processor may also be a combination that implements a computing function, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0301] Optionally, the device 4000 further includes a bus. The bus is used to transmit information between the components of the device 4000. The bus may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.33 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0302] The memory 4003 is, for example, a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 4003 is, for example, independent and connected to the processor 4001 via a bus. The memory 4003 can also be integrated with the processor 4001.

[0303] The communication interface 4004 uses any transceiver-like device to communicate with other devices or communication networks, and the communication network can be Ethernet, a radio access network (RAN) or a wireless local area network (WLAN), etc. The communication interface 4004 may include a wired communication interface and may also include a wireless communication interface. Specifically, the communication interface 4004 may be an Ethernet interface, a Fast Ethernet (FE) interface, a Gigabit Ethernet (GE) interface, an Asynchronous Transfer Mode (ATM) interface, a wireless local area network (WLAN) interface, a cellular network communication interface or a combination thereof. The Ethernet interface may be an optical interface, an electrical interface or a combination thereof. In an embodiment of the present application, the communication interface 4004 may be used for the device 4000 to communicate with other devices.

[0304] In a specific implementation, as an embodiment, the processor 4001 may include one or more CPUs, such as Fig.33 0 and CPU1 shown in FIG. Each of these processors may be a single-CPU processor or a multi-CPU processor. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0305] In a specific implementation, as an embodiment, the device 4000 may include multiple processors. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0306] In a specific implementation, as an embodiment, the device 4000 may also include an output device and an input device. The output device communicates with the processor 2001 and can display information in a variety of ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 4001 and can receive user input in a variety of ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensor device.

[0307] In some embodiments, the memory 4003 is used to store the program code 4010 for executing the solution of the present application, and the processor 4001 can execute the program code 4010 stored in the memory 4003. That is, the device 4000 can implement the various functions of the above-mentioned PHY through the processor 4001 and the program code 4010 in the memory 4003. The program code 4010 may include one or more software modules. Optionally, the processor 4001 itself can also store the program code or instruction for executing the solution of the present application.

[0308] The embodiment of the present application also provides a computer-readable storage medium, in which at least one computer instruction is stored. The computer instruction is loaded and executed by a processor to implement various functions such as negotiation, encryption and decryption.

[0309] The exemplary embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only an exemplary embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the present application shall be included in the scope of protection of the present application.

[0310] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the module is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or it can be an electrical, mechanical or other form of connection.

[0311] In this application, the terms "first" and "second" and the like are used to distinguish between identical or similar items having substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first" and "second", nor is the quantity and execution order limited. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various described examples, the first encryption unit may be referred to as the second encryption unit, and similarly, the second encryption unit may be referred to as the first encryption unit. Both the first encryption unit and the second encryption unit may be encryption units, and in some cases, may be separate and different encryption units.

[0312] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0313] The term "at least one" in this application means one or more, and the term "plurality" in this application means two or more.

[0314] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application should be included in the protection scope of the present application.

Claims

1. A physical layer PHY, characterized in that: The PHY includes an encryption module; The encryption module is used to receive a first code stream; The encryption module is further used to encrypt the first code stream to obtain a second code stream, the first code stream and the second code stream have the same encoding format, the second code stream includes a plurality of ciphertext segments, each of the plurality of ciphertext segments includes a plurality of second code blocks, and the plurality of second code blocks correspond to the plurality of first code blocks in the first code stream; The encryption module is further used to output the second code stream.

2. The PHY according to claim 1, wherein: The PHY further includes a coding module and a transcoding module, the encryption module is located between the coding module and the transcoding module, and the coding format is 64B / 66B coding; The encoding module is used to send the first code stream to the encryption module; The transcoding module is used to receive the second code stream sent by the encryption module.

3. The PHY according to claim 2, wherein: The first code stream includes a plurality of idle code blocks; The encryption module is further used to delete at least one idle code block among the multiple idle code blocks.

4. The PHY according to claim 2 or 3, characterized in that: Each of the plurality of first code blocks comprises a first synchronization header; The encryption module is further used to compress the first synchronization header of each first code block to obtain a second synchronization header, and the second code block in the second code stream includes the encrypted second synchronization header.

5. The PHY according to claim 4, wherein: The length of the first synchronization header is 2 bits, and the length of the second synchronization header is 1 bit.

6. The PHY according to any one of claims 2 to 5, characterized in that: The first code stream includes a third code block, and the second code stream includes a fourth code block and a fifth code block; The encryption module is further used to load part of the encrypted content of the third code block into the payload of the fourth code block and to load the remaining content of the encrypted third code block into the payload of the fifth code block.

7. The PHY according to any one of claims 2 to 6, characterized in that: Each ciphertext segment of the plurality of ciphertext segments comprises N second code blocks; The encryption module is also used to load the M first code blocks in the encrypted first code stream into the payloads of the N second code blocks, where M and N satisfy the following relationship: M*K=N*64, where K is the number of bits of each first code block in the M first code blocks during encryption.

8. The PHY according to claim 7, wherein: The encryption module is also used to insert a start S code block and an end T code block at the head and tail of the N second code blocks respectively, and encapsulate them into a ciphertext segment in the second code stream, wherein the S code block is a start mark of the ciphertext segment in the second code stream, and the T code block is an end mark of the ciphertext segment in the second code stream.

9. The PHY according to claim 8, wherein: The encryption module is further used to insert a code block carrying integrity check information between the N second code blocks and the T code block.

10. The PHY according to any one of claims 2 to 9, characterized in that: The encryption module is also used to insert an idle code block between two adjacent ciphertext segments in the multiple ciphertext segments.

11. The PHY according to claim 1, wherein: The PHY also includes an AM insertion module and a physical medium attachment PMA sublayer; The encryption module is located between the AM insertion module and the PMA sublayer, and the first code stream is the code stream output by the AM insertion module.

12. The PHY according to claim 11, wherein: The PHY further includes a distribution module, the encryption module includes a first encryption unit and a second encryption unit, the first encryption unit is located between the AM insertion module and the distribution module, and the second encryption unit is located between the distribution module and the PMA sublayer; The first encryption unit is used to determine the AM fields of multiple logical channels in the first code stream, add ciphertext segment information to the AM field of each logical channel in the multiple logical channels according to the AM cycle, obtain a third code stream, and send the third code stream to the distribution module, each AM cycle includes multiple AM ​​fields, and the adjacent code streams after the AM fields included in each AM cycle are used to form a ciphertext segment, and in each logical channel, the ciphertext segment information of the xth ciphertext segment includes the starting identifier and decryption parameters of the xth ciphertext segment, or the starting identifier of the xth ciphertext segment and the decryption parameters of the x+nth ciphertext segment, where x is a positive integer and n is a non-negative integer; The distribution module is used to distribute the received code stream to the multiple logical channels; The second encryption unit is used to encrypt the code stream between AMs in each logical channel to obtain the second code stream.

13. The PHY according to claim 1, wherein: The PHY further comprises a first encryption module, an encoding module, a transcoding module, an AM insertion module and a PMA sublayer, wherein the encryption module is located between the encoding module and the transcoding module, and the first encryption module is located between the AM insertion module and the PMA sublayer; The encryption module is further used to receive the first code stream sent by the encoding module and send the second code stream to the transcoding module; The first encryption module is used to encrypt the fourth code stream to obtain a fifth code stream, and send the fifth code stream to the PMA sublayer, the fourth code stream is the code stream after the second code stream is processed by the transcoding module and the AM insertion module, and the fourth code stream has the same encoding format as the fifth code stream.

14. The PHY according to any one of claims 1 to 13, characterized in that: The encryption module is located in the physical coding sublayer PCS.

15. A physical layer PHY, characterized in that: The PHY includes a decryption module; The decryption module is used to receive a first encrypted code stream, the first encrypted code stream includes a plurality of ciphertext segments, each of the plurality of ciphertext segments includes a plurality of first encrypted code blocks; The decryption module is further configured to decrypt the first encryption code stream to obtain a decryption code stream, wherein the decryption code stream has the same encoding format as the first encryption code stream, and the plurality of first encryption code blocks correspond to the plurality of first decryption code blocks in the decryption code stream; The decryption module is further configured to output the decrypted code stream.

16. The PHY according to claim 15, wherein: The PHY also includes a reverse transcoding module and a decoding module; The decryption module is located between the reverse transcoding module and the decoding module, and the encoding format is 64B / 66B encoding; The reverse transcoding module is used to send the first encrypted code stream to the decryption module; The decoding module is used to receive the decrypted code stream sent by the decryption module.

17. The PHY according to claim 16, wherein: Each of the plurality of first decrypted code blocks comprises a second synchronization header; The decryption module is further used to restore the second synchronization header of each first decrypted code block to obtain the first synchronization header.

18. The PHY according to claim 17, wherein: The length of the first synchronization header is 2 bits, and the length of the second synchronization header is 1 bit.

19. The PHY according to any one of claims 16 to 18, characterized in that: The first encryption code stream includes a second encryption code block and a third encryption code block, and the decryption code stream includes the second decryption code block; The decryption module is further used to unload the content of the decrypted second encryption code block belonging to the second decryption code block into the second decryption code block, and unload the content of the decrypted third encryption code block belonging to the second decryption code block into the second decryption code block.

20. The PHY according to any one of claims 16 to 19, characterized in that: Each ciphertext segment of the plurality of ciphertext segments includes N first encrypted code blocks; The decryption module is also used to unload N first encryption code blocks in the decrypted ciphertext segment into M first decryption code blocks, where M and N satisfy the following relationship: M*K=N*64, where K is the number of bits of each first decryption code block in the M first decryption code blocks.

21. The PHY according to claim 20, wherein: The decryption module is further used to determine a start S code block and an end T code block in the first encryption code stream, wherein the S code block is a start mark of a ciphertext segment in the first encryption code stream, and the T code block is an end mark of a ciphertext segment in the first encryption code stream; The N first encryption code blocks decrypted between the S code blocks and the T code blocks are unloaded into the M first decryption code blocks.

22. The PHY according to claim 21, wherein: The code block adjacent to the S code block is a code block loaded with the first decryption parameter; The decryption module is further used to obtain the first decryption parameter from the adjacent code block after the S code block, and use the first decryption parameter to decrypt the N first encrypted code blocks and unload them into the M first decrypted code blocks.

23. The PHY according to claim 21 or 22, characterized in that: The code block adjacent to the T code block is a code block carrying integrity check information; The decryption module is further used to use the integrity check information to perform integrity check on the corresponding ciphertext segment.

24. The PHY according to claim 15, wherein: The PHY also includes an alignment mark AM deletion module and an AM locking module; The decryption module is located between the AM deletion module and the AM locking module; The first encrypted code stream is the code stream output by the AM locking module.

25. The PHY according to claim 24, wherein: The first encrypted code stream is a code stream composed of code streams of multiple logical channels, the code stream of each logical channel in the multiple logical channels includes multiple AM ​​fields, the AM fields in the code stream of each logical channel are divided into multiple AM ​​periods, and the adjacent code streams after the AM fields included in each AM period constitute a ciphertext segment; The PHY further includes a reordering module, and the decryption module includes a first decryption unit and a second decryption unit; The first decryption unit is located between the AM locking module and the rearrangement module; The second decryption unit is located between the rearrangement module and the AM deletion module; The first decryption unit is used to determine the ciphertext segment of each logical channel based on the AM field in the code stream of each logical channel, decrypt the ciphertext segment of each logical channel based on the cached second decryption parameter of the ciphertext segment of each logical channel, obtain a second decryption code stream, and send the second decryption code stream to the second decryption unit; The second decryption unit is used to obtain the second decryption parameter of each ciphertext segment in each logical channel from the AM field of the received decryption code stream according to the AM period. For each logical channel, the second decryption parameter carried by the xth ciphertext segment is used to decrypt the x+kth ciphertext segment, where x and k are positive integers.

26. The PHY of claim 15, wherein: The PHY further includes a first decryption module, an AM deletion module, an AM locking module, a reverse transcoding module and a decoding module; The first decryption module is located between the AM deletion module and the AM locking module, and the decryption module is located between the reverse transcoding module and the decoding module; The first decryption module is used to receive the second encrypted code stream sent by the AM locking module, decrypt the second encrypted code stream to obtain a third encrypted code stream, and send the third encrypted code stream to the AM deletion module, wherein the second encrypted code stream has the same encoding format as the third encrypted code stream; The decryption module is also used to receive the first encrypted code stream sent by the reverse transcoding module, and output the decrypted code stream to the decoding module, wherein the first encrypted code stream is the code stream after the third encrypted code stream is processed by the AM deletion module and the reverse transcoding module.

27. The PHY according to any one of claims 15 to 26, characterized in that: The decryption module is located in the physical coding sublayer PCS.

28. A physical layer PHY system, characterized in that: The PHY system comprises the PHY according to any one of claims 1 to 14 and the PHY according to any one of claims 15 to 27.

29. A physical layer PHY encryption method, characterized in that: The method is applied to the PHY according to any one of claims 1 to 14.

30. A physical layer PHY decryption method, characterized in that: The method is applied to the physical layer PHY as claimed in any one of claims 15 to 27.

31. A chip, characterized in that: The chip comprises the physical layer PHY according to any one of claims 1 to 14 and / or the PHY according to any one of claims 15 to 27.

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