Slave Address Determination Device, Method, Storage Medium, and Electronic Device

Abstract

The present invention discloses a slave address determination device, method, storage medium, and electronic device, which relate to the technical field of automotive integrated circuit design and application. The slave address determination device includes: a voltage input module, an analog-to-digital converter (ADC) sampling module, a first number of sampling result decoding modules, and a slave address decoding circuit; the voltage input module inputs a first number of voltage values to the ADC sampling module; the ADC sampling module receives the voltage values, converts each received voltage value into a corresponding voltage sampling value to obtain a first number of voltage sampling values, and inputs the first number of voltage sampling values into the first number of sampling result decoding modules respectively; the slave address decoding circuit obtains an interval value corresponding to the first numerical interval where the voltage sampling value input to each sampling decoding module is located and output by each sampling decoding module, and determines the slave address according to the obtained interval value, so as to improve the convenience of setting the slave address.

Description

Technical Field

[0001] The present invention relates to the technical field of automotive integrated circuit design and application, and particularly to a slave address determination device, method, storage medium, and electronic device. Background Art

[0002] In automotive electronic systems, the scenario where a master controls multiple slaves is very common. For example, in modern intelligent vehicles, the interaction between an ECU (Electronic Control Unit) and multiple sensors. The ECU, as the master, can control the slaves, such as collecting various sensor data from the sensors.

[0003] The architecture of a master controlling slaves is usually used to achieve centralized control and distributed execution to ensure the efficiency and reliability of the system. For example, communication protocols such as CAN, LIN, I2C, and SPI are used to complete the system application of a master controlling multiple slaves. In these applications, multiple identical chips as slaves need to match the correct addresses to ensure normal communication with the master in the application and complete the entire function implementation.

[0004] In related technologies, a method of programming the slave address into the NVM (Non-Volatile Memory) can be adopted to record the slave address. Thus, the master can determine the slave address from the NVM and communicate with the corresponding slave.

[0005] However, this implementation method must be programmed at the board level in most scenarios. Because different slaves often perform different functions in the application, the correct address must be programmed at the correct position. The programming process is complex and requires a special fixture for cooperation. And for chips with OTP (One Time Programmable) media, the address can only be set once. Once the slave address is written incorrectly, the programmed chip will be wasted, which is not convenient enough. Summary of the Invention

[0006] The present invention aims to at least solve one of the technical problems in the related technologies to some extent. For this purpose, an object of the present invention is to provide a slave address determination device, method, storage medium, and electronic device to improve the convenience of setting the slave address.

[0007] According to a first aspect of an embodiment of the present invention, a slave address determination device is provided. The device includes: a voltage input module, an ADC (Analog-to-Digital Converter) sampling module, a first number of sampling result decoding modules, and a slave address decoding circuit;

[0008] The voltage input module is configured to input a first number of voltage values to the ADC sampling module;

[0009] The ADC sampling module is configured to receive the voltage value; convert each received voltage value into a corresponding voltage sampling value to obtain a first number of voltage sampling values; and input the first number of voltage sampling values into the first number of sampling result decoding modules respectively.

[0010] The slave address decoding circuit is configured to obtain an interval value corresponding to the first numerical interval where the voltage sampling value input to each sampling decoding module is located, which is output by each sampling decoding module; and determine the slave address according to the obtained interval value.

[0011] Optionally, the first numerical interval is obtained in the following manner:

[0012] Obtain a preset reference voltage;

[0013] Divide the reference voltage into a valid voltage interval and an invalid voltage interval;

[0014] Divide the valid voltage interval into at least two first numerical intervals, and different first numerical intervals correspond to different interval values.

[0015] Optionally, the device further includes a fault signal generation module;

[0016] The fault signal generation module is configured to generate a fault signal based on a fault indication pin and / or a preset register flag bit if there is at least one interval value output by a sampling decoding module that is located in a second numerical interval representing the invalid voltage interval.

[0017] Optionally, when the first number is greater than or equal to 2, the slave address decoding circuit determines the slave address according to the obtained interval value, including:

[0018] Determine the coefficients corresponding to each sampling decoding module;

[0019] Perform a weighted sum on each interval value based on the determined coefficients to obtain the slave address corresponding to the sum result.

[0020] Optionally, the voltage input module includes a first number of resistor networks formed by series resistors with different resistances, and inputs a voltage value to the ADC sampling module based on each resistor network.

[0021] Optionally, the device further includes an address register;

[0022] The address register is used to store the determined slave address after the slave address decoding circuit determines the slave address according to the obtained interval value, so that the host can obtain the slave address in the address register through a preset communication interface and compare it with the target slave address set in the host for communication.

[0023] According to a second aspect of an embodiment of the present invention, a method for determining a slave address is provided. The method includes:

[0024] Input a first number of voltage values;

[0025] Convert each voltage value into a corresponding voltage sampling value to obtain a first number of voltage sampling values;

[0026] Obtain an interval value corresponding to a first numerical interval where the obtained voltage sampling values are located;

[0027] Determine the slave address according to the obtained interval value.

[0028] According to a third aspect of an embodiment of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the above method for determining a slave address is implemented.

[0029] According to a fourth aspect of an embodiment of the present invention, an electronic device is provided, including: a memory, a processor; a computer program is stored on the memory, and when the computer program is executed by the processor, the above method for determining a slave address is implemented.

[0030] In the solution provided by the embodiment of the present invention, through different combinations of the first number of input voltage values, different combinations of voltage sampling values can be sampled, and then different interval values can be correspondingly obtained to determine different slave addresses. In the case of having multiple slaves, different slaves can be set to different slave addresses. Through the adjustment of the voltage value of the voltage input module, flexible address setting can be achieved. If the slave address is written wrong, it can also be repaired through the adjustment of the voltage setting module, thereby providing convenience for address setting.

[0031] Moreover, the above solution does not need to identify the slave address through NVM, which can save materials and reduce the complexity of determining the slave address.

[0032] In addition, by obtaining the voltage sampling value from the input voltage value, and then performing combined decoding through the obtained corresponding interval value to obtain the slave address, it enables the setting of more slave addresses with fewer input voltage values, which can reduce the number of pins required for input voltage values. Less pin overhead is suitable for application scenarios with fewer chip pins, further improving the convenience.

[0033] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. Description of the Drawings

[0034] Figure 1 is a schematic structural diagram of a first slave address determination device provided by an embodiment of the present invention;

[0035] Figure 2 is a schematic structural diagram of a second slave address determination device provided by an embodiment of the present invention;

[0036] Figure 3 is a schematic flowchart of a slave address determination method provided by an embodiment of the present invention;

[0037] Figure 4 is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. Detailed Embodiments

[0038] The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are intended to explain the present invention, and should not be construed as limiting the present invention.

[0039] The slave address determination device, method, storage medium, and electronic device according to the embodiments of the present invention will be described below with reference to the drawings.

[0040] In an embodiment of the present invention, referring to Figure 1 , a slave address determination device is provided, including: a voltage input module, an ADC sampling module, a first number of sampling result decoding modules, and a slave address decoding circuit; the voltage input module is configured to input a first number of voltage values to the ADC sampling module;

[0041] The ADC sampling module is configured to receive the voltage values; convert each received voltage value into a corresponding voltage sampling value to obtain a first number of voltage sampling values; and input the first number of voltage sampling values into the first number of sampling result decoding modules respectively;

[0042] The slave address decoding circuit is configured to obtain an interval value corresponding to the first numerical interval where the voltage sampling value input to each sampling decoding module is located and output by each sampling decoding module; and determine the slave address according to the obtained interval value.

[0043] In an embodiment of the present invention, when electronic device A can control electronic device B, for example, obtain data of electronic device B, electronic device A is referred to as the host and electronic device B as the slave. The above-mentioned device can be applied to any one of multiple slaves controlled by the host.

[0044] Figure 1 The case where there are 2 sampling result decoding modules is shown. In other cases, the number of sampling result decoding modules can exceed 2, or there can be only one.

[0045] The above voltage input module can preset the overall range of voltage value adjustment. This range can be given by the internal power supply voltage or the reference voltage specifically used for the ADC (Analog-to-Digital Converter) sampling module, so that each voltage value input by the voltage input module is within this overall range.

[0046] See Figure 2 , the voltage input module is the peripheral voltage dividing circuit in the figure. The ADDR1 and ADDR2 pins will be externally voltage-divided to input the voltage values required for the corresponding addresses. In the Figure 2 embodiment shown, the first quantity is 2.

[0047] The ADC sampling module converts each voltage value into a voltage sampling numerical value. Specifically, it includes the following steps:

[0048] 1. Sampling: The ADC first samples the analog signal, that is, captures the voltage value of the signal at specific time points. According to the Nyquist sampling theorem, the sampling frequency must be at least twice the highest frequency of the signal to avoid aliasing.

[0049] 2. Holding: After sampling, the ADC will temporarily hold this voltage value for subsequent quantization processing. This stage is called "sample and hold".

[0050] 3. Quantization: In the quantization stage, the ADC converts the voltage value of the sample and hold into a discrete digital value. This process involves mapping the continuous analog voltage to a finite number of discrete levels. The quantization accuracy depends on the resolution of the ADC, usually expressed in bits, such as 8 bits, 10 bits, 12 bits, etc. An n-bit ADC can quantize the analog signal into 2 to the power of n different levels.

[0051] 4. Encoding: The discrete levels after quantization are converted into binary codes, which is a format that can be understood and processed by digital systems. For example, a 3-bit ADC can quantize the analog signal into 8 levels and represent them with 3-bit binary numbers (from 000 to 111).

[0052] 5. Output: Finally, the ADC outputs this binary value, which is the voltage sampling value.

[0053] For example, assume there is a 10-bit ADC with a reference voltage of 5V. This means the ADC can quantize the voltage range from 0V to 5V into 1024 different levels (2^10). The voltage increment represented by each level is 5V / 1024 ≈ 4.88mV. If the ADC samples a voltage of 2.5V, it will output a value close to 512 (because 2.5V / 4.88mV ≈ 512).

[0054] From the above, after ADC sampling, the voltage sampling values of VADDR1 and VADDR2 are obtained.

[0055] Figure 2 In it, VREFH represents the reference voltage, and [1 / 8 VREFH, 1 / 4 VREFH), [1 / 4 VREFH, 3 / 8VREFH), [3 / 8 VREFH, 1 / 2 VREFH), [1 / 2 VREFH, 5 / 8 VREFH), [5 / 8 VREFH, 3 / 4VREFH), [3 / 4VERFH, 7 / 8VREFH] are the first numerical intervals generated by segmenting the effective region of the reference voltage.

[0056] Specifically, the first numerical interval can be obtained in the following way:

[0057] Obtain the preset reference voltage; divide the reference voltage into an effective voltage interval and an ineffective voltage interval; divide the effective voltage interval into no less than 2 first numerical intervals, and different first numerical intervals correspond to different interval values.

[0058] Figure 2 The ineffective voltage interval is also shown in it, that is, the segments representing "invalid" in the ADDR1 decoding module and the ADDR2 decoding module, which are the lowest voltage segment [0, 1 / 8 VREFH] and the highest voltage segment [7 / 8 VREFH, VREFH], respectively, as the fault regions shorted to the power supply and shorted to the ground, so as to report faults for fault diagnosis when a short circuit scenario occurs. When the voltage sampling falls in the ineffective region, an error flag bit is generated, and the host can identify the fault by obtaining the error flag bit.

[0059] In the figure, the effective voltage region is divided into the above 6 first numerical intervals, that is, the effective regions 0 - 5 in the ADDR1 decoding module and the ADDR2 decoding module. Combining the voltage values input to the ADC sampling module by 2 pins, the combined decoding by the slave address decoding circuit can support up to 36 different slave addresses. Mathematically, the multiplication combination of the 6 first numerical intervals of the two pins can obtain 36 different results.

[0060] Taking Figure 2 the specific embodiments as an example, the ADDR1 decoding module and the ADDR2 decoding module are decoding modules for the first number of sampling results, the first number is 2, and they respectively receive the inputs of the pin VADDR1 and the pin VADDR2. Figure 2 Among the 6 first numerical ranges of ADDR1, they are the valid regions 0 to 5 in sequence, corresponding to different range values respectively, which are the slave address segments [0, 5], [6, 11], [12, 17], [18, 23], [24, 29], [30, 35], where the address is an integer. Then, the corresponding specific slave address is obtained according to the 6 valid ranges 0 to 5 of ADDR2.

[0061] For example, in the ADDR1 decoding module, if the voltage sampling value falls within the valid region 1, the corresponding slave address segment is [6, 11]; in the ADDR2 decoding module, if the voltage sampling value falls within the valid region 5, then the address with the subscript 5 in the [6, 11] array is selected, and the slave address corresponding to this slave is recognized as 11 after identification. Abstracted at the mathematical level, it can be understood that the valid regions 0 to 5 of ADDR1 sequentially represent the base addresses A_base of the slave addresses as 0, 6, 12, 18, 24, 30. And the valid region 0 to 5 of ADDR2 can represent the offset of the slave address based on the base address A_base, with the range of 0 to 5. For example, in the scenario exemplified above, the slave address is 11, which is obtained by adding the base address 6 and the offset address 5. Different addresses of the slave can be preset with different numbers. In this way, the specified slave address can be found through the number 11.

[0062] Further abstracting the mathematical logic, if the encodings of the valid regions 0 to 5 are 0 to 5, and the address encodings of ADDR1 and ADDR2 are defined as Code_A1 and Code_A0 respectively, then the slave address can be expressed as 6 * Code_A1 + Code_A0. That is, different sampling decoding modules correspond to different coefficients, that is, the range value Code_A1 corresponds to the coefficient 6, and Code_A0 corresponds to the coefficient 1. That is, when the first number is greater than or equal to 2, the coefficients corresponding to each sampling decoding module can be determined; based on the determined coefficients, weighted summation is performed on each range value to obtain the slave address corresponding to the summation result.

[0063] Specifically, Figure 2In the illustrated embodiment, it is assumed that the reference voltage VREFH of the ADC is 5V. For the first number of voltage values input to the slave address recognition circuit after voltage division by the peripheral voltage division circuit, they need to be within 5V. The slave address recognition circuit is a circuit jointly composed of the above-mentioned ADC sampling module, sampling result decoding module, and slave address decoding circuit. A situation where the voltage is higher than 5V will be recognized as a short circuit to the power supply. It is assumed that when the entire system is operating, the two voltage values ADDR1 and ADDR2 of the peripheral circuit are 2.8V and 1.56V respectively. According to the above Figure 2 illustrated embodiment, ADDR1 falls within the valid region 3, and the corresponding sampling decoding module outputs an interval value of 3. ADDR2 falls within the valid region 1, and the corresponding sampling decoding module outputs an interval value of 1. Therefore, the slave address decoding circuit outputs a slave address of 6*3 + 1 = 19. The address 19 will be automatically stored in the current register for communication with the host.

[0064] Figure 2 In the embodiment, the reference voltage is not a fixed value and can be determined according to the design of the entire system, such as 3.3V, 1.8V, etc. There can be multiple setting references.

[0065] Moreover, for the division of the valid voltage interval and the invalid voltage interval, it is not limited to Figure 2 the 8 equal divisions in. Among them, more interval segments can be set for the valid voltage interval or the invalid voltage interval, or, alternatively, an unequal division method can be used for the division. The embodiments of the present invention do not limit this.

[0066] When there are more than 2 sampling decoding modules, there can also be more coefficients. For example, the coefficient of ADDR1 is 6 and the coefficient of ADDR2 is 1. If there is an interval value corresponding to ADDR3, only by setting the coefficient to be not less than 36, it can be ensured that the calculated value is in one-to-one mapping with the address.

[0067] When there is only 1 sampling decoding module, for example, only ADDR1, which falls within the valid region 3, and the corresponding sampling decoding module outputs an interval value of 3, then the address pre-marked as the value 3 is used as the slave address.

[0068] In the solution provided by the embodiments of the present invention, through different combinations of the first number of input voltage values, different combinations of voltage sampling values can be sampled, and then different interval values can be correspondingly obtained to determine different slave addresses. In the case of having multiple slaves, different slaves can be set to different slave addresses. Through the adjustment of the voltage values of the voltage input module, flexible address setting can be achieved. If the slave address is written incorrectly, it can also be repaired through the adjustment of the voltage setting module, thereby providing convenience for address setting.

[0069] Moreover, the above solution does not require the NVM to identify the slave address, which can save materials and reduce the complexity of determining the slave address.

[0070] In addition, the voltage sampling value is obtained from the input voltage value, and then the slave address is obtained through combined decoding by obtaining the corresponding interval value. This enables the setting of a larger number of slave addresses with fewer input voltage values, reducing the number of pins required for the input voltage value. The smaller pin overhead is suitable for application scenarios with fewer chip pins, further enhancing convenience.

[0071] In one embodiment of the present invention, the device further includes a fault signal generation module; the fault signal generation module is configured to generate a fault signal based on the fault indication pin and / or a preset register flag bit if there is at least one interval value output by a sampling and decoding module that is located in a second numerical interval representing an invalid voltage interval.

[0072] As Figure 2 shown, ADDR1 / 2 are respectively the first pin and the second pin of the input address. When any one of the sampling values of ADDR1 or ADDR2 is determined to be in the invalid area, the fault indication pin DIAG will display the fault status for the host to obtain, and the corresponding register flag bit can also be set to 1 for the host to read to troubleshoot the cause of the fault.

[0073] In this way, in a short - circuit scenario, the above device can support the diagnosis and identification of short - circuit faults, meeting application scenarios with high functional safety requirements.

[0074] In one embodiment of the present invention, the voltage input module includes a first number of resistor networks formed by series resistors with different resistances, and inputs a voltage value to the ADC sampling module based on each resistor network.

[0075] As Figure 2 shown, there is a voltage - dividing circuit in the voltage input module. The voltage - dividing circuit is a basic circuit structure used to distribute the input voltage to different components or reduce the voltage magnitude. Its working principle is based on Ohm's law and the law of resistor voltage division. In the voltage - dividing circuit, two resistors are connected in series to form a resistor network. For example, resistor R1 and R2 form a resistor network, and R3 and R4 form another resistor network. In any resistor network, one resistor is connected to the input voltage, that is, the voltage - dividing source in the figure, and the other is connected to the ground wire, that is, the GND wire in the figure.

[0076] In this way, the voltages output to ADDR1 and ADDR2 are part of the input voltage, and the magnitude of the output voltage can be controlled by adjusting the resistance ratio of the two resistors in any resistor network, enabling the pins of the ADC sampling module to obtain different voltages.

[0077] In one embodiment of the present invention, the device further includes an address register; the address register is used to store the determined slave address after the slave address decoding circuit determines the slave address according to the obtained interval value, so that the host can obtain the slave address in the address register through a preset communication interface and compare it with the target slave address set in the host for communication.

[0078] In this way, the host can also read the address through the communication interface to confirm whether it is consistent with the target slave address that the peripheral circuit expects to recognize.

[0079] Moreover, by storing the slave address in the address register, it is also possible to avoid using NVM programming and reduce the complexity of address storage.

[0080] The communication interface can be a communication interface set based on communication protocols such as CAN, LIN, I2C, SPI, etc. The target slave address is set in the host. When it is determined that the slave address in the address register of the slave is consistent with the target slave address, communication can be carried out with the slave, so that the slave address can be recognized through the address register.

[0081] In one embodiment of the present invention, as Figure 3 shown, a method for determining a slave address is provided, and the method includes the following steps S301 - S304.

[0082] S301: Input a first number of voltage values;

[0083] S302: Convert each voltage value into a corresponding voltage sampling value to obtain a first number of voltage sampling values;

[0084] S303: Obtain the interval value corresponding to the first numerical interval where the obtained voltage sampling value is located;

[0085] S304: Determine the slave address according to the obtained interval value.

[0086] In the solution provided by the embodiment of the present invention, through different combinations of the first number of input voltage values, different combinations of voltage sampling values can be sampled, and then different interval values can be obtained correspondingly, and different slave addresses can be determined. In the case of having multiple slaves, different slaves can be set to different slave addresses. Through the adjustment of the voltage value of the voltage input module, flexible address setting can be achieved. If the slave address is written incorrectly, it can also be repaired through the adjustment of the voltage setting module, thus providing the convenience of address setting.

[0087] Moreover, the above solution does not require identifying the slave address through NVM, which can save materials and reduce the complexity of determining the slave address.

[0088] In addition, a voltage sampling value is obtained from the input voltage value, and then the slave address is obtained through combined decoding by obtaining the corresponding interval value. This enables the setting of a larger number of slave addresses with a smaller number of input voltage values, reducing the number of pins required for the input voltage value. The lower pin overhead is suitable for application scenarios with a small number of chip pins, further enhancing convenience.

[0089] In one embodiment of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned method for determining the slave address is implemented.

[0090] In one embodiment of the present invention, an electronic device is provided, including: a memory and a processor; a computer program is stored on the memory, and when the computer program is executed by the processor, the above-mentioned method for determining the slave address is implemented.

[0091] Figure 4 It is a structural block diagram of the electronic device according to the embodiment of the present invention.

[0092] As Figure 4 shown, the electronic device 400 includes: a processor 401 and a memory 403. Among them, the processor 401 and the memory 403 are connected, such as through a bus 402. Optionally, the electronic device 400 may further include a transceiver 404. It should be noted that in practical applications, the transceiver 404 is not limited to one, and the structure of the electronic device 400 does not constitute a limitation to the embodiment of the present invention.

[0093] The processor 401 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logical blocks, modules, and circuits described in connection with the disclosure of the present invention. The processor 401 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0094] The bus 402 may include a path for transmitting information among the above components. The bus 402 can be a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The bus 402 can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, Figure 4 it is represented by only one thick line in Figure 4 , but this does not mean that there is only one bus or one type of bus.

[0095] The memory 403 is used to store a computer program corresponding to the slave address determination method of the foregoing embodiments of the present invention, and the computer program is controlled and executed by the processor 401. The processor 401 is used to execute the computer program stored in the memory 403 to implement the content shown in the foregoing method embodiments.

[0096] Among them, the electronic device 400 includes but is not limited to: mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Tablet Computers), PMPs (Portable Multimedia Players), in-vehicle terminals (such as in-vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 4 The shown electronic device 400 is only an example and should not impose any limitations on the functions and usage scope of the embodiments of the present invention.

[0097] Note that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a definite sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or used in combination with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of the computer-readable medium include the following: an electrical connection part with one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other appropriate processing as necessary, and then stored in a computer memory.

[0098] It should be understood that each part of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0099] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0100] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0101] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0102] In the present invention, unless otherwise clearly specified and defined, the terms such as "mounted", "connected", "connected to", "fixed" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0103] In the present invention, unless otherwise clearly specified and defined, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0104] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as a limitation to the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A device for determining a slave address, characterized in that: The device comprises: a voltage input module, an analog-to-digital converter ADC sampling module, a first number of sampling result decoding modules, a slave address decoding circuit and a fault signal generating module; The voltage input module comprises a first number of resistor networks formed by series-connected resistors with different resistance values, and is used to input a first number of voltage values ​​to the ADC sampling module; The ADC sampling module is used to receive the voltage value; convert each received voltage value into a corresponding voltage sampling value to obtain a first number of voltage sampling values; and input the first number of voltage sampling values ​​into a first number of sampling result decoding modules respectively; The slave address decoding circuit is used to obtain the interval value output by each sampling decoding module and corresponding to the first value interval where the voltage sampling value input to the sampling decoding module is located; determine the slave address according to the obtained interval value; The fault signal generating module is configured to generate a fault signal based on a fault indication pin and / or a preset register flag bit if at least one interval value output by the sampling decoding module is located in a second numerical interval representing an invalid voltage interval; The preset reference voltage is divided into a valid voltage interval and an invalid voltage interval, the valid voltage interval is divided into no less than 2 first numerical intervals, different first numerical intervals correspond to different interval values, the invalid voltage interval corresponds to the second numerical interval, and the invalid voltage interval includes a lowest voltage segment and a highest voltage segment, which are respectively used as fault areas of short circuit to ground and short circuit to power supply; When the first number is greater than or equal to 2, the slave address decoding circuit determines the slave address according to the obtained interval value, including: determining the coefficient corresponding to each sampling decoding module; performing weighted summation on each interval value based on the determined coefficient to obtain the slave address corresponding to the summation result; The weighted summation process is as follows: assuming that the code of the effective area is 0-5, the address codes of the first sampling decoding module and the second sampling decoding module are defined as Code_A1 and Code_A0 respectively, and the slave address is expressed as 6*Code_A1+Code_A0, wherein Code_A1 corresponds to a coefficient of 6 and Code_A0 corresponds to a coefficient of 1.

2. The device according to claim 1, characterized in that The voltage input module inputs a voltage value to the ADC sampling module based on each resistor network.

3. The device according to claim 1, characterized in that The device also includes an address register; The address register is used to store the determined slave address after the slave address decoding circuit determines the slave address according to the obtained interval value, so that the host obtains the slave address in the address register through a preset communication interface and compares it with the target slave address to be communicated set in the host.

4. A method for determining a slave address, wherein the device according to any one of claims 1 to 3 is used to perform the method, characterized in that: The method comprises: inputting a first number of voltage values; Convert each voltage value into a corresponding voltage sampling value to obtain a first number of voltage sampling values; Obtaining an interval value corresponding to a first numerical interval in which the obtained voltage sampling value is located; The slave address is determined based on the obtained interval value.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the slave address determination method as claimed in claim 4 is implemented.

6. An electronic device, characterized in that: include: Memory, processor; The memory stores a computer program, and when the computer program is executed by the processor, the slave address determination method as claimed in claim 4 is implemented.

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