Self-biased ctia pixel readout circuit, image sensor, and electronic device

Abstract

The application discloses a self-bias CTIA pixel readout circuit, an image sensor and electronic equipment, and relates to the technical field of integrated circuits.The technical scheme points are as follows: the circuit comprises a pixel and an integrator composed of an integration operational amplifier and an integration capacitor, the integration operational amplifier is a single-ended input inverting amplifier, and the circuit further comprises: a bias voltage storage module, which is used for storing the bias voltage of the integration operational amplifier in the reset stage of the pixel readout circuit and outputting the bias voltage to the bias end of the integration operational amplifier in the integration stage of the pixel readout circuit, so as to eliminate the offset voltage; and a load pre-charging module, which is used for adjusting the initial voltage of the output end of the integration operational amplifier to a reference voltage in the reset stage of the pixel readout circuit.Through the combination of self-bias integration and load capacitor pre-charging, the application eliminates the offset of the pixel readout circuit and the output mismatch between the pixel circuits, suppresses and eliminates the FPN of the pixel array of the image sensor caused by the circuit offset and mismatch, and improves the uniformity of the pixels.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to self-biased CTIA pixel readout circuits, image sensors, and electronic devices. Background Technology

[0002] Image sensors, as a key component of digital imaging technology, are responsible for converting optical information into electronic information. In recent years, image sensors have been widely used in various fields such as mobile communications, security monitoring, autonomous driving, low-light night vision, industrial control, biomedicine, and aerospace. With the rapid development of sensor technology, higher requirements have been placed on image sensor performance, including imaging quality, system size, weight, and power consumption (SWaP), making the development trend of image sensors with high imaging quality and small pixels increasingly prominent.

[0003] As a crucial component of image sensor technology, the readout integrated circuit (ROIC) has seen continuous advancements in structure and performance alongside the development of image sensors. An image sensor readout circuit is a mixed-signal system, primarily composed of pixel readout circuits, signal processing circuits, timing circuits, and analog-to-digital conversion circuits. The image sensor directly converts the detected weak photocurrent signal into a voltage signal through the front-end pixel readout circuit, and then reconstructs and presents the image information through subsequent readout circuits and image processing algorithms. Therefore, the performance of the pixel readout circuit directly affects the image sensor's imaging signal quality. As pixel area shrinks, the size of the pixel readout unit circuit also gradually decreases. Smaller device sizes lead to greater mismatches, and the effects of mismatches between pixel readout unit circuits and between pixel readout circuits become increasingly severe (e.g., larger fixed-mode noise, FPN). Therefore, in the design of small-pixel (e.g., pixel pitch of 15μm and below) readout circuits, it is necessary to minimize the impact of readout circuit mismatches and their effects on the ROIC image signal.

[0004] Depending on the materials and operating methods of the pixels used in the sensor, the structure of the ROIC varies. Common pixel readout circuits include Direct Injection (DI), Gate Modulated Injection (GMI), Source Follower (SFD), and Capacitive Transimpedance Amplifier (CTIA). Among these, DI and SFD readout methods cannot guarantee high linearity when processing wide dynamic range input signals; the current gain and injection efficiency of the GMI readout method are very sensitive to the threshold voltage of the MOSFET, resulting in a large offset voltage between different pixels; the CTIA readout method can achieve good linearity and high injection efficiency over a wide dynamic range, making it a more widely applicable readout method.

[0005] Therefore, how to research and design a self-biased CTIA pixel readout circuit, image sensor, and electronic device that can overcome the above-mentioned defects is a problem that we urgently need to solve. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a self-biased CTIA pixel readout circuit, an image sensor, and an electronic device. By combining self-biased integration and load capacitor pre-charging, the offset of the pixel readout circuit and the output mismatch between pixel circuits are eliminated, suppressing and eliminating the FPN of the image sensor pixel array caused by circuit offset and mismatch, thereby improving pixel uniformity.

[0007] The above-mentioned technical objective of the present invention is achieved through the following technical solution:

[0008] Firstly, a self-biased CTIA pixel readout circuit is provided, including a pixel and an integrator composed of an integrating operational amplifier and an integrating capacitor. The integrating operational amplifier is a single-ended input inverting amplifier, and the circuit also includes:

[0009] The bias voltage storage module is used to store the bias voltage of the integrating operational amplifier during the reset phase of the pixel readout circuit, and output the bias voltage to the bias terminal of the integrating operational amplifier during the integration phase of the pixel readout circuit to eliminate the offset voltage.

[0010] The load precharge module is used to adjust the initial voltage of the output terminal of the integrating operational amplifier to the reference voltage during the reset phase of the pixel readout circuit.

[0011] Furthermore, the bias voltage storage module achieves bias voltage storage and bias voltage output through an offset storage capacitor connected in series between the bias terminal and the ground terminal of the integrating operational amplifier.

[0012] And / or, the load pre-charge module achieves load pre-charging through a load capacitor connected in series between the output terminal of the integral operational amplifier and the ground terminal.

[0013] Furthermore, the pixel readout circuit also includes a reset switch S1, a reset switch S2, and a reset switch S3;

[0014] The two ends of the reset switch S1 are respectively connected to the output terminal and the bias terminal of the integrating operational amplifier;

[0015] The two ends of the reset switch S2 are respectively connected to the bias node of the pixel and the reference voltage terminal;

[0016] The two ends of the reset switch S3 are connected to the integrating capacitor and the reference voltage terminal, respectively.

[0017] Furthermore, at time t0 during the reset phase, reset switches S1, S2, and S3 are all closed, and the pixel readout circuit's operating cycle begins.

[0018] Furthermore, the pixel readout circuit also includes a reset switch S4, the two ends of which are connected to a reference voltage terminal and an output port, respectively.

[0019] Furthermore, at time t1 during the reset phase, the reset switch S4 is closed to precharge the integrator output.

[0020] Furthermore, the pixel readout circuit also includes an integral control switch S5, the two ends of which are connected to the connection point between the integral capacitor and the reset switch S3, and the output terminal of the integral operational amplifier, respectively.

[0021] Furthermore, at time t2 during the reset phase, reset switches S2, S3, and S4 are disconnected, and integration control switch S5 is closed, causing the pixel readout circuit to enter the integration state.

[0022] In a second aspect, an image sensor is provided, comprising at least one self-biased CTIA pixel readout circuit as described in any one of the first aspects.

[0023] Thirdly, an electronic device is provided, comprising at least one image sensor as described in the second aspect.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The self-biased CTIA pixel readout circuit provided by this invention has a self-biased integration module that eliminates the influence of integrator offset on pixel bias voltage through adaptive integration; and a load pre-charge module that eliminates the influence of integrator offset on output voltage by pre-charging the output at the end of reset. This can suppress and eliminate FPN in the image sensor readout circuit caused by circuit offset and mismatch. This circuit structure can be used in various image sensor readout circuits. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0027] Figure 1 This is a schematic diagram of the structure of a CTIA-type pixel readout circuit in the prior art;

[0028] Figure 2 This is a schematic diagram of the working timing of the CTIA-type pixel readout circuit in the prior art;

[0029] Figure 3 This is a schematic diagram of the equivalent circuit of the CTIA type pixel readout circuit in the reset state in the prior art;

[0030] Figure 4 This is a schematic diagram of the equivalent circuit of the integration state of the CTIA-type pixel readout circuit in the prior art;

[0031] Figure 5 This is a schematic diagram of the structure of a CTIA-type pixel readout circuit under conditions of misalignment in the prior art;

[0032] Figure 6 This is a timing diagram of the operation of a CTIA-type pixel readout circuit under misalignment conditions in the prior art;

[0033] Figure 7 This is a schematic diagram of the equivalent circuit of the CTIA type pixel readout circuit in the reset state under the condition of misalignment in the prior art;

[0034] Figure 8 This is a schematic diagram of the equivalent circuit of the CTIA-type pixel readout circuit integration state under the condition of misalignment in the prior art;

[0035] Figure 9 This is a schematic diagram of the self-biased CTIA pixel readout circuit in an embodiment of the present invention;

[0036] Figure 10 This is a schematic diagram of the structure of the self-biased CTIA pixel readout circuit in an embodiment of the present invention;

[0037] Figure 11This is a schematic diagram of the working timing of the self-biased CTIA pixel readout circuit in an embodiment of the present invention;

[0038] Figure 12 This is an equivalent schematic diagram of the reset stage 1 of the self-biased CTIA pixel readout circuit in an embodiment of the present invention;

[0039] Figure 13 This is an equivalent schematic diagram of the reset stage 2 of the self-biased CTIA pixel readout circuit in an embodiment of the present invention;

[0040] Figure 14 This is an equivalent schematic diagram of the integration stage of the self-biased CTIA pixel readout circuit in an embodiment of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0042] Example

[0043] As the pixel area shrinks, the effects of misalignment and mismatch in the pixel-level CTIA type readout circuit become more severe, as detailed below.

[0044] Taking a photovoltaic image sensor as an example, its pixels are photodiodes (PDs), and the current-voltage relationship of a PD can be expressed as follows:

[0045]

[0046] In equation (1), I d (t) represents the total current generated by the photodiode at time t, I p (t) represents the photocurrent generated by the photodiode at time t, I o For saturation leakage current, V b This is the bias voltage of the photodiode. If the external radiation power is constant, the light intensity received by the PD remains unchanged, therefore I... p (t) remains unchanged, I d (t) is a constant value I d .

[0047] In the design of ROIC (Real-in-Chips) for small-pixel infrared focal plane sensors, the limited pixel area necessitates the use of a minimal number of components in the pixel readout circuit. One advantage of this approach is reduced power consumption and noise. For example... Figure 1As shown, in order to reduce area and power consumption, the amplifiers that make up CTIA do not use differential input operational amplifiers (OpAmp), but instead use single-ended input inverting amplifiers, such as the single-ended input inverting amplifier Amp composed of field-effect transistors MP1 and MN2. It can also be a single-ended input inverting amplifier composed of other devices, and the number of devices is not limited.

[0048] Figure 1 The right side of the image shows the pixel readout circuit; the left side shows the pixel array bias circuit providing bias. In the pixel readout circuit, PD represents the pixel; the single-ended input inverting amplifier Amp and the integrating capacitor C... int Together with the integrator reset switch S1, they form a CTIA-type integrator amplifier to integrate and amplify the input PD current. MP5, MP3, and MP1 in the bias circuit are mirror images of each other, and MN2 and MN4 form a current mirror. Ideally, Figure 1 The voltage V of A A =V ref Therefore, the bias voltage of the PD is V. ref and V BIAS_PDN When V BIAS_PDN ≥V ref At this time, the PD is in the reverse bias or zero bias state required for normal operation.

[0049] like Figure 2 As shown, S1 and V B The figures show the control timing of the reset switch S1 and the curves of the voltage at point B changing over time. Figure 2 A high level indicates that the switch is closed, and a low level indicates that the switch is open.

[0050] At time t0, the integral reset switch S1 is closed, and the pixel readout circuit is reset. The equivalent circuit in the reset state is as follows: Figure 3 As shown. Figure 1 The gate of MP1 is shorted to the drain of MN2. In CTIA, the current of the single-ended input inverting amplifier is proportional to the current flowing through MP5 in the pixel array bias circuit (reference). Figure 1 For the current I flowing through MP1 and MN2 D1_MP1 and I D1_MN2 have:

[0051]

[0052] In formulas (2) and (3), μ p and μ n C represents the mobility of P-channel and N-channel MOSFET devices, respectively. ox Here, W represents the gate oxide capacitance per unit area of ​​the MOSFET device, where W is the channel width and L is the channel length. This is the ratio of the channel width to the length of MP1. V is the ratio of the channel width to the length of MN2. THP V THN The absolute values ​​of the threshold voltages of P-channel and N-channel MOSFETs, respectively, V SG*_MP1 V is the source-gate voltage difference of MP1. GS*_MN2 V is the gate-source voltage difference of MN2. b3 is the gate voltage of MN2.

[0053] The charge at node A during the reset phase is:

[0054] Q1=(V A -V B C int +(V A -V BIAS_PDN C PD (4).

[0055] In formula (4), V BIAS_PDN for Figure 2 The cathode bias voltage of the PD.

[0056] At time t1, the integral reset switch S1 is opened, and the readout circuit enters the integration state. For example... Figure 4 As shown, the circuit integrates and amplifies the weak photocurrent generated by the pixel until the reset switch S1 is closed, at which point the integration cycle ends. Figure 4 With the gate of MP1 floating, and ideally without the influence of offset or other factors, the current flowing through MP1 and MN2 remains at I. bias The output voltage V of the CTIA remains unchanged. If the PD does not generate photocurrent, then the output voltage V of the CTIA remains unchanged. out Maintain voltage V at the end of reset ref If the PD generates photocurrent input, during the integration phase, the current from the PD flows into point A, and the CTIA's output voltage V... out From V ref Initially, the charge at point A changes linearly with the integration time, so at time t2, the charge at point A is Q2 = Q1 + I. int ×t int That is, the charge of node A is:

[0057] Q2=(V A -V out C int +(V A -V BIAS_PDN C PD (5);

[0058] In equation (5), V out for Figure 4 The output voltage of CTIA, i.e. Figure 4 China V B =Vout For V in equation (5) A Ideally, it is I D1_MP5 =I D1_MP3 =I D1_MN4 have:

[0059]

[0060] In formula (6), V ref Since it is the gate voltage of MP5, therefore:

[0061]

[0062] byI D1_MP1 =I D1_MN2 have:

[0063]

[0064] Therefore:

[0065]

[0066] Substituting equation (7) into equation (9), we get:

[0067]

[0068] For equation (10), if Then for V in equation (5) A have:

[0069] V A =V ref (11);

[0070] In equation (5), let the integration time t int =t2-t1. Combining equations (4) and (5), by the law of conservation of charge, Q2 = Q1 + I int ×t int Therefore, under ideal conditions, the output voltage V of a traditional CTIA-type pixel readout circuit is... out have:

[0071]

[0072] In equation (12), t int For the integration time, I int For the integral current, C int This is the integrating capacitor. At time t4, the reset switch S1 closes, ending one working cycle of the readout circuit. The pixel readout circuit outputs the integrated voltage result to the subsequent system, which will then output the corresponding image information based on the integration result and perform imaging.

[0073] Formula (12) yields the ideal output voltage V of the traditional CTIA type pixel readout circuit. out However, ideal readout circuits and pixel units do not exist. Due to manufacturing process limitations (process deviations in oxide layer thickness, diffusion doping, etching, etc.), the device parameters (such as current gain, threshold voltage, etc.) of the transistors in the operational amplifiers of the CTIA circuit cannot be perfectly matched. These mismatches lead to offset voltage. Furthermore, temperature changes also cause variations in offset voltage. Let's assume the offset voltage caused by device and current mirror mismatch is V. os Then, the equivalent circuit of the CTIA-type pixel readout circuit and its pixel array bias circuit under misalignment conditions are as follows: Figure 5 As shown.

[0074] like Figure 6 As shown, at time t0, the integral reset switch S1 is closed, and the pixel readout circuit is reset (as shown). Figure 7 As shown), due to circuit offset, assume that the equivalent bias voltage of MN2 is determined by V. b3 Change to V b3 -V os For the current I flowing through MP1 and MN2 D2_MP1 and I D2_MN2 have:

[0075]

[0076] The charge at point A is:

[0077] Q1=(V A -V B C int +(V A -V BIAS_PDN C PD (15).

[0078] Subsequently, the integral reset switch S1 is opened, and the readout circuit enters the integral state, as follows: Figure 8 As shown, the circuit integrates and amplifies the current generated by the pixel PD until the reset switch S1 is closed, at which point the integration cycle ends. During the integration phase, the current from the PD flows into point A, and the output voltage V of CTIA... out From V ref Initially, the charge at node A changes linearly with the integration time, and at time t2, the charge is:

[0079] Q2=(V A -V B C int +(V A -V BIAS_PDN C PD (16);

[0080] For V in equation (16)A , by I D2_MP1 =I D2_MN2 have:

[0081]

[0082] Therefore:

[0083]

[0084] Substituting equation (7) into equation (18) yields:

[0085]

[0086] For equation (19), if Then, for V in equation (19) A have:

[0087]

[0088] Therefore, in equation (16), V A As shown in equation (20), V B =V out Integration time t int =t2-t1. Let equation (20) be... Combining equations (15) and (16), by the conservation of charge Q2=Q1+I int ×t int Therefore, under actual misalignment conditions, the output voltage V of the traditional CTIA type pixel readout circuit is... out have:

[0089]

[0090] As analyzed above, the operational amplifier's offset will cause the PD's bias voltage to deviate from the ideal (V) BIAS_PDN -V ref ) becomes (V BIAS_PDN -V A Therefore, according to equation (1), the change in PD current caused by the change in PD bias voltage is:

[0091]

[0092] Combining equations (21) and (12), we can obtain the CTIA output voltage deviation ΔV caused by op-amp offset. out for:

[0093]

[0094] In equation (23), ΔI int =ΔI dSubstituting equation (22) into equation (23), we can see that, under the misalignment condition, the output voltage deviation ΔV generated by the i-th pixel unit CTIA in the pixel array is... out _ i It can be represented as:

[0095]

[0096] In equation (24) above, the first term is the output voltage change caused by the offset of the pixel readout circuit; the second term is the integrator output change caused by the dark current offset due to the offset of the pixel reverse bias voltage. Since the offset of each pixel in the pixel array is different, the output of any pixel readout circuit is different. These offsets eventually cause the non-uniformity of the pixel array output, i.e., fixed pattern noise (FPN).

[0097] The self-biased CTIA pixel readout circuit described in this invention, such as Figure 9 As shown, it includes a pixel and an integrator composed of an integrating operational amplifier and an integrating capacitor. The integrating operational amplifier is a single-ended input inverting amplifier. It also includes a bias voltage storage module and a load precharge module.

[0098] The bias voltage storage module is used to store the bias voltage of the integrating operational amplifier during the reset phase of the pixel readout circuit and output the bias voltage to the bias terminal of the integrating operational amplifier during the integration phase of the pixel readout circuit to eliminate the offset voltage; the load precharge module is used to adjust the initial voltage of the output terminal of the integrating operational amplifier to the reference voltage during the reset phase of the pixel readout circuit.

[0099] The bias voltage storage module and the load precharge module can be executed independently during the reset phase, without any timing sequence restrictions.

[0100] Alternatively, both the bias voltage storage module and the load precharge module can be implemented using circuits or devices independent of the existing pixel readout circuitry, such as by configuring a controllable power supply for real-time regulation. They can also be integrated into the existing pixel readout circuitry.

[0101] Taking the CTIA pixel readout circuit as an example, such as Figure 10 As shown, the CTIA pixel readout circuit consists of an integrator (Amp+C) int ), reset switches S1-S4, integral control switch S5, offset storage capacitor C az Load capacitor C load and output port V out The integrator consists of an integrating operational amplifier (Amp) and an integrating capacitor. The integrating operational amplifier Amp is a single-ended input inverting amplifier composed of MP1 and MN2.

[0102] It should be noted that the load capacitor can be the parasitic capacitance of the integrator or a newly added capacitor.

[0103] like Figure 11 As shown, this is the operating timing sequence of the self-biased CTIA pixel readout circuit. S1, S2, and S3 represent the operating timing sequence of reset switches S1, S2, and S3, respectively, while S4 and S5 represent the operating timing sequence of output reset switch S4 and integral control switch S5, respectively. A high level indicates that the switch is closed, and a low level indicates that the switch is open.

[0104] like Figure 10 and Figure 11 As shown, at time t0, reset switches S1, S2, and S3 are closed, the readout circuit's operating cycle begins, and the readout circuit is in reset phase 1, as illustrated in the equivalent schematic diagram below. Figure 12 As shown. At this time, the voltages at points A, B, C, and D are respectively: V A1 =V D1 =V ref V B1 =V D1 =V GS_MN2 The current I flowing through MP1 and MN2 D3_MP1 and I D3_MN2 have:

[0105]

[0106] After the circuit stabilizes, the currents flowing through MP1 and MN2 are:

[0107] I D4_MP1 =I D4_MN2 (27).

[0108] At time t1, the reset switch S1 is opened, and the output reset switch S4 is closed to pre-charge the integrator output. For example... Figure 13 As shown, the voltage V at point B at this time is... B Reset to V ref Then reset phase 2 ends. The current I flowing through MP1 and MN2... D5_MP1 and I D5_MN2 have:

[0109]

[0110] The charge at points A and B during this stage is:

[0111] Q A2 =(V A2 -V ref C int +(V A2 -V BIAS_PDN C PD (29);

[0112] Q B2 =Q D2 =(V B2 -V ref C int +(V B2 -0)C load (30);

[0113] The voltages at points A, B, and D in equations (29) and (30) are respectively: V A2 =V B2 =V D2 =V ref Because there is no current path, the voltage at point C (i.e., C) is... az The voltage on the plate maintains the V of the previous stage. GS_MN2 constant.

[0114] At time t2, disconnect reset switches S2, S3, and S4, and close integral control switch S5, as follows. Figure 14 As shown, the self-biased CTIA pixel readout circuit enters the integration state. At this time, the readout circuit integrates and amplifies the integrating current until the integrating control switch S5 is opened at time t4, at which point the entire readout circuit cycle ends. During the integration phase, the current from PD flows into point A, so the charge Q at point A at time t2... A3 =Q A2 +I int ×t int Therefore, the charge at points A and B is:

[0115] Q A3 =(V A3 -V B3 C int +(V A3 -V BIAS_PDN C PD (31);

[0116] Q B3 =Q D3 =(V B3 -V A3 C int +(V B3 -0)C load (32);

[0117] In equations (31) and (32), V B3 =V out .

[0118] For point C, due to the instantaneous disconnection of reset switch S1 at time t1, the offset storage capacitor C at point C is... az The stored charge cannot change abruptly, and after time t1, there is no charge discharge path at point C. Therefore, after time t1, point C...az The charge stored on the output remains constant during the pre-charging and reset phases, as given by equations (27) and (28):

[0119] I D4_MP1 =I D4_MN2 =I D5_MP1 =I D5_MN2 (33);

[0120] At time t2, reset switch S2 is open, and the voltage at point A is V. A3 In the floating state, the current I flowing through MP1 and MN2 at this time is... D6_MP1 I D6_MN2 The currents I flowing through MP1 and MN2 before being disconnected from S2 respectively D5_MP1 I D5_MN2 It remains unchanged, therefore:

[0121] I D6_MP1 =I D6_MN2 (34);

[0122] From equation (28), the voltage V at point A during the integration phase can be obtained. A3 The voltage V at point A during reset phase 2 A2 Equal, that is:

[0123] V A3 =V A2 =V ref (35)

[0124] contrast Figure 8 The equivalent circuit of the integral state of the CTIA-type pixel readout circuit under offset conditions is described in this invention. The self-biased integration technique proposed in this invention can ensure that the voltage V at point A of each pixel in the pixel array remains constant during the integration amplification process of the pixel readout circuit. A Always maintain V A =V ref It remains unchanged. From formulas (22) and (24), it can be seen that the reverse bias voltage difference V of each pixel photodiode in the circuit pixel array remains unchanged. b The change in integrated current ΔI of each pixel photodiode in the pixel array compared to the case without offset is fixed. int =ΔI d =0, the effect of inconsistent PD dark current caused by input mismatch between pixel circuits in the pixel array is eliminated.

[0125] For point B, at time t2, reset switch S4 is open, integral control switch S5 is closed, and the readout circuit enters the integration phase. The voltage values ​​V at points A and B are then calculated. A3 V B2 V B3 Substituting into equations (30) and (32), we get:

[0126] Q B2 =V ref C load (36);

[0127] Q B3 =(V out -V ref C int +V out C load (37)

[0128] Considering that no charge is injected into point B at the instant the integral control switch S5 closes, according to the law of conservation of charge, the charge Q at point B immediately after the integral control switch S5 closes is... B3_0 Q B2 =Q B3_0 The combined equations (36) and (37) are:

[0129] (V out -V ref (C) load +C int ) = 0(38).

[0130] Because C load C int All are actual capacitors, (C load +C int Since V > 0, we can know from equation (38) that V out =V ref That is, for the initial voltage V at point B during the integration phase B3_0 have:

[0131] V B3_0 =V out_0 =V ref (39);

[0132] Among them, V out_0 The initial voltage is output at the moment the integration begins.

[0133] Therefore, the initial output voltage V of the self-biased CTIA pixel readout circuit embodiment proposed in this invention is... out =V B3_0 That is, the initial value of point B remains unchanged during the integration phase. The mismatch error calibration readout method proposed in this invention, which combines self-biased integration technology and load capacitor pre-charging technology, can simultaneously eliminate the output mismatch between pixel circuits and reduce the pixel array FPN.

[0134] Substituting the above values ​​into formulas (29) and (31), we can see that:

[0135] Q A2 =(V ref -V BIAS_PDN CPD -V os C az (40);

[0136]

[0137] Combining formulas (40) and (41), let the integration time t int = t3 - t2, according to the law of conservation of charge Q A3 =Q A2 +I int ×t int have:

[0138]

[0139] Substituting the values ​​in equations (35) and (39) into equation (42), it can be seen that the output voltage V of the self-biased CTIA pixel readout circuit embodiment proposed in this invention is... out for:

[0140]

[0141] It can be seen that the expression of formula (43) is the same as the output expression (12) of the CTIA pixel readout circuit under the above-mentioned ideal condition without offset, and is independent of the MOSFET device parameters in CTIA. Therefore, an embodiment of the readout method combining pixel circuit self-biasing integration technology and load capacitor pre-charging technology proposed in this invention: the self-biased CTIA pixel readout circuit can eliminate the output mismatch between pixel circuits, the mismatch of PD reverse bias voltage, and eliminate the pixel array FPN.

[0142] like Figure 10 An embodiment of a self-biased CTIA-type pixel readout circuit is shown. The combined readout method of the pixel circuit self-biasing integration technology and the load capacitor pre-charging technology proposed in this invention ensures that the voltage V at the pixel bias node A during the integration period of the CTIA readout circuit is guaranteed. A Always maintain the reference voltage V ref Simultaneously, this causes the output voltage V at output node B to... out The initial value is the reference voltage V. ref During the integration and amplification process of the self-biased CTIA pixel readout circuit, the reverse bias voltage difference V of the photodiodes of each pixel in the pixel array of the readout circuit is... b As can be seen from formulas (22) and (24), the change in the integrated current ΔI of the photodiode of each pixel in the pixel array remains unchanged. int =ΔI d=0, therefore, the combined readout method of self-biased integration technology and load capacitor pre-charging technology proposed in this invention can effectively suppress the phenomenon of inconsistent PD dark current caused by mismatch between pixel circuits in the pixel array. Simultaneously, the combined readout method of self-biased integration technology and load capacitor pre-charging technology proposed in this invention effectively fixes the output starting voltage of each pixel unit during the integration process, eliminating the influence of mismatch between pixel circuits on the integration output. Therefore, the combined readout method of self-biased integration technology and load capacitor pre-charging technology proposed in this invention can effectively eliminate the pixel array FPN and reduce the non-uniformity of the image sensor readout circuit.

[0143] The present invention also describes an image sensor comprising at least one self-biased CTIA-type pixel readout circuit as described above.

[0144] The present invention also describes an electronic device comprising at least one image sensor as described above.

[0145] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0146] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0147] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0148] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0149] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A self-biased CTIA pixel readout circuit, comprising a pixel and an integrator composed of an integrating operational amplifier and an integrating capacitor, wherein the integrating operational amplifier is a single-ended input inverting amplifier, characterized in that it also... include: The bias voltage storage module is used to store the bias voltage of the integrating operational amplifier during the reset phase of the pixel readout circuit and output the bias voltage to the bias terminal of the integrating operational amplifier during the integration phase of the pixel readout circuit to eliminate the offset voltage. The bias voltage storage module realizes the bias voltage storage and bias voltage output through an offset storage capacitor connected in series between the bias terminal and the ground terminal of the integrating operational amplifier. The load pre-charge module is used to adjust the initial voltage of the output terminal of the integral operational amplifier to the reference voltage during the reset phase of the pixel readout circuit. The load pre-charge module achieves load pre-charging through a load capacitor connected in series between the output terminal of the integral operational amplifier and the ground terminal. The pixel readout circuit also includes a reset switch S1, a reset switch S2, and a reset switch S3; The two ends of the reset switch S1 are respectively connected to the output terminal and the bias terminal of the integrating operational amplifier; The two ends of the reset switch S2 are respectively connected to the bias node of the pixel and the reference voltage terminal; The two ends of the reset switch S3 are respectively connected to the integrating capacitor and the reference voltage terminal; The pixel readout circuit also includes a reset switch S4, the two ends of which are connected to a reference voltage terminal and an output port, respectively. The pixel readout circuit also includes an integral control switch S5, the two ends of which are connected to the connection point between the integral capacitor and the reset switch S3, and the output terminal of the integral operational amplifier, respectively.

2. The self-biased CTIA pixel readout circuit according to claim 1, characterized in that, At time t0 during the reset phase, reset switches S1, S2, and S3 are all closed, and the working cycle of the pixel readout circuit begins.

3. The self-biased CTIA pixel readout circuit according to claim 1, characterized in that, At time t1 during the reset phase, the reset switch S4 is closed to precharge the integrator output.

4. The self-biased CTIA pixel readout circuit according to claim 1, characterized in that, At time t2 during the reset phase, reset switches S2, S3, and S4 are disconnected, and integral control switch S5 is closed, causing the pixel readout circuit to enter the integral state.

5. An image sensor, characterized in that, It includes at least one self-biased CTIA pixel readout circuit as described in any one of claims 1-4.

6. An electronic device, characterized in that, It includes at least one image sensor as described in claim 5.

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