A ctia pixel readout circuit, image sensor and electronic device

Abstract

The application discloses a CTIA image element readout circuit, an image sensor and electronic equipment, and relates to the technical field of integrated circuits.The technical scheme points are as follows: the CTIA image element readout circuit comprises an image element and an integrator composed of an integration operational amplifier and an integration capacitor, and the CTIA image element readout circuit further comprises: a dislocation pre-storage module, which is used for pre-storing a dislocation voltage obtained for the integration operational amplifier to an inverting input end of the integration operational amplifier in a reset stage of the image element readout circuit; and a load pre-charging module, which is used for adjusting an initial voltage of an output end of the integration operational amplifier to a reference voltage in the reset stage of the image element readout circuit.The combination of dislocation voltage pre-storage and load capacitor pre-charging eliminates dislocations of image element circuits and output mismatches between the image element circuits, suppresses and eliminates FPN of an image sensor image element array caused by circuit dislocations and mismatches, and improves the uniformity of pixels.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a CTIA pixel readout circuit, an image sensor, and an electronic device. Background Technology

[0002] Image sensors, as a key component of digital imaging technology, are responsible for converting optical information into electronic information. In recent years, image sensors have been widely used in various fields such as mobile communications, security monitoring, autonomous driving, low-light night vision, industrial control, biomedicine, and aerospace. With the rapid development of sensor technology, higher requirements have been placed on image sensor performance, including imaging quality, system size, weight, and power consumption (SWaP), making the development trend of image sensors with high imaging quality and small pixels increasingly prominent.

[0003] As a crucial component of image sensor technology, the readout integrated circuit (ROIC) has seen continuous advancements in structure and performance alongside the development of image sensors. An image sensor readout circuit is a mixed-signal system, primarily composed of pixel readout circuits, signal processing circuits, timing circuits, and analog-to-digital conversion circuits. The image sensor directly converts the detected weak photocurrent signal into a voltage signal through the front-end pixel readout circuit, and then reconstructs and presents the image information through subsequent readout circuits and image processing algorithms. Therefore, the performance of the pixel readout circuit directly affects the image sensor's imaging signal quality. As pixel area shrinks, the size of the pixel readout unit circuit also gradually decreases. Smaller device sizes lead to greater mismatches, and the effects of mismatches between pixel readout unit circuits and between pixel readout circuits become increasingly severe (e.g., larger fixed-mode noise, FPN). Therefore, in the design of small-pixel (e.g., pixel pitch of 15μm and below) readout circuits, it is necessary to minimize the impact of readout circuit mismatches and their effects on the ROIC image signal.

[0004] Depending on the materials and operating methods of the pixels used in the sensor, the structure of ROICs varies. Common pixel readout circuits include Direct Injection (DI), Gate Modulated Injection (GMI), Source Follower (SFD), and Capacitive Transimpedance Amplifier (CTIA). Among these, DI and SFD readout methods cannot guarantee high linearity when processing wide dynamic range input signals; the current gain and injection efficiency of the GMI readout method are very sensitive to the threshold voltage of the MOSFET, resulting in a large offset voltage between different pixels; the CTIA readout method can achieve good linearity and high injection efficiency over a wide dynamic range, making it a more widely applicable readout method.

[0005] Therefore, how to research and design a CTIA pixel readout circuit, image sensor, and electronic device that can overcome the above-mentioned defects is a problem that we urgently need to solve. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a CTIA pixel readout circuit, an image sensor, and an electronic device. By combining offset voltage pre-storage and load capacitor pre-charging, the offset of the pixel circuit and the output mismatch between pixel circuits are eliminated, suppressing and eliminating the FPN of the image sensor pixel array caused by circuit offset and mismatch, thereby improving pixel uniformity.

[0007] The above-mentioned technical objective of the present invention is achieved through the following technical solution:

[0008] In a first aspect, a CTIA pixel readout circuit is provided, including a pixel and an integrator composed of an integrating operational amplifier and an integrating capacitor, wherein the integrating operational amplifier is a differential input operational amplifier, and further includes:

[0009] The offset pre-storage module is used to pre-store the offset voltage obtained for the integrating operational amplifier to the inverting input terminal of the integrating operational amplifier during the reset phase of the pixel readout circuit.

[0010] The load precharge module is used to adjust the initial voltage of the output terminal of the integrating operational amplifier to the reference voltage during the reset phase of the pixel readout circuit.

[0011] Furthermore, the offset pre-storage module achieves offset voltage pre-storage through an offset storage capacitor connected in series between the bias node of the pixel and the inverting input terminal of the integrating operational amplifier.

[0012] And / or, the load pre-charge module achieves load pre-charging through a load capacitor connected in series between the output terminal of the integral operational amplifier and the ground terminal.

[0013] Furthermore, the pixel readout circuit also includes a reset switch S1, a reset switch S2, and a reset switch S3;

[0014] The two ends of the reset switch S1 are respectively connected to the output terminal and the inverting input terminal of the integrating operational amplifier;

[0015] The two ends of the reset switch S2 are respectively connected to the bias node of the pixel and the reference voltage terminal;

[0016] The two ends of the reset switch S3 are connected to the integrating capacitor and the reference voltage terminal, respectively.

[0017] Furthermore, at time t0 during the reset phase, reset switches S1, S2, and S3 are all closed, causing the voltage at the inverting input of the integrating operational amplifier to be equal to the sum of the reference voltage and the offset voltage.

[0018] Furthermore, the pixel readout circuit also includes a reset switch S4, the two ends of which are connected to a reference voltage terminal and an output port, respectively.

[0019] Furthermore, at time t1 during the reset phase, the reset switch S1 is opened and the reset switch S4 is closed to precharge the integrator output.

[0020] Furthermore, the pixel readout circuit also includes an integral control switch S5, the two ends of which are connected to the connection point between the integral capacitor and the reset switch S3, and the output terminal of the integral operational amplifier, respectively.

[0021] Furthermore, at time t2 during the reset phase, reset switches S2, S3, and S4 are disconnected, and integral control switch S5 is closed, causing the pixel readout circuit to enter the integral state.

[0022] In a second aspect, an image sensor is provided, comprising at least one CTIA pixel readout circuit as described in any one of the first aspects.

[0023] Thirdly, an electronic device is provided, comprising at least one image sensor as described in the second aspect.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The present invention provides a CTIA pixel readout circuit, which, through a combination of offset voltage pre-storage and load capacitor pre-charging, ensures that the voltage of the pixel bias node A during the integration period of the CTIA pixel readout circuit remains at the reference voltage, while ensuring that the initial value of the output voltage at the output node is the reference voltage. This eliminates the offset of the pixel circuit and the output mismatch between the pixel circuits, suppresses and eliminates the FPN of the image sensor pixel array caused by circuit offset and mismatch, and improves the uniformity of pixels. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0027] Figure 1 This is a schematic diagram of the structure of a CTIA-type pixel readout circuit in the prior art;

[0028] Figure 2 This is a schematic diagram of the working timing of the CTIA-type pixel readout circuit in the prior art;

[0029] Figure 3 This is a schematic diagram of the equivalent circuit of the CTIA type pixel readout circuit in the reset state in the prior art;

[0030] Figure 4 This is a schematic diagram of the equivalent circuit of the integration state of the CTIA-type pixel readout circuit in the prior art;

[0031] Figure 5 This is a schematic diagram of the equivalent circuit of the CTIA-type pixel readout circuit under the condition of misalignment in the prior art;

[0032] Figure 6 This is a timing diagram of the operation of a CTIA-type pixel readout circuit under misalignment conditions in the prior art;

[0033] Figure 7 This is a schematic diagram of the equivalent circuit of the CTIA type pixel readout circuit in the reset state under the condition of misalignment in the prior art;

[0034] Figure 8 This is a schematic diagram of the equivalent circuit of the CTIA-type pixel readout circuit integration state under the condition of misalignment in the prior art;

[0035] Figure 9 This is a schematic diagram of the CTIA pixel readout circuit in an embodiment of the present invention;

[0036] Figure 10 This is a schematic diagram of the CTIA pixel readout circuit in an embodiment of the present invention;

[0037] Figure 11This is a schematic diagram of the working timing of the CTIA pixel readout circuit in an embodiment of the present invention;

[0038] Figure 12 This is a schematic diagram of the offset elimination of the CTIA pixel readout circuit in an embodiment of the present invention;

[0039] Figure 13 This is an equivalent schematic diagram of the CTIA pixel readout circuit reset stage 1 in an embodiment of the present invention;

[0040] Figure 14 This is an equivalent schematic diagram of the CTIA pixel readout circuit reset stage 2 in an embodiment of the present invention;

[0041] Figure 15 This is an equivalent schematic diagram of the integration stage of the CTIA pixel readout circuit in an embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0043] Example

[0044] As the pixel area shrinks, the effects of misalignment and mismatch in the pixel-level CTIA type readout circuit become more severe, as detailed below.

[0045] Taking a photovoltaic image sensor as an example, its pixels are photodiodes (PDs), and the current-voltage relationship of a PD can be expressed as:

[0046] (1);

[0047] In equation (1), I d (t) represents the total current generated by the photodiode at time t, I p (t) represents the photocurrent generated by the photodiode at time t, I o For saturation leakage current, V b This is the bias voltage of the photodiode. If the external radiation power is constant, the light intensity received by the PD remains unchanged, therefore I... p (t) remains unchanged, I d (t) is a constant value I d .

[0048] like Figure 1 As shown, the photodiode (PD) is a pixel, and the integrating operational amplifier Amp and integrating capacitor C are... int Together they form an integrator; S1 is an integrator reset switch; V outFor the output port, the integrating operational amplifier Amp and the integrating capacitor C int The most basic unit constituting the CTIA structure. Voltage V at point A. A and V BIAS_PDN The voltage provides the required reverse bias voltage to the PD. Under their influence, the current generated on the sensor pixel is input to the integrator for integration and outputs a light intensity-related voltage signal.

[0049] It should be noted that the integrating operational amplifier is a differential input operational amplifier.

[0050] like Figure 2 As shown, S1 and V B The curves representing the control timing of reset switch S1 and the voltage at point B over time are shown below. Figure 2 A high level indicates that the switch is closed, and a low level indicates that the switch is open.

[0051] At time t0, reset switch S1 is closed, and the pixel readout circuit is reset. The equivalent circuit in the reset state is as follows: Figure 3 As shown. The charge at node A during the reset phase is:

[0052] (2);

[0053] In equation (2), V A = V B =V ref V ref C is the reference voltage at the non-inverting input of the integrating operational amplifier. PD It is a PD capacitor.

[0054] At time t1, reset switch S1 is open, and the pixel readout circuit enters the integration state. The equivalent circuit of the pixel readout circuit in the integration state is as follows: Figure 4 As shown, the circuit integrates and amplifies the weak photocurrent generated by the pixel until the reset switch S1 is closed, at which point the integration cycle ends. Figure 2 As shown. The charge at node A at time t2 is:

[0055] (3);

[0056] In equation (3), V A = V ref V out for Figure 4 The voltage at point B of the CTIA shown is also the output voltage of the CTIA, i.e., V. B =V out Let the integration time be t. int =t2-t1. By the law of conservation of charge, Q2=Q1+I int ×t intTherefore, by combining equations (1) and (2), we can obtain the output voltage V of the traditional CTIA type pixel readout circuit under ideal conditions. out have:

[0057] (4);

[0058] In equation (4), V ref As the reference voltage, t int For the integration time, I int For the integral current, C int This is the integrating capacitor. At time t3, the reset switch S1 closes, ending one working cycle of the readout circuit. The pixel readout circuit outputs the integrated voltage result to the subsequent system, which will then output the corresponding image information based on the integration result and perform imaging.

[0059] Formula (4) yields the ideal output voltage V of the traditional CTIA type pixel readout circuit. out However, ideal readout circuits and pixel units do not exist. Due to manufacturing process limitations (process deviations in oxide layer thickness, diffusion doping, etching, etc.), the device parameters (such as current gain, threshold voltage, etc.) of the transistors in the op-amp in the CTIA circuit cannot be perfectly matched. This mismatch will cause the op-amp to generate an offset voltage. Furthermore, temperature changes will also cause changes in the offset voltage. Assume the op-amp offset voltage caused by device mismatch is V. os The equivalent circuit of the CTIA-type pixel readout circuit under misalignment conditions is as follows: Figure 5 As shown.

[0060] like Figure 6 As shown, during times t0~t1, the reset switch S1 is closed, and the pixel readout circuit is reset, as follows. Figure 7 As shown, the charge at point A is:

[0061] (5);

[0062] In equation (5), the voltage V at points A and B is... A = V B =V ref +V os .

[0063] Subsequently, reset switch S1 is opened, and the pixel readout circuit enters the integration state, such as... Figure 8 As shown, the circuit integrates and amplifies the current generated by the pixel PD until the reset switch S1 is closed, at which point the integration cycle ends. Figure 6 As shown, the charge at node A at time t2 is:

[0064] (6);

[0065] In equation (6), the voltage V at points A and B is... A =V ref +V os V B = V out Integration time t int =t2-t1. By the principle of charge conservation, Q2=Q1+I int ×t int Combining equations (1) and (2), we can obtain that, under actual misalignment conditions, the output voltage V of the traditional CTIA type pixel readout circuit is... out have:

[0066] (7);

[0067] As analyzed above, the operational amplifier's offset will cause the PD's bias voltage to deviate from the ideal (V) BIAS_PDN -V ref The change is (V) BIAS_PDN -V ref -V os From equation (1), it can be seen that the change in current of the photodiode caused by the change in PD bias voltage is:

[0068] (8);

[0069] By combining equations (7) and (4), we can obtain the CTIA output voltage deviation ΔV caused by op-amp offset. out for:

[0070] (9);

[0071] In equation (9), ΔI int =ΔI d Substituting equation (8) into equation (9), we can see that, under the misalignment condition, the output voltage deviation ΔV generated by the i-th pixel unit CTIA in the pixel array is... out_i It can be represented as:

[0072] (10);

[0073] In equation (10) above, V os_i Let be the equivalent input offset voltage of the CTIA operational amplifier for the i-th pixel in the pixel array; the first term is the output voltage change caused by the offset of the pixel readout circuit; the second term is the dark current offset caused by the offset of the photodiode reverse bias voltage, resulting in the integrator output change. Since the offsets of each pixel in the pixel array are different, the outputs of any pixel readout circuit will vary. These offsets ultimately cause non-uniformity in the pixel array output, i.e., fixed-mode noise (FPN).

[0074] A CTIA pixel readout circuit, such as Figure 9 As shown, it includes a pixel and an integrator composed of an integrating operational amplifier and an integrating capacitor, as well as an offset pre-storage module and a load pre-charge module.

[0075] The offset pre-storage module is used to pre-store the offset voltage obtained for the integrating operational amplifier to the inverting input terminal of the integrating operational amplifier during the reset phase of the pixel readout circuit; the load pre-charge module is used to adjust the initial voltage of the output terminal of the integrating operational amplifier to the reference voltage during the reset phase of the pixel readout circuit.

[0076] It should be noted that the offset voltage is obtained from the integrating operational amplifier using negative feedback technology, or it can be obtained and analyzed from the integrator using a detection circuit or device.

[0077] Furthermore, the offset pre-storage module and the load pre-charge module can be executed independently during the reset phase, without any timing sequence restrictions.

[0078] Furthermore, both the offset pre-storage module and the load pre-charge module can be implemented using circuits or devices independent of the existing pixel readout circuitry, such as by configuring a controllable power supply for real-time adjustment. Alternatively, the offset pre-storage module and the load pre-charge module can be integrated into the existing pixel readout circuitry.

[0079] Taking the CTIA pixel readout circuit as an example, this invention provides a specific embodiment of the CTIA pixel readout circuit structure, the structure of which is as follows: Figure 10 As shown, it consists of an integrator, reset switches S1-S4, integral control switch S5, and offset storage capacitor C. az Load capacitor C load and output port V out The integrator consists of an integrating operational amplifier (Amp) and an integrating capacitor (C). int .

[0080] like Figure 11 The diagram shows the timing sequence of the readout circuit 1 with offset cancellation function. S1, S2, and S3 represent the timing sequence of reset switches S1, S2, and S3, respectively, while S4 and S5 represent the timing sequence of the output reset switch S4 and the integral control switch S5, respectively. A high level in the diagram represents a closed switch, and a low level represents an open switch.

[0081] like Figure 10 and Figure 11 As shown, at time t0, reset switches S1, S2, and S3 are closed, the pixel readout circuit's operating cycle begins, and the readout circuit is in reset phase 1, as follows. Figure 13 As shown. The charges at points A, B, and C are respectively:

[0082] (11);

[0083] (12);

[0084] The voltages at points A, B, and C in equations (11) and (12) are respectively: V A1 =V ref V B1 =V C1 =V ref +V os .

[0085] Subsequently, at time t1, reset switch S1 is opened, and reset switch S4 at the output terminal is closed to pre-charge the integrator output. For example... Figure 14 As shown, the voltage V at point B at this time is... B By V ref + V os Reset to V ref The reset phase then ends. The charge at points A, B, and C during this phase is:

[0086] (13);

[0087] (14);

[0088] (15);

[0089] The voltages at points A, B, and C in equations (13), (14), and (15) are respectively: V A2 = V B2 =V ref V C2 =V ref +V os .

[0090] It should be noted that the load capacitor can be the parasitic capacitance of the integrator or a newly added capacitor.

[0091] Subsequently, at time t2, reset switches S2, S3, and S4 are opened, and integral control switch S5 is closed, causing the CTIA pixel readout circuit with offset cancellation function to enter the integration state. For example... Figure 15 As shown, the pixel readout circuit integrates and amplifies the integrating current until the integrating control switch S5 is opened at time t4, at which point the entire readout circuit cycle ends. The charge quantities at points A, B, and C are:

[0092] (16);

[0093] (17);

[0094] (18);

[0095] In equations (16), (17), and (18), V B3 =V out V C3 =V ref +V os .

[0096] For point C, the voltage V at point C can be determined from the virtual short and virtual open circuits of the operational amplifier. C2 =V ref +V os The voltage values ​​V at points A, B, and C are... A2 V B2 V C2 Substituting into equation (15), we can see that Q C2 =V os C az Since point C is in a floating state after the reset, C... az The charge stored in the output remains constant during the pre-charging and reset phases, therefore:

[0097] (19);

[0098] From equation (18), we can know that the voltage V at point A during the integration phase is... A3 The expression is:

[0099] (20);

[0100] The voltage V at point C C3 =V ref +V os Substituting equation (19) into equation (20), we can obtain the voltage V at point A during the integration phase. A3 have:

[0101] (twenty one);

[0102] contrast Figure 8 The equivalent circuit of the CTIA-type pixel readout circuit integration state under offset conditions is described in this invention. The pixel circuit offset voltage pre-storage technology proposed in this invention can ensure that the voltage at point A of each pixel in the pixel array remains constant at V during the integration amplification process of the pixel readout circuit. A =V ref It remains unchanged. From formulas (8) and (10), it can be seen that the reverse bias voltage difference V of each pixel photodiode in the pixel array of the circuit remains unchanged. b The change in integral current ΔI of each pixel photodiode in the pixel array compared to the case without offset is fixed. int =ΔI d =0, the effect of inconsistent PD dark current caused by input mismatch between pixel circuits in the pixel array is eliminated.

[0103] For point B, at time t2, reset switch S4 is open, integral control switch S5 is closed, and the readout circuit enters the integration phase. The voltage values ​​V at points A and B are then calculated. A3 V B2 V B3 Substituting into equations (14) and (17), we get:

[0104] (twenty two);

[0105] (twenty three);

[0106] Considering that there is no integral current injection at point A due to PD at the instant the integral control switch S5 closes, according to the law of charge conservation, the charge Q at point B at the instant the integral control switch S5 closes is... B30 Q B2 = Q B30 The combined equations (22) and (23) are:

[0107] (twenty four)

[0108] Because C load and C int These are all actual capacitors, so (C) load +C int ) > 0, therefore V out =V ref That is, for the initial voltage V at point B during the integration phase B30 have:

[0109] (25);

[0110] Among them, V out0 The initial voltage is output at the moment the integration begins.

[0111] Therefore, the initial output voltage V of the CTIA pixel readout circuit embodiment with offset cancellation function proposed in this invention is... out =V B30 That is, the initial value of point B remains unchanged during the integration phase. The mismatch error calibration combined readout method proposed in this invention, which combines mismatch pre-storage technology and load capacitor pre-charging technology, can simultaneously eliminate the output mismatch between pixel circuits and reduce the pixel array FPN.

[0112] Substituting the above values ​​into formulas (13) and (16), we can see that:

[0113] (26);

[0114] (27);

[0115] Combining formulas (26) and (27), let the integration time tint =t3-t2, according to the principle of charge conservation, Q A2 =Q A3 +I int ×t int have:

[0116] (28);

[0117] Substituting the values ​​in equations (21) and (25) into equation (28), it can be seen that, under actual misalignment conditions, the output voltage V of the CTIA pixel readout circuit embodiment with misalignment cancellation function proposed in this invention is... out for:

[0118] (29);

[0119] It can be seen that the expression of formula (29) is the same as the output expression (4) of the CTIA pixel readout circuit under the ideal condition of no offset mentioned above. Therefore, an embodiment of the combined readout method of pixel circuit offset voltage pre-storage technology and load capacitor pre-charging technology proposed in this invention: the CTIA pixel readout circuit with offset cancellation function can eliminate the effects of output offset of pixel circuit, mismatch of PD reverse bias voltage and output mismatch between pixels in the pixel array, thereby reducing the pixel array FPN and improving the non-uniformity of the pixel array.

[0120] like Figure 10 The embodiment shown in this invention utilizes a combined readout method combining pixel circuit offset voltage pre-storage technology and load capacitor pre-charging technology to ensure the voltage V at pixel bias node A during the integration period of the CTIA pixel readout circuit. A Always maintain the reference voltage V ref Simultaneously, this causes the output voltage V at output node B to... out The initial value is the reference voltage V. ref During the integration and amplification process of the CTIA pixel readout circuit with offset cancellation function, the reverse bias voltage difference V of each pixel photodiode in the pixel array of the readout circuit is... b As can be seen from formulas (8) and (10), the change in integral current ΔI of each pixel photodiode in the pixel array compared to the case without offset is constant. int =ΔI d=0, therefore, the combined readout method of offset voltage pre-storage technology and load capacitor pre-charging technology proposed in this invention can effectively reduce the impact of inconsistent PD dark current caused by offset of each pixel circuit in the pixel array. Simultaneously, the combined readout method of pixel circuit offset voltage pre-storage technology and load capacitor pre-charging technology proposed in this invention effectively fixes the starting voltage of each pixel unit during integration, eliminating the influence of pixel circuit offset on the integration output. Therefore, the combined readout method of pixel circuit offset voltage pre-storage technology and load capacitor pre-charging technology proposed in this invention can effectively eliminate the pixel array FPN and reduce the non-uniformity of the image sensor readout circuit.

[0121] The present invention also describes an image sensor comprising at least one CTIA pixel readout circuit as described above.

[0122] The present invention also describes an electronic device comprising at least one image sensor as described above.

[0123] Working principle: This invention ensures that the voltage of the pixel bias node A remains at the reference voltage during the integration period of the CTIA pixel readout circuit by combining offset voltage pre-storage and load capacitor pre-charging. At the same time, it ensures that the initial value of the output voltage at the output node is the reference voltage, thereby eliminating the offset of the pixel circuit and the output mismatch between the pixel circuits. It also suppresses and eliminates the FPN of the image sensor pixel array caused by circuit offset and mismatch, and improves the uniformity of pixels.

[0124] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A CTIA pixel readout circuit, comprising a pixel and an integrator composed of an integrating operational amplifier and an integrating capacitor, wherein the integrating operational amplifier is a differential input operational amplifier, characterized in that it further comprises... include: The offset pre-storage module is used to pre-store the offset voltage obtained for the integrating operational amplifier to the inverting input terminal of the integrating operational amplifier during the reset phase of the pixel readout circuit. The offset pre-storage module achieves offset voltage pre-storage through an offset storage capacitor connected in series between the bias node of the pixel and the inverting input of the integrating operational amplifier. The load pre-charge module is used to adjust the initial voltage of the output terminal of the integral operational amplifier to the reference voltage during the reset phase of the pixel readout circuit. The load pre-charge module achieves load pre-charging through a load capacitor connected in series between the output terminal of the integral operational amplifier and the ground terminal. The load pre-charge module and the offset pre-storage module are executed independently during the reset phase without any timing sequence restrictions. The pixel readout circuit also includes a reset switch S1, a reset switch S2, and a reset switch S3; The two ends of the reset switch S1 are respectively connected to the output terminal and the inverting input terminal of the integrating operational amplifier; The two ends of the reset switch S2 are respectively connected to the bias node of the pixel and the reference voltage terminal; The two ends of the reset switch S3 are respectively connected to the integrating capacitor and the reference voltage terminal; The pixel readout circuit also includes a reset switch S4, the two ends of which are connected to a reference voltage terminal and an output port, respectively. The pixel readout circuit also includes an integral control switch S5, the two ends of which are connected to the connection point between the integral capacitor and the reset switch S3, and the output terminal of the integral operational amplifier, respectively.

2. The CTIA pixel readout circuit according to claim 1, characterized in that, in At time t0 during the reset phase, reset switches S1, S2, and S3 are all closed, making the voltage at the inverting input of the integrating operational amplifier equal to the sum of the reference voltage and the offset voltage.

3. A CTIA pixel readout circuit according to claim 1, characterized in that, in At time t1 during the reset phase, the reset switch S1 is opened and the reset switch S4 is closed to precharge the integrator output.

4. A CTIA pixel readout circuit according to claim 1, characterized in that, in At time t2 during the reset phase, reset switches S2, S3, and S4 are disconnected, and integral control switch S5 is closed, causing the pixel readout circuit to enter the integral state.

5. An image sensor, characterized in that, It includes at least one CTIA pixel readout circuit as described in any one of claims 1-4.

6. An electronic device, characterized in that, It includes at least one image sensor as described in claim 5.

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