Dynamic random access memory device and manufacturing method thereof

Abstract

The invention provides a dynamic random access memory device and a manufacturing method thereof. The device includes a substrate having an active region, a stack structure and a capacitive contact structure. The stack structure is over the substrate and extends along a first direction, and includes a bit line structure, a mask structure, and a spacer structure. The bit line structure is over the substrate and electrically connected to the active region. The mask structure is located on the bit line structure and comprises a first dielectric layer, a second dielectric layer and a third dielectric layer which are sequentially formed on the bit line structure and arranged in the second direction, and the dielectric constant of the second dielectric layer is smaller than the dielectric constant of the first dielectric layer and the dielectric constant of the third dielectric layer. The spacing structure is located on the side walls of the bit line structure and the mask structure. The capacitor contact structure is located on the substrate and laterally separated from the stack structure, wherein the capacitor contact structure is electrically connected with the active region.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device and a manufacturing method thereof, and in particular to a dynamic random access memory device and a manufacturing method thereof which can reduce parasitic capacitance and improve electrical performance. Background Art

[0002] Dynamic Random Access Memory (DRAM) devices are widely used in consumer electronic products. In order to increase the density of components in DRAM devices and improve their overall performance, the current manufacturing technology of DRAM devices continues to strive towards the miniaturization of component size. However, as the manufacturing technology of components continues to develop towards the miniaturization of component size, many challenges arise. For example, as the size of DRAM devices decreases, the distance between the landing pad of the capacitor and the laterally adjacent bit line becomes closer, so that the parasitic capacitance between the landing pad of the capacitor and the bit line has a greater impact on the electrical performance of the DRAM device.

[0003] In addition, in the existing DRAM device, before the bit line material layer is formed, if it is affected by the previous process (such as the residue of contaminants or particles of the film layer itself), the film layer may be unexpectedly uneven, so that the subsequently formed bit line material layer is unexpectedly raised. As a result, the raised bit line material layer may be exposed in the subsequent planarization process, and the exposed bit line material layer is easily damaged, resulting in the problem of poor profile or even broken wires of the subsequently formed bit line stack structure. In order to solve this problem, the existing DRAM device proposes to increase the thickness of the hard mask layer above the bit line material layer. However, after the thickness of the hard mask layer is increased, the process conditions of the ion implantation in the active area of ​​the peripheral area must be adjusted to achieve the desired ion implantation range and depth. This adjustment requirement will increase the process difficulty and development time. In addition, as the size of the DRAM device is reduced, increasing the thickness of the hard mask layer may cause the subsequent ion implantation in the active area of ​​the peripheral area to fail to reach the expected ion implantation range and depth, thereby causing the failure of the peripheral circuit and reducing the yield rate of the DRAM device. Summary of the invention

[0004] Some embodiments of the present invention provide a DRAM device, comprising: a substrate having an active region; a stacked structure located above the substrate and extending along a first direction; and a capacitor contact structure located on the substrate and laterally separated from the stacked structure, wherein the capacitor contact structure is electrically connected to the active region. The stacked structure of the present invention includes a bit line structure, a mask structure, and a spacing structure. The bit line structure is located above the substrate and electrically connected to the active region. The mask structure is located on the bit line structure, wherein the mask structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer sequentially formed on the bit line structure and stacked along a second direction, wherein the dielectric constant of the second dielectric layer is less than the dielectric constants of the first dielectric layer and the third dielectric layer. The spacing structure is located on the sidewalls of the bit line structure and the mask structure.

[0005] Some embodiments of the present invention provide a method for manufacturing a DRAM device, including providing a substrate having an active region; forming a bit line material layer above the substrate; forming a mask material stacking layer above the bit line material layer; patterning the mask material stacking layer and the bit line material layer to form a stacking structure extending along a first direction; and forming a capacitor contact structure above the substrate, wherein the capacitor contact structure and the stacking structure are laterally separated from each other, wherein the capacitor contact structure is electrically connected to the active region. The stacking structure of the present invention includes a bit line structure, a mask structure, and a spacing structure. The bit line structure is located above the substrate and is electrically connected to the active region. The mask structure is located on the bit line structure, wherein the mask structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer sequentially formed on the bit line structure and stacked along a second direction, wherein the dielectric constant of the second dielectric layer is less than the dielectric constant of the first dielectric layer and the third dielectric layer. The spacing structure is located on the sidewalls of the bit line structure and the mask structure.

[0006] According to the DRAM device and the manufacturing method thereof provided by the present invention, a mask structure composed of a mixture of different dielectric material layers is arranged above the bit line structure to reduce the parasitic capacitance between the landing pad of the capacitor contact structure and the adjacent bit line structure, thereby improving the electrical performance of the DRAM device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 1 is a partial top view of an array region and a peripheral region of a DRAM device in one of the steps according to some embodiments of the present invention.

[0008] Figure 2 Examples along Figure 1 Schematic diagram of the cross section taken along the section line BB in FIG.

[0009] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 Schematic cross-sectional views of a DRAM device at various intermediate manufacturing stages according to some embodiments of the present invention.

[0010] Fig. 10A is a partial top view of an array region of a DRAM device according to some embodiments of the present invention.

[0011] Figure 13-Figure 15 Schematic cross-sectional views of a DRAM device at various intermediate manufacturing stages according to some embodiments of the present invention.

[0012] Fig.16 FIG. 4 is a partial enlarged schematic diagram of an array region of a DRAM device according to some embodiments of the present invention.

[0013] Reference numerals:

[0014] 10,10':DRAM device

[0015] 100: substrate

[0016] 100a, 2520a, 252a, 253a, 26a, 274a, 281a: top surface 252b, 285b: bottom surface

[0017] 101: Active Area

[0018] 102: Isolation Structure

[0019] 104: Word Line

[0020] 1041: Gate dielectric layer

[0021] 1042: Barrier layer

[0022] 1043: first work function layer

[0023] 1044: second work function layer

[0024] 1045: Insulation layer

[0025] 106: Dielectric material layer

[0026] 21: Bit line contact

[0027] 212: Depression

[0028] 23: Stacked structure (bit line)

[0029] 23A: First stacking structure

[0030] 23B: Second stacking structure

[0031] 24: Bit line structure

[0032] 24A: First bit line structure

[0033] 24B: Second bit line structure

[0034] 240: bit line material layer

[0035] 241,241': semiconductor material layer

[0036] 242: first conductive material layer

[0037] 242': first conductive layer

[0038] 243: second conductive material layer

[0039] 243': second conductive layer

[0040] 25: Mask structure

[0041] 25A: First mask structure

[0042] 25B: Second mask structure

[0043] 250: Mask material stacking layer

[0044] 251, 251A': first dielectric material layer

[0045] 251': first dielectric layer

[0046] 2520,252: second dielectric material layer

[0047] 252', 252A': second dielectric layer

[0048] 253 third dielectric material layer

[0049] 253', 253A': third dielectric layer

[0050] 251B': fourth dielectric layer

[0051] 252B': fifth dielectric layer

[0052] 253B': sixth dielectric layer

[0053] 26: Oxide layer

[0054] 27: Interval structure

[0055] 27L,2851:lower part

[0056] 27U,2852: Upper

[0057] 271, 271': first spacer material layer

[0058] 272: Second spacer material layer

[0059] 273, 273': third spacer material layer

[0060] 274, 274': fourth spacer material layer

[0061] 280: Capacitor contact structure

[0062] 281: Node contact plug

[0063] 281b: Bottom

[0064] 281': Polysilicon layer

[0065] 282: Metal silicide layer

[0066] 2830: Barrier material layer

[0067] 283: Barrier layer

[0068] 2840: Conductive material layer

[0069] 284: Conductive layer

[0070] 285: Landing Pad

[0071] 291: Insulation layer

[0072] 32: Component structure

[0073] 320: Gate oxide layer

[0074] 321: Semiconductor layer

[0075] 322: first gate conductive layer

[0076] 323: second gate conductive layer

[0077] 325: Hard mask layer

[0078] 327: Spacer

[0079] 328: Covering layer

[0080] 501: Particles

[0081] A1: Array area

[0082] A2: Surrounding area

[0083] H2,H2-1,H3,H4:Thickness

[0084] HR1: First thickness

[0085] HR2: Second thickness

[0086] D1: First direction

[0087] D2: Second direction

[0088] D3: Third direction

[0089] AA,BB: Section line DETAILED DESCRIPTION

[0090] The following content provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the present invention. In addition, if the description mentions that a first element is formed above or located on a second element, unless otherwise specifically excluded, it may mean that the first element and the second element are in direct contact, or it may be an embodiment in which the first element and the second element are not in direct contact. In addition, for the purpose of simplicity and clarity, the embodiments of the present invention may use the same or similar element symbols for the same or similar elements in many examples, and may only show parts of the DRAM device related to the present invention.

[0091] The following describes a DRAM device and a method for manufacturing the same according to an embodiment of the present invention. Figure 1 . Figure 1 FIG. 1 is a partial cross-sectional view of an array area A1 and a peripheral area A2 of a DRAM device of the present embodiment in one of the steps, wherein the array area A1 is along the Figure 1 The section line AA in is shown.

[0092] According to some embodiments, the DRAM device 10 includes a substrate 100, a plurality of word lines 104, a bit line contact 21, a bit line 23, and a capacitor contact (although not shown in FIG. Figure 1 shown, but in the subsequent Fig. 10A2 ). The substrate 100 includes a plurality of doped regions as active regions 101. An isolation structure 102 surrounding the active region 101 and a plurality of word lines 104 may be formed in the substrate 100. In some embodiments, the bit line 23 may include a plurality of material layers stacked on the substrate 100 along the second direction D2. Each bit line 23 may extend along the first direction D1, and these bit lines 23 may be arranged along the third direction D3. The first direction D1 is, for example (but not limited to), perpendicular to the second direction D2. Furthermore, each word line 104 may extend along the third direction D3, that is, the word line 104 may intersect with the bit line 23, and these word lines 104 may be arranged along the first direction D1. In one embodiment, the extension direction of each active region 101 may present an angle (e.g., approximately 10° to 40°) with the third direction D3 to increase the integration degree. In some embodiments, each active region 101 may intersect two word lines 104 and one bit line 23, and may be electrically connected to the upper bit line 23 through the bit line contact 21. In a top view, the bit line contacts 21 may be arranged in a staggered manner, and may be arranged spaced apart from the word line 104 in the extending direction of the bit line 23 (e.g., in the first direction D1).

[0093] Figure 2 Examples along Figure 1 . In the present embodiment, the word line 104 may be formed in the substrate 100 so that its top surface is lower than the top surface 100a of the substrate 100, and thus may be referred to as a buried word line. Each word line 104 may include a gate dielectric layer 1041, a barrier layer 1042, and a conductive material layer (e.g., a first work function layer 1043 and a second work function layer 1044) formed in sequence. An insulating layer 1045 is formed above each word line 104 (e.g., above the second work function layer 1044).

[0094] In one embodiment, the gate dielectric layer 1041 may include silicon oxide, silicon nitride, other suitable materials or combinations thereof. The material of the barrier layer 1042 includes a conductive metal, such as a metal, a metal alloy, a metal nitride or a metal silicide.

[0095] In some embodiments, a first work function layer 1043 is formed on the barrier layer 1042. The material of the first work function layer 1043 includes a conductive metal, such as a metal, a metal alloy, a metal nitride, or a metal silicide. In one embodiment, the material of the first work function layer 1043 includes tungsten, tantalum, titanium, ruthenium, aluminum, tungsten nitride, titanium nitride, titanium silicon nitride, tantalum nitride, or other suitable conductive materials.

[0096] In some embodiments, a second work function layer 1044 is formed above the first work function layer 1043. The second work function layer 1044, for example, includes doped or undoped polysilicon, or metal, metal alloy, metal nitride, metal silicide, etc. In one embodiment, the barrier layer 1042 includes titanium nitride, and the first work function layer 1043 includes tungsten. The material of the second work function layer 1044 includes polysilicon, titanium nitride, titanium silicon nitride, tantalum nitride, tungsten nitride, tantalum, titanium, tungsten, ruthenium, aluminum, or other suitable conductive materials.

[0097] Of course, if Figure 2 The related components and configuration of the word line 104 shown are only for illustration purposes. The DRAM device 10 proposed in the present invention can adopt any known word line structure and process, and is not limited thereto.

[0098] The present invention proposes a new bit line stacking structure to improve the electrical performance of the DRAM device 10 (for example, it can reduce the parasitic capacitance between the capacitor contact structure and the adjacent bit lines), and can also avoid the problem of poor profile or even broken line of the subsequent bit lines caused by uneven film layers. Furthermore, the manufacturing method proposed in the embodiment of the present invention does not affect the process of other components of the DRAM device 10. For example, it does not need to change the process of the components (such as transistor components) located in the peripheral area, so it is easy to integrate with the existing process, shortening the development time of the DRAM device 10. The following is a manufacturing method of a DRAM device according to some embodiments of the present invention with accompanying drawings.

[0099] The material of the substrate 100 may include a semiconductor material, for example, silicon, gallium arsenide, gallium nitride, silicon germanium or a combination thereof. In another embodiment, the substrate 100 may be a substrate with a semiconductor on an insulating layer. In this embodiment, the substrate 100 is a silicon substrate and includes an array region and a peripheral region (as described later). Figure 3 In this document, when the film layer is formed in a blanket manner, it means that the formed film layer covers both the array region A1 and the peripheral region A2.

[0100] In some embodiments, the isolation structure 102 may be a shallow trench isolation structure, for example, including an isolation liner and an isolation filler formed in sequence. The isolation liner and the isolation filler may include nitrides or oxides, such as silicon oxide, silicon nitride, silicon oxynitride, and / or a combination of the foregoing materials. It should be understood that the isolation structure 102 in the figure is not intended to limit the content of the present invention, and the present invention may adopt any known isolation structure 102 and its manufacturing method.

[0101] Furthermore, refer to Figure 2According to some embodiments of the present invention, after forming the insulating layer 1045 above the word line 104, a dielectric material layer 106 is blanket formed above the substrate 100. In some embodiments, the dielectric material layer 106 may include a nitride layer and an oxide layer formed sequentially, but the present invention is not limited thereto.

[0102] Afterwards, refer to Figure 3 , a bit line material layer 240 and a first dielectric material layer 251 are formed on the dielectric material layer 106 of the array area A1, and a plurality of device structures 32 are formed in the peripheral area A2. In this embodiment, the bit line material layer 240 includes a semiconductor material layer 241, a first conductive material layer 242, and a second conductive material layer 243, but the present invention is not limited thereto. In addition, a bit line contact 21 can be formed that penetrates the semiconductor material layer 241, the dielectric material layer 106, and extends into the substrate 100.

[0103] In some embodiments, the semiconductor material layer 241 may be an undoped semiconductor layer, a doped semiconductor layer, or a polysilicon layer. The bit line contact 21 may include polysilicon, a metal, or a metal nitride. The first conductive material layer 242 and the second conductive material layer 243 may include undoped or doped polysilicon, a metal, or a metal nitride, such as tungsten (W), titanium (Ti), or titanium nitride (TiN). The resistance of the second conductive material layer 243 is, for example, lower than the resistance of the semiconductor material layer 241. In some examples, the semiconductor material layer 241 is, for example, polysilicon, the first conductive material layer 242 is a titanium nitride layer, and the second conductive material layer 243 is a metal tungsten layer.

[0104] Afterwards, a first dielectric material layer 251 is blanket formed on the bit line material layer 240. The first dielectric material layer 251 includes, for example, nitride, other suitable dielectric materials, or a combination thereof. The first dielectric material layer 251 can prevent the underlying bit line material layer 240 from being damaged. For example, the first dielectric material layer 251 includes a silicon nitride layer.

[0105] According to one embodiment, the device structure 32 may be, for example, a gate stack of a transistor device. In one embodiment, the device structure 32 includes a gate oxide layer 320, a semiconductor layer 321 (e.g., a polysilicon layer), a first gate conductive layer 322 (e.g., a titanium nitride layer), a second gate conductive layer 323 (e.g., a metal tungsten layer), and a hard mask layer 325 (e.g., a silicon nitride layer) sequentially formed on the substrate 100.

[0106] In some embodiments, after forming the device structure 32, a local implantation (not shown) may be performed on the substrate 100 surrounding the device structure 32. This local implantation is also called a ring or pocket implantation to block the expansion of the source / drain PN junction formed subsequently, thereby preventing the device structure with a short channel from being broken down. According to an embodiment of the present invention, since the second dielectric material layer 252 and the third dielectric material layer 253 are deposited after the device structure 32 and the local implantation are formed (as described later in the following description), the device structure 32 may be formed into a substrate 100 that is surrounded by the device structure 32. Figure 3 to Figure 6 Therefore, the manufacturing method proposed in this embodiment can achieve the advantage of reducing parasitic capacitance without affecting the process of the original device structure of the peripheral area A2 (described in detail later).

[0107] According to some embodiments, spacers 327 may be formed on the sidewalls of the bit line material layer 240, the first dielectric material layer 251, and the device structure 32. Source / drain regions (not shown) are formed in the substrate 100 on both sides of the device structure 32. Afterwards, a capping layer 328 is conformally and blanket deposited on the substrate 100.

[0108] In one embodiment, the cover layer 328 may include silicon nitride. In the subsequent figures, since the cover layer 328 and the first dielectric material layer 251 are made of the same material, the interface between the cover layer 328 and the first dielectric material layer 251 is omitted to simplify the figure, and the cover layer 328 is omitted.

[0109] Afterwards, refer to Figure 4 According to one embodiment, a second dielectric material layer 2520 is blanket formed on the cover layer 328 to provide a flat surface. In this example, the second dielectric material layer 2520 covers the first dielectric material layer 251 in the array area A1 and the device structure 32 in the peripheral area A2, and fills the gaps between the devices below. The thickness of the second dielectric material layer 2520 can make its top surface 2520a a flat surface.

[0110] According to the present invention, the dielectric constant of the second dielectric material layer 2520 is less than the dielectric constant of the first dielectric material layer 251. In some embodiments, the first dielectric material layer 251 includes nitride, and the second dielectric material layer 2520 includes oxide (e.g., silicon oxide). In this example, the second dielectric material layer 2520 includes a flowable oxide to facilitate filling of the gaps.

[0111] In some embodiments, after forming the second dielectric material layer 2520 , an annealing process may be performed to solidify the second dielectric material layer 2520 .

[0112] Reference Figure 5According to some embodiments, the second dielectric material layer 2520 in the array area A1 and the peripheral area A2 is thinned simultaneously so that the thinned second dielectric material layer 252 has a flat top surface 252a. In the present embodiment, the thinned second dielectric material layer 252 may have a thickness H2-1 in the array area A1, which is not greater than the thickness H2 of the second dielectric material layer 252 above the device structure 32 in the peripheral area A2, but the present invention is not limited thereto. In an embodiment not shown, the thickness H2-1 may be greater than the thickness H2. In some embodiments, the second dielectric material layer 2520 may be thinned by a planarization process, an etching process, or a combination thereof. The planarization process is, for example, a chemical mechanical polishing (CMP) process. The etching process includes a dry etching process, a wet etching process, or a combination thereof. In the present embodiment, the second dielectric material layer 2520 may be thinned by multiple stages (e.g., two stages). For example, the second dielectric material layer 2520 is first thinned to a first thickness HR1 by a CMP process, and then thinned to a second thickness HR2 by a dry etching process, wherein the first thickness HR1 is greater than the second thickness HR2. In this way, the thinning efficiency and flatness of the second dielectric material layer 252 can be improved.

[0113] According to the present embodiment, the thinned second dielectric material layer 252 will subsequently form a portion of the mask structure above the bit line. In contrast, in the conventional process, the cover layer equivalent to the present embodiment is used as a stop layer, and the second dielectric material layer equivalent to the present embodiment is planarized. Since the top surface of the cover layer located in the array region is higher than the top surface of the cover layer located in the peripheral region, the second dielectric material layer in the array region will be completely removed. That is, the conventional process does not form a thinned second dielectric material layer on the cover layer in the array region.

[0114] Afterwards, refer to Figure 6 , a third dielectric material layer 253 different from the second dielectric material layer 2520 is formed on the thinned second dielectric material layer 252. In a preferred embodiment, the thickness of the thinned second dielectric material layer 252 may be less than or equal to the thickness of the third dielectric material layer 253, and the dielectric constant of the second dielectric material layer 2520 is less than the dielectric constant of the third dielectric material layer 253, so as to further improve the flatness of the top surface 253a of the third dielectric material layer 253, improve the protection of the underlying film layer, and reduce the subsequent formation of the conductive material layer 284 and the second conductive layer 243 '(such as Fig.12In the present invention, the first dielectric material layer 251, the second dielectric material layer 252 and the third dielectric material layer 253 constitute a mask material stacking layer 250 formed on the bit line material layer 240. For example, the thickness of the thinned second dielectric material layer 252 can be one-half to four-fifths of the thickness of the third dielectric material layer 253, but the present invention is not limited thereto.

[0115] Furthermore, according to an embodiment of the present invention, the third dielectric material layer 253 and the second dielectric material layer 252 include different materials. For example, the second dielectric material layer 252 is a silicon oxide layer. The third dielectric material layer 253 is a silicon nitride layer. In some embodiments, the third dielectric material layer 253 and the first dielectric material layer 251 include the same material. For example, the third dielectric material layer 253 and the first dielectric material layer 251 are silicon nitride layers, respectively.

[0116] Afterwards, refer to Figure 7 According to some embodiments, the mask material stack layer 250 and the bit line material layer 240 may be subjected to a suitable patterning process to form a plurality of mask structures 25 and a plurality of bit line structures 24 in the array area A1, respectively, wherein the mask structures 25 and the bit line structures 24 are collectively referred to as stack structures 23 herein.

[0117] More specifically, in some embodiments, the mask material stack layer 250 may be patterned to form a plurality of mask structures 25 including a third dielectric layer 253', a second dielectric layer 252' and a first dielectric layer 251'. Afterwards, a suitable patterning process is performed on the underlying bit line material layer 240 according to the mask structure 25 to form a plurality of bit line structures 24 including a second conductive layer 243', a first conductive layer 242' and a semiconductor material layer 241'.

[0118] In addition, in some embodiments, Figure 7 As shown, when forming the stack structure 23, the bit line contact 21 and the substrate 100 around it are partially removed to form a recess 212 surrounding the bit line contact 21. Each recess 212 exposes a portion of the active region 101 and a portion of the isolation structure 102.

[0119] Reference Figure 8According to some embodiments, a first spacer material layer 271 may be conformally formed on the sidewall of the stacked structure 23 and the surface of the recess 212, a second spacer material layer 272 may be formed to fill the recess 212, and a third spacer material layer 273 may be conformally formed on the first spacer material layer 271. In some embodiments, the first spacer material layer 271, the second spacer material layer 272, and the third spacer material layer 273 may each include, for example, silicon oxide, silicon nitride, other suitable dielectric materials, or a combination thereof. For example, the first spacer material layer 271 and the second spacer material layer 272 are silicon nitride layers, and the third spacer material layer 273 is a silicon oxide layer, but the present invention is not limited thereto.

[0120] Afterwards, refer to Fig. 9 According to some embodiments, a fourth spacer material layer 274 is conformally formed on the third spacer material layer 273, and an oxide layer 26 is formed on the fourth spacer material layer 274 to fill the gap. The fourth spacer material layer 274 and the oxide layer 26 may be planarized so that a top surface 274a of the fourth spacer material layer 274 is coplanar with a top surface 26a of the oxide layer 26. The fourth spacer material layer 274 may include, for example, silicon oxide, silicon nitride, other suitable dielectric materials, or a combination thereof. In some embodiments, the fourth spacer material layer 274 and the third spacer material layer 273 may include different materials. For example, the fourth spacer material layer 274 is a silicon nitride layer.

[0121] Afterwards, refer to Fig. 10A and Fig.10 According to some embodiments, the horizontal portions of the oxide layer 26 and the fourth spacer material layer 274 between the stacked structures 23 are removed to form a node contact hole 281h exposing the substrate 100. In one embodiment, the exposed substrate 100 may be further etched so that the node contact hole 281h extends to below the dielectric material layer 106. Fig.10 The array area A1 is along Fig. 10A The section line AA in FIG.

[0122] In some examples, after the node contact hole 281h is formed, over-etching may be performed so that the top surfaces of the third dielectric layer 253', the first spacer material layer 271', the third spacer material layer 273' and the fourth spacer material layer 274' are substantially coplanar. Herein, the first spacer material layer 271', the third spacer material layer 273' and the fourth spacer material layer 274' are collectively referred to as the bit line spacer structure 27.

[0123] Thereafter, according to some embodiments, a node contact plug 281 is formed in the node contact hole 281h, which is located at one side of the stack structure 23 and contacts the active region 101. A top surface 281a of the node contact plug 281 may be lower than a top surface 23a of the stack structure 23. In some examples, a height of the top surface 281a of the node contact plug 281 may be located between a top surface 252a and a bottom surface 252b of the second dielectric layer 252'. For example, a height of the top surface 281a of the node contact plug 281 may be close to or equal to a height of a bottom surface 252b of the second dielectric layer 252' of the mask structure 25, but the present invention is not limited thereto. In some embodiments, the conductive material forming the node contact plug 281 may include, for example, doped polysilicon, metal, or metal nitride, metal silicide, or a combination thereof. In this embodiment, the node contact plug 281 includes a doped polysilicon layer 281 ′ and a metal silicide layer 282 (eg, cobaltized silicon (CoSi)) formed in sequence to reduce subsequent contact resistance.

[0124] According to some embodiments, spacer structure 27 may include an upper portion 27U located above top surface 281a of node contact plug 281 and a lower portion 27L located below top surface 281a of node contact plug 281. Each node contact plug 281 may have a bottom surface 281b located below dielectric material layer 106.

[0125] Next, refer to Fig.11 According to some embodiments, a barrier material layer 2830 may be conformally formed on the mask structure 25 and in the node contact hole 281h in which the node contact plug 281 is formed, and an excess conductive material layer 2840 may be formed on the barrier material layer 2830. The barrier material layer 2830 may include a metal nitride, such as titanium nitride (TiN). The conductive material layer 2840 may include doped polysilicon, a metal, or a metal nitride, such as metal tungsten (W).

[0126] Next, refer to Fig.12 According to some embodiments, a portion of the barrier material layer 2830 and a portion of the conductive material layer 2840 are removed to form a landing pad 285 including a barrier layer 283 and a conductive layer 284. Thereafter, an insulating layer 291 is formed between two adjacent landing pads 285. In some embodiments, a lower portion 2851 of the landing pad 285 is adjacent to an upper portion 27U of the spacing structure 27, and an upper portion 2852 of the landing pad 285 is located on the third dielectric layer 253'. The landing pad 285 is used to electrically connect the node contact plug 281 to a capacitor formed subsequently. In this document, the landing pad 285 and the node contact plug 281 are collectively referred to as a capacitor contact structure 280. The capacitor contact structure 280 is electrically connected to the active region 101. In this embodiment, the insulating layer 291 may include silicon nitride.

[0127] Furthermore, in some embodiments, after removing a portion of the blocking material layer 2830 and a portion of the conductive material layer 2840, over-etching may be performed to remove a portion of the third dielectric layer 253' and the spacer structure 27, so that the shortest distance between the subsequently formed insulating layer 291 and the top surface 252a of the second dielectric layer 252' is less than the maximum thickness of the third dielectric layer 253'. Furthermore, the insulating layer 291 and the third dielectric layer 253' may have the same material (e.g., silicon nitride), so that the insulating layer 291 can compensate for the removed portion of the third dielectric layer 253', so that the bit line structure 24 and the landing pad 285 can be separated by a composite dielectric structure formed by stacking different dielectric materials. In this embodiment, the bit line structure 24 and the landing pad 285 are separated by a dielectric structure composed of a mixture of a nitride layer (ie, the first dielectric layer 251') - an oxide layer (ie, the second dielectric layer 252') - a nitride layer (ie, the third dielectric layer 253' or the insulating layer 291).

[0128] In a preferred embodiment, the bottom surface 285b of the lower portion 2851 of the landing pad 285 may not be lower than the bottom surface 252b of the second dielectric layer 252' of the mask structure 25, so as to further reduce the parasitic capacitance between the landing pad 285 and the bit line structure 24. Furthermore, in order to control the impedance of the capacitor contact structure 280 within a preferred range, the height of the bottom surface 285b of the lower portion 2851 of the landing pad 285 may be located between the top surface 252a and the bottom surface 252b of the second dielectric layer 252'.

[0129] After forming the capacitor contact structure 280, additional components such as capacitors, metal layers, etc. may be formed to complete the fabrication of the DRAM device. It is worth noting that in the above-mentioned embodiment or its variant embodiments, each step may include other known applicable processes. In order to simplify the drawings and clearly illustrate the embodiments, the drawing and detailed description of these known processes are omitted.

[0130] The DRAM device proposed in some embodiments of the present invention can not only reduce the parasitic capacitance between the landing pad 285 of the capacitor contact structure 280 and the laterally adjacent bit line structure 24 as described above, but also solve the problem of poor profile or even disconnection of subsequent bit lines caused by uneven film defects (such as contaminants or particles in the film itself, which cause the film layer to protrude locally). An example is proposed below and is explained with reference to the drawings.

[0131] Figure 13-Figure 15 Schematic cross-sectional views of a DRAM device at various intermediate manufacturing stages according to some embodiments of the present invention. Figure 13-Figure 15 Zhongyu Figure 1-Figure 6 and Fig.12The same or similar components are given the same or similar reference numbers, and reference may be made to the contents regarding these components in the above embodiments, which will not be repeated here.

[0132] According to some embodiments, during the manufacturing process before the second dielectric material layer 2520 is formed, contaminants (such as residual particles of nitride or oxide) may fall off, causing the subsequent film layer covering the contaminants to have a protrusion, or the film layer itself has particles with larger particle sizes and has a local protrusion phenomenon. Fig.13 , which illustrates that a particle 501 falls on a substrate 100, and the film layers covering the particle 501, for example, sequentially include a semiconductor material layer 241, a first conductive material layer 242, and a second conductive material layer 243, which conformably protrude upward locally along the surface of the particle 501. However, the second dielectric material layer 2520 covering the first dielectric material layer 251 of the present invention can provide a flat top surface 2520a, that is, reduce the influence of the previous film layer protruding locally upward.

[0133] Next, refer to Fig.14 , a portion of the second dielectric material layer 2520 is removed, so that the thinned second dielectric material layer 252 has a flat top surface 252a.

[0134] In conventional processes, the planarization process is performed until at least the surface of the first dielectric material layer similar to the present invention is exposed. In this way, if the surface of the first dielectric material layer has a local protrusion, the planarization process may expose the protruding bit line material layer (e.g., tungsten layer) below. If the tungsten layer is exposed, the cleaning solution may react with tungsten in the cleaning process after the planarization process, and even diffuse outward to damage a larger area of ​​the tungsten layer, thereby causing the subsequently formed bit line structure to have a defect of poor profile or even a problem of bit line disconnection.

[0135] According to the DRAM device and the manufacturing method thereof proposed in some embodiments of the present invention, the thinned second dielectric material layer 252 has different thicknesses H3 and H4. The thickness H4 is less than the thickness H3, and the position of the thickness H4 corresponds to the position of the particle 501, thereby further preventing the second conductive material layer 243 from being exposed. In some examples, the thickness H4 is greater than or equal to 0 nm. Therefore, the second dielectric material layer 252 of the present invention can provide a buffer space for the uneven film layer, so as to avoid the defect of the bit line structure 24B having a poor profile or even a broken line.

[0136] Reference Fig.15 According to some embodiments, after forming the second dielectric material layer 252 , a third dielectric material layer 253 is formed on the second dielectric material layer 252 .

[0137] When a DRAM device is actually manufactured, there may be portions with particles 501 and portions without particles 501 on the same bit line (ie, in a stacked structure). Fig.16 The cross sections of different bit lines are shown, including a position of one bit line containing particles 501 and a position of another bit line not containing particles, so as to illustrate how the mask structure of the embodiment provides a buffer space for particles 501 that may exist in the film layer.

[0138] In some embodiments, the stacked structure of the DRAM device of the present invention may include different mask structures. Fig.16 As shown, the DRAM device 10' may include a first stacked structure 23A made of a flat film layer, and a second stacked structure 23B made of a partially protruding film layer, wherein the second stacked structure 23B has particles 501. In detail, the first stacked structure 23A includes a first bit line structure 24A and a first mask structure 25A located above the first bit line structure 24A. The first mask structure 25A includes a first dielectric layer 251A' (e.g., a nitride layer), a second dielectric layer 252A' (e.g., an oxide layer), and a third dielectric layer 253A' (e.g., a nitride layer). Furthermore, the second stacked structure 23B includes a second bit line structure 24B and a second mask structure 25B located above the second bit line structure 24B. The second mask structure 25B includes a fourth dielectric layer 251B' (e.g., a nitride layer), a fifth dielectric layer 252B' (e.g., an oxide layer), and a sixth dielectric layer 253B' (e.g., a nitride layer). The first bit line structure 24A and the second bit line structure 24B respectively include a second conductive layer 243', a first conductive layer 242' and a semiconductor material layer 241', and the structural difference between them is that each film layer of the second bit line structure 24B has a relatively uneven surface, while each film layer of the first bit line structure 24A has a relatively flat surface.

[0139] In some examples, the thickness of the fifth dielectric layer 252B' in the second mask structure 25B may be different from the thickness of the second dielectric layer 252A' of the first mask structure 25 A. For example, the thickness of the fifth dielectric layer 252B' may be less than the thickness of the second dielectric layer 252A'.

[0140] Furthermore, in an embodiment not shown, the first mask structure 25A and the second mask structure 25B may have dielectric layer combinations with different numbers of dielectric material layers. For example, the second mask structure 25B located above the particle 501 may only have the fourth dielectric layer 251B' and the sixth dielectric layer 253B', but no fifth dielectric layer 252B' (i.e., thickness H4=0).

[0141] Based on the above, in some embodiments of the present invention, regardless of whether the dielectric layer combination of the mask structure has the same oxide layer thickness or the same number of dielectric material layers, according to the manufacturing method proposed in the embodiment of the present invention, the second dielectric material layer 252 in the mask material stack layer 250 can provide a buffer space for the unevenness of the film layer, thereby forming a bit line structure 24 with a good profile.

[0142] In summary, according to some embodiments of the present invention, the DRAM device and the manufacturing method thereof can reduce the parasitic capacitance between the landing pad of the capacitor contact structure and the laterally adjacent bit line structure by setting a mask structure composed of different dielectric material layers (such as nitride layer-oxide layer-nitride layer) above each bit line structure, thereby improving the electrical performance and yield of the manufactured DRAM device. Furthermore, according to the manufacturing method proposed in some embodiments, the problem of poor profile or even broken line of the subsequent bit line structure caused by the defect of uneven film layer (such as contaminants or particles of the film layer itself) in the traditional process can be solved, thereby forming a bit line structure with a good profile and improving the yield of the manufactured DRAM device. Furthermore, according to the manufacturing method proposed in the present invention, its manufacturing method is simple, and is compatible with the existing process and suitable for mass production. For example, the manufacturing method proposed in the present invention can achieve the above-mentioned effect of reducing parasitic capacitance and forming a good bit line structure without affecting the process of the original components of the peripheral area A2 (such as without changing the conditions of the ring injection of the MOS structure), thereby shortening the development time. Therefore, the DRAM device and the manufacturing method thereof proposed in the present invention can achieve the above-mentioned benefits without increasing the production cost.

[0143] The present invention is suitable for manufacturing miniaturized DRAM devices to increase the total number of chips on a wafer. Therefore, the present invention can reduce the production cost and energy consumption of manufacturing a single IC, and reduce the production energy consumption of subsequent packaging, thereby reducing carbon emissions in the production process of each unit DRAM device. In addition, since the yield rate of the DRAM device and the manufacturing method of the present invention is improved, the waste of the manufacturing process is reduced, and the present invention provides a green semiconductor technology.

Claims

1. A dynamic random access memory device, characterized in that: include: a substrate having an active region; A stacking structure is located above the substrate and extends along a first direction, the stacking structure comprising: a bit line structure located above the substrate and electrically connected to the active region; a mask structure located on the bit line structure, wherein the mask structure comprises a first dielectric layer, a second dielectric layer and a third dielectric layer sequentially formed on the bit line structure and stacked along a second direction, wherein a dielectric constant of the second dielectric layer is smaller than dielectric constants of the first dielectric layer and the third dielectric layer; and A spacer structure is located on the sidewalls of the bit line structure and the mask structure; and A capacitor contact structure is located on the substrate and is laterally separated from the stack structure, wherein the capacitor contact structure is electrically connected to the active region.

2. The dynamic random access memory device according to claim 1, wherein: The first dielectric layer and the third dielectric layer include nitride, respectively, and the second dielectric layer includes oxide.

3. The dynamic random access memory device according to claim 1, wherein: The capacitive contact structure comprises: a node contact plug located at one side of the stack structure and contacting the active region; and A landing pad is located on the node contact plug, wherein a bottom surface of a lower portion of the landing pad is not lower than a bottom surface of the second dielectric layer, and an upper portion of the landing pad is located on the third dielectric layer.

4. The dynamic random access memory device according to claim 3, wherein: The bottom surface of the lower portion of the landing pad is at a height between the top surface and the bottom surface of the second dielectric layer.

5. The dynamic random access memory device according to claim 3, wherein: A top surface of the node contact plug is lower than a top surface of the second dielectric layer of the mask structure.

6. The dynamic random access memory device according to claim 1, wherein: The bit line structure includes: a semiconductor material layer located above the substrate; a first conductive layer located above the semiconductor material layer; and a second conductive layer, located on the first conductive layer, and having a resistance value lower than that of the semiconductor material layer; The second conductive layer and the second dielectric layer are separated by the first dielectric layer.

7. The dynamic random access memory device according to claim 1, wherein: The stack structure includes a first portion and a second portion, and the mask structure of the second portion and the mask structure of the first portion have different dielectric layer combinations.

8. The dynamic random access memory device according to claim 7, wherein: The stack structure includes a first portion and a second portion, and the second dielectric layer of the mask structure of the second portion and the second dielectric layer of the mask structure of the first portion have different thicknesses.

9. The dynamic random access memory device according to claim 1, wherein: The thickness of the second dielectric layer of the mask structure is equal to or less than the thickness of the third dielectric layer.

10. A method for manufacturing a dynamic random access memory device, characterized in that: include: Providing a substrate having an active region; forming a bit line material layer above the substrate; forming a mask material stacking layer above the bit line material layer; The mask material stack layer and the bit line material layer are patterned to form a stack structure extending along a first direction, wherein the stack structure comprises: a bit line structure located above the substrate and electrically connected to the active region; and a mask structure located on the bit line structure, wherein the mask structure comprises a first dielectric layer, a second dielectric layer and a third dielectric layer sequentially formed on the bit line structure and stacked along a second direction, wherein a dielectric constant of the second dielectric layer is smaller than dielectric constants of the first dielectric layer and the third dielectric layer; and A spacer structure is located on the sidewalls of the bit line structure and the mask structure; and A capacitor contact structure is formed above the substrate, and the capacitor contact structure and the stack structure are laterally separated from each other, wherein the capacitor contact structure is electrically connected to the active region.

11. The method for manufacturing a dynamic random access memory device according to claim 10, wherein: Forming the mask material stack layer above the bit line material layer includes: forming a first dielectric material layer on the bit line material layer, wherein the first dielectric material layer comprises nitride; forming a second dielectric material layer on the first dielectric material layer, wherein the second dielectric material layer comprises oxide; Thinning the second dielectric material layer so that the thinned second dielectric material layer has a flat top surface; A third dielectric material layer is formed on the thinned second dielectric material layer, wherein the third dielectric material layer includes nitride.

12. The method for manufacturing a dynamic random access memory device according to claim 11, wherein: Thinning the second dielectric material layer includes: Thinning the second dielectric material layer to a first thickness by a grinding process; The second dielectric material layer is thinned to a second thickness by dry etching, Wherein, the first thickness is greater than the second thickness.

13. The method for manufacturing a dynamic random access memory device according to claim 10, wherein: Forming the capacitor contact structure includes: forming a node contact plug adjacent to a lower portion of the spacer structure, wherein a bottom of the node contact plug contacts the active region and a top surface of the node contact plug is lower than a top surface of the stack structure; and A landing pad is formed on the node contact plug, wherein the landing pad is adjacent to an upper portion of the spacing structure, a bottom surface of a lower portion of the landing pad is not lower than a bottom surface of the second dielectric layer, and an upper portion of the landing pad is located on the third dielectric layer.

14. The method for manufacturing a dynamic random access memory device according to claim 13, wherein: The bottom surface of the lower portion of the landing pad is at a height between the top surface and the bottom surface of the second dielectric layer.

15. The method for manufacturing a dynamic random access memory device according to claim 13, wherein: The top surface of the node contact plug is lower than a top surface of the second dielectric layer.

16. The method for manufacturing a dynamic random access memory device according to claim 10, wherein: The thickness of the second dielectric layer of the mask structure is equal to or less than the thickness of the third dielectric layer.

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