Dynamic random access memory architecture and forming method thereof

Abstract

A dynamic random access memory architecture and a forming method thereof, the forming method comprising: forming a substrate having a first surface and a second surface opposite to each other, the substrate comprising a plurality of active regions, the active regions comprising a plurality of word line regions; forming a word line gate groove in each word line area; two word line gate structures which are separated from each other are formed in each word line gate groove; forming a plurality of bit line layers on the first surface; injecting source and drain ions into the substrate from the second surface to the first surface, and forming a second source and drain doping layer in each active region; and forming a plurality of capacitor structures on the second surface. The manufacturing process for forming the capacitor structure is put at the last, so that a high-temperature process can be normally adopted in the manufacturing process before the capacitor structure is formed, and the capacitor structure cannot be damaged. The second source-drain doping layer is formed by injecting source-drain ions from the second surface to the first surface, so that the distribution uniformity of the source-drain ions in the second source-drain doping layer can be effectively improved, and the performance of the transistor is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a dynamic random access storage architecture and a forming method thereof. Background Art

[0002] With the rapid development of technology today, semiconductor memory is widely used in electronic devices. Dynamic random access memory (DRAM) is a type of volatile memory. For applications that store large amounts of data, DRAM is the most commonly used solution.

[0003] Typically, a dynamic random access memory is composed of a plurality of memory cells, each of which is mainly composed of a transistor and a capacitor controlled by the transistor, and each of the memory cells is electrically connected to each other through a word line and a bit line.

[0004] However, the existing dynamic random access memory architecture still has many problems. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a dynamic random access memory architecture and a forming method thereof, so as to ensure the normal use of high temperature processes and improve the performance of transistors.

[0006] To solve the above problems, the technical solution of the present invention provides a method for forming a dynamic random access memory architecture, comprising: forming a substrate, the substrate having a first surface and a second surface opposite to each other, the substrate comprising a plurality of active areas that are separate from each other and parallel to a first direction, and the plurality of active areas are arranged along a second direction, a first isolation trench is provided between adjacent active areas, the first isolation trench extends along the first direction, the first direction is perpendicular to the second direction, each of the active areas comprises a plurality of word line areas and isolation areas that are separate from each other, and the word line areas and the isolation areas in each of the active areas are arranged at intervals along the first direction; forming a first isolation structure in the first isolation trench; forming a first source-drain doping layer in each of the active areas, the first surface exposing the first source-drain doping layer; forming a word line gate trench in each of the word line areas, and forming a second isolation trench in each of the isolation areas, the word line gate trench and the second isolation trench extending from the first surface to the second surface, and the word line gate trench and the second isolation trench penetrating the active area along the second direction; forming a second isolation structure in each of the second isolation trenches structure; forming an initial word line gate structure in each of the word line gate grooves; after forming the second isolation structure and the initial word line gate structure, forming a plurality of bit line layers parallel to the first direction on the first surface, each of the bit line layers being electrically connected to a plurality of the first source-drain doped layers in a corresponding one of the active regions; after forming the bit line layers, performing a first thinning process on the substrate from the second surface to the first surface; after the first thinning process, etching a portion of the initial word line gate structure from the first surface to the second surface, so that the initial word line gate structure forms two mutually independent word line gate structures, and the two word line gate structures are respectively located on the opposite side walls of the word line gate groove along the first direction; after forming the word line gate structure, performing a source-drain ion implantation process on the substrate from the second surface to the first surface, forming a second source-drain doped layer in each of the active regions, and exposing the second source-drain doped layer on the second surface; after forming the second source-drain doped layer, forming a plurality of capacitor structures on the second surface, each of the capacitor structures being electrically connected to a corresponding one of the second source-drain doped layers.

[0007] Optionally, the second isolation structure is a conductive structure.

[0008] Optionally, the material of the conductive structure includes: titanium nitride.

[0009] Optionally, the second isolation structure is an insulating structure.

[0010] Optionally, the material of the insulating structure includes: silicon oxide or air.

[0011] Optionally, the method for forming the initial word line gate structure in each of the word line gate grooves includes: forming a word line gate material layer on the sidewalls and bottom surface of the word line gate groove; removing a portion of the word line gate material layer located on the sidewalls of the word line gate groove to form a first cut-off opening and a second cut-off opening, so that the word line gate material layer forms the initial word line gate structure.

[0012] Optionally, the first cut-off opening and the second cut-off opening are respectively located in the initial word line gate structure on the side walls of the word line gate groove arranged opposite to each other along the first direction, and the first cut-off opening and the second cut-off opening are also respectively located on both sides of the initial word line gate structure along the second direction.

[0013] Optionally, after forming the bit line layer and before performing the first thinning process, the method further includes: forming a bit line isolation structure between adjacent bit line layers.

[0014] Optionally, the bit line isolation structure is a cavity structure.

[0015] Optionally, the depth of the word line gate trench is less than the depth of the first isolation trench; and the depth of the second isolation trench is less than the depth of the first isolation trench.

[0016] Optionally, the first thinning process is performed until the first isolation structure is exposed.

[0017] Optionally, after forming the word line gate structure and before forming the second source-drain doping layer, the method further includes: performing a second thinning process on the substrate from the second surface toward the first surface until at least the second isolation structure is exposed.

[0018] Optionally, the depth of the word line gate trench is equal to the depth of the first isolation trench; and the depth of the second isolation trench is equal to the depth of the first isolation trench.

[0019] Optionally, the first thinning process is performed until at least the first isolation structure, the second isolation structure and the initial word line gate structure are exposed.

[0020] Optionally, after forming the bit line layer and before performing the first thinning process, it also includes: providing a logic circuit wafer; bonding the logic circuit wafer to the substrate facing the first surface, the logic circuit wafer being electrically connected to the bit line layer and the initial word line gate structure respectively.

[0021] Optionally, after the initial word line gate structure forms two separate word line gate structures, the logic circuit wafer is electrically connected to the word line gate structure.

[0022] Optionally, the second isolation structure is a conductive structure, and the logic circuit wafer is also electrically connected to the second isolation structure.

[0023] Optionally, along the first direction, the first conductive plug used to electrically connect the second isolation structure and the logic circuit wafer has a first central axis, and the second conductive plug used to electrically connect the initial word line gate structure and the logic circuit wafer has a second central axis, and the first central axis coincides with the second central axis.

[0024] Optionally, along the first direction, the first conductive plug used to electrically connect the second isolation structure and the logic circuit wafer has a first central axis, and the second conductive plug used to electrically connect the initial word line gate structure and the logic circuit wafer has a second central axis, and the first central axis does not coincide with the second central axis.

[0025] Optionally, the process of etching a portion of the initial word line gate structure from the first surface to the second surface also includes: etching a portion of the second isolation structure from the first surface to the second surface, so that the projection of the second isolation structure along the first direction is within the projection range of the word line gate structure along the first direction.

[0026] Correspondingly, the technical solution of the present invention also provides a dynamic random access storage architecture, which is formed by the formation method described in any one of the above technical solutions, and the dynamic random access storage architecture includes: a substrate, the substrate has a first surface and a second surface opposite to each other, the substrate includes a plurality of active areas that are separate from each other and parallel to a first direction, and the plurality of active areas are arranged along a second direction, and a first isolation trench is provided between adjacent active areas, the first isolation trench extends along the first direction, the first direction is perpendicular to the second direction, each of the active areas includes a plurality of word line areas and isolation areas that are separate from each other, and the word line areas and the isolation areas in each of the active areas are arranged at intervals along the first direction; a first isolation structure located in the first isolation trench; a first source-drain doped layer located in each of the active areas, the first surface exposing the first source-drain doped layer; a word line gate trench located in each of the word line areas, the word line gate trench extending along the first direction ... second direction, the word line gate trench extending along the second direction, the word line gate trench extending along the second direction, A word line gate groove extends from the first surface to the second surface, and the word line gate groove penetrates the active area along the second direction; a second isolation groove located in each of the isolation areas, the second isolation groove extends from the first surface to the second surface, and the second isolation groove penetrates the active area along the second direction; a second isolation structure located in each of the second isolation grooves; two mutually independent word line gate structures located in each of the word line gate grooves, the two word line gate structures are respectively located on opposite side walls of the word line gate groove along the first direction; a plurality of bit line layers located on the first surface and parallel to the first direction, each of the bit line layers is electrically connected to a plurality of the first source and drain doping layers in a corresponding one of the active areas; a second source and drain doping layer located in each of the active areas, the second surface exposing the second source and drain doping layer; a plurality of capacitor structures located on the second surface, each of the capacitor structures is electrically connected to a corresponding one of the second source and drain doping layers.

[0027] Optionally, the second isolation structure is a conductive structure.

[0028] Optionally, the material of the conductive structure includes: titanium nitride.

[0029] Optionally, the second isolation structure is an insulating structure.

[0030] Optionally, the material of the insulating structure includes: silicon oxide or air.

[0031] Optionally, it also includes: a bit line isolation structure located between adjacent bit line layers.

[0032] Optionally, the bit line isolation structure is a cavity structure.

[0033] Optionally, it further includes: a logic circuit wafer, wherein the logic circuit wafer is bonded to the substrate toward the first surface, and the logic circuit wafer is electrically connected to the bit line layer and the word line gate structure respectively.

[0034] Optionally, the second isolation structure is a conductive structure, and the logic circuit wafer is also electrically connected to the second isolation structure.

[0035] Optionally, along the first direction, the first conductive plug used to electrically connect the second isolation structure and the logic circuit wafer has a first central axis, and the second conductive plug used to electrically connect the word line gate structure and the logic circuit wafer has a second central axis, and the first central axis coincides with the second central axis.

[0036] Optionally, along the first direction, the first conductive plug used to electrically connect the second isolation structure and the logic circuit wafer has a first central axis, and the second conductive plug used to electrically connect the word line gate structure and the logic circuit wafer has a second central axis, and the first central axis does not coincide with the second central axis.

[0037] Optionally, the two separate word line gate structures are also located on opposite side walls of the word line gate trench along the second direction; and the two second conductive plugs respectively electrically connected to the two separate word line gate structures are distributed on opposite sides of the word line gate trench along the second direction.

[0038] Optionally, a projection of the second isolation structure along the first direction is located within a projection range of the word line gate structure along the first direction.

[0039] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0040] In the method for forming a dynamic random access memory architecture of the technical solution of the present invention, by placing the process of forming the capacitor structure at the end, it is possible to ensure that a high temperature process is normally used in the process before forming the capacitor structure without causing damage to the capacitor structure. In addition, the second source-drain doped layer is formed by injecting source-drain ions from the second surface to the first surface, which can effectively improve the distribution uniformity of source-drain ions in the second source-drain doped layer, thereby effectively improving the performance of the transistor.

[0041] Furthermore, the second isolation structure is a conductive structure. By applying a negative voltage to the second isolation structure, adjacent memory cells arranged along the first direction can be effectively isolated, thereby reducing the impact of the row hammer effect on the memory cells.

[0042] Furthermore, the first cut-off opening and the second cut-off opening are respectively located in the initial word line gate structure on the side walls of the word line gate trench arranged oppositely along the first direction, and the first cut-off opening and the second cut-off opening are also respectively located in the two sides of the initial word line gate structure along the second direction. By retaining part of the initial word line gate structure on the opposite side walls of the word line gate trench along the second direction, the second conductive plugs subsequently formed on the opposite sides of the initial word line gate structure along the second direction can make more contact with the initial word line gate structure, thereby improving the electrical contact performance between the second conductive plug and the word line gate structure subsequently formed by the initial word line gate structure.

[0043] Furthermore, the bit line isolation structure is a cavity structure. The cavity structure has a strong electrical isolation effect, thereby effectively reducing the crosstalk between adjacent bit line layers.

[0044] Furthermore, the depths of the word line gate trench and the second isolation trench are less than the depth of the first isolation trench. After the first thinning process, the initial word line gate structure in the word line gate trench will not be exposed, thereby effectively reducing the process risk of metal exposure.

[0045] Furthermore, along the first direction, the first conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a first central axis, and the second conductive plug for electrically connecting the initial word line grid structure and the logic circuit wafer has a second central axis, and the first central axis does not coincide with the second central axis. By staggering the first conductive plug and the second conductive plug along the first direction, the exposure window for forming the first conductive plug and the second conductive plug can be further increased, thereby increasing the volume of the first conductive plug and the second conductive plug to improve the electrical conduction performance.

[0046] Furthermore, the process of etching part of the initial word line gate structure from the first surface to the second surface also includes: etching part of the second isolation structure from the first surface to the second surface, so that the projection of the second isolation structure along the first direction is within the projection range of the word line gate structure along the first direction, thereby reducing the influence of the second isolation structure on adjacent storage cells when a negative voltage is applied.

[0047] In the dynamic random access memory architecture of the technical solution of the present invention, by placing the process of forming the capacitor structure at the end, it is possible to ensure that a high temperature process is normally used in the process before forming the capacitor structure without causing damage to the capacitor structure. In addition, the second source-drain doped layer is formed by injecting source-drain ions from the second surface to the first surface, which can effectively improve the distribution uniformity of source-drain ions in the second source-drain doped layer, thereby effectively improving the performance of the transistor.

[0048] Furthermore, the second isolation structure is a conductive structure. By applying a negative voltage to the second isolation structure, adjacent memory cells arranged along the first direction can be effectively isolated, thereby reducing the impact of the row hammer effect on the memory cells.

[0049] Furthermore, the bit line isolation structure is a cavity structure. The cavity structure has a strong electrical isolation effect, thereby effectively reducing the crosstalk between adjacent bit line layers.

[0050] Furthermore, along the first direction, the first conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a first central axis, and the second conductive plug for electrically connecting the initial word line grid structure and the logic circuit wafer has a second central axis, and the first central axis does not coincide with the second central axis. By staggering the first conductive plug and the second conductive plug along the first direction, the exposure window for forming the first conductive plug and the second conductive plug can be further increased, thereby increasing the volume of the first conductive plug and the second conductive plug to improve the electrical conduction performance.

[0051] Furthermore, the two mutually independent word line gate structures are also located on the opposite side walls of the word line gate trench along the second direction; and the two second conductive plugs electrically connected to the two mutually independent word line gate structures are distributed on opposite sides of the word line gate trench along the second direction, thereby increasing the contact area between the second conductive plug and the corresponding word line gate structure, and improving the electrical contact performance between the second conductive plug and the corresponding word line gate structure.

[0052] Furthermore, the projection of the second isolation structure along the first direction is located within the projection range of the word line gate structure along the first direction, thereby reducing the influence of the second isolation structure on adjacent storage cells when a negative voltage is applied. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figures 1 to 39 It is a schematic structural diagram of each step of a method for forming a dynamic random access memory architecture according to an embodiment of the present invention;

[0054] Fig.40A schematic diagram of the structure of a pillar capacitor in a dynamic random access memory architecture according to an embodiment of the present invention;

[0055] Fig.41 A schematic diagram of the structure of a cup capacitor in a dynamic random access memory architecture according to an embodiment of the present invention;

[0056] Fig.42 A schematic diagram of the structure of a cylinder capacitor in a dynamic random access memory architecture according to an embodiment of the present invention;

[0057] Fig.43 A schematic diagram of the distribution of first conductive plugs and second conductive plugs in a dynamic random access memory architecture according to another embodiment of the present invention. DETAILED DESCRIPTION

[0058] As described in the background art, the existing dynamic random access memory architecture still has many problems, which will be described in detail below.

[0059] The dynamic random access memory architecture in the prior art is to first make the capacitor structure and then do the back process, which means that high-temperature processes cannot be used in the back process, otherwise it will affect the high-K dielectric layer in the capacitor structure, thereby causing the capacitor structure to fail. In addition, the back source and drain doping layer in the dynamic random access memory architecture is formed by ion implantation from the front side, which easily causes poor uniformity of ion distribution in the transistor and reduces the performance of the transistor.

[0060] On this basis, the present invention provides a dynamic random access memory architecture and a method for forming the same. By placing the process of forming the capacitor structure at the end, it is possible to ensure that a high temperature process is normally used in the process before forming the capacitor structure without causing damage to the capacitor structure. In addition, the second source-drain doped layer is formed by injecting source-drain ions from the second surface to the first surface, which can effectively improve the distribution uniformity of the source-drain ions in the second source-drain doped layer, thereby effectively improving the performance of the transistor.

[0061] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0062] Figures 1 to 39 It is a schematic structural diagram of each step of a method for forming a dynamic random access memory architecture according to an embodiment of the present invention; Fig.40 A schematic diagram of the structure of a pillar capacitor in a dynamic random access memory architecture according to an embodiment of the present invention; Fig.41 A schematic diagram of the structure of a cup capacitor in a dynamic random access memory architecture according to an embodiment of the present invention; Fig.42A schematic diagram of the structure of a cylinder capacitor in a dynamic random access memory architecture according to an embodiment of the present invention; Fig.43 A schematic diagram of the distribution of first conductive plugs and second conductive plugs in a dynamic random access memory architecture according to another embodiment of the present invention.

[0063] Please refer to Figures 1 to 3 , Figure 2 yes Figure 1 Schematic diagram of the cross section along line AA, Figure 3 yes Figure 1 A cross-sectional schematic diagram along line BB in FIG. 1 is a schematic diagram showing a substrate 100 formed, wherein the substrate 100 has a first surface 100 a and a second surface 100 b opposite to each other, wherein the substrate 100 includes a plurality of active regions 101 separated from each other and parallel to a first direction X, and wherein the plurality of active regions 101 are arranged along a second direction Y, wherein a first isolation trench 102 is provided between adjacent active regions 101, wherein the first isolation trench 102 extends along the first direction X, and the first direction X is perpendicular to the second direction Y, wherein each active region 101 includes a plurality of word line regions 1011 and isolation regions 1012 separated from each other, and wherein the word line regions 1011 and the isolation regions 1012 in each active region 101 are arranged at intervals along the first direction X.

[0064] In this embodiment, the method for forming the substrate 100 includes: providing an initial substrate (not shown); forming a first patterned layer (not shown) on the initial substrate; etching the initial substrate using the first patterned layer as a mask to form a plurality of first isolation trenches 102, and forming the substrate 100 from the initial substrate, wherein the active area 101 is formed between adjacent first isolation trenches 102.

[0065] In this embodiment, the substrate 100 is made of silicon.

[0066] In other embodiments, the material of the substrate 100 may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0067] It should be noted that, in this embodiment, the first surface 100a is the front side of the memory unit in the final dynamic random access memory architecture, and the second surface 100b is the back side of the memory unit in the final dynamic random access memory architecture.

[0068] Please refer to Figure 4 and Figure 5 , Figure 5 yes Figure 4 In the cross-sectional diagram along line CC, a first isolation structure 103 is formed in the first isolation trench 102 .

[0069] In this embodiment, the method for forming the first isolation structure 103 includes: depositing an isolation material layer (not shown), the isolation material layer filling the first isolation trench 102 and being located on the first surface 100a, and planarizing the isolation material layer until the first surface 100a of the substrate 100 is exposed, thereby forming the first isolation structure 103.

[0070] In this embodiment, the first isolation structure 103 is made of silicon oxide.

[0071] Please refer to Figure 6 , Figure 6 and Figure 5 In accordance with the viewing direction, after forming the first isolation structure 103 , a first source-drain doped layer 104 is formed in each of the active regions 101 , and the first surface 100 a exposes the first source-drain doped layer 104 .

[0072] In this embodiment, the method for forming the first source-drain doped layer 104 includes: implanting source-drain ions into the substrate 100 from the first surface 100a to the second surface 100b, and annealing the implanted source-drain ions to form the first source-drain doped layer 104 in the active area 101.

[0073] Please refer to Figures 7 to 9 , Figure 8 yes Figure 7 Schematic diagram of the cross section along line DD, Fig. 9 yes Figure 7 In the schematic cross-sectional view along line EE, after forming the first source-drain doping layer 104, a word line gate trench (not marked) is formed in each of the word line regions 1011, and a second isolation trench (not marked) is formed in each of the isolation regions 1012, the word line gate trench and the second isolation trench extend from the first surface 100a to the second surface 100b, and the word line gate trench and the second isolation trench penetrate the active region 101 along the second direction Y.

[0074] In this embodiment, the formation of the word line gate trench and the second isolation trench includes: forming a second patterned layer (not shown) on the substrate 100; etching the word line region 1011 and the first isolation structure 103 of the active area 101 using the second patterned layer as a mask to form the word line gate trench, and etching the isolation region 1012 and the first isolation structure 103 of the active area 101 using the second patterned layer as a mask to form the second isolation trench.

[0075] In this embodiment, the depth of the word line gate trench is less than the depth of the first isolation trench 102 ; and the depth of the second isolation trench is less than the depth of the first isolation trench 102 .

[0076] In other embodiments, the depth of the word line gate trench may also be equal to the depth of the first isolation trench 102 ; the depth of the second isolation trench may also be equal to the depth of the first isolation trench 102 .

[0077] Please continue to refer to Figures 7 to 9 After forming the word line gate trench and the second isolation trench, the word line gate trench and the second isolation trench are fully filled with a sacrificial layer 105 .

[0078] It should be noted that in this embodiment, since different device structures are formed in the word line gate trench and the second isolation trench respectively in the subsequent process, the word line gate trench and the second isolation trench are first filled with the sacrificial layer 105, and in the subsequent process, the sacrificial layer 105 in the corresponding trench is removed step by step to form the required device structure.

[0079] In this embodiment, the sacrificial layer 105 is made of spin-on carbon.

[0080] Please refer to Figures 10 to 12 , Fig.11 yes Fig.10 Schematic diagram of the cross section along line FF, Fig.12 yes Fig.10 In the cross-sectional diagram along line GG, after the sacrificial layer 105 is formed, a second isolation structure 106 is formed in each of the second isolation trenches.

[0081] It should be noted that, in this embodiment, before forming the second isolation structure 106 , the sacrificial layer 105 filled in the second isolation trench needs to be removed.

[0082] In this embodiment, the second isolation structure 106 is a conductive structure, and the material of the conductive structure is titanium nitride. Since the second isolation structure 106 is a conductive structure, a negative voltage can be applied to the second isolation structure 106, so that the second isolation structure 106 can effectively isolate adjacent memory cells arranged along the first direction X, thereby reducing the impact of the row hammer effect on the memory cells.

[0083] It should be noted that, in this embodiment, before forming the second isolation structure 106, a dense oxide layer (not shown) is formed on the surface of the second isolation trench to repair the surface of the second isolation trench, and the formed second isolation structure 106 does not fill the second isolation trench completely. After forming the second isolation structure 106, a protective layer 107 is formed on the second isolation structure 106 to fill the second isolation trench completely. The purpose of the second isolation structure 106 not filling the second isolation trench completely is to reduce the height of the second isolation structure 106, so that the height of the second isolation structure 106 facing the first surface 100a cannot be higher than the height of the subsequently formed initial word line gate structure facing the first surface 100a, so as to ensure that the projection of the finally formed second isolation structure 106 along the first direction X is located within the projection range of the finally formed word line gate structure along the first direction X.

[0084] In other embodiments, the second isolation structure 106 may also be an insulating structure, and the material of the insulating structure may be silicon oxide or air. When the insulating structure is silicon oxide, it is only necessary to deposit silicon oxide material to fill the second isolation trench; when the insulating structure is air, by adjusting the parameters of the deposition process, the deposited material seals the opening of the second isolation trench, and the interior of the second isolation trench is air. The insulating isolation effect of air is relatively strong, and can effectively improve the isolation effect of the second isolation structure 106.

[0085] Please refer to Figures 13 to 15 , Fig.13 is a top view omitting the insulating material in the word line gate trench, Fig.14 yes Fig.13 Schematic diagram of the cross section along the HH line, Fig.15 yes Fig.13 In the schematic cross-sectional view along line II, after the second isolation structure 106 is formed, an initial word line gate structure 108 is formed in each of the word line gate trenches.

[0086] It should be noted that, in this embodiment, before forming the initial word line gate structure 108, the sacrificial layer 105 filled in the word line gate trench needs to be removed, and the word line gate trench needs to be extended to increase the volume of the word line gate trench.

[0087] Please refer to Fig.16 and Fig.17In the present embodiment, the method for forming the initial word line gate structure 108 in each of the word line gate grooves includes: forming a word line gate material layer 109 on the sidewalls and bottom surface of the word line gate groove; removing a portion of the word line gate material layer 109 located on the sidewalls of the word line gate groove to form a first cut-off opening 110 and a second cut-off opening 111, so that the word line gate material layer 109 forms the initial word line gate structure 108.

[0088] Please continue to refer to Fig.16 and Fig.17 In the present embodiment, the first cut-off opening 110 and the second cut-off opening 111 are respectively located in the initial word line gate structure 108 on the side walls of the word line gate grooves that are arranged opposite to each other along the first direction X, and the first cut-off opening 110 and the second cut-off opening 111 are also respectively located in both sides of the initial word line gate structure 108 along the second direction Y.

[0089] By retaining a portion of the initial word line gate structure 108 on the opposite side walls of the word line gate groove along the second direction Y, the second conductive plugs subsequently formed on the opposite sides of the initial word line gate structure 108 along the second direction Y can make more contact with the initial word line gate structure 108, thereby improving the electrical contact performance between the second conductive plugs and the word line gate structure subsequently formed by the initial word line gate structure 108.

[0090] It should be noted that, in this embodiment, before forming the initial word line gate structure 108, a dense oxide layer (not shown) is formed on the surface of the word line gate groove to repair the surface of the word line gate groove. Then, a word line gate material layer 109 is formed on the sidewall and bottom surface of the word line gate groove, wherein the word line gate material layer 109 includes a word line gate dielectric material layer (not shown) and a word line gate material layer (not shown). After forming the word line gate material layer 109, an insulating material is deposited in the word line gate groove to fill the word line gate groove. Then, the insulating material above the position where the word line gate material layer 109 needs to be cut is removed, and then the first cut-off opening 110 and the second cut-off opening 111 are formed, so that the word line gate material layer 109 is formed into the initial word line gate structure 108. After forming the initial word line gate structure 108, an insulating material is deposited again to fill the word line gate groove.

[0091] In this embodiment, the word line gate dielectric material layer is made of silicon oxide, and the word line gate material layer 109 is made of titanium nitride or tungsten.

[0092] In this embodiment, the second isolation structure 106 is formed first and then the initial word line gate structure 108 is formed.

[0093] In other embodiments, the initial word line gate structure 108 may be formed first and then the second isolation structure 106 may be formed.

[0094] Please refer to Figures 18 to 20 , Fig.19 yes Fig.18 Schematic diagram of the cross section along the JJ line. Fig. 20 yes Fig.18 In the schematic cross-sectional view along line KK, after the initial word line gate structure 108 is formed, a plurality of bit line layers 112 parallel to the first direction X are formed on the first surface 100a, and each of the bit line layers 112 is electrically connected to a plurality of the first source-drain doped layers 104 in a corresponding active area 101.

[0095] In this embodiment, before forming the bit line layer 112, the first source-drain doped layer 104 exposed on the first surface 100a is metallized so that a portion of the first source-drain doped layer 104 forms a metal silicide layer 113. By forming the metal silicide layer 113, the contact resistance between the bit line layer 112 and the first source-drain doped layer 104 can be effectively reduced.

[0096] In this embodiment, the bit line layer 112 is a double-layer structure, and includes a first metal layer (not labeled) and a second metal layer (not labeled) located on the first metal layer. The first metal layer is made of titanium nitride, and the second metal layer is made of tungsten.

[0097] Please continue to refer to Figures 18 to 20 After the bit line layers 112 are formed, a bit line isolation structure 114 is formed between adjacent bit line layers 112 .

[0098] In this embodiment, the bit line isolation structure 114 is a cavity structure. The specific formation process is to adjust the parameters of the deposition process so that the deposited silicon oxide material seals the opening between the adjacent bit line layers 112, thereby forming a cavity structure between the adjacent bit line layers 112. The cavity structure has a strong electrical isolation effect, thereby effectively reducing the crosstalk between the adjacent bit line layers 112.

[0099] In other embodiments, the deposited silicon oxide material may be directly used to fill the gap between adjacent bit line layers 112 to serve as the bit line isolation structure 114 .

[0100] Please refer to Figure 21 to Figure 25 , Fig.21 This is a top view of the dynamic random access memory architecture without the logic circuit wafer. Fig. 22 yes Fig.21 Schematic diagram of the cross section along line LL, Fig.23 yes Fig.21 Schematic diagram of the cross section along the MM line, Fig.24 yes Fig.21 Schematic diagram of the cross section along the NN line, Fig.25 yes Fig.21 In the cross-sectional diagram along line OO, after the bit line layer 112 is formed, a logic circuit wafer 200 is provided; the logic circuit wafer 200 is bonded to the substrate 100 toward the first surface 100a, and the logic circuit wafer 200 is electrically connected to the bit line layer 112 and the initial word line gate structure 108, respectively.

[0101] It should be noted that, in this embodiment, the logic circuit wafer 200 is bonded to logically control operations such as reading, writing and refreshing of each storage unit.

[0102] In this embodiment, the second isolation structure 106 is a conductive structure, the logic circuit wafer 200 is also electrically connected to the second isolation structure 106 , and the logic circuit wafer 200 also includes an operation of applying a negative voltage to the second isolation structure 106 .

[0103] In this embodiment, along the first direction X, the first conductive plug 115 for electrically connecting the second isolation structure 106 and the logic circuit wafer 200 has a first central axis S1, and the second conductive plug 116 for electrically connecting the initial word line gate structure 108 and the logic circuit wafer 200 has a second central axis, and the first central axis S1 coincides with the second central axis S2.

[0104] It should be noted that, in this embodiment, before forming the first conductive plug 115, the protective layer 107 covering the second isolation structure 106 needs to be removed. Before forming the second conductive plug 116, the insulating material covering the initial word line gate structure 108 needs to be removed.

[0105] Please refer to Fig.43 In other embodiments, along the first direction X, the first conductive plug 115 for electrically connecting the second isolation structure 106 and the logic circuit wafer 200 has a first central axis S1, and the second conductive plug 116 for electrically connecting the initial word line gate structure 108 and the logic circuit wafer 200 has a second central axis S2, and the first central axis S1 does not coincide with the second central axis S2. By staggering the first conductive plug 115 and the second conductive plug 116 along the first direction X, the exposure window for forming the first conductive plug 115 and the second conductive plug 116 can be further increased, thereby increasing the volume of the first conductive plug 115 and the second conductive plug 116 to improve the electrical conductivity.

[0106] In this embodiment, the logic circuit wafer 200 is electrically connected to the bit line layer 112 through a plurality of third conductive plugs 117 .

[0107] In this embodiment, after the first surface 100a (i.e., the front side) of the substrate 100 is bonded to the logic circuit wafer 200, when the second surface 100b (i.e., the back side) process of the substrate 100 is performed, there is no need to provide an additional temporary wafer to support the back side process of the substrate 100. The logic circuit wafer 200 can provide support for the back side process of the substrate 100. Therefore, the process support can be simplified and the production cost can be reduced.

[0108] Please refer to Figure 26 to Figure 29 , Fig. 27 yes Fig.26 Schematic diagram of the cross section along the PP line, Fig.28 yes Fig.26 Schematic diagram of the cross section along line QQ, Fig.29 yes Fig.26 In the cross-sectional view along line RR, after bonding the logic circuit wafer 200, the substrate 100 is subjected to a first thinning process from the second surface 100b toward the first surface 100a.

[0109] In this embodiment, since the depths of the word line gate trench and the second isolation trench are less than the depth of the first isolation trench 102, the first thinning process is performed until the first isolation structure 103 is exposed. This ensures that the initial word line gate structure 108 located in the word line gate trench will not be exposed after the first thinning process, thereby effectively reducing the process risk of metal exposure.

[0110] In other embodiments, when the depths of the word line gate trench and the second isolation trench are equal to the depth of the first isolation trench 102 , the first thinning process is performed until at least the first isolation structure 103 , the second isolation structure 106 and the initial word line gate structure 108 are exposed.

[0111] The first thinning process includes: a physical mechanical polishing process, a chemical mechanical polishing process or a wet etching process.

[0112] In this embodiment, the first thinning process adopts a chemical mechanical polishing process.

[0113] Please refer to Figure 30 to Figure 32 , Fig.30 and Fig. 27 The viewing direction is consistent with Fig.31 and Fig.28 The viewing direction is consistent with Fig.32 and Fig.29 In accordance with the viewing direction, after the first thinning treatment, a portion of the initial word line gate structure 108 is etched from the first surface 100a to the second surface 100b, so that the initial word line gate structure 108 forms two separate word line gate structures 118, and the two word line gate structures 118 are respectively located on opposite side walls of the word line gate trench along the first direction X.

[0114] It should be noted that, in this embodiment, after the initial word line gate structure 108 forms two separate word line gate structures 118 , the logic circuit wafer 200 is electrically connected to the word line gate structure 118 .

[0115] In this embodiment, the purpose of forming the initial word line gate structure 108 into two separate word line gate structures 118 is to ensure that each word line gate trench has two word line gate structures 118 to respectively control the channels on both sides of the word line gate trench.

[0116] It should be noted that, in the present embodiment, before etching the initial word line gate structure 108, the exposed first isolation structure 103 is first etched until the initial word line gate structure 108 and the second isolation structure 106 are exposed. After the first isolation structure 103 exposes the bottom surfaces of the initial word line gate structure 108 and the second isolation structure 106, a wet etching process is used to etch and remove the bottom surface of the initial word line gate structure 108 and the second isolation structure 106. Since the wet etching process has the characteristic of being isotropic, the bottom surface of the initial word line gate structure 108 located in the active area 101 can also be removed laterally, thereby ensuring that each initial word line gate structure 108 can form two separate word line gate structures 118. Furthermore, the selected wet etching process needs to have a relatively fast etching rate for the second isolation structure 106, so as to ensure that the height of the second isolation structure 106 after the final etching is lower than the height of the word line gate structure 108, that is, the projection of the second isolation structure 106 formed in the final direction X is located within the projection range of the word line gate structure 118 in the first direction X, so as to reduce the influence of the second isolation structure 106 on the adjacent storage cells when a negative voltage is applied. After the wet etching, an insulating material is deposited to fill the word line gate trench and the second isolation trench.

[0117] Please refer to Fig.33 and Fig.34 , Fig.33 A top view of a dynamic random access memory architecture is shown in order to omit the insulating material filled into the word line gate trench and the second isolation trench on the back side. Fig.34 yes Fig.33 In the schematic cross-sectional view along line SS, after the word line gate structure 118 is formed, the substrate 100 is subjected to a second thinning process from the second surface 100b toward the first surface 100a until at least the second isolation structure 106 is exposed.

[0118] The second thinning process includes: a physical mechanical polishing process, a chemical mechanical polishing process or a wet etching process.

[0119] In this embodiment, the second thinning process adopts a chemical mechanical polishing process.

[0120] In this embodiment, the purpose of exposing the second isolation structure 106 by the second thinning process is to disconnect each active region 101 along the first direction X by the second isolation structure 106 , thereby forming separate memory cells.

[0121] Please refer to Fig.35 , Fig.35 and Fig.34 In accordance with the viewing direction, after the second thinning treatment, the substrate 100 is implanted with source and drain ions from the second surface 100b to the first surface 100a to form a second source and drain doped layer 119 in each of the active areas 101, and the second surface 100b exposes the second source and drain doped layer 119.

[0122] The second source-drain doped layer 119 is formed by injecting source-drain ions from the second surface 100b to the first surface 100a, which can effectively improve the distribution uniformity of the source-drain ions in the second source-drain doped layer 119, thereby effectively improving the performance of the transistor.

[0123] In this embodiment, after the source and drain ions are implanted, the source and drain ions need to be annealed to form the second source and drain doped layer 119 .

[0124] Please refer to Figure 36 to Figure 39 , Fig.36 is a top view of the insulating material with the bottom filling of the word line gate trench and the second isolation trench omitted, Fig.37 yes Fig.36 Schematic diagram of the cross section along the TT line, Fig.38 yes Fig.36 Schematic diagram of the cross section along the UU line. Fig.39 yes Fig.36 The cross-sectional schematic diagram along line VV in the figure shows that after the second source-drain doped layer 119 is formed, a plurality of capacitor structures 120 are formed on the second surface 100 b , and each of the capacitor structures 120 is electrically connected to a corresponding one of the second source-drain doped layers 119 .

[0125] By placing the process of forming the capacitor structure 120 at the end, it is possible to ensure that a high temperature process is normally used in the process before forming the capacitor structure 120 without causing damage to the capacitor structure 120 .

[0126] In this embodiment, the capacitor structure 120 includes a pillar capacitor (eg Fig.40 As shown), cup capacitors (such as Fig.41 ) or a cylinder capacitor (such as Fig.42 as shown).

[0127] In this embodiment, before forming the capacitor structures 120 , fourth conductive plugs 121 are formed on the exposed second source-drain doped layer 119 , and each capacitor structure 120 is electrically connected to a corresponding fourth conductive plug 121 .

[0128] In other embodiments, the capacitor structure 120 may also be directly electrically connected to the corresponding second source-drain doped layer 119 .

[0129] Accordingly, a dynamic random access storage architecture is also provided in the embodiment of the present invention, please continue to refer to Figure 36 to Figure 39The dynamic random access memory architecture is formed by the formation method described in any one of the above embodiments, and the dynamic random access memory architecture includes: a substrate 100, the substrate 100 has a first surface 100a and a second surface 100b opposite to each other, the substrate 100 includes a plurality of active regions 101 separated from each other and parallel to a first direction X, and the plurality of active regions 101 are arranged along a second direction Y, and a first isolation trench 102 is provided between adjacent active regions 101, the first isolation trench 102 extends along the first direction X, and the first direction X and the second direction are parallel to each other. Y is vertical, each of the active areas 101 includes a plurality of mutually independent word line areas 1011 and isolation areas 1012, and the word line areas 1011 and the isolation areas 1012 in each of the active areas 101 are arranged at intervals along the first direction X; a first isolation structure 103 is located in the first isolation trench 102; a first source-drain doped layer 104 is located in each of the active areas 101, and the first surface 100a exposes the first source-drain doped layer 104; a word line gate trench is located in each of the word line areas 1011, and the word line gate trench is formed from the first surface 100 a extends from the first surface 100a to the second surface 100b, and the word line gate trench penetrates the active area 101 along the second direction Y; a second isolation trench located in each of the isolation regions 1012, the second isolation trench extends from the first surface 100a to the second surface 100b, and the second isolation trench penetrates the active area 101 along the second direction Y; a second isolation structure 106 located in each of the second isolation trenches; two mutually independent word line gate structures 118 located in each of the word line gate trenches, the two word line gate structures 118 are located in the word line gate trenches respectively; Side walls of the groove opposite to each other along the first direction X; a plurality of bit line layers 112 located on the first surface 100a and parallel to the first direction X, each of the bit line layers 112 being electrically connected to a plurality of the first source-drain doped layers 104 in a corresponding one of the active areas 101; a second source-drain doped layer 119 located in each of the active areas 101, the second surface 100b exposing the second source-drain doped layer 119; a plurality of capacitor structures 120 located on the second surface 100b, each of the capacitor structures 120 being electrically connected to a corresponding one of the second source-drain doped layers 119.

[0130] By placing the process of forming the capacitor structure 120 at the end, it is possible to ensure that a high temperature process is normally used in the process before forming the capacitor structure 120, without causing damage to the capacitor structure 120. In addition, the second source-drain doped layer 119 is formed by injecting source-drain ions from the second surface 100b to the first surface 100a, which can effectively improve the distribution uniformity of source-drain ions in the second source-drain doped layer 119, thereby effectively improving the performance of the transistor.

[0131] In this embodiment, the second isolation structure 106 is a conductive structure, and the material of the conductive structure is titanium nitride. Since the second isolation structure 106 is a conductive structure, a negative voltage can be applied to the second isolation structure 106, so that the second isolation structure 106 can effectively isolate adjacent memory cells arranged along the first direction X, thereby reducing the impact of the row hammer effect on the memory cells.

[0132] In other embodiments, the second isolation structure 106 may also be an insulating structure, and the material of the insulating structure may be silicon oxide or air. When the insulating structure is silicon oxide, it is only necessary to deposit silicon oxide material to fill the second isolation trench; when the insulating structure is air, by adjusting the parameters of the deposition process, the deposited material seals the opening of the second isolation trench, and the interior of the second isolation trench is air. The insulating isolation effect of air is relatively strong, and can effectively improve the isolation effect of the second isolation structure 106.

[0133] In this embodiment, the dynamic random access memory architecture further includes: a metal silicide layer 113 located between the first source-drain doped layer 104 and the bit line layer 112. The contact resistance between the bit line layer 112 and the first source-drain doped layer 104 can be effectively reduced by forming the metal silicide layer 113.

[0134] In this embodiment, the bit line layer 112 is a double-layer structure, and includes a first metal layer and a second metal layer located on the first metal layer, wherein the first metal layer is made of titanium nitride, and the second metal layer is made of tungsten.

[0135] In this embodiment, the dynamic random access storage architecture further includes: a bit line isolation structure 114 located between adjacent bit line layers 112; the bit line isolation structure 114 is a cavity structure. The specific formation process is to adjust the parameters of the deposition process so that the deposited silicon oxide material seals the opening between the adjacent bit line layers 112, thereby forming a cavity structure between the adjacent bit line layers 112. The cavity structure has a strong electrical isolation effect, thereby effectively reducing the crosstalk between the adjacent bit line layers 112.

[0136] In this embodiment, the dynamic random access memory architecture further includes: a logic circuit wafer 200, wherein the logic circuit wafer 200 is bonded to the substrate 100 toward the first surface 100a, and the logic circuit wafer 200 is electrically connected to the bit line layer 112 and the word line gate structure 118 respectively.

[0137] It should be noted that, in this embodiment, the logic circuit wafer 200 is bonded to logically control operations such as reading, writing and refreshing of each storage unit.

[0138] In this embodiment, the second isolation structure 106 is a conductive structure, the logic circuit wafer 200 is also electrically connected to the second isolation structure 106 , and the logic circuit wafer 200 also includes an operation of applying a negative voltage to the second isolation structure 106 .

[0139] Please continue to refer to Fig.21 In this embodiment, along the first direction X, the first conductive plug 115 for electrically connecting the second isolation structure 106 and the logic circuit wafer 200 has a first central axis S1, and the second conductive plug 116 for electrically connecting the word line gate structure 118 and the logic circuit wafer 200 has a second central axis S2, and the first central axis S1 coincides with the second central axis S2.

[0140] Please continue to refer to Fig.43 In other embodiments, along the first direction X, the first conductive plug 115 for electrically connecting the second isolation structure 106 and the logic circuit wafer 200 has a first central axis S1, and the second conductive plug 116 for electrically connecting the word line grid structure 118 and the logic circuit wafer 200 has a second central axis S2, and the first central axis S1 does not coincide with the second central axis S2. By staggering the first conductive plug 115 and the second conductive plug 116 along the first direction X, the exposure window for forming the first conductive plug 115 and the second conductive plug 116 can be further increased, thereby increasing the volume of the first conductive plug 115 and the second conductive plug 116 to improve the electrical conductivity.

[0141] In this embodiment, the logic circuit wafer 200 is electrically connected to the bit line layer 112 through a plurality of third conductive plugs 117 .

[0142] In this embodiment, the capacitor structure 120 includes a pillar capacitor (eg Fig.40 As shown), cup capacitors (such as Fig.41 ) or a cylinder capacitor (such as Fig.42 as shown).

[0143] In this embodiment, each of the capacitor structures 120 is electrically connected to the corresponding second source-drain doped layer 119 through a fourth conductive plug 121 .

[0144] In other embodiments, the capacitor structure 120 may also be directly electrically connected to the corresponding second source-drain doped layer 119 .

[0145] In this embodiment, the two separate word line gate structures 118 are also located on the opposite side walls of the word line gate trench along the second direction Y; the two second conductive plugs 116 electrically connected to the two separate word line gate structures 118 are distributed on opposite sides of the word line gate trench along the second direction Y. In this way, the contact area between the second conductive plug 116 and the corresponding word line gate structure 116 is increased, and the electrical contact performance between the second conductive plug 116 and the corresponding word line gate structure 118 is improved.

[0146] In this embodiment, the projection of the second isolation structure 106 along the first direction X is located within the projection range of the word line gate structure 118 along the first direction X, thereby reducing the influence of the second isolation structure 106 on adjacent memory cells when a negative voltage is applied.

[0147] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a dynamic random access memory architecture, characterized in that: include: Forming a substrate, the substrate having a first surface and a second surface opposite to each other, the substrate comprising a plurality of active regions which are separated from each other and parallel to a first direction, and the plurality of active regions are arranged along a second direction, a first isolation trench is provided between adjacent active regions, the first isolation trench extends along the first direction, the first direction is perpendicular to the second direction, each of the active regions comprises a plurality of word line regions and isolation regions which are separated from each other, and the word line regions and the isolation regions in each of the active regions are arranged at intervals along the first direction; forming a first isolation structure in the first isolation trench; forming a first source-drain doped layer in each of the active regions, wherein the first surface exposes the first source-drain doped layer; forming a word line gate trench in each of the word line regions, and forming a second isolation trench in each of the isolation regions, wherein the word line gate trench and the second isolation trench extend from the first surface to the second surface, and the word line gate trench and the second isolation trench penetrate the active region along the second direction; forming a second isolation structure in each of the second isolation trenches; forming an initial word line gate structure in each of the word line gate trenches; After forming the second isolation structure and the initial word line gate structure, forming a plurality of bit line layers parallel to the first direction on the first surface, each of the bit line layers being electrically connected to a plurality of the first source-drain doped layers in a corresponding one of the active regions; After forming the bit line layer, performing a first thinning process on the substrate from the second surface to the first surface; After the first thinning process, etching a portion of the initial word line gate structure from the first surface toward the second surface, so that the initial word line gate structure forms two mutually independent word line gate structures, and the two word line gate structures are respectively located on opposite side walls of the word line gate trench along the first direction; After forming the word line gate structure, performing source and drain ion implantation from the second surface to the first surface of the substrate to form a second source and drain doped layer in each of the active regions, wherein the second surface exposes the second source and drain doped layer; After the second source-drain doped layer is formed, a plurality of capacitor structures are formed on the second surface, and each of the capacitor structures is electrically connected to a corresponding one of the second source-drain doped layers.

2. The method for forming a dynamic random access memory architecture as claimed in claim 1, wherein: The second isolation structure is a conductive structure.

3. The method for forming a dynamic random access memory architecture as claimed in claim 2, wherein: The material of the conductive structure includes: titanium nitride.

4. The method for forming a dynamic random access memory architecture as claimed in claim 1, wherein: The second isolation structure is an insulating structure.

5. The method for forming a dynamic random access memory architecture as claimed in claim 4, wherein: The materials of the insulating structure include: silicon oxide or air.

6. The method for forming a dynamic random access memory architecture as claimed in claim 1, wherein: The method for forming the initial word line gate structure in each of the word line gate grooves includes: forming a word line gate material layer on the sidewalls and bottom surface of the word line gate groove; removing a portion of the word line gate material layer located on the sidewalls of the word line gate groove to form a first cut-off opening and a second cut-off opening, so that the word line gate material layer forms the initial word line gate structure.

7. The method for forming a dynamic random access memory architecture as claimed in claim 6, wherein: The first cut-off opening and the second cut-off opening are respectively located in the initial word line gate structure on the side walls of the word line gate groove arranged opposite to each other along the first direction, and the first cut-off opening and the second cut-off opening are also respectively located in both sides of the initial word line gate structure along the second direction.

8. The method for forming a dynamic random access memory architecture as claimed in claim 1, wherein: After forming the bit line layer and before performing the first thinning process, the method further includes: forming a bit line isolation structure between adjacent bit line layers.

9. The method for forming a dynamic random access memory architecture as claimed in claim 8, wherein: The bit line isolation structure is a cavity structure.

10. The method for forming a dynamic random access memory architecture as claimed in claim 1, wherein: The depth of the word line gate trench is less than the depth of the first isolation trench; the depth of the second isolation trench is less than the depth of the first isolation trench.

11. The method for forming a dynamic random access memory architecture as claimed in claim 10, wherein: The first thinning process is performed until the first isolation structure is exposed.

12. The method for forming a dynamic random access memory architecture as claimed in claim 11, wherein: After forming the word line gate structure and before forming the second source-drain doping layer, the method further includes: performing a second thinning process on the substrate from the second surface toward the first surface until at least the second isolation structure is exposed.

13. The method for forming a dynamic random access memory architecture as claimed in claim 1, wherein: The depth of the word line gate trench is equal to the depth of the first isolation trench; the depth of the second isolation trench is equal to the depth of the first isolation trench.

14. The method for forming a dynamic random access memory architecture as claimed in claim 13, wherein: The first thinning process is performed until at least the first isolation structure, the second isolation structure, and the initial word line gate structure are exposed.

15. The method for forming a dynamic random access memory architecture as claimed in claim 1, wherein: After forming the bit line layer and before performing the first thinning process, the method further includes: providing a logic circuit wafer; bonding the logic circuit wafer to the substrate facing the first surface, the logic circuit wafer being electrically connected to the bit line layer and the initial word line gate structure respectively.

16. The method for forming a dynamic random access memory architecture as claimed in claim 15, wherein: After the initial word line gate structure forms two separate word line gate structures, the logic circuit wafer is electrically connected to the word line gate structure.

17. The method for forming a dynamic random access memory architecture as claimed in claim 16, wherein: The second isolation structure is a conductive structure, and the logic circuit wafer is also electrically connected to the second isolation structure.

18. The method for forming a dynamic random access memory architecture as claimed in claim 17, wherein: Along the first direction, the first conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a first central axis, and the second conductive plug for electrically connecting the initial word line gate structure and the logic circuit wafer has a second central axis, and the first central axis coincides with the second central axis.

19. The method for forming a dynamic random access memory architecture as claimed in claim 17, wherein: Along the first direction, the first conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a first central axis, and the second conductive plug for electrically connecting the initial word line gate structure and the logic circuit wafer has a second central axis, and the first central axis does not overlap with the second central axis.

20. The method for forming a dynamic random access memory architecture as claimed in claim 1, wherein: The process of etching part of the initial word line gate structure from the first surface to the second surface also includes: etching part of the second isolation structure from the first surface to the second surface, so that the projection of the second isolation structure along the first direction is within the projection range of the word line gate structure along the first direction.

21. A dynamic random access memory architecture, characterized in that: The dynamic random access memory architecture is formed by a forming method according to any one of claims 1 to 20, and the dynamic random access memory architecture comprises: A substrate, wherein the substrate has a first surface and a second surface opposite to each other, the substrate comprises a plurality of active regions which are separated from each other and parallel to a first direction, and the plurality of active regions are arranged along a second direction, a first isolation trench is provided between adjacent active regions, the first isolation trench extends along the first direction, the first direction is perpendicular to the second direction, each of the active regions comprises a plurality of word line regions and isolation regions which are separated from each other, and the word line regions and the isolation regions in each of the active regions are arranged at intervals along the first direction; a first isolation structure located in the first isolation trench; A first source-drain doped layer located in each of the active regions, the first surface exposing the first source-drain doped layer; A word line gate trench located in each of the word line regions, the word line gate trench extending from the first surface to the second surface, and the word line gate trench penetrating the active region along the second direction; a second isolation trench located in each of the isolation regions, the second isolation trench extending from the first surface to the second surface, and the second isolation trench penetrating the active region along the second direction; a second isolation structure located in each of the second isolation trenches; Two mutually independent word line gate structures located in each of the word line gate trenches, the two word line gate structures are respectively located on opposite side walls of the word line gate trench along the first direction; A plurality of bit line layers located on the first surface and parallel to the first direction, each of the bit line layers being electrically connected to a plurality of the first source-drain doped layers in a corresponding one of the active regions; a second source-drain doped layer located in each of the active regions, the second surface exposing the second source-drain doped layer; A plurality of capacitor structures are located on the second surface, and each of the capacitor structures is electrically connected to a corresponding second source-drain doped layer.

22. The dynamic random access memory architecture of claim 21, wherein: The second isolation structure is a conductive structure.

23. The dynamic random access memory architecture of claim 22, wherein: The materials of the conductive structure include: titanium nitride.

24. The dynamic random access memory architecture of claim 21, wherein: The second isolation structure is an insulating structure.

25. The dynamic random access memory architecture of claim 24, wherein: The materials of the insulating structure include: silicon oxide or air.

26. The dynamic random access memory architecture of claim 21, wherein: Also includes: A bit line isolation structure is located between adjacent bit line layers.

27. The dynamic random access memory architecture of claim 26, wherein: The bit line isolation structure is a cavity structure.

28. The dynamic random access memory architecture of claim 21, wherein: Also includes: A logic circuit wafer is bonded to the substrate toward the first surface, and the logic circuit wafer is electrically connected to the bit line layer and the word line gate structure respectively.

29. The dynamic random access memory architecture of claim 28, wherein: The second isolation structure is a conductive structure, and the logic circuit wafer is also electrically connected to the second isolation structure.

30. The dynamic random access memory architecture of claim 28, wherein: Along the first direction, the first conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a first central axis, and the second conductive plug for electrically connecting the word line gate structure and the logic circuit wafer has a second central axis, and the first central axis coincides with the second central axis.

31. The dynamic random access memory architecture of claim 28, wherein: Along the first direction, the first conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a first central axis, and the second conductive plug for electrically connecting the word line gate structure and the logic circuit wafer has a second central axis, and the first central axis does not coincide with the second central axis.

32. The dynamic random access memory architecture of claim 30 or 31, wherein: The two separate word line gate structures are also located on opposite side walls of the word line gate trench along the second direction; the two second conductive plugs electrically connected to the two separate word line gate structures are distributed on opposite sides of the word line gate trench along the second direction.

33. The dynamic random access memory architecture of claim 21, wherein: A projection of the second isolation structure along the first direction is located within a projection range of the word line gate structure along the first direction.

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