Dynamic random access memory architecture and forming method thereof

Abstract

The invention discloses a dynamic random access memory architecture and a forming method thereof, and the forming method comprises the steps: forming a substrate and a bit line layer, the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active regions, each active region comprises a plurality of word line regions, and the bit line layer is located on the first surface; forming a word line gate groove in each word line area; two word line gate structures which are separated from each other are formed in each word line gate groove; injecting source and drain ions into the substrate from the second surface to the first surface, and forming a second source and drain doping layer in each active region; and forming a plurality of capacitor structures on the second surface. The manufacturing process for forming the capacitor structure is put at the last, so that a high-temperature process can be normally adopted in the manufacturing process before the capacitor structure is formed, and the capacitor structure cannot be damaged. The second source-drain doping layer is formed by injecting source-drain ions from the second surface to the first surface, so that the distribution uniformity of the source-drain ions in the second source-drain doping layer can be effectively improved, and the performance of the transistor is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a dynamic random access storage architecture and a forming method thereof. Background Art

[0002] With the rapid development of technology today, semiconductor memory is widely used in electronic devices. Dynamic random access memory (DRAM) is a type of volatile memory. For applications that store large amounts of data, DRAM is the most commonly used solution.

[0003] Typically, a dynamic random access memory is composed of a plurality of memory cells, each of which is mainly composed of a transistor and a capacitor controlled by the transistor, and each of the memory cells is electrically connected to each other through a word line and a bit line.

[0004] However, the existing dynamic random access memory architecture still has many problems. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a dynamic random access memory architecture and a forming method thereof, so as to ensure the normal use of high temperature processes and improve the performance of transistors.

[0006] In order to solve the above problems, the technical solution of the present invention provides a method for forming a dynamic random access memory architecture, comprising: forming a substrate and a plurality of bit line layers, the substrate having a first surface and a second surface opposite to each other, the substrate comprising a plurality of active areas which are mutually discrete and parallel to a first direction, and the plurality of active areas are arranged along a second direction, each of the active areas has a first source-drain doping layer, the first surface exposes the first source-drain doping layer, a first isolation trench is provided between adjacent active areas, a first isolation structure is provided in the first isolation trench, the first isolation trench extends along the first direction, the first direction is perpendicular to the second direction, each of the active areas comprises a plurality of mutually discrete word line areas and isolation areas, and the word line areas and the isolation areas in each of the active areas are arranged at intervals along the first direction, a plurality of the bit line layers are located on the first surface and are parallel to the first direction, and each of the bit line layers is electrically connected to a plurality of the first source-drain doping layers in a corresponding one of the active areas; after forming the substrate and the bit line layers, from the second surface to the first The substrate is thinned in the direction of the first surface until the first isolation structure is exposed; after the thinning, a word line gate trench is formed in each word line area, and a second isolation trench is formed in each isolation area, the word line gate trench and the second isolation trench extend from the first surface to the second surface, and the word line gate trench and the second isolation trench penetrate the active area along the second direction; a second isolation structure is formed in each second isolation trench; two mutually independent word line gate structures are formed in each word line gate trench, and the two word line gate structures are respectively located on the opposite side walls of the word line gate trench along the first direction; after the word line gate structure is formed, the substrate is implanted with source and drain ions from the second surface to the first surface, and a second source and drain doping layer is formed in each active area, and the second surface exposes the second source and drain doping layer; after the second source and drain doping layer is formed, a plurality of capacitor structures are formed on the second surface, and each of the capacitor structures is electrically connected to a corresponding second source and drain doping layer.

[0007] Optionally, the second isolation structure is a conductive structure.

[0008] Optionally, the material of the conductive structure includes: titanium nitride.

[0009] Optionally, the second isolation structure is an insulating structure.

[0010] Optionally, the material of the insulating structure includes: silicon oxide or air.

[0011] Optionally, the method for forming the substrate and the several bit line layers includes: providing an initial substrate, the initial substrate having the first surface and the second surface relative to each other; performing a patterning etching process on the initial substrate to form several first isolation trenches, wherein the active area is between adjacent first isolation trenches; forming the first isolation structure in the first isolation trench; after forming the isolation structure, forming the first source-drain doping layer in the active area to form the substrate; after forming the substrate, forming the several bit line layers.

[0012] Optionally, the method for forming the bit line layer includes: performing metallization treatment on the first source and drain doped layer exposed on the first surface so that a portion of the first source and drain doped layer forms a metal silicide layer, and using the metal silicide layer as the bit line layer.

[0013] Optionally, after forming the substrate and before forming the bit line layer, the method further includes: etching a portion of the first isolation structure from the first surface to the second surface to form a bit line isolation groove between adjacent active areas; and forming a bit line isolation structure in the bit line isolation groove.

[0014] Optionally, the method for forming the substrate and the several bit line layers includes: providing an initial substrate, the initial substrate having the first surface and the second surface relative to each other; forming the first source-drain doped layer in the initial substrate; after forming the source-drain doped layer, forming a bit line material layer on the first surface; performing a patterning etching process on the bit line material layer and the initial substrate to form several first isolation trenches, the active area being between adjacent first isolation trenches, and making the bit line material layer form the bit line layer; after the patterning etching process, forming the first isolation structure in the first isolation trench to form the substrate.

[0015] Optionally, after forming the substrate and the bit line layer, the method further includes: etching a portion of the first isolation structure from the first surface to the second surface to form a bit line isolation groove between adjacent active areas; and forming a bit line isolation structure in the bit line isolation groove.

[0016] Optionally, the bit line isolation structure is a cavity structure.

[0017] Optionally, after forming the bit line layer and before performing the thinning process, it also includes: providing a logic circuit wafer; bonding the logic circuit wafer to the substrate toward the first surface, and the logic circuit wafer is electrically connected to the bit line layer respectively.

[0018] Optionally, after the word line gate structure is formed, the logic circuit wafer is electrically connected to the word line gate structure.

[0019] Optionally, the method for electrically connecting the logic circuit wafer to the word line gate structure includes: forming a plurality of first conductive plugs before bonding the logic circuit wafer and the substrate, and after forming the word line gate structure, electrically connecting the first conductive plugs to the corresponding word line gate structures; after bonding the logic circuit wafer and the substrate, electrically connecting the logic circuit wafer to the first conductive plugs.

[0020] Optionally, the second isolation structure is a conductive structure, and after the second isolation structure is formed, the logic circuit wafer is electrically connected to the second isolation structure.

[0021] Optionally, the method in which the logic circuit wafer is also electrically connected to the second isolation structure respectively includes: forming a plurality of second conductive plugs before bonding the logic circuit wafer and the substrate, and after forming the second isolation structure, the second conductive plugs are electrically connected to the corresponding second isolation structures; after bonding the logic circuit wafer and the substrate, the logic circuit wafer is electrically connected to the second conductive plugs.

[0022] Optionally, along the first direction, the first conductive plug has a first central axis, the second conductive plug has a second central axis, and the first central axis coincides with the second central axis.

[0023] Optionally, along the first direction, the first conductive plug has a first central axis, the second conductive plug has a second central axis, and the first central axis does not coincide with the second central axis.

[0024] Optionally, the two separate word line gate structures are also located on opposite side walls of the word line gate trench along the second direction; and the two first conductive plugs respectively electrically connected to the two separate word line gate structures are distributed on opposite sides of the word line gate trench along the second direction.

[0025] Optionally, a projection of the second isolation structure along the first direction is located within a projection range of the word line gate structure along the first direction.

[0026] Correspondingly, the technical solution of the present invention further provides a dynamic random access storage architecture, which is formed by the formation method described in any one of the above technical solutions, and the dynamic random access storage architecture includes: a substrate, the substrate has a first surface and a second surface opposite to each other, the substrate includes a plurality of active areas that are separate from each other and parallel to a first direction, and the plurality of active areas are arranged along a second direction, and a first isolation trench is provided between adjacent active areas, the first isolation trench extends along the first direction, the first direction is perpendicular to the second direction, each of the active areas includes a plurality of separate word line areas and isolation areas, and the word line areas and the isolation areas in each of the active areas are arranged at intervals along the first direction; a first isolation structure located in the first isolation trench; a first source-drain doping layer located in each of the active areas, the first surface exposing the first source-drain doping layer; a word line gate trench located in each of the word line areas, the word line gate trench extending along the first direction ... A word line gate groove extends from the first surface to the second surface, and the word line gate groove penetrates the active area along the second direction; a second isolation groove located in each of the isolation areas, the second isolation groove extends from the first surface to the second surface, and the second isolation groove penetrates the active area along the second direction; a second isolation structure located in each of the second isolation grooves; two mutually independent word line gate structures located in each of the word line gate grooves, the two word line gate structures are respectively located on opposite side walls of the word line gate groove along the first direction; a plurality of bit line layers located on the first surface and parallel to the first direction, each of the bit line layers is electrically connected to a plurality of the first source and drain doping layers in a corresponding one of the active areas; a second source and drain doping layer located in each of the active areas, the second surface exposing the second source and drain doping layer; a plurality of capacitor structures located on the second surface, each of the capacitor structures is electrically connected to a corresponding one of the second source and drain doping layers.

[0027] Optionally, the second isolation structure is a conductive structure.

[0028] Optionally, the material of the conductive structure includes: titanium nitride.

[0029] Optionally, the second isolation structure is an insulating structure.

[0030] Optionally, the material of the insulating structure includes: silicon oxide or air.

[0031] Optionally, it also includes: a bit line isolation structure located between adjacent bit line layers.

[0032] Optionally, the bit line isolation structure is a cavity structure.

[0033] Optionally, it further includes: a logic circuit wafer, wherein the logic circuit wafer is bonded to the substrate toward the first surface, and the logic circuit wafer is electrically connected to the bit line layer and the word line gate structure respectively.

[0034] Optionally, the second isolation structure is a conductive structure, and the logic circuit wafer is electrically connected to the second isolation structure.

[0035] Optionally, along the first direction, the first conductive plug used to electrically connect the word line gate structure and the logic circuit wafer has a first central axis, and the second conductive plug used to electrically connect the second isolation structure and the logic circuit wafer has a second central axis, and the first central axis coincides with the second central axis.

[0036] Optionally, along the first direction, the first conductive plug used to electrically connect the word line gate structure and the logic circuit wafer has a first central axis, and the second conductive plug used to electrically connect the second isolation structure and the logic circuit wafer has a second central axis, and the first central axis does not coincide with the second central axis.

[0037] Optionally, the two separate word line gate structures are also located on opposite side walls of the word line gate trench along the second direction; and the two first conductive plugs respectively electrically connected to the two separate word line gate structures are distributed on opposite sides of the word line gate trench along the second direction.

[0038] Optionally, a projection of the second isolation structure along the first direction is located within a projection range of the word line gate structure along the first direction.

[0039] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0040] In the method for forming a dynamic random access memory architecture of the technical solution of the present invention, by placing the process of forming the capacitor structure at the end, it is possible to ensure that a high temperature process is normally used in the process before forming the capacitor structure without causing damage to the capacitor structure. In addition, the second source-drain doped layer is formed by injecting source-drain ions from the second surface to the first surface, which can effectively improve the distribution uniformity of source-drain ions in the second source-drain doped layer, thereby effectively improving the performance of the transistor.

[0041] Furthermore, the second isolation structure is a conductive structure. By applying a negative voltage to the second isolation structure, adjacent memory cells arranged along the first direction can be effectively isolated, thereby reducing the impact of the row hammer effect on the memory cells.

[0042] Furthermore, the bit line isolation structure is a cavity structure. The cavity structure has a strong electrical isolation effect, thereby effectively reducing the crosstalk between adjacent bit line layers.

[0043] Furthermore, along the first direction, the first conductive plug has a first central axis, the second conductive plug has a second central axis, and the first central axis does not coincide with the second central axis. By staggering the first conductive plug and the second conductive plug along the first direction, the exposure window for forming the first conductive plug and the second conductive plug can be further increased, thereby increasing the volume of the first conductive plug and the second conductive plug to improve electrical conductivity.

[0044] Furthermore, the two mutually independent word line gate structures are also located on the opposite side walls of the word line gate groove along the second direction; and the two first conductive plugs electrically connected to the two mutually independent word line gate structures are distributed on opposite sides of the word line gate groove along the second direction, thereby increasing the contact area between the first conductive plug and the corresponding word line gate structure, and improving the electrical contact performance between the first conductive plug and the corresponding word line gate structure.

[0045] Furthermore, the projection of the second isolation structure along the first direction is located within the projection range of the word line gate structure along the first direction, thereby reducing the influence of the second isolation structure on adjacent storage cells when a negative voltage is applied.

[0046] In the dynamic random access memory architecture of the technical solution of the present invention, by placing the process of forming the capacitor structure at the end, it is possible to ensure that a high temperature process is normally used in the process before forming the capacitor structure without causing damage to the capacitor structure. In addition, the second source-drain doped layer is formed by injecting source-drain ions from the second surface to the first surface, which can effectively improve the distribution uniformity of source-drain ions in the second source-drain doped layer, thereby effectively improving the performance of the transistor.

[0047] Furthermore, the second isolation structure is a conductive structure. By applying a negative voltage to the second isolation structure, adjacent memory cells arranged along the first direction can be effectively isolated, thereby reducing the impact of the row hammer effect on the memory cells.

[0048] Furthermore, the bit line isolation structure is a cavity structure. The cavity structure has a strong electrical isolation effect, thereby effectively reducing the crosstalk between adjacent bit line layers.

[0049] Furthermore, along the first direction, the first conductive plug has a first central axis, the second conductive plug has a second central axis, and the first central axis does not coincide with the second central axis. By staggering the first conductive plug and the second conductive plug along the first direction, the exposure window for forming the first conductive plug and the second conductive plug can be further increased, thereby increasing the volume of the first conductive plug and the second conductive plug to improve electrical conductivity.

[0050] Furthermore, the two mutually independent word line gate structures are also located on the opposite side walls of the word line gate groove along the second direction; and the two first conductive plugs electrically connected to the two mutually independent word line gate structures are distributed on opposite sides of the word line gate groove along the second direction, thereby increasing the contact area between the first conductive plug and the corresponding word line gate structure, and improving the electrical contact performance between the first conductive plug and the corresponding word line gate structure.

[0051] Furthermore, the projection of the second isolation structure along the first direction is located within the projection range of the word line gate structure along the first direction, thereby reducing the influence of the second isolation structure on adjacent storage cells when a negative voltage is applied. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figures 1 to 30 It is a schematic diagram of the structure of each step of the method for forming a dynamic random access memory architecture according to an embodiment of the present invention;

[0053] Fig.31 A schematic diagram of the structure of a pillar capacitor in a dynamic random access memory architecture according to an embodiment of the present invention;

[0054] Fig.32 A schematic diagram of the structure of a cup capacitor in a dynamic random access memory architecture according to an embodiment of the present invention;

[0055] Fig.33 A schematic diagram of the structure of a cylinder capacitor in a dynamic random access memory architecture according to an embodiment of the present invention;

[0056] Figure 34 to Figure 38 It is a schematic structural diagram of each step of a method for forming a substrate and a bit line layer of a dynamic random access memory architecture in another embodiment of the present invention;

[0057] Fig.39 A schematic diagram of the distribution of first conductive plugs and second conductive plugs in a dynamic random access memory architecture according to another embodiment of the present invention. DETAILED DESCRIPTION

[0058] As described in the background art, the existing dynamic random access memory architecture still has many problems, which will be described in detail below.

[0059] The dynamic random access memory architecture in the prior art is to first make the capacitor structure and then do the back process, which means that high-temperature processes cannot be used in the back process, otherwise it will affect the high-K dielectric layer in the capacitor structure, thereby causing the capacitor structure to fail. In addition, the back source and drain doping layer in the dynamic random access memory architecture is formed by ion implantation from the front side, which easily causes poor uniformity of ion distribution in the transistor and reduces the performance of the transistor.

[0060] On this basis, the present invention provides a dynamic random access memory architecture and a method for forming the same. By placing the process of forming the capacitor structure at the end, it is possible to ensure that a high temperature process is normally used in the process before forming the capacitor structure without causing damage to the capacitor structure. In addition, the second source-drain doped layer is formed by injecting source-drain ions from the second surface to the first surface, which can effectively improve the distribution uniformity of the source-drain ions in the second source-drain doped layer, thereby effectively improving the performance of the transistor.

[0061] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0062] Figures 1 to 30 It is a schematic structural diagram of each step of a method for forming a dynamic random access memory architecture according to an embodiment of the present invention; Fig.31 A schematic diagram of the structure of a pillar capacitor in a dynamic random access memory architecture according to an embodiment of the present invention; Fig.32 A schematic diagram of the structure of a cup capacitor in a dynamic random access memory architecture according to an embodiment of the present invention; Fig.33 A schematic diagram of the structure of a cylinder capacitor in a dynamic random access memory architecture according to an embodiment of the present invention; Fig.39 A schematic diagram of the distribution of first conductive plugs and second conductive plugs in a dynamic random access memory architecture according to another embodiment of the present invention.

[0063] A substrate and a plurality of bit line layers are formed, wherein the substrate has a first surface and a second surface opposite to each other, the substrate includes a plurality of active areas that are mutually discrete and parallel to a first direction, and the plurality of active areas are arranged along a second direction, each of the active areas has a first source-drain doping layer, the first surface exposes the first source-drain doping layer, a first isolation trench is provided between adjacent active areas, a first isolation structure is provided in the first isolation trench, the first isolation trench extends along the first direction, the first direction is perpendicular to the second direction, each of the active areas includes a plurality of mutually discrete word line areas and isolation areas, and the word line areas and the isolation areas in each active area are arranged at intervals along the first direction, a plurality of bit line layers are located on the first surface and are parallel to the first direction, and each of the bit line layers is electrically connected to a plurality of the first source-drain doping layers in a corresponding one of the active areas. For the specific formation process of the substrate and the bit line layers, please refer to Figures 1 to 7 .

[0064] Please refer to Figures 1 to 3 , Figure 2 yes Figure 1 Schematic diagram of the cross section along line AA, Figure 3 yes Figure 1 In the cross-sectional diagram along line BB, an initial substrate 100 is provided, wherein the initial substrate 100 has the first surface 100a and the second surface 100b opposite to each other; the initial substrate 100 is subjected to a patterning etching process to form a plurality of the first isolation trenches 101, and the active area 102 is between adjacent first isolation trenches 101.

[0065] In this embodiment, a plurality of active regions 102 extend along the first direction X and are arranged separately and parallel to each other along the second direction Y. The first direction X is perpendicular to the second direction Y.

[0066] In this embodiment, the word line regions 1021 and the isolation regions 1022 in each of the active regions 102 are arranged along the first direction X at intervals.

[0067] In this embodiment, the material of the initial substrate 100 is silicon.

[0068] In other embodiments, the material of the initial substrate 100 may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0069] It should be noted that, in this embodiment, the first surface 100a is the front side of the memory unit in the final dynamic random access memory architecture, and the second surface 100b is the back side of the memory unit in the final dynamic random access memory architecture.

[0070] Please refer to Figure 4 and Figure 5 , Figure 5 yes Figure 4 In the cross-sectional diagram along line CC, a first isolation structure 103 is formed in the first isolation trench 101 .

[0071] In this embodiment, the method for forming the first isolation structure 103 includes: depositing an isolation material layer (not shown), the isolation material layer filling the first isolation trench 101 and being located on the first surface 100a, and planarizing the isolation material layer until the first surface 100a of the substrate is exposed, thereby forming the first isolation structure 103.

[0072] In this embodiment, the first isolation structure 103 is made of silicon oxide.

[0073] Please refer to Figure 6 , Figure 6 and Figure 5 In accordance with the viewing direction, after forming the first isolation structure 103 , a first source-drain doped layer 104 is formed in each of the active regions 102 , and the first surface 100 a exposes the first source-drain doped layer 104 .

[0074] In this embodiment, the method for forming the first source-drain doped layer 104 includes: implanting source-drain ions into the substrate from the first surface 100 a to the second surface 100 b , and annealing the implanted source-drain ions to form the first source-drain doped layer 104 in the active area 102 .

[0075] From now on, the substrate 105 is formed completely.

[0076] Please refer to Figure 7 After forming the substrate 105 , the bit line layer 106 is formed.

[0077] In this embodiment, the method for forming the bit line layer 106 includes: performing metallization treatment on the first source-drain doped layer 104 exposed by the first surface 100a, so that a portion of the first source-drain doped layer 104 forms a metal silicide layer, and using the metal silicide layer as the bit line layer 106. By directly using the metal silicide layer as the bit line layer 106, the contact resistance between the bit line layer 106 and the first source-drain doped layer 104 can be effectively reduced.

[0078] In this embodiment, after forming the substrate 105 and before forming the bit line layer 106, it also includes: etching a portion of the first isolation structure 103 from the first surface 100a to the second surface 100b to form a bit line isolation groove (not marked) between adjacent active areas 102; and forming a bit line isolation structure 107 in the bit line isolation groove.

[0079] In this embodiment, the bit line isolation structure 107 is a cavity structure. The specific formation process is to adjust the parameters of the deposition process so that the deposited silicon oxide material seals the openings between the adjacent bit line layers 106, thereby forming a cavity structure between the adjacent bit line layers 106. The cavity structure has a strong electrical isolation effect, thereby effectively reducing the crosstalk between the adjacent bit line layers 106.

[0080] Please refer to Figures 8 to 12 , Figure 8 This is a top view of the wafer with the logic circuit omitted. Fig. 9 yes Figure 8 Schematic diagram of the cross section along the DD line, Fig.10 yes Figure 8 Schematic diagram of the cross section along line EE, Fig.11 yes Figure 8 Schematic diagram of the cross section along line FF, Fig.12 yes Figure 8 In the cross-sectional diagram along the GG line, after forming the substrate 105 and the bit line layer 106, a logic circuit wafer 200 is provided; the logic circuit wafer 200 is bonded to the substrate 105 toward the first surface 100a, and the logic circuit wafer 200 is electrically connected to the bit line layer 106 respectively.

[0081] It should be noted that, in this embodiment, the logic circuit wafer 200 is bonded to logically control operations such as reading, writing and refreshing of each storage unit.

[0082] In this embodiment, a plurality of first conductive plugs 108 are formed before bonding the logic circuit wafer 200 and the substrate 105. After forming a word line gate structure in a subsequent process, the first conductive plugs 108 are used to electrically connect to the corresponding word line gate structures. After bonding the logic circuit wafer 200 and the substrate 105, the logic circuit wafer 200 is electrically connected to the first conductive plugs 108.

[0083] In this embodiment, a plurality of second conductive plugs 109 are formed before bonding the logic circuit wafer 200 and the substrate 105, and after a second isolation structure is formed in a subsequent process, and the second isolation structure is a conductive structure, the second conductive plugs 109 are electrically connected to the corresponding second isolation structure; after bonding the logic circuit wafer 200 and the substrate 105, the logic circuit wafer 200 is electrically connected to the second conductive plugs 109.

[0084] In this embodiment, the method for electrically connecting the logic circuit wafer 200 to the bit line layer 106 respectively includes: before bonding the logic circuit wafer 200 and the substrate 105, forming a plurality of third conductive plugs 110, and the third conductive plugs 110 are electrically connected to the corresponding bit line layers 106; after bonding the logic circuit wafer 200 and the substrate 105, the logic circuit wafer 200 is electrically connected to the third conductive plugs 110.

[0085] In this embodiment, along the first direction X, the first conductive plug 108 has a first central axis S1 , and the second conductive plug 109 has a second central axis S2 , and the first central axis S1 coincides with the second central axis S2 .

[0086] Please refer to Fig.39 In other embodiments, along the first direction X, the first conductive plug 108 has a first central axis S1, and the second conductive plug 109 has a second central axis S2, and the first central axis S1 does not coincide with the second central axis S2. By staggering the first conductive plug 108 and the second conductive plug 109 along the first direction X, the exposure window for forming the first conductive plug 108 and the second conductive plug 109 can be further increased, thereby increasing the volume of the first conductive plug 108 and the second conductive plug 109 to improve the electrical conductivity.

[0087] In this embodiment, after the first surface 100a (i.e., the front side) of the substrate 105 is bonded to the logic circuit wafer 200, when performing the process of the second surface 100b (i.e., the back side) of the substrate 105, there is no need to provide an additional temporary wafer to support the back side process of the substrate 105. The logic circuit wafer 200 can provide support for the back side process of the substrate 105. Therefore, the process support can be simplified and the production cost can be reduced.

[0088] Please refer to Figures 13 to 16 , Fig.14 yes Fig.13 Schematic diagram of the cross section along the HH line, Fig.15 yes Fig.13 Schematic diagram of the cross section along line II, Fig.16yes Fig.13 In the schematic cross-sectional view along line JJ, after the logic circuit wafer 200 and the substrate 105 are bonded, the substrate 105 is thinned from the second surface 100b toward the first surface 100a until the first isolation structure 103 is exposed.

[0089] The thinning process includes: a physical mechanical polishing process, a chemical mechanical polishing process or a wet etching process.

[0090] In this embodiment, the thinning process adopts a chemical mechanical polishing process.

[0091] Please refer to Figures 17 to 19 , Fig.18 yes Fig.17 Schematic diagram of the cross section along the KK line, Fig.19 yes Fig.17 A cross-sectional schematic diagram along line LL shows that after the thinning process, a word line gate trench (not marked) is formed in each word line region 1021, and a second isolation trench (not marked) is formed in each isolation region 1022, and the word line gate trench and the second isolation trench extend from the first surface 100a to the second surface 100b, and the word line gate trench and the second isolation trench pass through the active area 102 along the second direction Y.

[0092] In this embodiment, the formation of the word line gate trench and the second isolation trench includes: forming a patterned layer (not shown) on the substrate 105; etching the word line region 1021 and the first isolation structure 103 of the active area 102 using the patterned layer as a mask to form the word line gate trench, and etching the isolation region 1022 and the first isolation structure 103 of the active area 102 using the second patterned layer as a mask to form the second isolation trench.

[0093] It should be noted that, in this embodiment, the word line gate trench formed needs to expose the corresponding first conductive plug 108, so that the word line gate structure subsequently formed in the word line gate trench can be electrically connected to the first conductive plug 108. The second isolation trench formed needs to correspondingly expose the second conductive plug 109, so that the second isolation structure subsequently formed in the second isolation trench can be electrically connected to the second conductive plug 109.

[0094] Please continue to refer to Figures 17 to 19 After forming the word line gate trench and the second isolation trench, the word line gate trench and the second isolation trench are fully filled with a sacrificial layer 111 .

[0095] It should be noted that in this embodiment, since different device structures are formed in the word line gate trench and the second isolation trench respectively in the subsequent process, the word line gate trench and the second isolation trench are first filled with the sacrificial layer 111, and in the subsequent process, the sacrificial layer 111 in the corresponding trench is removed step by step to form the required device structure.

[0096] In this embodiment, the sacrificial layer 111 is made of spin-on carbon.

[0097] Please refer to Fig. 20 and Fig.21 , Fig. 20 and Fig.18 The viewing direction is consistent with Fig.21 and Fig.19 In accordance with the viewing direction, after forming the sacrificial layer 111, a second isolation structure 112 is formed in each of the second isolation trenches.

[0098] It should be noted that, in this embodiment, before forming the second isolation structure 112 , the sacrificial layer 111 filled in the second isolation trench needs to be removed.

[0099] In this embodiment, the second isolation structure 112 is a conductive structure, and the material of the conductive structure is titanium nitride. Since the second isolation structure 112 is a conductive structure, a negative voltage can be applied to the second isolation structure 112 through the logic circuit wafer 200, so that the second isolation structure 112 can effectively isolate adjacent storage cells arranged along the first direction X, thereby reducing the impact of the row hammer effect on the storage cells.

[0100] It should be noted that, in this embodiment, before forming the second isolation structure 112, a dense oxide layer (not shown) is formed on the surface of the second isolation trench to repair the surface of the second isolation trench, and then an insulating material is first filled in the second isolation trench to raise the second isolation structure 112, thereby ensuring that the projection of the second isolation structure 112 formed in the first direction X is located within the projection range of the word line gate structure along the first direction X. The second isolation structure 112 is then formed, and the second isolation structure 112 does not fill the second isolation trench completely. The second isolation structure 112 is electrically connected to the corresponding second conductive plug 109, thereby making the second isolation structure 112 electrically connected to the logic circuit wafer 200. After forming the second isolation structure 112, a protective layer 113 is formed on the second isolation structure 112 to fill the second isolation trench completely. The purpose of the second isolation structure 112 not filling up the second isolation groove is to lower the height of the second isolation structure 112 so that the height of the second isolation structure 112 toward the first surface 100a cannot be higher than the height of the subsequently formed initial word line gate structure toward the first surface 100a, thereby ensuring that the projection of the finally formed second isolation structure 112 along the first direction X is within the projection range of the finally formed word line gate structure along the first direction X.

[0101] In this embodiment, the insulating material deposited at the bottom of the second isolation trench is silicon oxide, and the material of the protection layer 113 is silicon nitride.

[0102] In other embodiments, the second isolation structure 112 may also be an insulating structure, and the material of the insulating structure may be silicon oxide or air. When the insulating structure is silicon oxide, it is only necessary to deposit silicon oxide material to fill the second isolation groove; when the insulating structure is air, by adjusting the parameters of the deposition process, the deposited material seals the opening of the second isolation groove, and the interior of the second isolation groove is air. The insulating isolation effect of air is relatively strong, and can effectively improve the isolation effect of the second isolation structure 112.

[0103] Please refer to Figure 22 to Figure 24 , Fig.23 yes Fig. 22 Schematic diagram of the cross section along the MM line, Fig.24 yes Fig.17 In the cross-sectional diagram along the NN line, after the second isolation structure 112 is formed, two separate word line gate structures 114 are formed in each word line gate trench, and the two word line gate structures 114 are respectively located on opposite side walls of the word line gate trench along the first direction X.

[0104] It should be noted that, in this embodiment, before forming the word line gate structure 114, the sacrificial layer 111 filled in the word line gate trench needs to be removed, and the word line gate trench needs to be extended to increase the volume of the word line gate trench.

[0105] Please continue to refer to Fig. 22 In the present embodiment, the method for forming the initial word line gate structure 114 in each of the word line gate trenches includes: forming a word line gate dielectric material layer (not shown) on the sidewall and bottom surface of the word line gate trench; removing the word line gate dielectric material layer located on the bottom surface of the word line gate trench; forming a word line gate material layer (not shown) on the surface of the word line gate dielectric material layer and the exposed bottom surface of the word line gate trench; removing the word line gate material layer located on the bottom surface of the word line gate trench; removing a portion of the word line gate material layer located on the sidewall of the word line gate trench to form a first cut-off opening 115 and a second cut-off opening 116, thereby forming two separate word line gate structures 114.

[0106] Please continue to refer to Fig. 22 In this embodiment, the two mutually independent word line gate structures 114 are also located on the opposite side walls of the word line gate trench along the second direction Y; the two first conductive plugs 108 electrically connected to the two mutually independent word line gate structures 114 are distributed on the opposite sides of the word line gate trench along the second direction Y. In this way, the contact area between the first conductive plug 108 and the corresponding word line gate structure 114 is increased, and the electrical contact performance between the first conductive plug 108 and the corresponding word line gate structure 114 is improved.

[0107] In this embodiment, the logic circuit wafer 200 is electrically connected to the word line gate structure 114 through the first conductive plug 108 .

[0108] It should be noted that, in this embodiment, before forming the word line gate structure 114, a dense oxide layer (not shown) is formed on the surface of the word line gate groove to repair the surface of the word line gate groove. After forming the word line gate structure 114, an insulating material is deposited again to fill the word line gate groove. Moreover, the insulating material filling the word line gate groove needs to have a larger etching selectivity with the material of the protective layer 113 filling the second isolation groove, so as to prevent the insulating material filled in the word line gate groove from being etched back, causing etching damage to the protective layer 113, and exposing the second isolation structure 112.

[0109] In this embodiment, the word line gate dielectric material layer is made of silicon oxide, and the word line gate material layer is made of titanium nitride or tungsten.

[0110] In this embodiment, the projection of the second isolation structure 112 finally formed along the first direction X is located within the projection range of the word line gate structure 114 along the first direction X, so as to reduce the influence of the second isolation structure 112 on the adjacent memory cells when a negative voltage is applied. After the wet etching, an insulating material is deposited to fill the word line gate trench and the second isolation trench.

[0111] In this embodiment, the second isolation structure 112 is formed first and then the initial word line gate structure 114 is formed.

[0112] In other embodiments, the initial word line gate structure 114 may be formed first and then the second isolation structure 112 may be formed.

[0113] Please refer to Figure 25 to Figure 26 , Fig.25 is a top view of the insulating material filled on the top of the word line gate trench and the protection layer 113 filled in the second isolation trench; Fig.26 yes Fig.25 In the cross-sectional diagram along line OO, after the word line gate structure 114 is formed, the substrate 105 is implanted with source and drain ions from the second surface 100b to the first surface 100a to form a second source and drain doped layer 117 in each of the active areas 102, and the second surface 100b exposes the second source and drain doped layer 117.

[0114] The second source-drain doped layer 117 is formed by injecting source-drain ions from the second surface 100b to the first surface 100a, which can effectively improve the distribution uniformity of the source-drain ions in the second source-drain doped layer 117, thereby effectively improving the performance of the transistor.

[0115] In this embodiment, after the source and drain ions are implanted, the source and drain ions need to be annealed to form the second source and drain doped layer 117 .

[0116] Please refer to Figures 27 to 30 , Fig. 27 is a top view of the insulating material filled on the top of the word line gate trench and the protection layer 113 filled in the second isolation trench, Fig.28 yes Fig. 27 Schematic diagram of the cross section along the PP line, Fig.29 yes Fig. 27 Schematic diagram of the cross section along the QQ line, Fig.30 yes Fig. 27 In the cross-sectional schematic diagram along line RR, after the second source-drain doped layer 117 is formed, a plurality of capacitor structures 118 are formed on the second surface 100 b , and each of the capacitor structures 118 is electrically connected to a corresponding second source-drain doped layer 117 .

[0117] By placing the process of forming the capacitor structure 118 at the end, it is possible to ensure that a high temperature process is normally used in the process before forming the capacitor structure 118 without causing damage to the capacitor structure 118 .

[0118] In this embodiment, the capacitor structure 118 includes a pillar capacitor (eg Fig.31 As shown), cup capacitors (such as Fig.32 as shown) or a cylinder capacitor (as Fig.33 as shown).

[0119] In this embodiment, before forming the capacitor structure 118 , a fourth conductive plug 119 is formed on the exposed second source-drain doped layer 117 , and the capacitor structure 118 is electrically connected to the corresponding fourth conductive plug 119 .

[0120] In other embodiments, the capacitor structure 118 may also be directly electrically connected to the corresponding second source-drain doped layer 117 .

[0121] Figure 34 to Figure 38 It is a schematic structural diagram of each step of a method for forming a substrate 105 and a bit line layer 106 of a dynamic random access memory architecture in another embodiment of the present invention.

[0122] Please refer to Fig.34 and Fig.35 , Fig.35 yes Fig.34 In the schematic cross-sectional view along line AA, an initial substrate 300 is provided. The initial substrate 300 has the first surface 300 a and the second surface 300 b opposite to each other.

[0123] In this embodiment, the material of the initial substrate 300 is silicon.

[0124] In other embodiments, the material of the initial substrate 300 may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0125] Please refer to Fig.36 , Fig.36 and Fig.35 The first source-drain doped layer 301 is formed in the initial substrate 300 in the same viewing direction.

[0126] In this embodiment, the method for forming the first source-drain doped layer 301 includes: implanting source-drain ions into the substrate 105 from the first surface 300a to the second surface 300b, and annealing the implanted source-drain ions to form the first source-drain doped layer 301 in the active area 102.

[0127] Please refer to Fig.37 After forming the first source-drain doping layer 301, a bit line material layer (not shown) is formed on the first surface 300a; the bit line material layer and the initial substrate 300 are patterned and etched to form a plurality of first isolation trenches 302, the active area 303 is between adjacent first isolation trenches 302, and the bit line material layer forms the bit line layer 304.

[0128] Please refer to Fig.38 After the patterning and etching process, the first isolation structure 305 is formed in the first isolation trench 302, and the substrate 306 is formed.

[0129] In this embodiment, the method for forming the first isolation structure 305 includes: depositing an isolation material layer (not shown), the isolation material layer filling the first isolation trench 302 and being located on the first surface 300a, and planarizing the isolation material layer until the first surface 300a of the substrate 306 is exposed, thereby forming the first isolation structure 305.

[0130] Please continue to refer to Fig.38 In the present embodiment, after forming the substrate 306 and the bit line layer 304, it further includes: etching a portion of the first isolation structure 305 from the first surface 300a to the second surface 300b to form a bit line isolation groove between adjacent active areas 303; and forming a bit line isolation structure 307 in the bit line isolation groove.

[0131] In this embodiment, the bit line isolation structure 307 is a cavity structure. The specific formation process is to adjust the parameters of the deposition process so that the deposited silicon oxide material seals the opening between the adjacent bit line layers 304, thereby forming a cavity structure between the adjacent bit line layers 304. The cavity structure has a strong electrical isolation effect, thereby effectively reducing the crosstalk between the adjacent bit line layers 304.

[0132] Accordingly, a dynamic random access storage architecture is also provided in the embodiment of the present invention, please continue to refer to Figures 27 to 30The dynamic random access memory architecture is formed by the formation method described in any one of the above embodiments, and the dynamic random access memory architecture includes: a substrate 105, the substrate 105 has a first surface 100a and a second surface 100b opposite to each other, the substrate 105 includes a plurality of active regions 102 separated from each other and parallel to a first direction X, and the plurality of active regions 102 are arranged along a second direction Y, and a first isolation trench 101 is provided between adjacent active regions 102, the first isolation trench 101 extends along the first direction X, and the first direction X and the second direction are parallel to each other. Y is vertical, each of the active areas 102 includes a plurality of mutually independent word line areas 1021 and isolation areas 1022, and the word line areas 1021 and the isolation areas 1022 in each of the active areas 102 are arranged at intervals along the first direction X; a first isolation structure 103 is located in the first isolation trench 101; a first source-drain doped layer 104 is located in each of the active areas 102, and the first surface 100a exposes the first source-drain doped layer 104; a word line gate trench is located in each of the word line areas 1021, and the word line gate trench is formed from the first surface 100 a extends from the first surface 100a to the second surface 100b, and the word line gate trench penetrates the active area 102 along the second direction Y; a second isolation trench located in each of the isolation regions 1022, the second isolation trench extends from the first surface 100a to the second surface 100b, and the second isolation trench penetrates the active area 102 along the second direction Y; a second isolation structure 112 located in each of the second isolation trenches; two mutually independent word line gate structures 114 located in each of the word line gate trenches, the two word line gate structures 114 are respectively located in the word line gate trenches; Side walls of the groove opposite to each other along the first direction X; a plurality of bit line layers 106 located on the first surface 100a and parallel to the first direction X, each of the bit line layers 106 being electrically connected to a plurality of the first source-drain doped layers 104 in a corresponding one of the active areas 102; a second source-drain doped layer 117 located in each of the active areas 102, the second surface 100b exposing the second source-drain doped layer 117; a plurality of capacitor structures 118 located on the second surface 100b, each of the capacitor structures 118 being electrically connected to a corresponding one of the second source-drain doped layers 117.

[0133] By placing the process of forming the capacitor structure 118 at the end, it is possible to ensure that a high temperature process is normally used in the process before forming the capacitor structure 118, without causing damage to the capacitor structure 118. In addition, the second source-drain doped layer 117 is formed by injecting source-drain ions from the second surface 100b to the first surface 100a, which can effectively improve the distribution uniformity of source-drain ions in the second source-drain doped layer 117, thereby effectively improving the performance of the transistor.

[0134] In this embodiment, the second isolation structure 112 is a conductive structure, and the material of the conductive structure is titanium nitride. Since the second isolation structure 112 is a conductive structure, a negative voltage can be applied to the second isolation structure 112 so that the second isolation structure 112 can effectively isolate adjacent memory cells arranged along the first direction X, thereby reducing the impact of the row hammer effect on the memory cells.

[0135] In other embodiments, the second isolation structure 112 may also be an insulating structure, and the material of the insulating structure may be silicon oxide or air. When the insulating structure is silicon oxide, it is only necessary to deposit silicon oxide material to fill the second isolation groove; when the insulating structure is air, by adjusting the parameters of the deposition process, the deposited material seals the opening of the second isolation groove, and the interior of the second isolation groove is air. The insulating isolation effect of air is relatively strong, and can effectively improve the isolation effect of the second isolation structure 112.

[0136] In this embodiment, the dynamic random access memory architecture further includes: a metal silicide layer between the first source-drain doped layer 104 and the bit line layer 106. The contact resistance between the bit line layer 106 and the first source-drain doped layer 104 can be effectively reduced by forming the metal silicide layer.

[0137] In this embodiment, the bit line layer 106 is a double-layer structure, and includes a first metal layer and a second metal layer located on the first metal layer, wherein the first metal layer is made of titanium nitride, and the second metal layer is made of tungsten.

[0138] In this embodiment, the dynamic random access memory architecture further includes: a bit line isolation structure 107 located between adjacent bit line layers 106; the bit line isolation structure 107 is a cavity structure. The specific formation process is to adjust the parameters of the deposition process so that the deposited silicon oxide material seals the opening between the adjacent bit line layers 106, thereby forming a cavity structure between the adjacent bit line layers 106. The cavity structure has a strong electrical isolation effect, thereby effectively reducing the crosstalk between the adjacent bit line layers 106.

[0139] In this embodiment, the dynamic random access memory architecture further includes: a logic circuit wafer 200, wherein the logic circuit wafer 200 is bonded to the substrate 105 toward the first surface 100a, and the logic circuit wafer 200 is electrically connected to the bit line layer 106 and the word line gate structure 114 respectively.

[0140] It should be noted that, in this embodiment, the logic circuit wafer 200 is bonded to logically control operations such as reading, writing and refreshing of each storage unit.

[0141] In this embodiment, the second isolation structure 112 is a conductive structure, the logic circuit wafer 200 is electrically connected to the second isolation structure 112 , and the logic circuit wafer 200 further includes an operation of applying a negative voltage to the second isolation structure 112 .

[0142] Please continue to refer to Figure 8 In this embodiment, along the first direction X, the first conductive plug 108 for electrically connecting the word line gate structure 114 and the logic circuit wafer 200 has a first central axis S1, and the second conductive plug 109 for electrically connecting the second isolation structure 112 and the logic circuit wafer 200 has a second central axis S2, and the first central axis S1 coincides with the second central axis S2.

[0143] Please continue to refer to Fig.39 In other embodiments, along the first direction X, the first conductive plug 108 for electrically connecting the word line grid structure 114 and the logic circuit wafer 200 has a first central axis S1, and the second conductive plug 109 for electrically connecting the second isolation structure 112 and the logic circuit wafer 200 has a second central axis S2, and the first central axis S1 does not coincide with the second central axis S2. By staggering the first conductive plug 108 and the second conductive plug 109 along the first direction X, the exposure window for forming the first conductive plug 108 and the second conductive plug 109 can be further increased, thereby increasing the volume of the first conductive plug 108 and the second conductive plug 109 to improve the electrical conductivity.

[0144] In this embodiment, the logic circuit wafer 200 is electrically connected to the bit line layer 106 through a plurality of third conductive plugs 110 .

[0145] In this embodiment, the capacitor structure 118 includes a pillar capacitor (eg Fig.31 As shown), cup capacitors (such as Fig.32 as shown) or a cylinder capacitor (as Fig.33 as shown).

[0146] In this embodiment, the capacitor structure 118 is electrically connected to the corresponding second source-drain doped layer 117 through a fourth conductive plug 119 .

[0147] In other embodiments, the capacitor structure 118 may also be directly electrically connected to the corresponding second source-drain doped layer 117 .

[0148] In this embodiment, the two separate word line gate structures 114 are also located on the opposite side walls of the word line gate trench along the second direction Y; the two second conductive plugs 109 electrically connected to the two separate word line gate structures 114 are distributed on opposite sides of the word line gate trench along the second direction Y. In this way, the contact area between the second conductive plug 109 and the corresponding word line gate structure 114 is increased, and the electrical contact performance between the second conductive plug 109 and the corresponding word line gate structure 114 is improved.

[0149] In this embodiment, the projection of the second isolation structure 112 along the first direction X is located within the projection range of the word line gate structure 114 along the first direction X, thereby reducing the influence of the second isolation structure 112 on adjacent memory cells when a negative voltage is applied.

[0150] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a dynamic random access memory architecture, characterized in that: include: Forming a substrate and a plurality of bit line layers, wherein the substrate has a first surface and a second surface opposite to each other, the substrate comprises a plurality of active areas which are separated from each other and parallel to a first direction, and the plurality of active areas are arranged along a second direction, each of the active areas has a first source-drain doping layer, the first surface exposes the first source-drain doping layer, a first isolation trench is provided between adjacent active areas, a first isolation structure is provided in the first isolation trench, the first isolation trench extends along the first direction, the first direction is perpendicular to the second direction, each of the active areas comprises a plurality of word line areas and isolation areas which are separated from each other, and the word line areas and the isolation areas in each of the active areas are arranged at intervals along the first direction, a plurality of the bit line layers are located on the first surface and parallel to the first direction, and each of the bit line layers is electrically connected to a plurality of the first source-drain doping layers in a corresponding one of the active areas; After forming the substrate and the bit line layer, thinning the substrate from the second surface toward the first surface until the first isolation structure is exposed; After the thinning process, a word line gate trench is formed in each of the word line regions, and a second isolation trench is formed in each of the isolation regions, wherein the word line gate trench and the second isolation trench extend from the first surface to the second surface, and the word line gate trench and the second isolation trench penetrate the active region along the second direction; forming a second isolation structure in each of the second isolation trenches; forming two mutually independent word line gate structures in each of the word line gate trenches, wherein the two word line gate structures are respectively located on opposite side walls of the word line gate trench along the first direction; After forming the word line gate structure, performing source and drain ion implantation from the second surface to the first surface of the substrate to form a second source and drain doped layer in each of the active regions, wherein the second surface exposes the second source and drain doped layer; After the second source-drain doped layer is formed, a plurality of capacitor structures are formed on the second surface, and each of the capacitor structures is electrically connected to a corresponding one of the second source-drain doped layers.

2. The method for forming a dynamic random access memory architecture as claimed in claim 1, wherein: The second isolation structure is a conductive structure.

3. The method for forming a dynamic random access memory architecture as claimed in claim 2, wherein: The material of the conductive structure includes: titanium nitride.

4. The method for forming a dynamic random access memory architecture as claimed in claim 1, wherein: The second isolation structure is an insulating structure.

5. The method for forming a dynamic random access memory architecture as claimed in claim 4, wherein: The materials of the insulating structure include: silicon oxide or air.

6. The method for forming a dynamic random access memory architecture as claimed in claim 1, wherein: The method for forming the substrate and the plurality of bit line layers comprises: providing an initial substrate, the initial substrate having the first surface and the second surface opposite to each other; performing a patterning etching process on the initial substrate to form a plurality of the first isolation trenches, wherein the active area is between adjacent first isolation trenches; forming the first isolation structure in the first isolation trench; after forming the isolation structure, forming the first source-drain doping layer in the active area to form the substrate; after forming the substrate, forming the plurality of bit line layers.

7. The method for forming a dynamic random access memory architecture as claimed in claim 6, wherein: The method for forming the bit line layer includes: performing metallization processing on the first source-drain doped layer exposed on the first surface, so that a portion of the first source-drain doped layer forms a metal silicide layer, and using the metal silicide layer as the bit line layer.

8. The method for forming a dynamic random access memory architecture as claimed in claim 7, wherein: After forming the substrate and before forming the bit line layer, the method further includes: etching a portion of the first isolation structure from the first surface to the second surface to form a bit line isolation groove between adjacent active areas; and forming a bit line isolation structure in the bit line isolation groove.

9. The method for forming a dynamic random access memory architecture as claimed in claim 1, wherein: The method for forming the substrate and the several bit line layers includes: providing an initial substrate, the initial substrate having the first surface and the second surface opposite to each other; forming the first source-drain doped layer in the initial substrate; after forming the source-drain doped layer, forming a bit line material layer on the first surface; performing a patterning etching process on the bit line material layer and the initial substrate to form several first isolation trenches, the active area being between adjacent first isolation trenches, and making the bit line material layer form the bit line layer; after the patterning etching process, forming the first isolation structure in the first isolation trench to form the substrate.

10. The method for forming a dynamic random access memory architecture as claimed in claim 9, wherein: After forming the substrate and the bit line layer, the method further includes: etching a portion of the first isolation structure from the first surface to the second surface to form a bit line isolation groove between adjacent active areas; and forming a bit line isolation structure in the bit line isolation groove.

11. The method for forming a dynamic random access memory architecture as claimed in claim 8 or 10, characterized in that: The bit line isolation structure is a cavity structure.

12. The method for forming a dynamic random access memory architecture as claimed in claim 1, wherein: After forming the bit line layer and before performing the thinning process, the method further includes: providing a logic circuit wafer; bonding the logic circuit wafer to the substrate toward the first surface, wherein the logic circuit wafer is electrically connected to the bit line layer respectively.

13. The method for forming a dynamic random access memory architecture as claimed in claim 12, wherein: After the word line gate structure is formed, the logic circuit wafer is electrically connected to the word line gate structure.

14. The method for forming a dynamic random access memory architecture as claimed in claim 13, wherein: The method for electrically connecting the logic circuit wafer to the word line grid structure comprises: forming a plurality of first conductive plugs before bonding the logic circuit wafer to the substrate, and electrically connecting the first conductive plugs to the corresponding word line grid structures after forming the word line grid structure; and electrically connecting the logic circuit wafer to the first conductive plugs after bonding the logic circuit wafer to the substrate.

15. The method for forming a dynamic random access memory architecture as claimed in claim 14, wherein: The second isolation structure is a conductive structure. After the second isolation structure is formed, the logic circuit wafer is electrically connected to the second isolation structure.

16. The method for forming a dynamic random access memory architecture as claimed in claim 15, wherein: The method in which the logic circuit wafer is also electrically connected to the second isolation structure respectively includes: forming a plurality of second conductive plugs before bonding the logic circuit wafer and the substrate, and after forming the second isolation structure, the second conductive plugs are electrically connected to the corresponding second isolation structures; after bonding the logic circuit wafer and the substrate, the logic circuit wafer is electrically connected to the second conductive plugs.

17. The method for forming a dynamic random access memory architecture as claimed in claim 16, wherein: Along the first direction, the first conductive plug has a first central axis, the second conductive plug has a second central axis, and the first central axis coincides with the second central axis.

18. The method for forming a dynamic random access memory architecture as claimed in claim 16, wherein: Along the first direction, the first conductive plug has a first central axis, the second conductive plug has a second central axis, and the first central axis does not coincide with the second central axis.

19. The method for forming a dynamic random access memory architecture as claimed in claim 14, wherein: The two separate word line gate structures are also located on opposite side walls of the word line gate trench along the second direction; the two first conductive plugs electrically connected to the two separate word line gate structures are distributed on opposite sides of the word line gate trench along the second direction.

20. The method for forming a dynamic random access memory architecture as claimed in claim 1, wherein: A projection of the second isolation structure along the first direction is located within a projection range of the word line gate structure along the first direction.

21. A dynamic random access memory architecture, characterized in that: The dynamic random access memory architecture is formed by a forming method according to any one of claims 1 to 20, and the dynamic random access memory architecture comprises: A substrate, wherein the substrate has a first surface and a second surface opposite to each other, the substrate comprises a plurality of active regions which are separated from each other and parallel to a first direction, and the plurality of active regions are arranged along a second direction, a first isolation trench is provided between adjacent active regions, the first isolation trench extends along the first direction, the first direction is perpendicular to the second direction, each of the active regions comprises a plurality of word line regions and isolation regions which are separated from each other, and the word line regions and the isolation regions in each of the active regions are arranged at intervals along the first direction; a first isolation structure located in the first isolation trench; A first source-drain doped layer located in each of the active regions, the first surface exposing the first source-drain doped layer; A word line gate trench located in each of the word line regions, the word line gate trench extending from the first surface to the second surface, and the word line gate trench penetrating the active region along the second direction; a second isolation trench located in each of the isolation regions, the second isolation trench extending from the first surface to the second surface, and the second isolation trench penetrating the active region along the second direction; a second isolation structure located in each of the second isolation trenches; Two mutually independent word line gate structures located in each of the word line gate trenches, the two word line gate structures are respectively located on opposite side walls of the word line gate trench along the first direction; A plurality of bit line layers located on the first surface and parallel to the first direction, each of the bit line layers being electrically connected to a plurality of the first source-drain doped layers in a corresponding one of the active regions; a second source-drain doped layer located in each of the active regions, the second surface exposing the second source-drain doped layer; A plurality of capacitor structures are located on the second surface, and each of the capacitor structures is electrically connected to a corresponding second source-drain doped layer.

22. The dynamic random access memory architecture of claim 21, wherein: The second isolation structure is a conductive structure.

23. The dynamic random access memory architecture of claim 22, wherein: The material of the conductive structure includes: titanium nitride.

24. The dynamic random access memory architecture of claim 21, wherein: The second isolation structure is an insulating structure.

25. The dynamic random access memory architecture of claim 24, wherein: The materials of the insulating structure include: silicon oxide or air.

26. The dynamic random access memory architecture of claim 21, wherein: Also includes: A bit line isolation structure is located between adjacent bit line layers.

27. The dynamic random access memory architecture of claim 26, wherein: The bit line isolation structure is a cavity structure.

28. The dynamic random access memory architecture of claim 21, wherein: Also includes: A logic circuit wafer is bonded to the substrate toward the first surface, and the logic circuit wafer is electrically connected to the bit line layer and the word line gate structure respectively.

29. The dynamic random access memory architecture of claim 28, wherein: The second isolation structure is a conductive structure, and the logic circuit wafer is electrically connected to the second isolation structure.

30. The dynamic random access memory architecture of claim 28, wherein: Along the first direction, the first conductive plug for electrically connecting the word line gate structure and the logic circuit wafer has a first central axis, and the second conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a second central axis, and the first central axis coincides with the second central axis.

31. The dynamic random access memory architecture of claim 28, wherein: Along the first direction, the first conductive plug for electrically connecting the word line gate structure and the logic circuit wafer has a first central axis, and the second conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a second central axis, and the first central axis does not overlap with the second central axis.

32. The dynamic random access memory architecture of claim 30, wherein: The two separate word line gate structures are also located on opposite side walls of the word line gate trench along the second direction; the two first conductive plugs electrically connected to the two separate word line gate structures are distributed on opposite sides of the word line gate trench along the second direction.

33. The dynamic random access memory architecture of claim 21, wherein: A projection of the second isolation structure along the first direction is located within a projection range of the word line gate structure along the first direction.

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