Semiconductor device, method of manufacturing the same, storage system, and electronic device

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, a storage system and an electronic device. The semiconductor device comprises a stack structure, an array region and a step region. The stack structure comprises a plurality of insulating layers and a plurality of gate functional layers which are stacked and arranged alternately. The stack structure further comprises the array region and the step region located at least one side of the array region. The stack structure has a plurality of steps corresponding to the plurality of gate functional layers in the step region. A gate isolation structure penetrates the stack structure and comprises a first sub-portion extending to the step region. A plurality of conductive columns are arranged in the step region and penetrate the stack structure. Each gate functional layer comprises a gate portion arranged at least in the array region, a first connecting portion arranged at the step, and a second connecting portion connected to the sidewall of the first sub-portion. The second connecting portion is connected between the first connecting portion and the gate portion. The first connecting portion is connected to the corresponding conductive column. The application can simplify the process difficulty, reduce the connection difficulty between the conductive column and the gate portion, and improve the yield of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, a storage system, and an electronic device. Background Technology

[0002] With the development of planar flash memory, semiconductor manufacturing processes have made tremendous progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, limitations of existing development technologies, and limits of storage electron density. Against this backdrop, in order to solve the difficulties encountered by planar flash memory and to pursue lower production costs per unit of storage cell, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D NAND) flash memory and 3D NAND (3D NAND) flash memory.

[0003] Among them, 3D NAND memory, with its small size and large capacity, adopts the design concept of highly integrated storage cells stacked in a three-dimensional pattern to produce memory with high storage density per unit area and high efficiency of storage cell performance. It has become the mainstream process for the design and production of emerging memory.

[0004] However, there are still significant defects in the current gate layer interconnection process of memory, which need to be improved. Summary of the Invention

[0005] This application provides a semiconductor device and its fabrication method, a storage system, and an electronic device, which can reduce the difficulty of connecting the conductive pillars and the gate portion, simplify the process, and improve the yield.

[0006] This application provides a semiconductor device comprising:

[0007] A stacked structure, the stacked structure including a plurality of insulating layers and a plurality of gate functional layers stacked and alternately arranged, the stacked structure further including an array region and a step region located on at least one side of the array region, the stacked structure having a plurality of steps in the step region corresponding to the plurality of gate functional layers respectively;

[0008] A gate isolation structure extends through the stacked structure and includes a first sub-section extending into the stepped region;

[0009] Multiple conductive pillars are disposed in the stepped area and penetrate the stacked structure;

[0010] Each of the gate functional layers includes at least a gate portion disposed in the array region, a first connecting portion disposed at the step, and a second connecting portion connected to the sidewall of the first sub-part. The second connecting portion is connected between the first connecting portion and the gate portion, and the first connecting portion is connected to the corresponding conductive post.

[0011] In some embodiments of this application, the gate functional layer further includes an interlayer dielectric portion disposed in the step region, and the interlayer dielectric portion is adjacent to the first connection portion and the gate portion.

[0012] In some embodiments of this application, the second connection portion is adjacent to the first sub-part and the interlayer medium portion.

[0013] In some embodiments of this application, the first connection portion in one gate functional layer and the interlayer dielectric portion in another gate functional layer are at least partially overlapped along the stacking direction of the stacked structure.

[0014] In some embodiments of this application, the thickness of the first connection portion is greater than the thickness of the interlayer dielectric portion.

[0015] In some embodiments of this application, the first sub-part extends along a first direction, the first direction being the direction from the array region to the step region, and the plurality of steps include a plurality of step groups arranged along a second direction, the second direction intersecting the first direction, and each step group including a plurality of steps arranged along the first direction;

[0016] The step group has a first sub-part on at least one side, and each first connecting part in the step group is connected to a second connecting part on the side wall of the first sub-part.

[0017] In some embodiments of this application, the semiconductor device further includes a channel structure disposed in the array region and extending through the stacked structure, and the gate portion is connected between the channel structure and the second connection portion.

[0018] In some embodiments of this application, the gate isolation structure further includes a second sub-section disposed within the array region, the gate sub-section being adjacent to the channel structure and the second sub-section.

[0019] In some embodiments of this application, the gate isolation structure further includes a third sub-part disposed between the array region and the step region, wherein the width of the third sub-part along a direction perpendicular to the first direction is greater than the width of the first sub-part along a direction perpendicular to the first direction, the first direction being the direction from the array region to the step region, and the width of the third sub-part along a direction perpendicular to the first direction is greater than the width of the second sub-part along a direction perpendicular to the first direction.

[0020] In some embodiments of this application, a plurality of first sub-parts are provided in the step area, a plurality of second sub-parts are provided in the array area, and a plurality of third sub-parts are provided between the array area and the step area. The array area includes a plurality of storage blocks, and a third sub-part is connected along the first direction between a first sub-part and a second sub-part, and is located between two adjacent storage blocks.

[0021] In some embodiments of this application, the gate isolation structure is beaded in a transverse section perpendicular to the stacking direction of the stacked structure along the extending direction of the gate isolation structure.

[0022] In some embodiments of this application, at least one of the conductive posts passes through a corresponding step and is connected to the first connecting portion at the corresponding step.

[0023] In accordance with the above-mentioned objectives of this application, embodiments of this application also provide a method for fabricating a semiconductor device, comprising the following steps:

[0024] Multiple insulating layers and multiple interlayer dielectric layers are stacked and alternately formed to form a stacked structure, the stacked structure including an array region and a step region located on at least one side of the array region, the stacked structure having multiple steps in the step region corresponding to the multiple interlayer dielectric layers respectively;

[0025] The interlayer dielectric layers are replaced with gate functional layers, and each gate functional layer has at least a gate portion located in the array region, a first connection portion located at the step, and a second connection portion connected between the gate portion and the first connection portion.

[0026] A gate isolation structure is formed that extends through the stacked structure, wherein a first sub-part is formed in the gate isolation structure that extends to the stepped region, and a second connecting part is connected to the sidewall of the first sub-part;

[0027] Multiple conductive pillars are formed in the stepped area and through the stacked structure, and the conductive pillars are connected to the corresponding first connecting portions.

[0028] In some embodiments of this application, the step of forming a plurality of stacked and alternating insulating layers and a plurality of interlayer dielectric layers to form a stacked structure includes:

[0029] A first sacrificial portion is formed at the step, located on the interlayer medium layer;

[0030] A plurality of gate isolation vias, channel vias, and step connection vias are formed through the stacked structure. The gate isolation vias are located at least in the array region and the step region, the channel vias are located in the array region, and the step connection vias are located in the step region, with at least one step connection via passing through a corresponding step.

[0031] A second sacrificial portion is formed within the gate isolation hole, the channel hole, and the step connection hole.

[0032] In some embodiments of this application, the step of replacing the plurality of interlayer dielectric layers with gate functional layers further includes:

[0033] The second sacrificial portion within the gate isolation hole is removed, and the plurality of gate isolation holes include a plurality of gate isolation hole groups, wherein a plurality of gate isolation holes arranged along a first direction are formed within the gate isolation hole group, the first direction being the direction from the array region to the step region;

[0034] Remove the insulating layer and the interlayer dielectric layer on the inner wall of the gate isolation hole to connect the plurality of gate isolation holes in the gate isolation hole group to form a first gate isolation trench located in the step region and a second gate isolation trench located in the array region;

[0035] The interlayer dielectric layer connected to the first gate isolation trench is replaced with the second connection portion, and the first sacrificial portion and the interlayer dielectric layer at the step are replaced with the connection portion. The interlayer dielectric layer of the array region is replaced with the gate portion through the second gate isolation trench.

[0036] In some embodiments of this application, the step of removing the insulating layer and the interlayer dielectric layer at the inner wall of the gate isolation via further includes:

[0037] A third gate isolation trench is formed between the array region and the step region, and the third gate isolation trench is connected between a first gate isolation trench and a second gate isolation trench along the first direction;

[0038] A third sub-section is formed within the third gate isolation trench to isolate the first gate isolation trench and the second gate isolation trench.

[0039] In some embodiments of this application, the step of forming a gate isolation structure throughout the stacked structure includes:

[0040] The first sub-part is formed in the first gate isolation trench and the second sub-part is formed in the second gate isolation trench to form the gate isolation structure.

[0041] In some embodiments of this application, the step of forming a plurality of conductive pillars located in the stepped region and penetrating the stacked structure includes:

[0042] Remove the second sacrificial portion from the stepped connecting hole;

[0043] The conductive post is formed in the step connection hole, and at least one of the conductive posts passes through a corresponding step and is connected to the first connection part at the corresponding step.

[0044] In accordance with the above objectives of this application, embodiments of this application also provide a storage system, the storage system including a controller and the semiconductor device, the controller being coupled to the semiconductor device and used to control the semiconductor device to store data.

[0045] In accordance with the above objectives of this application, embodiments of this application also provide an electronic device that includes the storage system.

[0046] This application provides a semiconductor device and its fabrication method, a memory system, and an electronic device. By providing a first connection portion at each step and a second connection portion connecting the first connection portion and the gate portion on the sidewall of the first sub-part, the conductive pillar can directly penetrate the stacked structure and connect with the first connection portion. This enables the conductive pillar to connect to the gate portion in the corresponding gate functional layer. Furthermore, in this application, the conductive pillar is designed to penetrate the stacked structure, eliminating the need for the conductive pillar to terminate at a corresponding step. This simplifies the manufacturing process, reduces the connection difficulty between the conductive pillar and the gate portion, and improves the yield of the semiconductor device. Attached Figure Description

[0047] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0048] Figure 1 A schematic diagram of a planar structure of a semiconductor device provided for some embodiments of this application;

[0049] Figure 2 Semiconductor devices provided for some embodiments of this application Figure 1 A schematic diagram of a cross-sectional structure of line A-A' in the middle;

[0050] Figure 3 Semiconductor devices provided for some embodiments of this application Figure 1 A schematic diagram of a cross-sectional structure of line B-B' in the middle;

[0051] Figure 4 A flowchart illustrating a method for fabricating a semiconductor device provided for some embodiments of this application;

[0052] Figures 5 to 15 A schematic diagram of the fabrication process of a semiconductor device provided for some embodiments of this application;

[0053] Figure 16 A schematic diagram of the structure of a storage system provided for some embodiments of this application;

[0054] Figure 17 This is a schematic diagram of the structure of an electronic device provided for some embodiments of this application. Detailed Implementation

[0055] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0056] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0057] This application provides a semiconductor device. Please refer to the embodiments thereof. Figure 1 , Figure 2 as well as Figure 3 The semiconductor device includes a stacked structure 10, a gate isolation structure 20, and a plurality of conductive pillars 30.

[0058] The stacked structure 10 includes a plurality of insulating layers 12 stacked and alternately arranged and a plurality of gate functional layers 11. The stacked structure 10 also includes an array region 101 and a step region 102 located on at least one side of the array region 101. The stacked structure 10 has a plurality of steps 110 in the step region 102 that are respectively corresponding to the plurality of gate functional layers 11. The gate isolation structure 20 penetrates the stacked structure 10 and includes a first sub-part 21 extending to the step region 102. A plurality of conductive pillars 30 are disposed in the step region 102 and penetrate the stacked structure 10.

[0059] Furthermore, each gate functional layer 11 includes at least a gate portion 111 disposed in the array region 101, a first connection portion 112 disposed at the step 110, and a second connection portion 113 connected to the side wall of the first sub-part 21. The second connection portion 113 is connected between the first connection portion 112 and the gate portion 111, and the first connection portion 112 is connected to the corresponding conductive post 30.

[0060] Continuing from the above, this embodiment of the application provides a first connecting portion 112 at each step 110 and a second connecting portion 113 connecting the first connecting portion 112 and the gate portion 111 on the side wall of the first sub-part 21. Thus, the conductive post 30 can directly penetrate the stacked structure 10 and connect with the first connecting portion 112, thereby enabling the conductive post 30 to connect to the gate portion 111 in the corresponding gate functional layer 11. Furthermore, in this embodiment of the application, the conductive post 30 is provided to penetrate the stacked structure 10, eliminating the need for the conductive post 30 to terminate at the corresponding step 110. This simplifies the manufacturing process, reduces the connection difficulty between the conductive post 30 and the gate portion 111, and improves the yield of semiconductor devices.

[0061] Specifically, please continue to combine Figure 1 , Figure 2 ,as well as Figure 3 In some embodiments, the semiconductor device includes a substrate 50, a stacked structure 10 disposed on the substrate 50, and the stacked structure 10 includes an array region 101, a step region 102 located on at least one side of the array region 101, and a transition region 103 located between the array region 101 and the step region 102.

[0062] The substrate 50 can be a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator), or GOI (Germanium On Insulator), etc. In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as SiC, and can also be a stacked structure, such as Si / SiGe, etc.

[0063] The stacked structure 10 includes a plurality of gate functional layers 11 and a plurality of insulating layers 12 stacked and alternately disposed on the substrate 50. Further, the stacked structure 10 also includes a plurality of steps 110 disposed in the step region 102, and the plurality of steps 110 are disposed in a one-to-one correspondence with the plurality of gate functional layers 11. The material of the insulating layer 12 can be silicon oxide.

[0064] The semiconductor device also includes a plurality of channel structures 40 disposed in the array region 101, and the plurality of channel structures 40 penetrate the stacked structure 10. The channel structure 40 may include a charge storage layer, a tunneling layer and a channel layer in sequence from the outside to the inside. In some embodiments, the material of the tunneling layer may be silicon oxide, the material of the charge storage layer may be silicon nitride or silicon oxynitride, and the material of the channel layer may be polysilicon.

[0065] In some embodiments, the semiconductor device further includes a plurality of virtual channel structures 41 disposed in the transition region 103, and the virtual channel structures 41 can be used to buffer stress and improve the reliability of the semiconductor device. The virtual channel structures 41 are not used for electrical connection functions or storage functions.

[0066] Within the step region 102 of the semiconductor device, multiple steps 110 are arranged in an array along a first direction X and a second direction Y, wherein the first direction X is the direction from the array region 101 to the step region 102, and the second direction Y intersects with the first direction X.

[0067] In some embodiments, the first direction X is perpendicular to the second direction Y.

[0068] The semiconductor device also includes a gate isolation structure 20 that extends through the stacked structure 10 and along the first direction X from the array region 101 to the step region 102; specifically, the gate isolation structure 20 includes a first sub-section 21 located in the step region 102, a second sub-section 22 located in the array region 101, and a third sub-section 23 located in the transition region 103, and the first sub-section 21, the second sub-section 22, and the third sub-section 23 all extend along the first direction X.

[0069] The width of the third sub-part 23 along the first direction X is greater than the width of the first sub-part 21 along the first direction X, and the width of the third sub-part 23 along the first direction X is greater than the width of the second sub-part 22 along the first direction X; and the gate isolation structure 20 is beaded in the transverse section perpendicular to the stacking direction of the stacked structure 10 along the extension direction of the gate isolation structure 20.

[0070] In some embodiments, the array region 101 includes a plurality of storage blocks arranged along the second direction Y, a third sub-section 23 is connected between a first sub-section 21 and a second sub-section 22 along the first direction X, and is located between two adjacent storage blocks; further, the second sub-section 22 not connected to the third sub-section 23 is located within each storage block, and each storage block can be divided into at least two sub-blocks, and the first sub-section 21 not connected to the third sub-section 23 is located between two adjacent rows of steps 110 arranged along the second direction Y.

[0071] In some embodiments, the gate functional layer 11 includes a gate portion 111 located in the array region 101 and the transition region 103, a first connection portion 112 located in the step region 102, and a second connection portion 113 located in the step region 102 and the transition region 103; wherein, the gate portion 111 is connected to the sidewall of the channel structure 40 and the second sub-portion 22, the first connection portion 112 is located at the step 110, the second connection portion 113 is connected to the sidewall of the first sub-portion 21, and the second connection portion 113 is also connected to the first connection portion 112. The second connection portion 113 is connected to the gate portion 111 on the side of the step region 102 near the transition region 103, and the second connection portion 113 is connected between the gate portion 111 and the first connection portion 112.

[0072] It should be noted that a first connecting part 112 is provided at each step 110, and the first sub-part 21 penetrates multiple steps 110. Then, a second connecting part 113 corresponding to each step 110 is connected to the side wall of the first sub-part 21. This allows the first connecting part 112 at the step 110 in each gate functional layer 11 to be connected to the gate part 111 in the gate functional layer 11 through the second connecting part 113, so that the gate part 111 in each gate functional layer 11 can be connected to the corresponding step 110 through the second connecting part 113.

[0073] In some embodiments, the plurality of steps 110 include a plurality of step groups arranged along the second direction Y, and each step group includes a plurality of steps 110 arranged along the first direction X; wherein, at least one side of the step group is provided with a first sub-part 21, and each first connecting part 112 in the step group is connected to a second connecting part 113 at the side wall of the first sub-part 21.

[0074] Furthermore, the semiconductor device also includes a plurality of conductive pillars 30 disposed in the step region 102, and at least one conductive pillar 30 is disposed at each step 110. The conductive pillars 30 at each step 110 penetrate the stacked structure 10 along the stacking direction of the stacked structure 10 and are connected to the first connection portion 112 at the corresponding step 110, so that each conductive pillar 30 is connected to the gate portion 111 in the corresponding gate functional layer 11 through the first connection portion 112 and the second connection portion 113. In this way, the signal can be selectively transmitted to the gate portion 111 of each gate functional layer 11 through the plurality of conductive pillars 30, and then the signal can be transmitted to the corresponding channel structure 40 through the gate portion 111.

[0075] In some embodiments, the gate portion 111, the first connection portion 112, and the second connection portion 113 can all be a stacked structure of a high-k dielectric layer, an adhesive layer, and a metal material layer. The high-k dielectric layer can be made of alumina or zirconium oxide, the adhesive layer can be made of titanium nitride, the metal material layer can be made of tungsten, and the conductive pillar 30 can also be made of tungsten. It should be noted that the high-k dielectric layer can also be omitted, such as... Figure 2 As shown, the first connecting part 112 and the second connecting part 113 are a stacked structure of an adhesive layer and a metal material layer.

[0076] In some embodiments, the gate functional layer 11 further includes at least an interlayer dielectric portion 114 disposed in the step region 102, the interlayer dielectric portion 114 being adjacent to the first connection portion 112 and the gate portion 111, and the second connection portion 113 being adjacent to the first sub-portion 21 and the interlayer dielectric portion 114; wherein the thickness of the first connection portion 112 is greater than the thickness of the interlayer dielectric portion 114.

[0077] In the plurality of gate functional layers 11 arranged along the stacking direction of the stacked structure 10, the first connection portion 112 of one gate functional layer 11 and the interlayer dielectric portion 114 of another gate functional layer 11 at least partially overlap along the stacking direction of the stacked structure 10. That is, the orthographic projection of the first connection portion 112 of one gate functional layer 11 on the substrate 50 is located within the orthographic projection of the interlayer dielectric portion 114 of another gate functional layer 11 on the substrate 50. As a result, the conductive post 30 at each step 110, in addition to passing through and connecting to the first connection portion 112 at the corresponding step 110, also passes through the interlayer dielectric portion 114 of other gate functional layers 11 in the stacking direction of the stacked structure 10. Thus, the conductive post 30 at each step 110 is electrically connected only to the gate portion 111 in the gate functional layer 11 corresponding to that step 110.

[0078] It should be noted that in some embodiments, the substrate 50 in the semiconductor device can be removed as needed in subsequent processes. As a result, since the conductive pillar 30 penetrates the stacked structure 10, signal input can be made from either or both sides of the stacked structure 10.

[0079] It is understood that, in this embodiment of the application, by providing a second connection portion 113 on the sidewall of the first sub-part 21 of the gate isolation structure 20 corresponding to each gate functional layer 11, and providing a first connection portion 112 connected to the second connection portion 113 at each step 110, and the second connection portion 113 can extend to the side of the step region 102 near the array region 101 and connect to the gate portion 111, the conductive pillar 30 can directly penetrate the stacked structure 10 to achieve electrical connection between the conductive pillar 30 and the gate portion 111 of the corresponding gate functional layer 11. Compared with related technologies, this is a significant improvement. In contrast to the requirement in the SCT process that each conductive post 30 needs to terminate at the corresponding step 110, and the requirement in the SCT process that the gate and conductive post need to extend towards each other to achieve contact, this reduces the difficulty of opening the conductive post 30 and the difficulty of connecting the conductive post 30 to the corresponding gate portion 111, thus simplifying the process and improving the yield and stability of the semiconductor device. At the same time, compared to the requirement in the SCT process to set a large area of ​​opening at each step to form the conductive post, the embodiments of this application can also reduce the area of ​​the opening of the conductive post 30 to improve the area utilization of the semiconductor device.

[0080] In summary, this embodiment of the application provides a first connecting portion 112 at each step 110 and a second connecting portion 113 connecting the first connecting portion 112 and the gate portion 111 on the side wall of the first sub-part 21. As a result, the conductive post 30 can directly penetrate the stacked structure 10 and connect with the first connecting portion 112, thus enabling the conductive post 30 to connect to the gate portion 111 in the corresponding gate functional layer 11. Furthermore, in this embodiment, the conductive post 30 is provided to penetrate the stacked structure 10, eliminating the need for the conductive post 30 to terminate at the corresponding step 110. This simplifies the manufacturing process, reduces the connection difficulty between the conductive post 30 and the gate portion 111, and improves the yield of semiconductor devices.

[0081] In addition, this application embodiment also provides a method for manufacturing a semiconductor device, which includes the following steps:

[0082] Multiple insulating layers and multiple interlayer dielectric layers are stacked and alternated to form a stacked structure. The stacked structure includes an array region and a step region located on at least one side of the array region. The stacked structure has multiple steps in the step region that correspond to the multiple interlayer dielectric layers respectively.

[0083] Multiple interlayer dielectric layers are replaced with gate functional layers, and each gate functional layer has at least a gate portion located in the array region, a first connection portion located at the step, and a second connection portion connected between the gate portion and the first connection portion.

[0084] A gate isolation structure is formed that runs through the stacked structure. A first sub-part is formed in the gate isolation structure that extends to the step region, and a second connecting part is connected to the sidewall of the first sub-part.

[0085] Multiple conductive pillars are formed in the stepped area and through the stacked structure, and the conductive pillars are connected to the corresponding first connecting parts.

[0086] Specifically, please combine Figure 1 , Figure 2 , Figure 3 , Figure 4 as well as Figures 5 to 14 The method for fabricating a semiconductor device provided in this application includes the following steps:

[0087] Step S10: Form a plurality of stacked and alternating insulating layers 12 and a plurality of interlayer dielectric layers 13 to form a stacked structure 10. The stacked structure 10 includes an array region 101 and a step region 102 located on at least one side of the array region 101. The stacked structure 10 forms a plurality of steps 110 in the step region 102 that correspond to the plurality of interlayer dielectric layers 13 respectively.

[0088] In step S10, a substrate 50 is provided. The substrate 50 can be a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator), or GOI (Germanium On Insulator), etc. In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as SiC, and can also be a stacked structure, such as Si / SiGe, etc.

[0089] Multiple insulating layers 12 and interlayer dielectric layers 13 are stacked and alternately formed on a substrate 50 to form a stacked structure 10. The stacked structure 10 includes an array region 101, a step region 102 located on at least one side of the array region 101, and a transition region 103 located between the array region 101 and the step region 102. The multiple insulating layers 12 and the multiple interlayer dielectric layers 13 are etched to form multiple steps 110 corresponding to the multiple interlayer dielectric layers 13 in the step region 102.

[0090] In some embodiments, the insulating layer 12 may be made of silicon oxide, and the interlayer dielectric layer 13 may be made of silicon nitride.

[0091] Next, a first sacrificial portion 14 is formed at each step 110 on the interlayer dielectric layer 13; in some embodiments, the material of the first sacrificial portion 14 may be polycrystalline silicon.

[0092] Then, an insulating dielectric layer 15 is formed covering multiple steps 110, such as... Figure 5 As shown, and in some embodiments, the material of the insulating dielectric layer 15 may include silicon oxide.

[0093] Next, a plurality of gate isolation vias 201, channel vias 401, dummy channel vias 410, and step connection vias 301 are formed in a through-thrust stacked structure 10. Gate isolation vias 201 are located at least in the array region 101 and the step region 102. Channel vias 401 are located in the array region 101. Dummy channel vias 410 are located in the transition region 103. Step connection vias 301 are located in the step region 102, and at least one step connection via 301 passes through a corresponding step 110, such as... Figure 6 As shown.

[0094] Then, a second sacrificial portion 31 is formed in the gate isolation hole 201, the channel hole 401, the virtual channel hole 410, and the step connection hole 301.

[0095] A capping layer 16 is formed on the side of the stacked structure 10 and the insulating dielectric layer 15 away from the substrate 50, such as Figure 7 As shown; in some embodiments, the material of the capping layer 16 may include polycrystalline silicon.

[0096] Step S20: Replace the multiple interlayer dielectric layers 13 with gate functional layers 11. Each gate functional layer 11 has at least a gate portion 111 located in the array region 101, a first connection portion 112 located at the step 110, and a second connection portion 113 connected between the gate portion 111 and the first connection portion 112.

[0097] In step S20, the second sacrificial portion 31 in the channel hole 401 can be removed first, and then a channel structure 40 can be formed in the channel hole 401. Specifically, a charge storage layer, a tunneling layer and a channel layer can be formed in the channel hole 401 in sequence. In some embodiments, the material of the tunneling layer can be silicon oxide, the material of the charge storage layer can be silicon nitride or silicon oxynitride, and the material of the channel layer can be polycrystalline silicon.

[0098] Next, the second sacrificial portion 31 within the gate isolation via 201 is removed, as follows: Figure 8 As shown; and the plurality of gate isolation holes 201 include a plurality of gate isolation hole groups, wherein a plurality of gate isolation holes 201 arranged along a first direction X are formed in the gate isolation hole groups, the first direction X being the direction from the array region 101 to the step region 102.

[0099] The insulating layer 12 and the interlayer dielectric layer 13 at the inner wall of the gate isolation via 201 are removed, thereby enlarging the aperture of the gate isolation via 201, such as... Figure 9As shown, this interconnects multiple gate isolation holes 201 within the gate isolation hole group to form a first gate isolation trench 2021 located in the step region 102, a second gate isolation trench 2022 located in the array region 101, and a third gate isolation trench 2023 located in the transition region 103. The third gate isolation trench 2023 is connected along the first direction X between a first gate isolation trench 2021 and a second gate isolation trench 2022, as shown. Figure 10 As shown; it should be noted that one of the first gate isolation trenches 2021 can correspond to one gate isolation hole group, one of the second gate isolation trenches 2022 can correspond to one gate isolation hole group, and one of the third gate isolation trenches 2023 can correspond to one gate isolation hole group.

[0100] It is understood that the array region 101 includes a plurality of storage blocks arranged along the second direction Y, a third sub-section 23 is connected along the first direction X between a first sub-section 21 and a second sub-section 22, and is located between two adjacent storage blocks; further, the second sub-section 22 not connected to the third sub-section 23 is located within each storage block, and can divide each storage block into at least two sub-blocks, and the first sub-section 21 not connected to the third sub-section 23 is located between two adjacent rows of steps 110 arranged along the second direction Y.

[0101] Between two adjacent memory blocks, a third sub-section 23 is formed within the third gate isolation trench 2023 to separate the first gate isolation trench 2021 and the second gate isolation trench 2022, as shown below. Figure 11 As shown.

[0102] Then, the portion of the interlayer dielectric layer 13 connected to the first gate isolation trench 2021 is replaced with the second connection portion 113 through the first gate isolation trench 2021, and the first sacrificial portion 14 and the interlayer dielectric layer 13 at the step 110 are replaced with the first connection portion 112. The interlayer dielectric layer 13 of the array region 101 is replaced with the gate portion 111 through the second gate isolation trench 2022. Figure 12 and Figure 13 As shown.

[0103] It should be noted that, since forming the gate portion 111 requires at least the removal of all interlayer dielectric layers 13 within the array region 101, while forming the first connection portion 112 and the second connection portion 113 only requires the removal of a portion of the interlayer dielectric layer 13 adjacent to the first gate isolation trench 2021, the amount of etchant required for the two is different, and the composition may also be different. Therefore, two separate etch replacement processes are required. In this embodiment, the third sub-portion 23 is filled with the third gate isolation trench 2023 in advance to isolate the first gate isolation trench 2021 and the second gate isolation trench 2022, so as to provide the prerequisite for two separate etching processes and avoid one etch replacement process from affecting the other etch replacement process.

[0104] For example, the interlayer dielectric layer 13 connected to the first gate isolation trench 2021 can be replaced with the second connection portion 113 through the first gate isolation trench 2021, and the first sacrificial portion 14 and the interlayer dielectric layer 13 at the step 110 can be replaced with the first connection portion 112. Then, the interlayer dielectric layer 13 of the array region 101 can be replaced with the gate portion 111 through the second gate isolation trench 2022. Alternatively, the interlayer dielectric layer 13 of the array region 101 can be replaced with the gate portion 111 through the second gate isolation trench 2022, and the interlayer dielectric layer 13 connected to the first gate isolation trench 2021 can be replaced with the second connection portion 113 through the first gate isolation trench 2021, and the first sacrificial portion 14 and the interlayer dielectric layer 13 at the step 110 can be replaced with the first connection portion 112.

[0105] It should be noted that during the process of replacing the portion of the interlayer dielectric layer 13 connected to the first gate isolation trench 2021 with the second connection portion 113 through the first gate isolation trench 2021, and replacing the first sacrificial portion 14 and the interlayer dielectric layer 13 at the step 110 with the first connection portion 112, the first sacrificial portion 14 and the capping layer 16 at the step 110 are selectively removed by the etching solution. Since the first sacrificial portion 14 is removed, the etching solution will be applied to the entire upper surface of the interlayer dielectric layer 13 at the step 110, so the interlayer dielectric layer 13 at the step 110 can be etched away. However, the contact area between the interlayer dielectric layer 13 at the sidewall of the first gate isolation trench 2021 and the etching solution is small, so only a portion of the interlayer dielectric layer 13 is etched away.

[0106] Step S30: A gate isolation structure 20 is formed through the stacked structure 10. A first sub-part 21 extending to the step region 102 is formed in the gate isolation structure 20. A second connecting part 113 is connected to the sidewall of the first sub-part 21.

[0107] In step S30, a first sub-part 21 is formed in the first gate isolation trench 2021, and a second sub-part 22 is formed in the second gate isolation trench 2022. The first sub-part 21, the second sub-part 22, and the third sub-part 23 together form the gate isolation structure 20. Figure 14 As shown.

[0108] In some embodiments, the first sub-part 21 includes a silicon nitride layer covering the inner wall of the first gate isolation trench 2021 and a silicon material layer filling the first gate isolation trench 2021; the second sub-part 22 includes a silicon nitride layer covering the inner wall of the second gate isolation trench 2022 and a silicon material layer filling the second gate isolation trench 2022; and the third sub-part 23 includes a silicon nitride layer covering the inner wall of the third gate isolation trench 2023 and a silicon material layer filling the third gate isolation trench 2023.

[0109] The gate portion 111 is connected between the channel structure 40 and the second sub-portion 22, and the second connecting portion 113 is connected between the first sub-portion 21 and the first connecting portion 112.

[0110] It should be noted that the portion of the interlayer dielectric layer 13 that is not etched and replaced forms the interlayer dielectric portion 114, and the interlayer dielectric portion 114 can be distributed in the step region 102 and the transition region 103. The interlayer dielectric portion 114 is adjacent to the first connection portion 112 and the gate portion 111, and the second connection portion 113 is adjacent to the first sub-portion 21 and the interlayer dielectric portion 114. Since the first connection portion 112 is obtained by removing the first sacrificial portion 14 and the interlayer dielectric layer 13 at the step 110, the thickness of the first connection portion 112 is greater than the thickness of the interlayer dielectric portion 114.

[0111] Since it is not necessary to remove all the interlayer dielectric layers 13 in the step region 102 in this embodiment, it is possible to avoid the drastic stress changes caused by the complete removal of the interlayer dielectric layers 13 in the step region 102, which would result in large bending of the semiconductor device and improve the yield and stability of the semiconductor device.

[0112] Step S40: A plurality of conductive pillars 30 are formed in the step area 102 and through the stacked structure 10, and the conductive pillars 30 are connected to the corresponding first connecting parts 112.

[0113] In step S40, the second sacrificial portion 31 within the stepped connecting hole 301 is removed, such as... Figure 15 As shown.

[0114] A conductive post 30 is formed within the stepped connecting hole 301, and at least one conductive post 30 passes through a corresponding step 110 and is connected to the first connecting portion 112 at the corresponding step 110, such as... Figure 2 As shown.

[0115] In a plurality of gate functional layers 11 arranged along the stacking direction of the stacked structure 10, the first connection portion 112 of one gate functional layer 11 and the interlayer dielectric portion 114 of another gate functional layer 11 at least partially overlap along the stacking direction of the stacked structure 10. That is, the orthographic projection of the first connection portion 112 of one gate functional layer 11 on the substrate 50 is located within the orthographic projection of the interlayer dielectric portion 114 of another gate functional layer 11 on the substrate 50. This makes the conductive post 30 at each step 110 pass through and connect to the first connection portion 112 at the corresponding step 110, and also pass through the interlayer dielectric portion 114 of other gate functional layers 11 in the stacking direction of the stacked structure 10. Thus, the conductive post 30 at each step 110 is electrically connected only to the gate portion 111 in the gate functional layer 11 corresponding to that step 110.

[0116] Continuing from the above, this embodiment of the application provides a first connecting portion 112 at each step 110 and a second connecting portion 113 connecting the first connecting portion 112 and the gate portion 111 on the sidewall of the first sub-part 21. This allows the conductive pillar 30 to directly penetrate the stacked structure 10 and connect with the first connecting portion 112, thus enabling the conductive pillar 30 to connect to the gate portion 111 in the corresponding gate functional layer 11. Compared to related technologies where each conductive pillar 30 needs to terminate at the corresponding step 110 and where the gate and conductive pillar need to extend towards each other to achieve contact in the SCT process, this simplifies the process and reduces the connection difficulty between the conductive pillar 30 and the gate portion 111, improving the yield of semiconductor devices. Furthermore, this embodiment of the application can form high aspect ratio channel vias 401, gate isolation vias 201, step connecting vias 301, and virtual channel vias 410 in the same process, reducing the need for high aspect ratio hole processes in semiconductor manufacturing, effectively simplifying the process difficulty of semiconductor device manufacturing, and reducing process costs.

[0117] In accordance with the above-mentioned objectives of this application, embodiments of this application also provide a storage system, please refer to... Figure 16 The storage system 60 includes a controller 61 and a semiconductor device 62 as described in the above embodiments. The controller 61 is coupled to the semiconductor device 62 and is used to control the semiconductor device 62 to store data. The semiconductor device 62 is a semiconductor device manufactured by the semiconductor device manufacturing method described in the above embodiments or a semiconductor device described in the above embodiments.

[0118] Specifically, controller 61 can control semiconductor device 62 via channel CH, and semiconductor device 62 can perform operations based on the control of controller 61 in response to requests from host 70. Semiconductor device 62 can receive commands CMD and addresses ADDR from controller 61 via channel CH and access the region selected from the memory array in response to that address. In other words, semiconductor device 62 can perform internal operations corresponding to commands on the region selected by the address.

[0119] In some embodiments, the storage system 60 may be implemented as including, but not limited to, a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC and Micro MMC, a Secure Digital Card in the form of SD, Mini SD and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0120] Specifically, the aforementioned storage system 60 can be used in terminal products such as computers, televisions, set-top boxes, and in-vehicle systems.

[0121] Further, please refer to Figure 17 Some embodiments of this application also provide an electronic device 80, which includes a storage system 81, and the storage system 81 is the storage system described in the above embodiments of this application. Specifically, the electronic device 80 may include, but is not limited to, any device capable of storing data such as a mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device, power bank, etc.

[0122] An electronic device provided by some embodiments of this application has the same beneficial effects as the storage system described above due to the inclusion of the storage system provided by some embodiments of this application.

[0123] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0124] The foregoing has provided a detailed description of a semiconductor device and its fabrication method, a storage system, and an electronic device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, include: A stacked structure, the stacked structure including a plurality of insulating layers and a plurality of gate functional layers stacked and alternately arranged, the stacked structure further including an array region and a step region located on at least one side of the array region, the stacked structure having a plurality of steps in the step region corresponding to the plurality of gate functional layers respectively; A gate isolation structure extends through the stacked structure and includes a first sub-section extending into the stepped region; Multiple conductive pillars are disposed in the stepped area and penetrate the stacked structure; Each of the gate functional layers includes at least a gate portion disposed in the array region, a first connecting portion disposed at the step, and a second connecting portion connected to the sidewall of the first sub-part. The second connecting portion is connected between the first connecting portion and the gate portion, and the first connecting portion is connected to the corresponding conductive post.

2. The semiconductor device according to claim 1, characterized in that, The gate functional layer further includes an interlayer dielectric portion disposed in the step region, and the interlayer dielectric portion is adjacent to the first connection portion and the gate portion.

3. The semiconductor device according to claim 2, characterized in that, The second connecting portion is adjacent to the first sub-part and the interlayer medium portion.

4. The semiconductor device according to claim 2, characterized in that, The first connection portion in one gate functional layer and the interlayer dielectric portion in another gate functional layer are disposed in at least partially overlapping each other along the stacking direction of the stacked structure.

5. The semiconductor device according to claim 2, characterized in that, The thickness of the first connecting portion is greater than the thickness of the interlayer medium portion.

6. The semiconductor device according to claim 1, characterized in that, The first sub-part extends along a first direction, which is the direction from the array region to the step region. The plurality of steps include a plurality of step groups arranged along a second direction, which intersects with the first direction. Each step group includes a plurality of steps arranged along the first direction. The step group has a first sub-part on at least one side, and each first connecting part in the step group is connected to a second connecting part on the side wall of the first sub-part.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a channel structure disposed in the array region and extending through the stacked structure, and the gate portion is connected between the channel structure and the second connection portion.

8. The semiconductor device according to claim 7, characterized in that, The gate isolation structure further includes a second sub-section disposed within the array region, the gate section being adjacent to the channel structure and the second sub-section.

9. The semiconductor device according to claim 8, characterized in that, The gate isolation structure further includes a third sub-part disposed between the array region and the step region. The width of the third sub-part along a direction perpendicular to the first direction is greater than the width of the first sub-part along a direction perpendicular to the first direction. The first direction is the direction from the array region to the step region. The width of the third sub-part along a direction perpendicular to the first direction is greater than the width of the second sub-part along a direction perpendicular to the first direction.

10. The semiconductor device according to claim 9, characterized in that, The stepped area is provided with a plurality of first sub-parts, the array area is provided with a plurality of second sub-parts, and a plurality of third sub-parts are provided between the array area and the stepped area. The array area includes a plurality of storage blocks, and a third sub-part is connected along the first direction between a first sub-part and a second sub-part, and is located between two adjacent storage blocks.

11. The semiconductor device according to claim 1, characterized in that, The gate isolation structure is beaded in the transverse section perpendicular to the stacking direction of the stacked structure, extending along the extension direction of the gate isolation structure.

12. The semiconductor device according to claim 1, characterized in that, At least one of the conductive posts passes through a corresponding step and is connected to the first connecting portion at the corresponding step.

13. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: Multiple insulating layers and multiple interlayer dielectric layers are stacked and alternated to form a stacked structure, the stacked structure including an array region and a step region located on at least one side of the array region, the stacked structure having multiple steps in the step region corresponding to the multiple interlayer dielectric layers respectively; The interlayer dielectric layers are replaced with gate functional layers, and each gate functional layer has at least a gate portion located in the array region, a first connection portion located at the step, and a second connection portion connected between the gate portion and the first connection portion. A gate isolation structure is formed that extends through the stacked structure, wherein a first sub-part is formed in the gate isolation structure that extends to the stepped region, and a second connecting part is connected to the sidewall of the first sub-part; Multiple conductive pillars are formed in the stepped area and through the stacked structure, and the conductive pillars are connected to the corresponding first connecting portions.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that, The step of forming a stacked and alternating plurality of insulating layers and a plurality of interlayer dielectric layers to form a stacked structure includes: A first sacrificial portion is formed at the step, located on the interlayer medium layer; A plurality of gate isolation vias, channel vias, and step connection vias are formed through the stacked structure. The gate isolation vias are located at least in the array region and the step region, the channel vias are located in the array region, and the step connection vias are located in the step region, with at least one step connection via passing through a corresponding step. A second sacrificial portion is formed within the gate isolation hole, the channel hole, and the step connection hole.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The step of replacing the plurality of interlayer dielectric layers with gate functional layers further includes: The second sacrificial portion within the gate isolation hole is removed, and the plurality of gate isolation holes include a plurality of gate isolation hole groups, wherein a plurality of gate isolation holes arranged along a first direction are formed within the gate isolation hole group, the first direction being the direction from the array region to the step region; Remove the insulating layer and the interlayer dielectric layer on the inner wall of the gate isolation hole to connect the plurality of gate isolation holes in the gate isolation hole group to form a first gate isolation trench located in the step region and a second gate isolation trench located in the array region; The interlayer dielectric layer connected to the first gate isolation trench is replaced with the second connection portion, and the first sacrificial portion and the interlayer dielectric layer at the step are replaced with the connection portion. The interlayer dielectric layer of the array region is replaced with the gate portion through the second gate isolation trench.

16. The method for fabricating a semiconductor device according to claim 15, characterized in that, The step of removing the insulating layer and the interlayer dielectric layer at the inner wall of the gate isolation hole further includes: A third gate isolation trench is formed between the array region and the step region, and the third gate isolation trench is connected between a first gate isolation trench and a second gate isolation trench along the first direction; A third sub-section is formed within the third gate isolation trench to isolate the first gate isolation trench and the second gate isolation trench.

17. The method for fabricating a semiconductor device according to claim 15, characterized in that, The step of forming a gate isolation structure that extends through the stacked structure includes: The first sub-part is formed in the first gate isolation trench and the second sub-part is formed in the second gate isolation trench to form the gate isolation structure.

18. The method for fabricating a semiconductor device according to claim 14, characterized in that, The step of forming a plurality of conductive pillars located in the stepped region and penetrating the stacked structure includes: Remove the second sacrificial portion from the stepped connecting hole; The conductive post is formed in the step connection hole, and at least one of the conductive posts passes through a corresponding step and is connected to the first connection part at the corresponding step.

19. A storage system, characterized in that, The storage system includes a controller and a semiconductor device as described in any one of claims 1 to 12, the controller being coupled to the semiconductor device and used to control the semiconductor device to store data.

20. An electronic device, characterized in that, Includes the storage system described in claim 19.

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