High-density three-dimensional ferroelectric memory structure and preparation method thereof

Abstract

The invention provides two high-density three-dimensional ferroelectric memory structures and a preparation method thereof, and the preparation method can reduce the deep hole etching difficulty in the preparation process of a three-dimensional ferroelectric memory, and can increase the effective area of a ferroelectric capacitor of a unit memory unit. According to the core structure and the preparation process of the high-density three-dimensional ferroelectric memory, a conductive through hole formed by deep hole etching is divided into two smaller sub through holes through an isolation groove to serve as discrete wires, the depth-to-width ratio of a deep hole structure during etching is reduced, and therefore the etching difficulty in the preparation process is reduced; by forming the groove structure on the vertical wire extending along the direction perpendicular to the substrate, the contact area between the wire and the ferroelectric material is increased, so that the effective capacitance area of the memory cell is increased, and sufficient memory windows can be maintained when process nodes are reduced. The memory density and reliability of the three-dimensional ferroelectric memory are improved, and the three-dimensional ferroelectric memory has a wide application prospect.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor data storage, and in particular to a high-density three-dimensional ferroelectric memory structure and a preparation method thereof. Background Art

[0002] With the development of technologies such as big data and AIoT, the demand for high-speed, low-power storage and access to massive amounts of data has posed a severe challenge to existing commercial mature storage technologies. Among the emerging non-volatile memories, storage devices based on two-terminal ferroelectric capacitors with a metal-ferroelectric-metal (MFM) structure are widely used in various types of ferroelectric random access memories (FeRAM) because of their fast read and write, ultra-low power access, and good reliability. In order to increase storage capacity and storage density, ferroelectric capacitors with MFM structure can be used in the form of cross-point lattice storage arrays, which have the ability to be three-dimensionally stacked in a direction perpendicular to the substrate.

[0003] In the three-dimensional ferroelectric memory and its preparation scheme provided by the previous technology, a three-dimensional ferroelectric capacitor stacking structure is formed in the stacking structure of the sacrificial layer and the metal layer by only one-step deep hole etching process. However, as the number of stacking layers of the three-dimensional ferroelectric memory in the direction perpendicular to the substrate increases and the line spacing in the direction parallel to the substrate decreases, the depth-to-width ratio of the storage deep hole increases rapidly, and the etching difficulty of the storage deep hole increases sharply; and the effective area of ​​the ferroelectric capacitor of the MFM structure decreases rapidly, and the ferroelectric flip charge of the unit capacitor decreases, resulting in a significant reduction in the storage window. Therefore, the previous technical methods still face many challenges in the process of shrinking the process node. Summary of the invention

[0004] The present invention provides a high-density three-dimensional ferroelectric memory structure and a preparation method thereof, aiming to ensure the high storage density of the three-dimensional ferroelectric memory while reducing the etching difficulty in the preparation process, improving the frame stability in the preparation process, and increasing the effective area of ​​the unit ferroelectric capacitor.

[0005] The specific technical solutions of the present invention are as follows:

[0006] A high-density three-dimensional ferroelectric memory comprises a substrate and a storage body located above or below the substrate, wherein a plurality of columns of first conductive lines are arranged in the storage body, the first conductive lines extend in a direction perpendicular to the substrate, and the first conductive lines are located in conductive through holes; a plurality of columns of isolation grooves are arranged in the storage body, the isolation grooves are perpendicular to the substrate, and extend in a direction perpendicular to the first conductive lines on a cross section parallel to the substrate, and the isolation grooves are located at the column center line position of each column of the first conductive lines for dividing the first conductive lines; the storage body is provided with alternately stacked isolation layers and second conductive line layers surrounded by ferroelectric materials; the storage body is provided with sacrificial through holes that are perpendicular to the substrate and penetrate the stacked layers, and the sacrificial through holes filled with isolation materials are placeholder unit positions; wherein the horizontal cross-sectional area of ​​the portion of the first conductive line located in the second conductive line layer parallel to the substrate direction is smaller than the horizontal cross-sectional area of ​​the portion of the first conductive line located in the isolation layer, and the first conductive line presents a semi-ring groove morphology in the second conductive line layer, which is recorded as the first semi-ring groove; the ferroelectric material is in contact with the first conductive line and the second conductive line at the position of the first semi-ring groove at the same time, that is, the first conductive line, the ferroelectric material and the second conductive line form a storage unit of an MFM structure in the shape of a semi-ring groove.

[0007] The present invention further provides a method for preparing the above-mentioned high-density three-dimensional ferroelectric memory, which comprises the following steps:

[0008] (1) forming a stacked layer of alternately stacked isolation layers and sacrificial layers on a substrate, the substrate comprising a wafer, a wafer cutting unit, and an integrated circuit, the isolation layer being used to isolate adjacent conductive lines;

[0009] (2) forming a plurality of rows of conductive vias in the stacked layer, wherein the conductive vias are perpendicular to the substrate, penetrate the stacked layer, and are completely filled with the conductive material of the first conductive wire;

[0010] (3) forming an isolation trench at the center line position of each column of conductive vias, the isolation trench being completely filled with an isolation material, the isolation trench dividing the column of conductive vias into two columns of sub-conductive vias, the two columns of sub-conductive vias will respectively form two columns of memory cells in a subsequent step, the conductive material in the sub-conductive vias serves as a first conductive wire, the first conductive wire can serve as a bit line of the memory array, and the depth of the isolation trench along the direction perpendicular to the substrate is equal to or less than the depth of the conductive via along the direction perpendicular to the substrate;

[0011] (4) forming a sacrificial through hole perpendicular to the substrate and penetrating the stacked layers by etching at the position of the placeholder unit in the stacked layers, wherein the sacrificial through hole exposes the sacrificial layer material on the side wall surface of the through hole to form a storage body frame, and the plurality of isolation layers are supported by the first conductive line;

[0012] (5) In the memory body frame, a portion of the conductive material of the first conductive line exposed on the surface layer between two adjacent isolation layers is removed by etching, and the first conductive line presents a semi-ring structure of a groove between any two adjacent isolation layers. The surface structure of the first conductive line between the two adjacent isolation layers is called a first semi-ring groove;

[0013] (6) depositing ferroelectric material and conductive material used for the second conductor on the surface of the storage body frame in sequence, and forming a plurality of second conductors with the conductive material between two adjacent isolation layers and at the position of the first semi-ring groove, wherein the second conductor can be used as a word line of the storage array; etching and removing the excess ferroelectric material and excess conductive material on the surface of the isolation layer, the side surface of the sacrificial through hole and the surface of the substrate; forming a storage unit with an MFM structure in the shape of a semi-ring groove with the first conductor, the ferroelectric material and the second conductor at the position of the first semi-ring groove; and the ferroelectric material is in contact with the first conductor and the second conductor at the position of the first semi-ring groove at the same time;

[0014] (7) Filling the sacrificial through-holes with isolation materials to form placeholder cells to obtain the final memory body.

[0015] Furthermore, in the method for preparing the high-density three-dimensional ferroelectric memory, the step (6) deposits a ferroelectric material and a conductive material used for the second wire in the storage body frame, and the thickness of the ferroelectric material is less than half of the distance between two adjacent isolation layers; the sum of the thickness of the ferroelectric material and the thickness of the conductive material is greater than half of the distance between two adjacent isolation layers.

[0016] On the other hand, the present invention also provides another high-density three-dimensional ferroelectric memory, comprising a substrate and a storage body located above or below the substrate, wherein a plurality of columns of first conductive wires are arranged in the storage body, the first conductive wires extend in a direction perpendicular to the substrate, and the first conductive wires are located in conductive through holes; a plurality of columns of isolation grooves are arranged in the storage body, the isolation grooves are perpendicular to the substrate, and extend in a direction perpendicular to the first conductive wires on a cross section parallel to the substrate, the isolation grooves are located at the center line position of each column of the first conductive wires, and are used to divide the first conductive wires; the storage body is provided with isolation layers and second conductive wire layers stacked alternately; the storage body is provided with a plurality of isolation grooves perpendicular to the substrate; A sacrificial through hole that penetrates the stacked layers, wherein the sacrificial through hole filled with the isolation material is a placeholder unit position; wherein the horizontal cross-sectional area of ​​the portion of the first wire located in the second wire layer parallel to the substrate direction is smaller than the horizontal cross-sectional area of ​​the portion of the first wire located in the isolation layer, and the first wire presents a semi-annular groove morphology in the second wire layer; the ferroelectric material is located on the inner wall of the conductive through hole, completely surrounding the first wire; the first wire and the ferroelectric material located between two adjacent isolation layers form a first semi-annular groove; the first wire, the ferroelectric material and the second wire at the position of the first semi-annular groove form a storage unit of an MFM structure in the shape of a semi-annular groove.

[0017] The present invention further provides a method for preparing a high-density three-dimensional ferroelectric memory corresponding to another aspect, the method comprising the following steps:

[0018] (1) forming a stacked layer of alternately stacked isolation layers and sacrificial layers on a substrate, the substrate comprising a wafer, a wafer cutting unit, and an integrated circuit, the isolation layer being used to isolate adjacent conductive lines;

[0019] (2) forming a plurality of columns of through holes of a columnar structure whose radii alternate between layers in the stacked layers, wherein the radius of the portion of the through hole in the sacrificial layer is smaller than the radius of the portion of the through hole in the isolation layer, and the morphology of the through hole is formed by two etching steps: etching a through hole penetrating the vertical sidewall of the stacked layers in a direction perpendicular to the substrate by anisotropic dry etching, and removing a portion of the isolation layer material by isotropic wet etching;

[0020] (3) depositing a ferroelectric material on the surface of the stacked layer and the sidewall surface of the through hole; depositing a conductive material used for the first conductive line on the surface of the ferroelectric material to completely fill the through hole to form a conductive through hole;

[0021] (4) firstly, removing the excess conductive material and ferroelectric material on the surface of the stacked layer by etching technology; then, forming an isolation trench at the center line position of each column of conductive vias, the isolation trench being completely filled with isolation material, the isolation trench dividing the column of conductive vias into two columns of sub-conductive vias, the two columns of sub-conductive vias will respectively form two columns of storage cells in subsequent steps, the conductive material in the sub-conductive vias serves as a first conductive wire, the first conductive wire can serve as a bit line of the storage array, and at the same time, the depth of the isolation trench along the direction perpendicular to the substrate is equal to or less than the depth of the conductive via along the direction perpendicular to the substrate;

[0022] (5) forming a sacrificial through hole perpendicular to the substrate and penetrating the stacked layers by etching at the position of the placeholder unit in the stacked layers, wherein the sacrificial through hole exposes the sacrificial layer material on the surface of the through hole side wall; etching and removing the sacrificial layer in the stacked layers, wherein the first conductive wire, the isolation layer, and the isolation groove constitute a storage body frame, wherein the plurality of isolation layers are supported by a plurality of columns of first conductive wires, and due to the columnar structure in which the radius of the conductive through hole alternately changes between layers, after removing the sacrificial layer, the first conductive wire and the ferroelectric material located between two adjacent isolation layers form a first semi-ring groove;

[0023] (6) depositing a conductive material used for the second conductive wire on the surface of the storage body frame, the conductive material forming a plurality of second conductive wires at positions between two adjacent isolation layers and at positions of the first semi-ring groove, the second conductive wires can be used as word lines of the storage array; etching to remove excess conductive material on the surface of the isolation layer, the side surface of the sacrificial through hole and the surface of the substrate; forming a storage unit of an MFM structure in the shape of a semi-ring groove with the first conductive wire, the ferroelectric material and the second conductive wire at the position of the first semi-ring groove; the ferroelectric material simultaneously contacts the first conductive wire and the second conductive wire at the position of the first semi-ring groove;

[0024] (7) Filling the sacrificial through-holes with isolation materials to form placeholder cells to obtain the final memory body.

[0025] In the method for preparing a high-density three-dimensional ferroelectric memory according to another aspect above, the thickness of the conductive material used for depositing the second conductive wire in the memory body frame in step (6) is greater than half of the distance between two adjacent isolation layers.

[0026] In the above two methods for preparing high-density three-dimensional ferroelectric memory, the isolation trench divides a column of conductive vias into two columns of sub-conductive vias, the depth of the isolation trench along the direction perpendicular to the substrate is equal to the depth of the conductive via along the direction perpendicular to the substrate, and the conductive materials of the two sub-conductive vias obtained by dividing the conductive vias by the isolation trench are not connected and belong to different first conductive wires respectively.

[0027] In the above two methods for preparing high-density three-dimensional ferroelectric memory, the isolation trench divides a column of conductive vias into two columns of sub-conductive vias, the depth of the isolation trench along the direction perpendicular to the substrate is smaller than the depth of the conductive via along the direction perpendicular to the substrate, and the conductive materials of the two sub-conductive vias obtained by dividing the conductive vias by the isolation trench are connected to serve as the same first wire.

[0028] In the above two methods for preparing high-density three-dimensional ferroelectric memory, the isolation layer material is an insulating dielectric material with a low relative dielectric constant, which can be SiO x The isolation material filled in the isolation trench and the sacrificial through hole is an insulating dielectric material with a relatively low dielectric constant; the sacrificial layer is made of a material that is easily removed by dry etching and wet etching, such as SiN x; In order to provide sufficient stress during the annealing process of the ferroelectric material to promote the crystallization of the ferroelectric dielectric layer to form a ferroelectric crystalline phase, the conductive material of the first wire is one of the following materials or is composed of at least two of the following materials: titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), platinum (Pt), molybdenum (Mo), ruthenium (Ru), tungsten (W), nickel (Ni), cobalt (Co), copper (Cu), polysilicon (Si), aluminum (Al), silicon and metal element compounds; the ferroelectric The material is one of the following materials or is composed of at least two of the following materials: traditional ferroelectric materials such as perovskite ferroelectrics (PZT, BFO, SBT), ferroelectric polymers (P(VDF-TrFE)), or new ferroelectric materials based on HfO2 that produce ferroelectricity under specific treatment (doping, stress, annealing, etc.); optionally, the above-mentioned dopants can be the following elements: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), lanthanum (La), strontium (Sr), gallium (Ga).

[0029] In the above two methods for preparing high-density three-dimensional ferroelectric memory, the cross-sectional shape of the conductive through hole completely filled with the conductive material of the first conductive wire is a closed shape of a circle, an ellipse, a polygon or other irregular shapes.

[0030] The technical effects of the present invention are as follows:

[0031] 1. In the above-mentioned memory preparation technical solution, a portion of the first conductor material located between two adjacent isolation layers is removed by etching to form a first semi-ring groove structure, and the first conductor, the second conductor and the ferroelectric material form a memory cell of an MFM structure in the shape of a semi-ring groove. Compared with the ring structure of the vertical side wall, the groove structure increases the contact area between the first conductor and the ferroelectric material and the contact area between the second conductor and the ferroelectric material, thereby increasing the effective capacitance area of ​​the MFM structure memory cell and ensuring that a sufficient storage window can be maintained when the process node is reduced.

[0032] 2. In the above-mentioned memory preparation technical scheme, two columns of stacked ferroelectric units with a three-dimensional structure are formed in a deep hole through two-step etching: first, a larger conductive through hole is etched, and then the isolation groove divides any conductive through hole into two sub-conductive through holes, and the first conductive wire formed by the conductive material in the two sub-conductive through holes respectively forms an independent MFM structure memory unit with multiple second conductive wires and the ferroelectric material therebetween. Under the condition of the same unit projection area of ​​the memory cell, since the etching depth-to-width ratio of the conductive through hole structure (one through hole corresponds to two columns of memory cells) and the isolation groove structure is greater than the etching depth-to-width ratio of the first conductive wire through hole in other previous technologies, the present technical scheme greatly reduces the etching difficulty of the etching process for forming the first conductive wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the structure of a high-density three-dimensional ferroelectric memory provided by an embodiment of the present invention;

[0034] Figure 2 A schematic flow chart of a method for preparing a high-density three-dimensional ferroelectric memory provided by an embodiment of the present invention;

[0035] Figure 3 A schematic diagram of a preparation process of a high-density three-dimensional ferroelectric memory provided by an embodiment of the present invention;

[0036] Figure 4 A schematic diagram of the structure of another high-density three-dimensional ferroelectric memory provided by an embodiment of the present invention;

[0037] Figure 5 A schematic flow chart of another method for preparing a high-density three-dimensional ferroelectric memory provided by an embodiment of the present invention;

[0038] Figure 6 A schematic diagram of the preparation process of another high-density three-dimensional ferroelectric memory provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The present invention will be further described below by way of embodiments in conjunction with the accompanying drawings.

[0040] Figure 1 A schematic diagram of the structure of a high-density three-dimensional ferroelectric memory provided by an embodiment of the present invention, Figure 1 (a) is a top view of the three-dimensional ferroelectric memory. Figure 1 (b) Figure 1 (a) is a cross-sectional view of the three-dimensional ferroelectric memory taken along the straight line AA' and perpendicular to the substrate. Figure 1 (c) is a schematic diagram of the structure and effective capacitance area of ​​a memory cell in the three-dimensional ferroelectric memory and a schematic diagram of the structure and effective capacitance area of ​​a memory cell in the prior art solution.

[0041] like Figure 1 As shown in (b), the high-density three-dimensional ferroelectric memory comprises: a substrate 1, the substrate 1 comprises a wafer, a wafer cutting unit and an integrated circuit, etc.; a storage body 2 located above or below the substrate 1. The storage body 2 comprises alternately stacked isolation layers 21 and a second wire 25 surrounded by a ferroelectric material 26; the storage body 2 also comprises a plurality of columns of first wires 22 and a plurality of columns of isolation grooves 23, the first wires 22 extend in a direction perpendicular to the surface of the substrate 1, and the extension direction of the isolation grooves 23 in the horizontal dimension is perpendicular to the straight line AA' and vertically passes through the first wires 22.

[0042] Among them, the conductive through hole is divided into two sub-conductive through holes by the isolation groove 23, and the first conductive wires 22 respectively formed in the two sub-conductive through holes respectively form independent MFM structure storage units with multiple second conductive wires 25 and the ferroelectric material 26 therebetween. Under the condition of equal storage unit projection area, since the ratio of the horizontal cross-sectional area to the depth of the conductive through hole structure (one conductive through hole corresponds to two columns of storage cells) and the isolation groove 23 is greater than the ratio of the horizontal cross-sectional area to the depth of the first conductive wire storage through hole in other related technologies, the technical solution greatly reduces the etching difficulty of the etching process for forming the first conductive wire 22.

[0043] Among them, the horizontal cross-sectional area of ​​the first wire 22 in the second wire 25 layer is smaller than the horizontal cross-sectional area of ​​the first wire 22 in the isolation layer 21, and the first wire 22 presents the morphology of a semi-ring groove in the layer where the second wire 25 is located; the ferroelectric material 26 contacts the first wire 22 and the second wire 25 at the position of the first semi-ring groove, that is, the first wire 22, the second wire 25 and the ferroelectric material 26 form a memory cell of the MFM structure in the shape of a semi-ring groove. Under the same process node conditions, compared with the annular column structure with vertical side walls, the groove structure greatly increases the effective area of ​​the ferroelectric capacitor of the memory cell, which can ensure that a sufficient storage window is achieved during the process of shrinking the process node.

[0044] In this embodiment, the cross section of the first conductive line 22 can be any closed shape such as a circle or a polygon.

[0045] In this embodiment, the isolation layer 21 is an insulating dielectric material, which is used to electrically isolate the plurality of second wires 25 or the first wires 22. The isolation layer 21 is preferably an insulating dielectric material with a relatively low dielectric constant. For example, the isolation layer 21 can be made of SiO x Material.

[0046] In this embodiment, in order to provide sufficient stress during the annealing process of the ferroelectric material to promote the crystallization of the ferroelectric dielectric layer to form a ferroelectric crystal phase, the first wire 22 or the second wire 25 is one of the following materials or is composed of at least two of the following materials: titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), platinum (Pt), molybdenum (Mo), ruthenium (Ru), tungsten (W), nickel (Ni), cobalt (Co), copper (Cu), polysilicon (Si), aluminum (Al), silicon and metal element compounds.

[0047] In this embodiment, the ferroelectric material 26 is one of the following materials or is composed of at least two of the following materials: traditional ferroelectric materials such as perovskite ferroelectrics (PZT, BFO, SBT), ferroelectric polymers (P(VDF-TrFE)), or new ferroelectric materials based on HfO2 that produce ferroelectricity under specific treatment (doping, stress, annealing, etc.); optionally, the above-mentioned dopants can use the following elements: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), lanthanum (La), strontium (Sr), gallium (Ga).

[0048] against Figure 1 The high-density three-dimensional ferroelectric memory described, Figure 2 A schematic diagram of a process for preparing the memory provided by an embodiment of the present invention. Figure 2 As shown, the method includes steps S31 to S37. Figure 3 The top view and cross-sectional view of the structure of the high-density three-dimensional ferroelectric memory in each step of the process of preparing the high-density three-dimensional ferroelectric memory are shown in FIG. S31: Alternately stacking and growing isolation layers 21 and sacrificial layers 27 on the substrate 1 in a direction perpendicular to the surface of the substrate 1 to form a stacked layer 01. Figure 3 (a) shown.

[0049] The substrate 1 includes a wafer, a wafer cutting unit, and an integrated circuit. The number of stacked layers of the isolation layer 21 and the sacrificial layer 27 can be freely adjusted according to actual conditions. The schematic diagram in this embodiment only illustrates the preparation method through a relatively simple case. The isolation layer 21 is preferably an insulating dielectric material with a low relative dielectric constant. For example, the isolation layer 21 can be made of SiO x The sacrificial layer 27 will be completely removed in the subsequent process. The sacrificial layer 27 is made of a material that is easily removed by dry etching or wet etching. For example, the sacrificial layer 27 is made of SiN x .

[0050] S32: forming a plurality of rows of conductive vias in the stacked layer 01. Figure 3 (b) and Figure 3 (c) as shown.

[0051] Specifically, at the location of the effective unit in the stacking layer 01, multiple rows of through holes penetrating the stacking layer 01 are etched in a direction perpendicular to the surface of the substrate 1, such as Figure 3 (b) as shown; depositing the conductive material used for the first wire 22 on the surface of the stacked layer 01 and the inner wall of the plurality of rows of through holes until the through holes are completely filled with the conductive material, and then etching away the excess conductive material on the surface of the stacked layer 01 to form a plurality of rows of conductive through holes, as shown Figure 3(c) is shown. The cross section of the through hole can be any closed figure. In order to provide sufficient stress during the annealing process of the ferroelectric material to promote the crystallization of the ferroelectric dielectric layer to form a ferroelectric crystal phase, the conductive material of the first wire 22 is one of the following materials or is composed of at least two of the following materials: titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), platinum (Pt), molybdenum (Mo), ruthenium (Ru), tungsten (W), nickel (Ni), cobalt (Co), copper (Cu), polysilicon (Si), aluminum (Al), silicon and metal element compounds.

[0052] S33: forming an isolation trench 23 at the center line position of each column of the plurality of columns of conductive vias. Figure 3 (d) and Figure 3 (e) as shown.

[0053] Specifically, on the center line of each column of conductive vias, a deep etching technique is used to etch a groove that penetrates all sacrificial layers 27 in a direction perpendicular to the surface of the substrate 1. The groove divides one column of conductive vias into two columns of sub-conductive vias, and the two columns of sub-conductive vias will form two columns of storage cells in subsequent steps. The conductive material in the sub-conductive vias serves as a first conductive wire, and the first conductive wire can serve as a bit line in the storage array. At the same time, the depth of the isolation trench in the direction perpendicular to the substrate is equal to or less than the depth of the conductive via in the direction perpendicular to the substrate. In this embodiment, the depth of the isolation trench is less than the depth of the conductive via; the extension direction of the trench in the top view is in a direction perpendicular to the first conductive wire, such as Figure 3 (d) As shown. An isolation material is deposited on the inner wall of the trench until the trench is completely filled with the isolation material to form an isolation trench 23, as shown in FIG. Figure 3 As shown in (e), the isolation material is preferably an insulating dielectric material with a low relative dielectric constant.

[0054] S34: Etching and removing the sacrificial layer 27 in the stacked layer 01 to form a storage body frame 02. Figure 3 (f) and Figure 3 (g) as shown.

[0055] Specifically, a sacrificial through hole penetrating the stacked layer 01 is etched in a direction perpendicular to the surface of the substrate 1 at the location of the placeholder unit 24, exposing the sacrificial layer 27 on the surface so that the sacrificial layer 27 can be removed by wet etching technology, such as Figure 3 (f) as shown; using an isotropic wet etching technique to remove the sacrificial layer 28 in the stacked layer 01 to form a storage body frame 02, such as Figure 3 As shown in (g), a plurality of isolation layers 21 are suspended in the air by being supported by first conductive wires 22 .

[0056] S35: In the memory body frame 02, a portion of the conductive material of the first conductive line 22 between two adjacent isolation layers 21 is etched. Figure 3 (h) shown.

[0057] Specifically, in the storage body frame 02, an isotropic wet etching technique is used to etch away part of the conductive material on the surface of the first wire 22 between two adjacent isolation layers 21, and the first wire 22 presents a semi-annular structure of a groove between any two adjacent isolation layers 21, such as Figure 3 The surface structure of the first conductive line 22 between two adjacent isolation layers 21 is called a first semi-annular groove 28 .

[0058] S36: forming a second conductive line 25 and a ferroelectric material 26 between any two adjacent isolation layers 21 in the memory body frame 02 to obtain a ferroelectric memory cell with an MFM structure. Figure 3 (i) Figure 3 (j) and Figure 3 (k) as shown.

[0059] Specifically, ferroelectric materials 26 are sequentially deposited on the surface of the memory body frame 02, such as Figure 3 Then, the conductive material used for the second wire 25 is deposited on the surface of the ferroelectric material 26 until the space between the two adjacent isolation layers 21 is completely filled with the conductive material. The conductive material between the two adjacent isolation layers and the first semi-ring groove 28 is the second wire 25. Figure 3 As shown in (j), the second conductive line can be used as a word line of the memory array. The excess ferroelectric material 26 and conductive material on the inner wall of the sacrificial through hole and the surface of the memory body frame 02 are removed by etching. Figure 3 (k) is shown. The ferroelectric material 26 is in contact with the first wire 22 and the second wire 25 at the first semi-ring groove 28, that is, the first wire 22, the second wire 25 and the ferroelectric material 26 form a ferroelectric memory cell of MFM structure in the first semi-ring groove 28. The semi-ring groove structure increases the effective area of ​​the ferroelectric capacitor in the memory cell.

[0060] In order to provide sufficient stress during the annealing process of the ferroelectric material 26 to promote the crystallization of the ferroelectric dielectric layer to form a ferroelectric crystalline phase, the conductive material of the second wire 25 is one of the following materials or is composed of at least two of the following materials: titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), platinum (Pt), molybdenum (Mo), ruthenium (Ru), tungsten (W), nickel (Ni), cobalt (Co), copper (Cu), polysilicon (Si), aluminum (Al), silicon and metal element compounds.

[0061] Among them, the ferroelectric material 26 is one of the following materials or is composed of at least two of the following materials: traditional ferroelectric materials such as perovskite ferroelectrics (PZT, BFO, SBT), ferroelectric polymers (P(VDF-TrFE)), or new ferroelectric materials based on HfO2 that produce ferroelectricity under specific treatment (doping, stress, annealing, etc.); optionally, the above-mentioned dopants can use the following elements: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), lanthanum (La), strontium (Sr), gallium (Ga).

[0062] S37: Fill the sacrificial through hole as a placeholder 24 to obtain the final memory body 2. Figure 3 (l) as shown.

[0063] Specifically, an isolation material is deposited on the inner wall of the sacrificial through hole until the sacrificial through hole is completely filled with the isolation material to form a placeholder unit 24, thereby obtaining the memory body 2. The isolation material is preferably an insulating dielectric with a low relative dielectric constant.

[0064] Figure 4 A schematic diagram of the structure of another high-density three-dimensional ferroelectric memory provided by an embodiment of the present invention, Figure 4 (a) is a top view of the high-density three-dimensional ferroelectric memory. Figure 4 (b) Figure 4 (a) is a cross-sectional view of the top view of the three-dimensional ferroelectric memory along the straight line AA' and perpendicular to the substrate. Figure 4 In the high-density three-dimensional ferroelectric memory structure described, the ferroelectric material 26 is located on the inner wall of the conductive through hole, completely surrounding the first conductive line 22; Figure 1 In the high-density three-dimensional ferroelectric memory structure described, the ferroelectric material 26 is located between two adjacent isolation layers 21 and in the first semi-ring groove 28, completely surrounding the second wire 25; the remaining descriptions are the same as Figure 1 The structure of the high-density three-dimensional ferroelectric memory described is consistent and will not be repeated in the embodiments of the present invention.

[0065] right Figure 4 The high-density three-dimensional ferroelectric memory described, Figure 5 A schematic diagram of a process for preparing the memory provided by an embodiment of the present invention. Figure 5 As shown, the method includes steps S41 to S47. Figure 6 The diagram is a top view and a cross-sectional view of the structure of the high-density three-dimensional ferroelectric memory in each step during the preparation of the high-density three-dimensional ferroelectric memory.

[0066] S41: Alternately stacking and growing isolation layers 21 and sacrificial layers 27 on the substrate 1 in a direction perpendicular to the surface of the substrate 1 to form a stacked layer 01. Figure 6 (a) shown.

[0067] The substrate 1 includes a wafer, a wafer cutting unit, and an integrated circuit. The number of stacked layers of the isolation layer 21 and the sacrificial layer 27 can be freely adjusted according to actual conditions. The schematic diagram in this embodiment only illustrates the preparation method through a relatively simple case. The isolation layer 21 is preferably an insulating dielectric material with a low relative dielectric constant. For example, the isolation layer 21 can be made of SiO x The sacrificial layer 27 will be completely removed in the subsequent process. The sacrificial layer 27 is made of a material that is easily removed by dry etching or wet etching. For example, the sacrificial layer 27 is made of SiN x .

[0068] S42: forming a plurality of columns of through holes in a columnar structure that penetrate the stacked layers and have radii that alternately change between layers in the stacked layer 01. Figure 6 (b) and Figure 6 (c) as shown.

[0069] Specifically, at the location of the effective unit in the stacked layer 01, multiple rows of through holes penetrating the stacked layer 01 are etched in a direction perpendicular to the surface of the substrate 1 by anisotropic dry etching, such as Figure 6 As shown in (b), the cross section of the through hole can be any closed pattern; a portion of the isolation layer 21 material on the inner wall of the through hole is selectively removed by an isotropic wet etching technique, such as Figure 6 As shown in (c), multiple rows of columnar through holes with radius changing alternately between layers are formed in the stacked layer 01. The radius of the through hole in the sacrificial layer 27 is smaller than the radius of the through hole in the isolation layer 21.

[0070] S43: Depositing ferroelectric material 26 and conductive material on the inner wall of the through hole to form a conductive through hole. Figure 6 (d) and Figure 6 (e) as shown.

[0071] Specifically, ferroelectric material 26 is deposited on the inner walls of the plurality of through holes and the surface of the stacked layer 01, such as Figure 6 (d) as shown; depositing the conductive material used in the first conductor 22 on the surface of the ferroelectric material 26 until the through hole is completely filled with the conductive material to form multiple columns of conductive through holes, such as Figure 6 (e) as shown.

[0072] In order to provide sufficient stress during the annealing process of the ferroelectric material to promote the crystallization of the ferroelectric dielectric layer to form a ferroelectric crystalline phase, the conductive material of the first wire 22 is one of the following materials or is composed of at least two of the following materials: titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), platinum (Pt), molybdenum (Mo), ruthenium (Ru), tungsten (W), nickel (Ni), cobalt (Co), copper (Cu), polysilicon (Si), aluminum (Al), silicon and metal element compounds.

[0073] Among them, the ferroelectric material 26 is one of the following materials or is composed of at least two of the following materials: traditional ferroelectric materials such as perovskite ferroelectrics (PZT, BFO, SBT), ferroelectric polymers (P(VDF-TrFE)), or new ferroelectric materials based on HfO2 that produce ferroelectricity under specific treatment (doping, stress, annealing, etc.); optionally, the above-mentioned dopants can use the following elements: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), lanthanum (La), strontium (Sr), gallium (Ga).

[0074] S44: forming an isolation trench 23 at the center line position of each column of the plurality of columns of conductive vias. Figure 6 (f) and Figure 6 (g) as shown.

[0075] Specifically, first, the excess conductive material and ferroelectric material 26 on the surface of the stacked layer 01 are removed by etching technology, and then a deep etching technology is used on the center line of each column of conductive vias to etch a groove that penetrates all the sacrificial layers 27 in a direction perpendicular to the surface of the substrate 1. The groove divides one column of conductive vias into two columns of sub-conductive vias, and these two columns of sub-conductive vias will form two columns of storage cells respectively in subsequent steps. The conductive material in the sub-conductive vias serves as a first conductive wire, and the first conductive wire can serve as a bit line in the storage array. At the same time, the depth of the isolation trench in the direction perpendicular to the substrate is equal to or less than the depth of the conductive via in the direction perpendicular to the substrate. In this embodiment, the depth of the isolation trench is less than the depth of the conductive via; the extension direction of the trench in the top view is along the direction perpendicular to the first conductive wire, such as Figure 6 (f) As shown. An isolation material is deposited on the inner wall of the trench until the trench is completely filled with the isolation material to form an isolation trench 23. Figure 6 As shown in (g), the isolation material is preferably an insulating dielectric material with a low relative dielectric constant.

[0076] S45: Etching and removing the sacrificial layer 27 in the stacked layer 01 to form a storage body frame 02. Figure 6 (h) and Figure 6 (i) as shown.

[0077] Specifically, a sacrificial through hole penetrating the stacked layer 01 is etched in a direction perpendicular to the surface of the substrate 1 at the location of the placeholder unit 24, exposing the sacrificial layer 27 on the surface so that the sacrificial layer 27 can be removed by wet etching technology, such as Figure 6 (h) as shown; using an isotropic wet etching technique to remove the sacrificial layer 27 in the stacked layer 01 to form a storage body frame 02, such as Figure 6 As shown in (i), a plurality of isolation layers 21 are suspended in the air by being supported by first conductive wires 22 .

[0078] Among them, since the radius of the conductive through hole changes alternately between layers, after removing the sacrificial layer 27, the first conductive wire 22 and the ferroelectric material 26 located between two adjacent isolation layers 21 form a first semi-annular groove 28;

[0079] S46: forming a second conductive line 25 between any two adjacent isolation layers 21 in the memory body frame 02 to obtain a MFM structure ferroelectric memory cell. Figure 6 (j) and Figure 6 (k) as shown.

[0080] Specifically, the conductive material used for the second conductive wire 25 is deposited on the surface of the storage body frame 02 until the space between the two adjacent isolation layers 21 is completely filled with the conductive material, and the conductive material between the two adjacent isolation layers and the first semi-annular groove 28 forms a plurality of second conductive wires 25, such as Figure 6 As shown in (j), the second conductive wire can be used as a word line of the memory array. The excess conductive material on the inner wall of the sacrificial through hole and the surface of the memory body frame 02 is removed by etching. Figure 6 (k) is shown. The ferroelectric material 26 is in contact with the first wire 22 and the second wire 25 at the first semi-ring groove 28, that is, the first wire 22, the second wire 25 and the ferroelectric material 26 form a ferroelectric memory cell of MFM structure in the first semi-ring groove 28. The semi-ring groove structure increases the effective area of ​​the ferroelectric capacitor in the memory cell.

[0081] In order to provide sufficient stress during the annealing process of the ferroelectric material 26 to promote the crystallization of the ferroelectric dielectric layer to form a ferroelectric crystalline phase, the conductive material of the second wire 25 is one of the following materials or is composed of at least two of the following materials: titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), platinum (Pt), molybdenum (Mo), ruthenium (Ru), tungsten (W), nickel (Ni), cobalt (Co), copper (Cu), polysilicon (Si), aluminum (Al), silicon and metal element compounds.

[0082] S47: Fill the sacrificial through hole as a placeholder unit 24 to obtain the final memory body 2. Figure 6 (l) as shown.

[0083] Specifically, an isolation material is deposited on the inner wall of the sacrificial through hole until the sacrificial through hole is completely filled with the isolation material to form a placeholder unit 24, thereby obtaining the memory body 2. The isolation material is preferably an insulating dielectric with a low relative dielectric constant.

[0084] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A high-density three-dimensional ferroelectric memory, comprising a substrate and a storage body located above or below the substrate, characterized in that: A plurality of columns of first conductive lines are arranged in the storage body, the first conductive lines extend in a direction perpendicular to the substrate, and the first conductive lines are located in the conductive through-holes; a plurality of columns of isolation grooves are arranged in the storage body, the isolation grooves are perpendicular to the substrate, and extend in a direction perpendicular to the first conductive lines on a cross section parallel to the substrate, the isolation grooves are located at the center line position of each column of the first conductive lines, and are used to divide the first conductive lines; an isolation layer stacked alternately and a second conductive line layer surrounded by a ferroelectric material are arranged in the storage body; a sacrificial through-hole perpendicular to the substrate and penetrating the stacked layers is arranged in the storage body, and the sacrificial through-hole filled with the isolation material is the position of the placeholder unit; wherein the horizontal cross-sectional area of ​​the portion of the first conductive line located in the second conductive line layer parallel to the substrate direction is smaller than the horizontal cross-sectional area of ​​the portion of the first conductive line located in the isolation layer, and the first conductive line presents the morphology of a semi-ring groove in the second conductive line layer, which is recorded as the first semi-ring groove; the ferroelectric material contacts the first conductive line and the second conductive line at the position of the first semi-ring groove at the same time, that is, the first conductive line, the ferroelectric material and the second conductive line form a storage unit of an MFM structure in the shape of a semi-ring groove.

2. A high-density three-dimensional ferroelectric memory, comprising a substrate and a storage body located above or below the substrate, characterized in that: A plurality of columns of first conductive lines are arranged in the storage body, the first conductive lines extend in a direction perpendicular to the substrate, and the first conductive lines are located in the conductive through-holes; a plurality of columns of isolation grooves are arranged in the storage body, the isolation grooves are perpendicular to the substrate, and extend in a direction perpendicular to the first conductive lines on a cross section parallel to the substrate, the isolation grooves are located at the column center line position of each column of the first conductive lines, and are used to divide the first conductive lines; an isolation layer and a second conductive line layer stacked alternately are arranged in the storage body; a sacrificial through-hole perpendicular to the substrate and penetrating the stacked layers is arranged in the storage body, and the sacrificial through-hole filled with isolation material is the position of the placeholder unit; wherein the horizontal cross-sectional area of ​​the part of the first conductive line located in the second conductive line layer parallel to the substrate direction is smaller than the horizontal cross-sectional area of ​​the part of the first conductive line located in the isolation layer, and the first conductive line presents the morphology of a semi-ring groove in the second conductive line layer; the ferroelectric material is located on the inner wall of the conductive through-hole, and completely surrounds the first conductive line; the first conductive line and the ferroelectric material located between two adjacent isolation layers form a first semi-ring groove; the first conductive line, the ferroelectric material, and the second conductive line at the position of the first semi-ring groove form a storage unit of an MFM structure in the shape of a semi-ring groove.

3. A method for preparing a high-density three-dimensional ferroelectric memory as claimed in claim 1, characterized in that: The steps include: (1) forming a stacked layer of alternately stacked isolation layers and sacrificial layers on a substrate, the substrate comprising a wafer, a wafer cutting unit, and an integrated circuit, the isolation layer being used to isolate adjacent conductive lines; (2) forming a plurality of rows of conductive vias in the stacked layer, wherein the conductive vias are perpendicular to the substrate, penetrate the stacked layer, and are completely filled with the conductive material of the first conductive wire; (3) forming an isolation trench at the center line position of each column of conductive vias, the isolation trench being completely filled with an isolation material, the isolation trench dividing the column of conductive vias into two columns of sub-conductive vias, the two columns of sub-conductive vias will respectively form two columns of memory cells in a subsequent step, the conductive material in the sub-conductive vias serves as a first conductive wire, the first conductive wire can serve as a bit line of the memory array, and the depth of the isolation trench along the direction perpendicular to the substrate is equal to or less than the depth of the conductive via along the direction perpendicular to the substrate; (4) forming a sacrificial through hole perpendicular to the substrate and penetrating the stacked layers by etching at the position of the placeholder unit in the stacked layers, wherein the sacrificial through hole exposes the sacrificial layer material on the side wall surface of the through hole to form a storage body frame, and the plurality of isolation layers are supported by the first conductive line; (5) In the memory body frame, a portion of the conductive material of the first conductive line exposed on the surface layer between two adjacent isolation layers is removed by etching, and the first conductive line presents a semi-ring structure of a groove between any two adjacent isolation layers. The surface structure of the first conductive line between the two adjacent isolation layers is called a first semi-ring groove; (6) depositing ferroelectric material and conductive material used for second conductive wires on the surface of the memory body frame in sequence, and forming a plurality of second conductive wires by the conductive material between two adjacent isolation layers and at the position of the first semi-ring groove, and the second conductive wires can be used as word lines of the memory array; Etching and removing excess ferroelectric material and excess conductive material on the surface of the isolation layer, the side surface of the sacrificial through hole and the surface of the substrate; The first conductive wire, the ferroelectric material and the second conductive wire at the position of the first semi-ring groove form a memory cell of an MFM structure in the shape of a semi-ring groove; the ferroelectric material is in contact with the first conductive wire and the second conductive wire at the position of the first semi-ring groove; (7) Filling the sacrificial through-holes with isolation materials to form placeholder cells to obtain the final memory body.

4. A method for preparing a high-density three-dimensional ferroelectric memory as claimed in claim 2, characterized in that: The steps include: (1) forming a stacked layer of alternately stacked isolation layers and sacrificial layers on a substrate, the substrate comprising a wafer, a wafer cutting unit, and an integrated circuit, the isolation layer being used to isolate adjacent conductive lines; (2) forming a plurality of columns of through holes of a columnar structure whose radii alternate between layers in the stacked layers, wherein the radius of the portion of the through hole in the sacrificial layer is smaller than the radius of the portion of the through hole in the isolation layer, and the morphology of the through hole is formed by two etching steps: etching a through hole penetrating the vertical sidewall of the stacked layers in a direction perpendicular to the substrate by anisotropic dry etching, and removing a portion of the isolation layer material by isotropic wet etching; (3) depositing a ferroelectric material on the surface of the stacked layer and the sidewall surface of the through hole; depositing a conductive material used for the first conductive line on the surface of the ferroelectric material to completely fill the through hole to form a conductive through hole; (4) firstly, removing the excess conductive material and ferroelectric material on the surface of the stacked layer by etching technology; then, forming an isolation trench at the center line position of each column of conductive vias, the isolation trench being completely filled with isolation material, the isolation trench dividing the column of conductive vias into two columns of sub-conductive vias, the two columns of sub-conductive vias will respectively form two columns of storage cells in subsequent steps, the conductive material in the sub-conductive vias serves as a first conductive wire, the first conductive wire can serve as a bit line of the storage array, and at the same time, the depth of the isolation trench along the direction perpendicular to the substrate is equal to or less than the depth of the conductive via along the direction perpendicular to the substrate; (5) forming a sacrificial through hole perpendicular to the substrate and penetrating the stacked layer by etching at the position of the placeholder unit in the stacked layer, wherein the sacrificial through hole exposes the sacrificial layer material on the surface of the through hole sidewall; The sacrificial layer in the stacked layer is removed by etching, and the first conductive wire, the isolation layer, and the isolation groove constitute a storage body frame, wherein the multiple isolation layers are supported by multiple columns of the first conductive wires. Due to the columnar structure in which the radius of the conductive through hole alternately changes between layers, after removing the sacrificial layer, the first conductive wire and the ferroelectric material located between two adjacent isolation layers form a first semi-ring groove; (6) depositing a conductive material used for second conductive lines on the surface of the memory body frame, the conductive material forming a plurality of second conductive lines at positions between two adjacent isolation layers and at positions of the first semi-ring grooves, the second conductive lines being used as word lines of the memory array; Etching to remove excess conductive material on the surface of the isolation layer, the side surface of the sacrificial through hole and the surface of the substrate; The first conductive wire, the ferroelectric material and the second conductive wire at the position of the first semi-ring groove form a memory cell of an MFM structure in the shape of a semi-ring groove; the ferroelectric material is in contact with the first conductive wire and the second conductive wire at the position of the first semi-ring groove; (7) Filling the sacrificial through-holes with isolation materials to form placeholder cells to obtain the final memory body.

5. The method for preparing a high-density three-dimensional ferroelectric memory according to claim 3 or 4, characterized in that: The isolation trench divides a column of conductive vias into two columns of sub-conductive vias. The depth of the isolation trench along the direction perpendicular to the substrate is equal to the depth of the conductive via along the direction perpendicular to the substrate. The conductive materials of the two sub-conductive vias obtained by dividing the conductive vias by the isolation trench are not connected and belong to different first conductive wires.

6. The method for preparing a high-density three-dimensional ferroelectric memory according to claim 3 or 4, characterized in that: The isolation trench divides a column of conductive vias into two columns of sub-conductive vias. The depth of the isolation trench along the direction perpendicular to the substrate is less than the depth of the conductive vias along the direction perpendicular to the substrate. The conductive materials of the two sub-conductive vias obtained by dividing the conductive vias by the isolation trench are connected to serve as the same first conductive wire.

7. The method for preparing a high-density three-dimensional ferroelectric memory according to claim 3 or 4, characterized in that: The isolation layer material is an insulating dielectric material with a low relative dielectric constant: SiO x ; The isolation material filled in the isolation trench and the sacrificial through hole is an insulating dielectric material with a low relative dielectric constant; The sacrificial layer is made of a material that is easily removed by dry etching or wet etching: SiN x ; The conductive material of the first conductive line is one of the following materials or is composed of at least two of the following materials: titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), platinum (Pt), molybdenum (Mo), ruthenium (Ru), tungsten (W), nickel (Ni), cobalt (Co), copper (Cu), polysilicon (Si), aluminum (Al), and a compound of silicon and metal elements; The ferroelectric material is one of the following materials or is composed of at least two of the following materials: traditional ferroelectric materials perovskite ferroelectrics (PZT, BFO, SBT), ferroelectric polymers (P(VDF-TrFE)) or new ferroelectric materials based on HfO2 that produce ferroelectricity under specific treatments of doping, stress, and annealing; the dopants are the following elements: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), lanthanum (La), strontium (Sr), and gallium (Ga).

8. The method for preparing a high-density three-dimensional ferroelectric memory according to claim 3, characterized in that: The step (6) deposits ferroelectric material and conductive material used for the second conductive line in the storage body frame, wherein the thickness of the ferroelectric material is less than half of the distance between two adjacent isolation layers; and the sum of the thickness of the ferroelectric material and the thickness of the conductive material is greater than half of the distance between two adjacent isolation layers.

9. The method for preparing a high-density three-dimensional ferroelectric memory according to claim 4, characterized in that: The thickness of the conductive material used in depositing the second conductive line in the storage body frame in step (6) is greater than half of the distance between two adjacent isolation layers.

10. The method for preparing a high-density three-dimensional ferroelectric memory according to claim 3 or 4, characterized in that: The conductive through hole is completely filled with the conductive material of the first conductive line, and its cross-sectional shape is a closed shape of a circle, an ellipse, a polygon or other irregular shapes.

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