Nanowire memory with boundary gap and manufacturing method thereof

Abstract

The invention discloses a nanowire memory with a boundary gap and a manufacturing method thereof. A first magnetic tunnel junction, a second magnetic tunnel junction, a third magnetic tunnel junction and a fourth magnetic tunnel junction are used for realizing data writing and reading and current injection. The gap between the second magnetic tunnel junction and the third magnetic tunnel junction is arranged at the boundary of one side of the magnetic layer, so that the Skyrmion can be annihilated due to the gap after a large current is injected, and the initial state of the nanowire memory is realized. The magnetic layer is used for providing an environment for the Skyrmion, the Skyrmion is small in size and can be stored in the nano channel in a high-density mode, the topological property of the Skyrmion can resist the influence of the external environment, and the stability of the device is improved. The thickness of the magnetic layer is in linear gradient change, so that the Skyrmion performs unidirectional or bidirectional movement, thereby realizing non-reciprocal transportation. The Skyrmion has the characteristic of being easy to erase, the Skyrmion can return to the initial position after current is stopped, and reverse current does not need to be injected. The return motion of the skyrmion does not need additional energy input, and low-power-consumption operation can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of memory, and in particular to a nanowire memory with a boundary gap and a manufacturing method thereof. Background Art

[0002] Traditional magnetic memories regulate the magnetization direction of magnetic layer units to represent "0" and "1" in computer binary. In these memories, magnetic read / write heads are key components that use electromagnetic induction technology to change or detect the magnetization direction to write and read data. However, as the size of storage devices continues to decrease, the physical size of magnetic layer units is gradually approaching the limit. This method has been significantly limited in improving storage density, becoming a bottleneck for the development of high-capacity magnetic memories in the future.

[0003] In recent years, new spin structures based on topological structures, such as skyrmions, have attracted widespread attention due to their unique topological stability, low power consumption, and behavioral characteristics in confined environments. Skyrmions are stable spin structures with topological protection that can achieve controllable motion at low energy under certain conditions. This property makes them have broad application potential in new low-power memory, logic devices, and neuromorphic computing. However, in geometrically confined systems, the dynamic behavior and stability of skyrmions are limited by many factors. For example, boundary effects and interactions between skyrmions may lead to the instability of topological structures; in addition, the existence of skyrmion Hall effect may affect the realization of its unidirectional motion, thereby limiting its practical application in micro-nano devices. In particular, how to stably control the behavior of skyrmions in confined systems and develop effective control methods to achieve precise motion of skyrmions in a specific direction remain important challenges in current research. In this context, the development of new skyrmion-based memories or logic devices has become a potential solution to break through the physical limitations of traditional magnetic memories. Summary of the invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a nanowire memory with a boundary gap.

[0005] To achieve the above purpose, the technical solution provided by the present invention is:

[0006] A nanowire memory with a boundary gap comprises a substrate, a magnetic layer, a first magnetic tunnel junction, a second magnetic tunnel junction, a third magnetic tunnel junction and a fourth magnetic tunnel junction;

[0007] Wherein, the substrate is stacked at the bottom of the magnetic layer;

[0008] The first magnetic tunnel junction, the second magnetic tunnel junction, the third magnetic tunnel junction and the fourth magnetic tunnel junction are respectively arranged on the upper surface of the magnetic layer;

[0009] The first magnetic tunnel junction and the fourth magnetic tunnel junction are respectively close to two ends of the magnetic layer, and are both used to change the magnetization state of the magnetic layer; the cross nodes corresponding to the first magnetic tunnel junction and the fourth magnetic tunnel junction have an exclusive OR relationship, and correspond to binary numbers 0 and 1 respectively;

[0010] The second magnetic tunnel junction and the third magnetic tunnel junction are disposed between the first magnetic tunnel junction and the fourth magnetic tunnel junction, and are both used to read the magnetization state of the magnetic layer;

[0011] A gap is provided at a boundary of one side of the magnetic layer and is located between the second magnetic tunnel junction and the third magnetic tunnel junction, and the thickness of the magnetic layer changes linearly from one end to the other end.

[0012] In this technical solution, when writing data, the magnetization direction of the magnetic arm is adjusted through the magnetic tunnel junction (MTJ) structure, thereby changing the magnetization state at the cross node. When reading data, the magnetization direction of the cross node is detected by electromagnetic induction through the MTJ structure to realize data reading.

[0013] Specifically:

[0014] By injecting spin current into the first or fourth magnetic tunnel junction to change the magnetization state in the magnetic layer, the cross nodes corresponding to this pair of magnetic arms only have an XOR relationship, that is, the skyrmion is the only one, and the corresponding position is close to the left or right side of the sample, corresponding to two independent magnetization states, corresponding to the binary numbers 0 and 1 respectively.

[0015] The magnetization state of the magnetic layer is detected at the second or third magnetic tunnel junction. When the magnetic layer is in two independent magnetization states, the impedance of the magnetic layer will change. At this time, the purpose of data reading can be achieved by injecting a detection current into the second or third magnetic tunnel junction.

[0016] Furthermore, the notch is triangular in shape.

[0017] Furthermore, the gap is located in the middle of one side of the magnetic layer.

[0018] Further, the magnetic layer includes a first heavy metal sublayer, an oxide sublayer, a magnetic sublayer and a second heavy metal sublayer;

[0019] The first heavy metal sublayer, the oxide sublayer, the magnetic sublayer and the second heavy metal sublayer are stacked in sequence from bottom to top.

[0020] Further, the height of the triangle is in the range of 15nm-20nm, and the length of the base is in the range of 70nm-90nm;

[0021] The maximum thickness of the magnetic layer is in the range of 12nm-15nm, and the minimum thickness is in the range of 10nm-11.9nm;

[0022] The thickness of the magnetic sublayer is 1.0 nm-1.6 nm.

[0023] Furthermore, the substrate is made of silicon or its oxide material;

[0024] The magnetic sublayer is made of CoFeB material.

[0025] Further, it comprises the following steps:

[0026] S1. sputtering a magnetic layer on a substrate using a vacuum magnetron sputtering technique, wherein the magnetic layer includes a first heavy metal sublayer, an oxide sublayer, a magnetic sublayer, and a second heavy metal sublayer stacked in sequence from bottom to top;

[0027] S2, sputtering to form an MTJ layer on the formed magnetic layer to form a preliminary whole;

[0028] S3, annealing the formed preliminary whole;

[0029] S4, etching the MTJ layer in the preliminary whole after annealing by using photolithography technology to obtain a first magnetic tunnel junction, a second magnetic tunnel junction, a third magnetic tunnel junction and a fourth magnetic tunnel junction;

[0030] S5. The magnetic layer is etched using photolithography technology to create a gap, and finally a nanowire memory with a boundary gap is obtained.

[0031] Furthermore, in step S1, when sputtering the oxide sub-layer and the magnetic sub-layer, a baffle is used to block and form a shadow area, so as to produce a magnetic layer with a thickness that varies in a linear gradient.

[0032] Further, the formed preliminary whole is subjected to annealing treatment, including:

[0033] The preliminary whole is placed in an annealing furnace, and the temperature is increased from room temperature to 280°C at a heating rate of 50°C to 60°C per minute, and the temperature is kept constant at the set temperature for 30 minutes, and then the temperature of the preliminary whole is slowly reduced to room temperature in a controlled cooling manner, and rapid temperature changes are avoided during the cooling process to prevent the generation of internal stress;

[0034] An out-of-plane magnetic field with a strength of 1kOe to 3kOe is applied during the annealing process to optimize the magnetic anisotropy and tunnel magnetoresistance properties.

[0035] Further, the MTJ layer in the preliminary whole after annealing is etched by using photolithography technology, including:

[0036] The preliminary whole after annealing is placed in a dust-free glove box, and a layer of positive or negative photoresist is coated on the surface of the MTJ layer by a spin coating process; then, a rectangular pattern is designed to develop the corresponding area through ultraviolet light or electron beam exposure; the developed MTJ layer is placed in an etching device, and an ion beam etching or reactive ion etching process is used to anisotropically etch the MTJ layer; finally, the remaining photoresist is removed by a stripping process to obtain a first magnetic tunnel junction, a second magnetic tunnel junction, a third magnetic tunnel junction and a fourth magnetic tunnel junction.

[0037] Compared with the prior art, the principles and advantages of this technical solution are as follows:

[0038] The first magnetic tunnel junction, the second magnetic tunnel junction, the third magnetic tunnel junction and the fourth magnetic tunnel junction are used to implement data writing and reading and current injection.

[0039] A gap is set between the second magnetic tunnel junction and the third magnetic tunnel junction at the boundary on one side of the magnetic layer, so that after a large current is injected, the skyrmions will be annihilated due to the gap, thereby realizing the initial state of the nanowire memory.

[0040] The magnetic layer is used to provide an environment for skyrmions. Skyrmions are small in size and can be stored at high density in nanochannels. The topological properties of skyrmions can effectively resist the influence of the external environment and improve the stability of the device.

[0041] The thickness of the magnetic layer changes linearly from one end to the other, which allows skyrmions to move in one or two directions, thus achieving non-reciprocal transport. It has the characteristic of easy erasure, and skyrmions will return to their initial position after the current is stopped, without the need to inject reverse current. The return motion of skyrmions does not require additional energy input, and low-power operation can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the services required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 A three-dimensional diagram of a nanowire memory device with a boundary gap according to the present invention;

[0044] Figure 2 A top view of a nanowire memory with a boundary gap according to the present invention;

[0045] Figure 3 A side view of a nanowire memory with a boundary gap according to the present invention;

[0046] Figure 4 It is a partial schematic diagram of a substrate stacked on the bottom of a magnetic layer in a nanowire memory with a boundary gap of the present invention;

[0047] Figure 5 The present invention is a flow chart of a method for manufacturing a nanowire memory with a boundary gap.

[0048] Reference numerals:

[0049] 1-substrate; 2-magnetic layer; 3-first magnetic tunnel junction; 4-second magnetic tunnel junction; 5-third magnetic tunnel junction; 6-fourth magnetic tunnel junction; 7-gap; 8-first heavy metal sublayer; 9-oxidized sublayer; 10-magnetic sublayer; 11-second heavy metal sublayer; DETAILED DESCRIPTION

[0050] The present invention will be further described below in conjunction with specific embodiments:

[0051] like Figure 1 The nanowire memory with a boundary gap described in this embodiment includes a substrate 1, a magnetic layer 2, a first magnetic tunnel junction 3, a second magnetic tunnel junction 4, a third magnetic tunnel junction 5 and a fourth magnetic tunnel junction 6; (the first magnetic tunnel junction 3, the second magnetic tunnel junction 4, the third magnetic tunnel junction 5 and the fourth magnetic tunnel junction 6 are all memory devices based on the magnetoresistance effect, and the structure of these magnetic tunnel junctions (MTJ, Magnetic Tunnel Junction) is composed of a ferromagnetic layer sandwiched by an insulating layer. When the magnetization directions of the ferromagnetic layers are parallel, the resistance is low; when they are anti-parallel, the resistance increases. This characteristic makes MTJ a core component of magnetic random access memory (MRAM), which can store binary data by controlling the resistance state).

[0052] The substrate 1 is stacked on the bottom of the magnetic layer 2; the first magnetic tunnel junction 3, the second magnetic tunnel junction 4, the third magnetic tunnel junction 5 and the fourth magnetic tunnel junction 6 are respectively arranged on the upper surface of the magnetic layer 2; the first magnetic tunnel junction 3 and the fourth magnetic tunnel junction 6 are respectively close to the two ends of the magnetic layer 2, and are both used to change the magnetization state of the magnetic layer 2; the cross nodes corresponding to the first magnetic tunnel junction 3 and the fourth magnetic tunnel junction 6 have an exclusive OR relationship, corresponding to the binary numbers 0 and 1 respectively; the second magnetic tunnel junction 4 and the third magnetic tunnel junction 5 are placed between the first magnetic tunnel junction 3 and the fourth magnetic tunnel junction 6, and are both used to read the magnetization state of the magnetic layer 2; a gap 7 located between the second magnetic tunnel junction 4 and the third magnetic tunnel junction 5 is provided in the middle of the boundary on one side of the magnetic layer 2, and the thickness of the magnetic layer 2 changes linearly from one end to the other end.

[0053] Specifically, in this embodiment, the magnetic layer 2 includes a first heavy metal sublayer 8, an oxide sublayer 9, a magnetic sublayer 10 and a second heavy metal sublayer 11, which are stacked in sequence from bottom to top, and the first heavy metal sublayer 8 is placed on top of the substrate 1 and is bonded to the substrate 1.

[0054] Specifically, in this embodiment, the gap 7 is triangular in shape, with a height of 19 nm and a base length of 71 nm; the maximum thickness range of the magnetic layer 2 is 13 nm and the minimum thickness range is 11 nm; and the thickness of the magnetic sublayer 10 is 1.1 nm.

[0055] Specifically, in this embodiment, the substrate 1 is made of silicon or its oxide material, which has strong stability. The magnetic sublayer 10 is made of CoFeB material.

[0056] The working principle of this embodiment is as follows:

[0057] When writing data, the magnetization direction of the magnetic arm is adjusted through the magnetic tunnel junction (MTJ) structure, thereby changing the magnetization state at the cross node. When reading data, the magnetization direction of the cross node is detected by electromagnetic induction through the MTJ structure to achieve data reading.

[0058] Specifically:

[0059] By injecting a spin current into the first or fourth magnetic tunnel junction 6 to change the magnetization state in the magnetic layer 2, the cross nodes corresponding to the pair of magnetic arms only have an XOR relationship, that is, two independent magnetization states corresponding to the binary numbers 0 and 1 respectively.

[0060] The magnetization state of the magnetic layer 2 is detected through the second or third magnetic tunnel junction 5. When the magnetic layer 2 is in two independent magnetization states, the impedance of the magnetic layer 2 will change. At this time, by injecting a detection current into the second or third magnetic tunnel junction 5, the purpose of data reading can be achieved.

[0061] In this embodiment,

[0062] The first magnetic tunnel junction 3 , the second magnetic tunnel junction 4 , the third magnetic tunnel junction 5 and the fourth magnetic tunnel junction 6 are used to implement data writing and reading and current injection.

[0063] A gap 7 is provided between the second magnetic tunnel junction 4 and the third magnetic tunnel junction 5 at the boundary of one side of the magnetic layer 2, so that after a large current is injected, the skyrmions will be annihilated due to the gap 7, thereby realizing the initial state of the nanowire memory.

[0064] The magnetic layer 2 is used to provide an environment for skyrmions. Skyrmions are small in size and can be stored at high density in nanochannels. The topological properties of skyrmions can effectively resist the influence of the external environment and improve the stability of the device.

[0065] The thickness of the magnetic layer 2 changes linearly from one end to the other, which allows skyrmions to move in one or two directions, thereby achieving non-reciprocal transport. It has the characteristic of easy erasure, and the skyrmions will return to their initial positions after the current is stopped, without the need to inject reverse current. The return motion of skyrmions does not require additional energy input, and low-power operation can be achieved.

[0066] In addition, this embodiment also provides a method for manufacturing the above-mentioned nanowire memory having the boundary gap 7, which comprises the following steps:

[0067] S1. forming a magnetic layer 2 on a substrate 1 by sputtering using a vacuum magnetron sputtering technique, the process comprising:

[0068] S1-1, sputtering heavy metal on the substrate 1 to form a first heavy metal sublayer 8;

[0069] S1-2, sputtering magnesium oxide on the first heavy metal sublayer 8 to form an oxide sublayer 9;

[0070] S1-3, sputtering a magnetic material on the oxide sub-layer 9 to form a magnetic sub-layer 10;

[0071] S1-4, sputtering heavy metal on the magnetic sub-layer 10 to form a second heavy metal sub-layer 11;

[0072] In the above, when the oxide sub-layer 9 and the magnetic sub-layer 10 are formed by sputtering, a baffle is used to block and form a shadow area, so as to produce a magnetic layer 2 with a linear gradient thickness.

[0073] S2, sputtering to form an MTJ layer on the formed magnetic layer 2 to form a preliminary whole;

[0074] S3, annealing the formed preliminary whole, including:

[0075] The annealing environment must meet the following requirements: vacuum degree is less than 1×10 -6 Torr; The temperature control system must have high-precision adjustment function to ensure that the temperature fluctuation range does not exceed ±2℃.

[0076] The preliminary whole is placed in an annealing furnace, and the temperature is raised from room temperature to 280°C at a heating rate of 50°C to 60°C per minute, and the temperature is kept constant at the set temperature for 30 minutes, and then the temperature of the preliminary whole is slowly lowered to room temperature in a controlled cooling manner, and rapid temperature changes are avoided during the cooling process to prevent internal stress from generating "defects";

[0077] An out-of-plane magnetic field with a strength of 1kOe to 3kOe is applied during the annealing process to optimize the magnetic anisotropy and tunnel magnetoresistance properties.

[0078] S4, etching the MTJ layer in the preliminary whole after annealing by photolithography technology to obtain a first magnetic tunnel junction 3, a second magnetic tunnel junction 4, a third magnetic tunnel junction 5 and a fourth magnetic tunnel junction 6;

[0079] This step specifically includes:

[0080] The preliminary whole after annealing is placed in a dust-free glove box, and a layer of positive or negative photoresist is coated on the surface of the MTJ layer by a spin coating process; then, a rectangular pattern is designed to develop the corresponding area through ultraviolet light or electron beam exposure; the developed MTJ layer is placed in an etching device, and an ion beam etching or reactive ion etching process is used to anisotropically etch the MTJ layer; finally, the remaining photoresist is removed by a stripping process to obtain a first magnetic tunnel junction 3, a second magnetic tunnel junction 4, a third magnetic tunnel junction 5 and a fourth magnetic tunnel junction 6.

[0081] S5. The magnetic layer 2 is etched by photolithography technology to produce the gap 7, and finally a nanowire memory having a boundary gap 7 is obtained.

[0082] The embodiments described above are only preferred embodiments of the present invention and are not intended to limit the scope of implementation of the present invention. Therefore, all changes made according to the shape and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A nanowire memory with a boundary gap, characterized in that: It includes a substrate, a magnetic layer, a first magnetic tunnel junction, a second magnetic tunnel junction, a third magnetic tunnel junction and a fourth magnetic tunnel junction; Wherein, the substrate is stacked at the bottom of the magnetic layer; The first magnetic tunnel junction, the second magnetic tunnel junction, the third magnetic tunnel junction and the fourth magnetic tunnel junction are respectively arranged on the upper surface of the magnetic layer; The first magnetic tunnel junction and the fourth magnetic tunnel junction are respectively close to two ends of the magnetic layer, and are both used to change the magnetization state of the magnetic layer; the cross nodes corresponding to the first magnetic tunnel junction and the fourth magnetic tunnel junction have an exclusive OR relationship, and correspond to binary numbers 0 and 1 respectively; The second magnetic tunnel junction and the third magnetic tunnel junction are disposed between the first magnetic tunnel junction and the fourth magnetic tunnel junction, and are both used to read the magnetization state of the magnetic layer; A gap is provided at a boundary of one side of the magnetic layer and is located between the second magnetic tunnel junction and the third magnetic tunnel junction, and the thickness of the magnetic layer changes linearly from one end to the other end.

2. The nanowire memory with a boundary gap according to claim 1, characterized in that: The notch is triangular in shape.

3. The nanowire memory with a boundary gap according to claim 2, characterized in that: The notch is located in the middle of one side of the magnetic layer.

4. The nanowire memory with a boundary gap according to claim 3, characterized in that: The magnetic layer includes a first heavy metal sublayer, an oxide sublayer, a magnetic sublayer, and a second heavy metal sublayer; The first heavy metal sublayer, the oxide sublayer, the magnetic sublayer and the second heavy metal sublayer are stacked in sequence from bottom to top.

5. The nanowire memory with a boundary gap according to claim 4, characterized in that: The height of the triangle is in the range of 15nm-20nm, and the length of the base is in the range of 70nm-90nm; The maximum thickness of the magnetic layer is in the range of 12nm-15nm, and the minimum thickness is in the range of 10nm-11.9nm; The thickness of the magnetic sublayer is 1.0 nm-1.6 nm.

6. The nanowire memory with a boundary gap according to claim 1, characterized in that: The substrate is made of silicon or its oxide material; The magnetic sublayer is made of CoFeB material.

7. A method for manufacturing the nanowire memory with a boundary gap according to claim 1, characterized in that: It includes the following steps: S1. sputtering a magnetic layer on a substrate using a vacuum magnetron sputtering technique; the magnetic layer includes a first heavy metal sublayer, an oxide sublayer, a magnetic sublayer, and a second heavy metal sublayer stacked in sequence from bottom to top; S2, sputtering to form an MTJ layer on the formed magnetic layer to form a preliminary whole; S3, annealing the formed preliminary whole; S4, etching the MTJ layer in the preliminary whole after annealing by using photolithography technology to obtain a first magnetic tunnel junction, a second magnetic tunnel junction, a third magnetic tunnel junction and a fourth magnetic tunnel junction; S5. The magnetic layer is etched using photolithography technology to create a gap, and finally a nanowire memory with a boundary gap is obtained.

8. The method for manufacturing a nanowire memory with a boundary gap according to claim 7, characterized in that: In step S1, when the oxide sub-layer and the magnetic sub-layer are formed by sputtering, a baffle is used to block and form a shadow area, so as to produce a magnetic layer with a linear gradient thickness.

9. The method for manufacturing a nanowire memory with a boundary gap according to claim 7, characterized in that: The formed preliminary whole is subjected to annealing treatment, including: The preliminary whole is placed in an annealing furnace, and the temperature is increased from room temperature to 280°C at a heating rate of 50°C to 60°C per minute, and the temperature is kept constant at the set temperature for 30 minutes, and then the temperature of the preliminary whole is slowly reduced to room temperature in a controlled cooling manner, and rapid temperature changes are avoided during the cooling process to prevent the generation of internal stress; An out-of-plane magnetic field with a strength of 1kOe to 3kOe is applied during the annealing process to optimize the magnetic anisotropy and tunnel magnetoresistance properties.

10. The method for manufacturing a nanowire memory with a boundary gap according to claim 7, characterized in that: The MTJ layer in the preliminary overall structure after annealing is etched using photolithography technology, including: The preliminary whole after annealing is placed in a dust-free glove box, and a layer of positive or negative photoresist is coated on the surface of the MTJ layer by a spin coating process; then, a rectangular pattern is designed to develop the corresponding area through ultraviolet light or electron beam exposure; the developed MTJ layer is placed in an etching device, and an ion beam etching or reactive ion etching process is used to anisotropically etch the MTJ layer; finally, the remaining photoresist is removed by a stripping process to obtain a first magnetic tunnel junction, a second magnetic tunnel junction, a third magnetic tunnel junction and a fourth magnetic tunnel junction.

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