Trench junction barrier Schottky diode and manufacturing method thereof

Abstract

The invention provides a trench junction barrier Schottky diode and a manufacturing method thereof, and relates to the technical field of semiconductors. Comprising an N-type epitaxial wafer; the terminal region and the active region are located on the surface layer of the N-type epitaxial wafer; wherein the active region comprises a plurality of P columns, the P columns are arranged at intervals, a groove region is arranged on the surface of each P column, an ohmic contact layer, a barrier metal layer and a first metal layer are arranged in each groove region, the ohmic contact layers are in contact with the bottoms and the side walls of the groove regions, and the barrier metal layers are located between the ohmic contact layers and the first metal layers; the current dispersion structure is located in the first metal layer and on the surface of the first metal layer, and the current dispersion structure is used for dispersing surge current to the two sides of the trench region when the surge current occurs; a passivation protection layer located on the surface of the terminal area; the second metal layer is located on the surface of the active region; and the third metal layer is located on the back of the epitaxial wafer. The method has the advantages that the forward surge current processing capability, the reliability and the robustness of the device are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a trench junction barrier Schottky diode and a method for manufacturing the same. Background Art

[0002] TrenchjunctionbarrierSchottky (TJBS, trench junction barrier Schottky diode) is an improved structure of JunctionBarrier Schottky (JBS, junction barrier Schottky diode). By grooved and then P-type implantation, the formed junction barrier is deeply embedded in the device. Compared with conventional JBS, this structure can more effectively shield the Schottky surface electric field without changing the parameters of the epitaxial layer, further reduce leakage current, and increase breakdown voltage. At the same time, the spacing between adjacent P-type ion implantation areas can be appropriately widened to reduce on-state resistance and forward conduction voltage drop VF, but it will also lead to an increase in chip area and unit cost.

[0003] In order to obtain better performance without increasing the chip area, the width of the P-type ion implantation area can only be reduced, but this will increase the aspect ratio of the trench, which will easily lead to excessive heat concentration in the trench area, that is, the heat will be concentrated in the middle of the trench area, resulting in poor forward surge current handling capability of the device, and even thermal breakdown may cause damage to the device.

[0004] In summary, the trench junction barrier Schottky diode in the prior art has the problem that heat concentration is prone to occur in the middle of the trench area, resulting in a deterioration in the forward surge current handling capability of the device. Summary of the invention

[0005] The purpose of the present application is to provide a trench junction barrier Schottky diode and a manufacturing method thereof, so as to solve the problem that heat concentration is easy to occur in the middle of the trench region of the trench junction barrier Schottky diode existing in the prior art.

[0006] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows: On the one hand, an embodiment of the present application provides a trench junction barrier Schottky diode, wherein the trench junction barrier Schottky diode comprises: N-type epitaxial wafer; The terminal area and the active area are located on the surface of the N-type epitaxial wafer; wherein the active area includes a plurality of P columns, the plurality of P columns are arranged at intervals, and a groove area is arranged on the surface of each of the P columns, an ohmic contact layer, a barrier metal layer and a first metal layer are arranged in the groove area, the ohmic contact layer is in contact with the bottom and sidewall of the groove area, and the barrier metal layer is located between the ohmic contact layer and the first metal layer; a current spreading structure located in the first metal layer and on the surface of the first metal layer, wherein the current spreading structure is used to spread the surge current to both sides of the groove area when a surge current occurs; A passivation protection layer located on the surface of the terminal region; A second metal layer is located on the surface of the active area and a third metal layer is located on the back of the epitaxial wafer, and the first metal layer and the second metal layer are made of the same material.

[0007] Optionally, the current dispersion structure includes a first dielectric layer, a second dielectric layer, a third dielectric layer, a fourth metal layer and a fourth dielectric layer, the first dielectric layer, the second dielectric layer and the third dielectric layer are arranged at intervals and are all located in the first metal layer, the second dielectric layer and the third dielectric layer are located on both sides of the first dielectric layer, and the heights of the second dielectric layer and the third dielectric layer are both less than the height of the first dielectric layer; The fourth metal layer is located on the surface of the first dielectric layer, the fourth dielectric layer is located on the surface of the fourth metal layer, and the surface of the fourth metal layer is flush with the surface of the first metal layer; The materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are different from the material of the fourth dielectric layer; and the materials used to make the first dielectric layer, the second dielectric layer and the third dielectric layer are materials with low dielectric constant and high thermal conductivity.

[0008] Optionally, the surface of the fourth dielectric layer is configured to be arc-shaped.

[0009] Optionally, the current spreading structure is arranged symmetrically about a vertical center line.

[0010] Optionally, the second dielectric layer has the same structure as the third dielectric layer, and parameters of the first dielectric layer, the second dielectric layer and the third dielectric layer satisfy the formula: H2<H3; L2>L3; a>b; Among them, H2 represents the height of the second dielectric layer and the third dielectric layer, H3 represents the height of the first dielectric layer; L2 represents the width of the second dielectric layer and the third dielectric layer, L3 represents the width of the first dielectric layer; a represents the spacing between the second dielectric layer, the third dielectric layer and the surface, side wall and bottom of the first metal layer, b represents the spacing between the second dielectric layer, the third dielectric layer and the first dielectric layer.

[0011] Optionally, the parameters of the fourth dielectric layer satisfy the formula: y ≥ L3; L3≤z≤L3+2b; Wherein, y represents the width of the fourth dielectric layer, L3 represents the width of the first dielectric layer, z represents the width of the first metal layer, and b represents the spacing between the second dielectric layer, the third dielectric layer and the first dielectric layer.

[0012] Optionally, the current spreading structure further includes a fifth metal layer and a sixth metal layer, the fifth metal layer is located between the first dielectric layer and the second dielectric layer, and the sixth metal layer is located between the first dielectric layer and the third dielectric layer; The resistivity of the fifth metal layer and the sixth metal layer is greater than the resistivity of the first metal layer and less than the resistivity of the fourth metal layer.

[0013] Optionally, the parameters of the groove region satisfy the formula: L1>A=B; A=B Among them, L1 represents the width of the groove area; A represents the distance between the left edge of the P column and the left side wall of the groove, B represents the distance between the right edge of the P column and the right side wall of the groove, H1 represents the depth of the groove area, and H represents the depth of the P column.

[0014] On the other hand, an embodiment of the present application further provides a method for manufacturing a trench junction barrier Schottky diode, which is used to manufacture the above-mentioned trench junction barrier Schottky diode, and the method comprises: Provide N-type epitaxial wafers; Based on the N-type epitaxial wafer, a terminal area and an active area are defined; wherein the active area includes a plurality of P columns, the plurality of P columns are spaced apart, and a groove area is provided on the surface of each of the P columns, an ohmic contact layer, a barrier metal layer and a first metal layer are provided in the groove area, the ohmic contact layer is in contact with the bottom and sidewall of the groove area, and the barrier metal layer is located between the ohmic contact layer and the first metal layer; a current dispersion structure is provided in the first metal layer and on the surface of the first metal layer, and the current dispersion structure is used to disperse the surge current to both sides of the groove area when a surge current occurs; Making a passivation protection layer based on the surface of the terminal area; Manufacturing a second metal layer based on the surface of the active area, wherein the first metal layer and the second metal layer are made of the same material; A third metal layer is produced based on the back side of the epitaxial wafer.

[0015] Optionally, the step of defining a terminal region and an active region based on the N-type epitaxial wafer includes: Etching a plurality of first grooves based on the epitaxial wafer, wherein the plurality of first grooves are spaced apart from each other; Performing P-type ion implantation based on the position of the first trench; ​Based on the terminal region ion implantation; High temperature furnace tube annealing; Depositing an ohmic contact metal on the surface of the first trench, and etching after annealing to form an ohmic contact layer; Depositing a barrier metal layer on the surface of the ohmic contact layer and etching it; Depositing a first sublayer based on the surface of the barrier metal layer and etching; Two second grooves spaced apart from each other are etched based on the first sub-layer; Filling the two second trenches with insulating dielectric and etching to form a second dielectric layer and a third dielectric layer; Depositing and etching a second sublayer based on the surfaces of the first sublayer, the second dielectric layer and the third dielectric layer; Etching a third trench based on the second sub-layer, wherein the third trench is located between two second trenches; Filling the third trench with an insulating medium and etching the third trench to form a first dielectric layer; Depositing a third sublayer on the surface of the second sublayer and the first dielectric layer and etching the third sublayer, wherein the first sublayer, the second sublayer and the third sublayer constitute the first metal layer; Etching a fourth trench based on the third sub-layer, wherein the bottom of the fourth trench exposes the first dielectric layer; Depositing a fourth metal layer based on the fourth groove and etching; the surface of the fourth metal layer is flush with the surface of the first metal layer; An insulating medium is deposited on the surface of the fourth metal layer and then etched to form a fourth dielectric layer.

[0016] Compared with the prior art, the embodiments of the present application have the following beneficial effects: The embodiment of the present application provides a trench junction barrier Schottky diode and a manufacturing method thereof, wherein the trench junction barrier Schottky diode comprises: an N-type epitaxial wafer; a terminal region and an active region located on the surface layer of the N-type epitaxial wafer; wherein the active region comprises a plurality of P columns, the plurality of P columns are arranged at intervals, and a trench region is provided on the surface of each P column, an ohmic contact layer, a barrier metal layer and a first metal layer are provided in the trench region, the ohmic contact layer is in contact with the bottom and sidewall of the trench region, and the barrier metal layer is located between the ohmic contact layer and the first metal layer; a current dispersion structure is located in the first metal layer and on the surface of the first metal layer, the current dispersion structure is used to disperse the surge current to both sides of the trench region when a surge current occurs; a passivation protection layer is located on the surface of the terminal region; a second metal layer is located on the surface of the active region, and a third metal layer is located on the back of the epitaxial wafer, and the first metal layer and the second metal layer are made of the same material. On the one hand, since the trench junction barrier Schottky diode provided by the present application is provided with a barrier metal layer, it can prevent the reaction between the first metal layer and the ohmic contact layer at high temperature, greatly improving the metal semiconductor contact electrical performance, surge performance, thermal performance and mechanical performance of the device, thereby greatly improving the electrical performance, reliability and robustness of the device. On the other hand, by setting a current dispersion structure, it can disperse the current under abnormal conditions such as surge current, reduce the large amount of heat generated by excessive concentration of current in the middle area and excessive current density, reduce the probability of thermal failure, effectively improve the forward surge current IFSM of the device, and greatly improve the reliability and robustness of the device.

[0017] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of the cross-sectional structure of a trench junction barrier Schottky diode provided in an embodiment of the present application.

[0020] Figure 2 A schematic cross-sectional view of a P-pillar and its internal structure provided in an embodiment of the present application.

[0021] Figure 3 A schematic diagram of current under a large surge current condition provided in an embodiment of the present application.

[0022] Figure 4A schematic diagram of parameters of the groove region provided in an embodiment of the present application.

[0023] Figure 5 Another cross-sectional structural schematic diagram of the P-pillar and its internal structure provided in an embodiment of the present application.

[0024] Figure 6 A schematic diagram of the cross-sectional structure corresponding to etching of a plurality of first grooves according to an embodiment of the present application.

[0025] Figure 7 This is a schematic diagram of the cross-sectional structure corresponding to the high-temperature furnace tube after annealing provided in an embodiment of the present application.

[0026] Figure 8 This is a schematic diagram of the cross-sectional structure corresponding to the deposition of the ohmic contact layer and the barrier metal layer provided in an embodiment of the present application.

[0027] Fig. 9 This is a schematic diagram of the corresponding cross-sectional structure after depositing the first sub-layer and etching provided in an embodiment of the present application.

[0028] Fig.10 A schematic diagram of the corresponding cross-sectional structure after two second trenches are filled with insulating medium and etched according to an embodiment of the present application.

[0029] Fig.11 A schematic diagram of the corresponding cross-sectional structure after the third trench is filled with an insulating medium and etched according to an embodiment of the present application.

[0030] In the figure: 110-substrate; 120-epitaxial layer; 130-terminal region; 140-P column; 150-ohmic contact layer; 160-barrier metal layer; 170-first metal layer; 180-current dispersion structure; 181-first dielectric layer; 182-second dielectric layer; 183-third dielectric layer; 184-fourth metal layer; 185-fourth dielectric layer; 186-fifth metal layer; 187-sixth metal layer; 190-passivation protection layer; 200-second metal layer; 210-third metal layer. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0032] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0033] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0034] It should be noted that, in this document, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0035] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0036] As described in the background art, in the prior art, the trench junction barrier Schottky diode has the problem that heat concentration is prone to occur in the middle of the trench region, resulting in a deterioration in the forward surge current handling capability of the device.

[0037] In view of this, the present application provides a trench junction barrier Schottky diode, which avoids the concentration of heat in the trench area under abnormal operating conditions such as large surge current by setting a barrier metal layer and a current dispersion structure, thereby greatly improving the electrical performance, reliability and robustness of the device.

[0038] The trench junction barrier Schottky diode provided in the present application is exemplarily described below: As an implementation, see Figure 1 , the trench junction barrier Schottky diode comprises: An N-type epitaxial wafer; a terminal region 130 and an active region located on the surface of the N-type epitaxial wafer; wherein the active region includes a plurality of P columns 140, the plurality of P columns 140 are arranged at intervals, and a groove region is arranged on the surface of each P column 140, an ohmic contact layer 150, a barrier metal layer 160 and a first metal layer 170 are arranged in the groove region, the ohmic contact layer 150 is in contact with the bottom and sidewall of the groove region, and the barrier metal layer 160 is located between the ohmic contact layer 150 and the first metal layer 170; a current dispersion structure 180 located in the first metal layer 170 and on the surface of the first metal layer 170, the current dispersion structure 180 is used to disperse the surge current to both sides of the groove region when a surge current occurs; a passivation protection layer 190 located on the surface of the terminal region 130; a second metal layer 200 located on the surface of the active region and a third metal layer 210 located on the back of the epitaxial wafer, and the first metal layer 170 and the second metal layer 200 are made of the same material.

[0039] The N-type epitaxial wafer provided in the present application includes a substrate 110 and an epitaxial layer 120. The substrate 110 may be a SiC substrate, and the epitaxial layer 120 may be an N - Of course, the substrate 110 and the epitaxial layer 120 can also be made of other materials, for example, they can be made of Si material.

[0040] It should be noted that in the prior art, the ohmic contact layer 150 is generally made of Ni metal material, and after high-temperature annealing, Ni metal will form an ohmic contact alloy with the SiC material or Si material in the epitaxial layer, which is recorded as NiSi x When the groove area is exposed to high temperatures, for example, under abnormal conditions such as large surge current, the heat is concentrated in the groove area, resulting in a high temperature in the groove area, causing the electrode metal (usually Al metal) to be exposed to the NiSi x The alloy reacts, which in turn causes the electrical performance, reliability and robustness of the device to deteriorate.

[0041] Therefore, the trench junction barrier Schottky diode provided in the present application is provided with a barrier metal layer 160, which is located between the ohmic contact layer 150 and the first metal layer 170, and isolates the ohmic contact layer 150 from the first metal layer 170, thereby preventing the electrode metal and NiSi from being heated under high temperature. x The alloy reacts, greatly improving the device's gold-semiconductor contact electrical performance, surge performance, thermal performance and mechanical performance, thereby greatly improving the device's electrical performance, reliability and robustness.

[0042] It should be noted that the barrier metal layer 160 can be made of a material having excellent properties such as low resistivity, high melting point, high diffusion activation energy, and good chemical stability. For example, the barrier metal layer 160 is made of TiN / TaN material.

[0043] It should also be noted that the large surge current described in this application may refer to the condition where the device is subjected to a large current shock at the moment of the circuit being turned on. Under this condition, the current in the trench junction barrier Schottky diode flows through the trench region, resulting in temperature concentration in the trench region, especially in the middle area of ​​the trench region, where the temperature concentration is particularly obvious.

[0044] As an implementation, see Figure 2 The current dispersion structure 180 includes a first dielectric layer 181, a second dielectric layer 182, a third dielectric layer 183, a fourth metal layer 184 and a fourth dielectric layer 185. The first dielectric layer 181, the second dielectric layer 182 and the third dielectric layer 183 are arranged at intervals and are all located in the first metal layer 170. The second dielectric layer 182 and the third dielectric layer 183 are located on both sides of the first dielectric layer 181, and the heights of the second dielectric layer 182 and the third dielectric layer 183 are both less than the height of the first dielectric layer 181. The fourth metal layer 184 is located on the surface of the first dielectric layer 181, and the fourth dielectric layer 185 is located on the surface of the fourth metal layer 184, and the surface of the fourth metal layer 184 is flush with the surface of the first metal layer 170. The materials of the first dielectric layer 181, the second dielectric layer 182 and the third dielectric layer 183 are different from the material of the fourth dielectric layer 185, and the materials used to make the first dielectric layer 181, the second dielectric layer 182 and the third dielectric layer 183 are low dielectric constant and high thermal conductivity materials.

[0045] Among them, the materials of the first dielectric layer 181, the second dielectric layer 182 and the third dielectric layer 183 are the same. By setting the first dielectric layer 181, the second dielectric layer 182 and the third dielectric layer 183, the current can be dispersed under abnormal conditions such as surge current, reducing the large amount of heat generated by excessive current concentration and high current density, reducing the probability of thermal failure, effectively improving the forward surge current IFSM of the device, and greatly improving the reliability and robustness of the device. In addition, the materials of the first dielectric layer 181, the second dielectric layer 182 and the third dielectric layer 183 can be materials with both low dielectric constant and high thermal conductivity properties, such as boron nitride BN material. On the one hand, the low dielectric constant can reduce the impact of the introduction of complex parasitic effects on device performance, thereby enhancing the dynamic characteristics of the device and its control ability; on the other hand, the high thermal conductivity can quickly transfer heat energy, which is conducive to enhancing the heat dissipation performance and heat dissipation efficiency of the device, and greatly improving the reliability and robustness of the device.

[0046] In order to facilitate guiding the current in the middle area to the two sides of the groove area, a fourth metal layer 184 is provided on the surface of the first dielectric layer 181, wherein the resistivity of the fourth metal layer 184 is higher than the resistivity of the first metal layer 170. As an implementation method, Ti metal is used as the material for making the fourth metal layer 184. By providing the fourth metal layer 184 between the first dielectric layer 181 and the fourth dielectric layer, it is beneficial to guide the surge current from the two sides of the groove area to the epitaxial layer.

[0047] Among them, the fourth dielectric layer 185 is not made of the same material as the first dielectric layer 181, the second dielectric layer 182, and the third dielectric layer 183, and the fourth dielectric layer 185 can be made of dielectric materials with excellent thermal stability, such as SiO2, polysilicon, etc. On the one hand, the fourth dielectric layer 185 can further play a role in buffering thermal stress and internal stress. By flexibly adjusting the size of the combination of the first dielectric layer 181, the second dielectric layer 182, the third dielectric layer 183, and the fourth dielectric layer 185, the thermal field distribution and internal stress in this area can be flexibly adjusted, thereby improving the stability, reliability, and robustness of the electrical performance of the device. On the other hand, the present application sets the surface of the fourth dielectric layer 185 to an arc shape, which can play a role in more effectively dispersing the current, thereby further reducing the large amount of heat generated by high current density, greatly reducing the heating power of the device and the probability of thermal failure, and ultimately greatly improving the reliability and robustness of the device.

[0048] See also Figure 3 , is a schematic diagram of the current under a large surge current condition. In the figure, the dotted arrow represents the current line. Among them, since the fourth dielectric layer 185 is set to an arc structure, and the fourth metal layer 184 uses a material with a higher resistivity than the first metal layer 170, it is not easy for the current to flow through the middle area. In addition, the first dielectric layer 181, the second dielectric layer 182 and the third dielectric layer 183 are set, so that more current lines are guided to the sides of the second dielectric layer 182 and the third dielectric layer 183 (i.e., both sides of the groove area) through the entire current dispersion structure 180, and only a small amount of current lines flow between the first dielectric layer 181 and the second dielectric layer 182, and the first dielectric layer 181 and the third dielectric layer 183. Therefore, in the groove area, the current lines are not easy to concentrate in the middle area of ​​the groove, avoiding a large amount of heat generated by excessive current density, reducing the probability of thermal failure, effectively improving the forward surge current IFSM of the device, and greatly improving the reliability and robustness of the device.

[0049] In addition, to improve the overall performance of trench junction barrier Schottky diodes, please refer to Figure 4 , the parameters set in this application are as follows: First, the parameters of the entire groove area satisfy the formula: L1>A=B; A=B Among them, L1 represents the width of the groove area; A represents the distance between the left edge of the P column and the left side wall of the groove, B represents the distance between the right edge of the P column and the right side wall of the groove, H1 represents the depth of the groove area, and H represents the depth of the P column 140.

[0050] On the one hand, setting L1>A=B can ensure that the size of the entire trench area is large. The large area size can make the ohmic contact more complete, which is beneficial to reduce the contact resistance at the bottom of the trench, improve the bipolar conduction characteristics of the device, and thus improve the surge current handling capability of the device. On the other hand, setting A=B

[0051] The current dispersion structure 180 is symmetrically arranged about the vertical center line as a whole, so that the overall structure inside the groove remains symmetrical, and the dimensions of each structure can be flexibly adjusted, which can comprehensively and efficiently adjust and improve the static and dynamic characteristics of the device, bipolar conduction performance, forward surge current IFSM, heat dissipation performance, etc., thereby making the device performance more stable and having higher reliability and robustness.

[0052] The second dielectric layer 182 and the third dielectric layer 183 have the same structure, and the parameters of the first dielectric layer 181, the second dielectric layer 182 and the third dielectric layer 183 satisfy the formula: H2<H3; L2>L3; a>b; Among them, H2 represents the height of the second dielectric layer 182 and the third dielectric layer 183, H3 represents the height of the first dielectric layer 181; L2 represents the width of the second dielectric layer 182 and the third dielectric layer 183, L3 represents the width of the first dielectric layer 181; a represents the distance between the second dielectric layer 182, the third dielectric layer 183 and the surface, side wall and bottom of the first metal layer 170, and b represents the distance between the second dielectric layer 182, the third dielectric layer 183 and the first dielectric layer 181.

[0053] This setting can prevent the heat caused by surge current from concentrating in the middle area of ​​the trench to the greatest extent, greatly improve the thermal field distribution and thermal stress of the device, and enhance the heat dissipation performance, electrical performance stability, reliability and robustness of the device.

[0054] It should be noted that, through research by the applicant, it is found that when a≥3b, the current dispersion effect is better, making it less likely for heat to concentrate in the middle of the groove area. Therefore, the present application sets a≥3b.​​

[0055] Furthermore, the parameters of the fourth dielectric layer 185 satisfy the formula: y ≥ L3; L3≤z≤L3+2b; Wherein, y represents the width of the fourth dielectric layer 185 , L3 represents the width of the first dielectric layer 181 , z represents the width of the first metal layer 170 , and b represents the spacing between the second dielectric layer 182 , the third dielectric layer 183 and the first dielectric layer 181 .

[0056] This arrangement is more conducive to guiding the surge current from both sides of the trench area to the epitaxial layer.

[0057] In another implementation, see Figure 5 The current dispersion structure 180 also includes a fifth metal layer 186 and a sixth metal layer 187. The fifth metal layer 186 is located between the first dielectric layer 181 and the second dielectric layer 182, and the sixth metal layer 187 is located between the first dielectric layer 181 and the third dielectric layer 183. The resistivity of the fifth metal layer 186 and the sixth metal layer 187 is greater than the resistivity of the first metal layer 170 and less than the resistivity of the fourth metal layer 184.

[0058] Since the resistivity of the fifth metal layer 186 and the sixth metal layer 187 is greater than that of the first metal layer 170 and less than that of the fourth metal layer 184, when a large surge current is present, the current is less likely to flow between the first dielectric layer 181 and the second dielectric layer 182, and between the first dielectric layer 181 and the third dielectric layer 183, so that the current can be more dispersed. That is, the current is less likely to flow through the middle area, but flows through both sides of the groove area, so that the heat can be effectively prevented from being concentrated in the middle of the groove area.

[0059] Based on the above implementation, the embodiment of the present application further provides a method for manufacturing a trench junction barrier Schottky diode, which is used to manufacture the above trench junction barrier Schottky diode. The method includes: S120, providing N-type epitaxial wafers; S104, defining a terminal region and an active region based on an N-type epitaxial wafer; wherein the active region includes a plurality of P columns, the plurality of P columns are spaced apart, and a groove region is provided on the surface of each P column, an ohmic contact layer, a barrier metal layer and a first metal layer are provided in the groove region, the ohmic contact layer is in contact with the bottom and sidewall of the groove region, and the barrier metal layer is located between the ohmic contact layer and the first metal layer; a current dispersion structure is provided in the first metal layer and on the surface of the first metal layer, and the current dispersion structure is used to disperse the surge current to both sides of the groove region when a surge current occurs; S106, forming a passivation protection layer based on the surface of the terminal area; S108, manufacturing a second metal layer based on the surface of the active area, wherein the first metal layer and the second metal layer are made of the same material; S110, forming a third metal layer based on the back side of the epitaxial wafer.

[0060] The following is an exemplary description of step S104 in conjunction with the accompanying drawings: See also Figure 6 First, a plurality of first grooves are etched based on the epitaxial wafer, wherein the plurality of first grooves are spaced apart from each other. It should be noted that the present application does not limit the number of first grooves, and the figure takes three first grooves as an example for illustration.

[0061] Performing P-type ion implantation based on the position of the first trench; Based on ion implantation in the terminal region; High temperature furnace tube annealing; the structure after annealing is as follows Figure 7 shown.

[0062] Depositing an ohmic contact metal on the surface of the first trench, and etching after annealing to form an ohmic contact layer; A barrier metal layer is deposited on the surface of the ohmic contact layer and then etched. The structure after the ohmic contact layer and the barrier metal layer are deposited is as follows: Figure 8 The etching mentioned in the present application refers to removing the redundant parts through an etching process.

[0063] See also Fig. 9 , a first sublayer is deposited and etched based on the surface of the barrier metal layer. The first sublayer is used to fill the second dielectric layer and the third dielectric layer, so the thickness of the deposited first sublayer can be determined based on the height of the second dielectric layer and the third dielectric layer.

[0064] Two second grooves are set based on the etching interval of the first sub-layer; See also Fig.10 , filling the two second trenches with insulating dielectric and etching to form a second dielectric layer and a third dielectric layer; The second sublayer is deposited and etched on the surfaces of the first sublayer, the second dielectric layer and the third dielectric layer. The purpose of depositing the second sublayer is to make the first dielectric layer, so the thickness of the second sublayer can be adjusted based on the height of the first dielectric layer.

[0065] Etching a third trench based on the second sub-layer, wherein the third trench is located between the two second trenches; See also Fig.11 , filling the third trench with an insulating dielectric and etching to form a first dielectric layer; Then, a third sublayer is deposited on the surface of the second sublayer and the first dielectric layer and then etched, wherein the first sublayer, the second sublayer and the third sublayer constitute a first metal layer; etching a fourth trench based on the third sub-layer, wherein the first dielectric layer is exposed at the bottom of the fourth trench; Depositing a fourth metal layer based on the fourth groove and etching; the surface of the fourth metal layer is flush with the surface of the first metal layer; Finally, an insulating medium is deposited on the surface of the fourth metal layer and then etched to form a fourth dielectric layer. By adjusting the photolithography and etching process parameters, the surface of the fourth dielectric layer can be curved.

[0066] In summary, the embodiment of the present application provides a trench junction barrier Schottky diode and a manufacturing method thereof, wherein the trench junction barrier Schottky diode comprises: an N-type epitaxial wafer; a terminal region and an active region located on the surface of the N-type epitaxial wafer; wherein the active region comprises a plurality of P columns, the plurality of P columns are arranged at intervals, and a trench region is provided on the surface of each P column, an ohmic contact layer, a barrier metal layer and a first metal layer are provided in the trench region, the ohmic contact layer is in contact with the bottom and sidewalls of the trench region, and the barrier metal layer is located between the ohmic contact layer and the first metal layer; a current dispersion structure located in the first metal layer and on the surface of the first metal layer, the current dispersion structure is used to disperse the surge current to both sides of the trench region when a surge current occurs; a passivation protection layer located on the surface of the terminal region; a second metal layer located on the surface of the active region and a third metal layer located on the back of the epitaxial wafer, and the first metal layer and the second metal layer are made of the same material. On the one hand, since the trench junction barrier Schottky diode provided by the present application is provided with a barrier metal layer, it can prevent the reaction between the first metal layer and the ohmic contact layer at high temperature, greatly improving the metal semiconductor contact electrical performance, surge performance, thermal performance and mechanical performance of the device, thereby greatly improving the electrical performance, reliability and robustness of the device. On the other hand, by setting a current dispersion structure, it can disperse the current under abnormal conditions such as surge current, reduce the large amount of heat generated by excessive concentration of current in the middle area and excessive current density, reduce the probability of thermal failure, effectively improve the forward surge current IFSM of the device, and greatly improve the reliability and robustness of the device.

[0067] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0068] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A trench junction barrier Schottky diode, characterized in that: The trench junction barrier Schottky diode comprises: N-type epitaxial wafer; The terminal area and the active area are located on the surface of the N-type epitaxial wafer; wherein the active area includes a plurality of P columns, the plurality of P columns are arranged at intervals, and a groove area is arranged on the surface of each of the P columns, an ohmic contact layer, a barrier metal layer and a first metal layer are arranged in the groove area, the ohmic contact layer is in contact with the bottom and sidewall of the groove area, and the barrier metal layer is located between the ohmic contact layer and the first metal layer; a current spreading structure located in the first metal layer and on the surface of the first metal layer, wherein the current spreading structure is used to spread the surge current to both sides of the groove area when a surge current occurs; A passivation protection layer located on the surface of the terminal region; A second metal layer is located on the surface of the active area and a third metal layer is located on the back of the epitaxial wafer, and the first metal layer and the second metal layer are made of the same material.

2. The trench junction barrier Schottky diode according to claim 1, characterized in that: The current dispersion structure comprises a first dielectric layer, a second dielectric layer, a third dielectric layer, a fourth metal layer and a fourth dielectric layer, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer are arranged at intervals and are all located in the first metal layer, the second dielectric layer and the third dielectric layer are located on both sides of the first dielectric layer, and the heights of the second dielectric layer and the third dielectric layer are both less than the height of the first dielectric layer; The fourth metal layer is located on the surface of the first dielectric layer, the fourth dielectric layer is located on the surface of the fourth metal layer, and the surface of the fourth metal layer is flush with the surface of the first metal layer; The materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are different from the material of the fourth dielectric layer; and the materials used to make the first dielectric layer, the second dielectric layer and the third dielectric layer are materials with low dielectric constant and high thermal conductivity.

3. The trench junction barrier Schottky diode according to claim 2, characterized in that: The surface of the fourth dielectric layer is configured to be arc-shaped.

4. The trench junction barrier Schottky diode according to claim 2, characterized in that: The current spreading structure is symmetrically arranged about the vertical center line.

5. The trench junction barrier Schottky diode according to claim 2, characterized in that: The second dielectric layer has the same structure as the third dielectric layer, and the parameters of the first dielectric layer, the second dielectric layer and the third dielectric layer satisfy the formula: H2<H3; L2>L3; a>b; Among them, H2 represents the height of the second dielectric layer and the third dielectric layer, H3 represents the height of the first dielectric layer; L2 represents the width of the second dielectric layer and the third dielectric layer, L3 represents the width of the first dielectric layer; a represents the spacing between the second dielectric layer, the third dielectric layer and the surface, side wall and bottom of the first metal layer, b represents the spacing between the second dielectric layer, the third dielectric layer and the first dielectric layer.

6. The trench junction barrier Schottky diode according to claim 5, characterized in that: The parameters of the fourth dielectric layer satisfy the formula: y ≥ L3; L3≤z≤L3+2b; Wherein, y represents the width of the fourth dielectric layer, L3 represents the width of the first dielectric layer, z represents the width of the first metal layer, and b represents the spacing between the second dielectric layer, the third dielectric layer and the first dielectric layer.

7. The trench junction barrier Schottky diode according to claim 2, characterized in that: The current spreading structure further includes a fifth metal layer and a sixth metal layer, wherein the fifth metal layer is located between the first dielectric layer and the second dielectric layer, and the sixth metal layer is located between the first dielectric layer and the third dielectric layer; The resistivity of the fifth metal layer and the sixth metal layer is greater than the resistivity of the first metal layer and less than the resistivity of the fourth metal layer.

8. The trench junction barrier Schottky diode according to claim 1, characterized in that: The parameters of the groove region satisfy the formula: L1>A=B; A=B<H1<1 / 2H; Among them, L1 represents the width of the groove area; A represents the distance between the left edge of the P column and the left side wall of the groove, B represents the distance between the right edge of the P column and the right side wall of the groove, H1 represents the depth of the groove area, and H represents the depth of the P column.

9. A method for manufacturing a trench junction barrier Schottky diode, characterized in that: For manufacturing the trench junction barrier Schottky diode according to any one of claims 1 to 8, the method comprises: Provide N-type epitaxial wafers; Based on the N-type epitaxial wafer, a terminal area and an active area are defined; wherein the active area includes a plurality of P columns, the plurality of P columns are spaced apart, and a groove area is provided on the surface of each of the P columns, an ohmic contact layer, a barrier metal layer and a first metal layer are provided in the groove area, the ohmic contact layer is in contact with the bottom and sidewall of the groove area, and the barrier metal layer is located between the ohmic contact layer and the first metal layer; a current dispersion structure is provided in the first metal layer and on the surface of the first metal layer, and the current dispersion structure is used to disperse the surge current to both sides of the groove area when a surge current occurs; Making a passivation protection layer based on the surface of the terminal area; Manufacturing a second metal layer based on the surface of the active area, wherein the first metal layer and the second metal layer are made of the same material; A third metal layer is produced based on the back side of the epitaxial wafer.

10. The method for manufacturing a trench junction barrier Schottky diode according to claim 9, characterized in that: The steps of defining the terminal area and the active area based on the N-type epitaxial wafer include: Etching a plurality of first grooves based on the epitaxial wafer, wherein the plurality of first grooves are spaced apart from each other; Performing P-type ion implantation based on the position of the first trench; Based on the terminal region ion implantation; High temperature furnace tube annealing; Depositing an ohmic contact metal on the surface of the first trench, and etching after annealing to form an ohmic contact layer; Depositing a barrier metal layer on the surface of the ohmic contact layer and etching it; Depositing a first sublayer based on the surface of the barrier metal layer and etching; Two second grooves spaced apart from each other are etched based on the first sub-layer; Filling the two second trenches with insulating dielectric and etching to form a second dielectric layer and a third dielectric layer; Depositing and etching a second sublayer based on the surfaces of the first sublayer, the second dielectric layer and the third dielectric layer; Etching a third trench based on the second sub-layer, wherein the third trench is located between two second trenches; Filling the third trench with an insulating medium and etching the third trench to form a first dielectric layer; Depositing a third sublayer on the surface of the second sublayer and the first dielectric layer and etching the third sublayer, wherein the first sublayer, the second sublayer and the third sublayer constitute the first metal layer; Etching a fourth trench based on the third sub-layer, wherein the bottom of the fourth trench exposes the first dielectric layer; Depositing a fourth metal layer based on the fourth groove and etching; the surface of the fourth metal layer is flush with the surface of the first metal layer; An insulating medium is deposited on the surface of the fourth metal layer and then etched to form a fourth dielectric layer.

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