A trench junction barrier Schottky diode and a manufacturing method thereof

Abstract

The present application provides a trench junction barrier Schottky diode and a manufacturing method thereof, relating to the field of semiconductor technology. It includes an N-type epitaxial wafer; a terminal region and an active region located on the surface layer of the N-type epitaxial wafer; wherein, the active region includes a plurality of P pillars, the plurality of P pillars are arranged at intervals, and a trench region is provided on the surface of each P pillar, an ohmic contact layer, a barrier metal layer and a first metal layer are provided in the trench region, the ohmic contact layer contacts the bottom and side walls of the trench region, and the barrier metal layer is located between the ohmic contact layer and the first metal layer; a current dispersion structure located inside and on the surface of the first metal layer, the current dispersion structure is used to disperse the surge current to both sides of the trench region when a surge current occurs; a passivation protection layer located on the surface of the terminal region; a second metal layer located on the surface of the active region and a third metal layer located on the back surface of the epitaxial wafer. The present application has the advantages of improving the forward surge current handling ability of the device, as well as the reliability and robustness of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology. Specifically, it relates to a trench junction barrier Schottky diode and a manufacturing method thereof. Background Art

[0002] Trench junction barrier Schottky (TJBS) is an improved structure of Junction Barrier Schottky (JBS). After grooving and then performing P-type implantation, the formed junction barrier penetrates deep into the device. Compared with the conventional JBS, this structure can more effectively shield the Schottky surface electric field without changing the epitaxial layer parameters, further reduce the leakage current, increase the breakdown voltage, and at the same time, the spacing between adjacent P-type ion implantation regions can be appropriately widened to reduce the on-state resistance and lower the forward conduction voltage drop VF. However, it will also lead to an increase in chip area and unit cost.

[0003] In order to obtain better performance without increasing the chip area, only the width of the P-type ion implantation region can be reduced, but this will lead to an increase in the aspect ratio of the trench, making it easy for the heat in the trench region to be overly concentrated, that is, the heat is concentrated in the middle position of the trench region, resulting in poor forward surge current handling ability of the device, and even thermal breakdown may damage the device.

[0004] In summary, in the prior art, there is a problem that heat is easily concentrated in the middle position of the trench region of the trench junction barrier Schottky diode, resulting in poor forward surge current handling ability of the device. Summary of the Invention

[0005] The purpose of this application is to provide a trench junction barrier Schottky diode and a manufacturing method thereof to solve the problem that heat is easily concentrated in the middle position of the trench region of the trench junction barrier Schottky diode in the prior art.

[0006] To achieve the above purpose, the technical solutions adopted in the embodiments of this application are as follows:

[0007] On the one hand, the embodiments of this application provide a trench junction barrier Schottky diode, and the trench junction barrier Schottky diode includes:

[0008] An N-type epitaxial wafer;

[0009] The terminal region and the active region located on the surface layer of the N-type epitaxial wafer; wherein, the active region includes a plurality of P pillars, the plurality of P pillars are arranged at intervals, and a trench region is provided on the surface of each P pillar, and an ohmic contact layer, a barrier metal layer and a first metal layer are provided in the trench region, the ohmic contact layer is in contact with the bottom and side walls of the trench region, and the barrier metal layer is located between the ohmic contact layer and the first metal layer;

[0010] A current dispersion structure located within and on the surface of the first metal layer, the current dispersion structure being configured to disperse surge current to both sides of the trench region when surge current occurs;

[0011] A passivation protection layer located on the surface of the terminal region;

[0012] A second metal layer located on the surface of the active region and a third metal layer located on the back surface of the epitaxial wafer, and the first metal layer and the second metal layer are made of the same material.

[0013] Optionally, the current dispersion structure includes a first dielectric layer, a second dielectric layer, a third dielectric layer, a fourth metal layer and a fourth dielectric layer, the first dielectric layer, the second dielectric layer and the third dielectric layer are arranged at intervals and are all located within the first metal layer, the second dielectric layer and the third dielectric layer are located on both sides of the first dielectric layer, and the heights of the second dielectric layer and the third dielectric layer are both less than the height of the first dielectric layer;

[0014] The fourth metal layer is located on the surface of the first dielectric layer, the fourth dielectric layer is located on the surface of the fourth metal layer, and the surface of the fourth metal layer is flush with the surface of the first metal layer;

[0015] The materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are different from the material of the fourth dielectric layer; and the materials for making the first dielectric layer, the second dielectric layer and the third dielectric layer are low dielectric constant and high thermal conductivity materials.

[0016] Optionally, the surface of the fourth dielectric layer is set to be arc-shaped.

[0017] Optionally, the current dispersion structure is symmetrically arranged about a vertical center line.

[0018] Optionally, the second dielectric layer and the third dielectric layer have the same structure, and the parameters of the first dielectric layer, the second dielectric layer and the third dielectric layer satisfy the formula:

[0019] H2 < H3;

[0020] L2 > L3;

[0021] a > b;

[0022] Wherein, H2 represents the height of the second dielectric layer and the third dielectric layer, and H3 represents the height of the first dielectric layer; L2 represents the width of the second dielectric layer and the third dielectric layer, and L3 represents the width of the first dielectric layer; a represents the distance between the second dielectric layer, the third dielectric layer and the surface, side wall and bottom of the first metal layer, and b represents the distance between the second dielectric layer, the third dielectric layer and the first dielectric layer.

[0023] Optionally, the parameters of the fourth dielectric layer satisfy the formula:

[0024] y ≥ L3;

[0025] L3 ≤ z ≤ L3 + 2b;

[0026] Wherein, y represents the width of the fourth dielectric layer, L3 represents the width of the first dielectric layer, z represents the width of the first metal layer, and b represents the distance between the second dielectric layer, the third dielectric layer and the first dielectric layer.

[0027] Optionally, the current dispersion structure further includes a fifth metal layer and a sixth metal layer. The fifth metal layer is located between the first dielectric layer and the second dielectric layer, and the sixth metal layer is located between the first dielectric layer and the third dielectric layer;

[0028] The resistivity of the fifth metal layer and the sixth metal layer is greater than the resistivity of the first metal layer and less than the resistivity of the fourth metal layer.

[0029] Optionally, the parameters of the trench region satisfy the formula:

[0030] L1 > A = B;

[0031] A = B < H1 < 1 / 2H;

[0032] Wherein, L1 represents the width of the trench region; A represents the distance between the left edge of the P column and the left side wall of the trench, B represents the distance between the right edge of the P column and the right side wall of the trench, H1 represents the depth of the trench region, and H represents the depth of the P column.

[0033] On the other hand, an embodiment of the present application also provides a method for manufacturing a trench junction barrier Schottky diode for manufacturing the above-mentioned trench junction barrier Schottky diode. The method includes:

[0034] Providing an N-type epitaxial wafer;

[0035] Define a terminal region and an active region based on the N-type epitaxial wafer; wherein, the active region includes a plurality of P-columns, the plurality of P-columns are spaced apart from each other, and a trench region is provided on the surface of each P-column, and an ohmic contact layer, a barrier metal layer, and a first metal layer are provided in the trench region, the ohmic contact layer is in contact with the bottom and side walls of the trench region, and the barrier metal layer is located between the ohmic contact layer and the first metal layer; a current dispersion structure is provided inside and on the surface of the first metal layer, and the current dispersion structure is used to disperse the surge current to both sides of the trench region when a surge current occurs;

[0036] Fabricate a passivation protection layer based on the surface of the terminal region;

[0037] Fabricate a second metal layer based on the surface of the active region, and the first metal layer and the second metal layer are made of the same material;

[0038] Fabricate a third metal layer based on the back surface of the epitaxial wafer.

[0039] Optionally, the step of defining a terminal region and an active region based on the N-type epitaxial wafer includes:

[0040] Etch a plurality of first trenches based on the epitaxial wafer, wherein the plurality of first trenches are spaced apart from each other;

[0041] Perform P-type ion implantation based on the positions of the first trenches;

[0042] Perform ion implantation based on the terminal region;

[0043] Anneal in a high-temperature furnace tube;

[0044] Deposit ohmic contact metal on the surface of the first trench and etch after annealing to form an ohmic contact layer;

[0045] Deposit a barrier metal layer on the surface of the ohmic contact layer and etch;

[0046] Deposit a first sub-layer on the surface of the barrier metal layer and etch;

[0047] Etch two second trenches spaced apart based on the first sub-layer;

[0048] Fill the insulating medium in the two second trenches and etch to form a second dielectric layer and a third dielectric layer;

[0049] Deposit a second sub-layer on the surfaces of the first sub-layer, the second dielectric layer, and the third dielectric layer and etch;

[0050] Etch a third trench based on the second sub-layer, wherein the third trench is located between the two second trenches;

[0051] Fill the third trench with an insulating dielectric and etch it to form a first dielectric layer;

[0052] Deposit and etch a third sub-layer on the surface of the second sub-layer and the first dielectric layer. Among them, the first sub-layer, the second sub-layer, and the third sub-layer form the first metal layer;

[0053] Etch a fourth trench based on the third sub-layer, and the bottom of the fourth trench exposes the first dielectric layer;

[0054] Deposit and etch a fourth metal layer based on the fourth trench; the surface of the fourth metal layer is flush with the surface of the first metal layer;

[0055] Deposit and etch an insulating dielectric on the surface of the fourth metal layer to form a fourth dielectric layer.

[0056] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0057] The embodiments of the present application provide a trench junction barrier Schottky diode and a manufacturing method thereof. The trench junction barrier Schottky diode includes: an N-type epitaxial wafer; a terminal region and an active region located on the surface layer of the N-type epitaxial wafer; among them, the active region includes a plurality of P-columns, and the plurality of P-columns are arranged at intervals, and an ohmic contact layer, a barrier metal layer, and a first metal layer are arranged in the trench region of each P-column. The ohmic contact layer contacts the bottom and side walls of the trench region, and the barrier metal layer is located between the ohmic contact layer and the first metal layer; a current dispersion structure located inside and on the surface of the first metal layer, and the current dispersion structure is used to disperse the surge current to both sides of the trench region when a surge current occurs; a passivation protection layer located on the surface of the terminal region; a second metal layer located on the surface of the active region and a third metal layer located on the back surface of the epitaxial wafer, and the materials of the first metal layer and the second metal layer are the same. On the one hand, since a barrier metal layer is provided in the trench junction barrier Schottky diode provided by the present application, it can prevent the reaction between the first metal layer and the ohmic contact layer at high temperatures, greatly improve the metal-semiconductor contact electrical performance, surge performance, thermal performance, and mechanical performance of the device, and thus greatly improve the electrical performance, reliability, and robustness of the device. On the other hand, by setting the current dispersion structure, it can play a role in dispersing current under abnormal conditions such as large surge currents, reduce the large amount of heat generated by the excessive concentration of current and high current density in the middle region, reduce the probability of thermal failure, effectively improve the forward surge current IFSM of the device, and greatly improve the reliability and robustness of the device.

[0058] In order to make the above objects, features, and advantages of the present application more obvious and understandable, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings. Description of the Drawings

[0059] To more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative efforts.

[0060] Figure 1 It is a schematic cross-sectional structure diagram of the trench junction barrier Schottky diode provided by the embodiment of the present application.

[0061] Figure 2 It is a schematic cross-sectional structure diagram of the P pillar and its internal structure provided by the embodiment of the present application.

[0062] Figure 3 It is a schematic current diagram under the condition of large surge current provided by the embodiment of the present application.

[0063] Figure 4 It is a schematic parameter diagram of the trench region provided by the embodiment of the present application.

[0064] Figure 5 It is another schematic cross-sectional structure diagram of the P pillar and its internal structure provided by the embodiment of the present application.

[0065] Figure 6 It is a schematic cross-sectional structure diagram corresponding to after etching a plurality of first trenches provided by the embodiment of the present application.

[0066] Figure 7 It is a schematic cross-sectional structure diagram corresponding to after high-temperature furnace tube annealing provided by the embodiment of the present application.

[0067] Figure 8 It is a schematic cross-sectional structure diagram corresponding to after depositing an ohmic contact layer and a barrier metal layer provided by the embodiment of the present application.

[0068] Figure 9 It is a schematic cross-sectional structure diagram corresponding to after depositing and etching the first sub-layer provided by the embodiment of the present application.

[0069] Figure 10 It is a schematic cross-sectional structure diagram corresponding to after filling and etching the insulating medium based on two second trenches provided by the embodiment of the present application.

[0070] Figure 11 It is a schematic cross-sectional structure diagram corresponding to after filling and etching the insulating medium based on the third trench provided by the embodiment of the present application.

[0071] In the figure:

[0072] 110 - Substrate; 120 - Epitaxial layer; 130 - Terminal region; 140 - P pillar; 150 - Ohmic contact layer; 160 - Barrier metal layer; 170 - First metal layer; 180 - Current dispersion structure; 181 - First dielectric layer; 182 - Second dielectric layer; 183 - Third dielectric layer; 184 - Fourth metal layer; 185 - Fourth dielectric layer; 186 - Fifth metal layer; 187 - Sixth metal layer; 190 - Passivation protection layer; 200 - Second metal layer; 210 - Third metal layer. Detailed implementation manners

[0073] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. The components of the embodiments of the present application usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0074] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts fall within the scope of protection of the present application.

[0075] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, the terms "first", "second", etc. are only used for differential description and cannot be understood as indicating or implying relative importance.

[0076] It should be noted that, in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0077] The following will describe in detail some implementation manners of the present application with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0078] As described in the background art, in the prior art, there is a problem that heat concentration is likely to occur at the middle position of the trench region in the trench junction barrier Schottky diode, resulting in poor forward surge current handling ability of the device.

[0079] In view of this, the present application provides a trench junction barrier Schottky diode. By setting a barrier metal layer and a current dispersion structure, it is possible to avoid the heat concentration in the trench region under abnormal working conditions such as large surge currents, and greatly improve the electrical performance, reliability, and robustness of the device.

[0080] The trench junction barrier Schottky diode provided by the present application will be exemplarily described below:

[0081] As an implementation manner, please refer to Figure 1 , the trench junction barrier Schottky diode includes:

[0082] An N-type epitaxial wafer; a terminal region 130 and an active region located on the surface layer of the N-type epitaxial wafer; wherein, the active region includes a plurality of P pillars 140, the plurality of P pillars 140 are arranged at intervals, and an ohmic contact layer 150, a barrier metal layer 160, and a first metal layer 170 are arranged in the trench region. The ohmic contact layer 150 is in contact with the bottom and side walls of the trench region, and the barrier metal layer 160 is located between the ohmic contact layer 150 and the first metal layer 170; a current dispersion structure 180 located inside and on the surface of the first metal layer 170, and the current dispersion structure 180 is used to disperse the surge current to both sides of the trench region when a surge current occurs; a passivation protection layer 190 located on the surface of the terminal region 130; a second metal layer 200 located on the surface of the active region and a third metal layer 210 located on the back surface of the epitaxial wafer, and the first metal layer 170 and the second metal layer 200 are made of the same material.

[0083] Among them, the N-type epitaxial wafer provided by the present application includes a substrate 110 and an epitaxial layer 120. The substrate 110 can adopt a SiC substrate, and the epitaxial layer 120 can be made of N - -doped SiC material. Of course, the substrate 110 and the epitaxial layer 120 can also be made of other materials. For example, they can be made of Si material.

[0084] It should be noted that in the prior art, the ohmic contact layer 150 is generally made of Ni metal material. After high-temperature annealing, Ni metal will form an ohmic contact alloy with the SiC material or Si material in the epitaxial layer, denoted as NiSi x alloy. When the trench region is in a high-temperature situation, for example, under abnormal working conditions such as large surge currents, the heat in the trench region is concentrated, resulting in a high temperature in the trench region, causing the electrode metal (generally Al metal) to react with NiSi x alloy, thereby deteriorating the electrical performance, reliability, and robustness of the device.

[0085] Therefore, a blocking metal layer 160 is provided in the trench junction barrier Schottky diode provided by the present application. The blocking metal layer 160 is located between the ohmic contact layer 150 and the first metal layer 170, and isolates the ohmic contact layer 150 from the first metal layer 170, thereby preventing the electrode metal and NiSi x from reacting with the alloy at high temperatures, greatly improving the metal-semiconductor contact electrical performance, surge performance, thermal performance and mechanical performance of the device, and thus greatly improving the electrical performance, reliability and robustness of the device.

[0086] It should be noted that the blocking metal layer 160 can be selected from materials with excellent properties such as low resistivity, high melting point, high diffusion activation energy, and good chemical stability. For example, the blocking metal layer 160 is made of TiN / TaN material.

[0087] It should also be noted that the large surge current described in the present application can refer to the condition where the device withstands a large current impact when the circuit is turned on instantaneously. Under this condition, the current in the trench junction barrier Schottky diode concentrates and flows through the trench region, resulting in temperature concentration in the trench region, especially in the middle region of the trench region, where the temperature concentration is particularly obvious.

[0088] As an implementation, please refer to Figure 2 , the current dispersion structure 180 includes a first dielectric layer 181, a second dielectric layer 182, a third dielectric layer 183, a fourth metal layer 184 and a fourth dielectric layer 185. The first dielectric layer 181, the second dielectric layer 182 and the third dielectric layer 183 are arranged at intervals and are all located in the first metal layer 170. The second dielectric layer 182 and the third dielectric layer 183 are located on both sides of the first dielectric layer 181, and the heights of the second dielectric layer 182 and the third dielectric layer 183 are both smaller than the height of the first dielectric layer 181; the fourth metal layer 184 is located on the surface of the first dielectric layer 181, the fourth dielectric layer 185 is located on the surface of the fourth metal layer 184, and the surface of the fourth metal layer 184 is flush with the surface of the first metal layer 170; the materials of the first dielectric layer 181, the second dielectric layer 182 and the third dielectric layer 183 are different from the material of the fourth dielectric layer 185, and the materials for making the first dielectric layer 181, the second dielectric layer 182 and the third dielectric layer 183 are low dielectric constant and high thermal conductivity materials.

[0089] Among them, the materials of the first dielectric layer 181, the second dielectric layer 182, and the third dielectric layer 183 are the same. By providing the first dielectric layer 181, the second dielectric layer 182, and the third dielectric layer 183, it is possible to disperse current under abnormal operating conditions such as large surge currents, reducing the large amount of heat generated by excessive current concentration and high current density, reducing the probability of thermal failure, effectively improving the forward surge current IFSM of the device, and significantly enhancing the reliability and robustness of the device. Moreover, the materials of the first dielectric layer 181, the second dielectric layer 182, and the third dielectric layer 183 can be materials with both low dielectric constant and high thermal conductivity properties. For example, boron nitride BN materials can be used. On the one hand, the low dielectric constant can reduce the impact of the introduction of complex parasitic effects on the device performance, thereby enhancing the dynamic characteristics and control ability of the device. On the other hand, the high thermal conductivity can quickly transfer heat energy, which is beneficial to enhancing the heat dissipation performance and heat dissipation efficiency of the device, and significantly improving the reliability and robustness of the device.

[0090] To facilitate guiding the current in the middle region to both sides of the trench region, a fourth metal layer 184 is provided on the surface of the first dielectric layer 181. Among them, the resistivity of the fourth metal layer 184 is higher than that of the first metal layer 170. As an implementation method, the material for fabricating the fourth metal layer 184 is Ti metal. By disposing the fourth metal layer 184 between the first dielectric layer 181 and the fourth dielectric layer, it is beneficial to guide the surge current to flow from both sides of the trench region to the epitaxial layer.

[0091] Among them, the material of the fourth dielectric layer 185 is different from that of the first dielectric layer 181, the second dielectric layer 182, and the third dielectric layer 183, and the fourth dielectric layer 185 can use dielectric materials with excellent thermal stability. For example, SiO2, polysilicon, etc. can be used. On the one hand, providing the fourth dielectric layer 185 can further play a role in buffering thermal stress and internal stress. By flexibly adjusting the dimensions of the combination of the first dielectric layer 181, the second dielectric layer 182, the third dielectric layer 183, and the fourth dielectric layer 185, the thermal field distribution and internal stress in this region can be flexibly adjusted, thereby improving the electrical performance stability, reliability, and robustness of the device. On the other hand, in this application, the surface of the fourth dielectric layer 185 is set to be arc-shaped, which can play a more effective role in dispersing current, thereby further reducing the large amount of heat generated by high current density, significantly reducing the heating power and thermal failure probability of the device, and ultimately significantly improving the reliability and robustness of the device.

[0092] Please refer to Figure 3, which is a current schematic diagram under the large surge current condition. In the figure, the dotted arrows represent current lines. Among them, since the fourth dielectric layer 185 is set as an arc structure and the fourth metal layer 184 uses a material with a resistivity higher than that of the first metal layer 170, it is not easy for current to flow through the middle area. In addition, by setting the first dielectric layer 181, the second dielectric layer 182, and the third dielectric layer 183, more current lines are guided to the sides of the second dielectric layer 182 and the third dielectric layer 183 (i.e., both sides of the trench area) through the entire current dispersion structure 180, while only a small number of current lines flow between the first dielectric layer 181 and the second dielectric layer 182, and between the first dielectric layer 181 and the third dielectric layer 183. Therefore, in the trench area, current lines are not easily concentrated in the middle area of the trench, avoiding a large amount of heat generated by too high current density, reducing the probability of thermal failure, effectively improving the forward surge current IFSM of the device, and greatly improving the reliability and robustness of the device.

[0093] In addition, in order to improve the overall performance of the trench junction barrier Schottky diode, please refer to Figure 4 , the parameters set in this application are as follows:

[0094] First of all, the parameters of the entire trench area satisfy the formula:

[0095] L1>A=B;

[0096] A=B<H1<1 / 2H;

[0097] Among them, L1 represents the width of the trench area; A represents the distance between the left edge of the P column and the left sidewall of the trench, B represents the distance between the right edge of the P column and the right sidewall of the trench, H1 represents the depth of the trench area, and H represents the depth of the P column 140.

[0098] On the one hand, setting L1>A=B can ensure that the size of the entire trench area is large. The large area size can make the ohmic contact more sufficient, which is beneficial to reducing the contact resistance at the bottom of the trench, improving the bipolar conduction characteristics of the device, and further improving the surge current handling ability of the device. On the other hand, setting A=B<H1<1 / 2H makes the large-area P region located at the bottom of the trench, guiding the surge current to be transmitted from the bottom of the trench to the epitaxial layer, which can greatly reduce the chip area, reduce the unit chip cost, and at the same time, the large-area P region at the bottom of the trench is more conducive to the collection of carriers, which is beneficial to reducing the series resistance on the current path and improving the ability of the device to handle large currents.

[0099] For the current dispersion structure 180, it is symmetrically arranged about the vertical center line as a whole, so that the overall structure inside the trench remains symmetric, and the sizes of each structure can be flexibly adjusted, which can comprehensively and efficiently adjust and improve the static and dynamic characteristics of the device, bipolar conduction performance, forward surge current IFSM, heat dissipation performance, etc., so that the device performance is more stable, and the reliability and robustness are higher.

[0100] Among them, the second dielectric layer 182 and the third dielectric layer 183 have the same structure, and the parameters of the first dielectric layer 181, the second dielectric layer 182, and the third dielectric layer 183 satisfy the formula:

[0101] H2 < H3;

[0102] L2 > L3;

[0103] a > b;

[0104] Among them, H2 represents the height of the second dielectric layer 182 and the third dielectric layer 183, H3 represents the height of the first dielectric layer 181; L2 represents the width of the second dielectric layer 182 and the third dielectric layer 183, L3 represents the width of the first dielectric layer 181; a represents the distance between the second dielectric layer 182, the third dielectric layer 183 and the surface, side wall and bottom of the first metal layer 170, and b represents the distance between the second dielectric layer 182, the third dielectric layer 183 and the first dielectric layer 181.

[0105] Through this setting method, it is possible to prevent the heat caused by the surge current from concentrating in the middle area of the trench to the greatest extent, greatly improve the device thermal field distribution and thermal stress, and improve the heat dissipation performance, electrical performance stability, reliability and robustness of the device.

[0106] It should be noted that through the applicant's research, it is found that when a ≥ 3b, the effect of current dispersion is better, making it more difficult for heat to concentrate in the middle position of the trench area. Therefore, in this application, a ≥ 3b is set.

[0107] And, the parameters of the fourth dielectric layer 185 satisfy the formula:

[0108] y ≥ L3;

[0109] L3 ≤ z ≤ L3 + 2b;

[0110] Among them, y represents the width of the fourth dielectric layer 185, L3 represents the width of the first dielectric layer 181, z represents the width of the first metal layer 170, and b represents the distance between the second dielectric layer 182, the third dielectric layer 183 and the first dielectric layer 181.

[0111] Through this setting method, it is more conducive to guiding the surge current to flow from both sides of the trench area to the epitaxial layer.

[0112] In another implementation, please refer to Figure 5, the current dispersion structure 180 further includes a fifth metal layer 186 and a sixth metal layer 187. The fifth metal layer 186 is located between the first dielectric layer 181 and the second dielectric layer 182, and the sixth metal layer 187 is located between the first dielectric layer 181 and the third dielectric layer 183; the resistivity of the fifth metal layer 186 and the sixth metal layer 187 is greater than the resistivity of the first metal layer 170 and less than the resistivity of the fourth metal layer 184.

[0113] Since the resistivity of the fifth metal layer 186 and the sixth metal layer 187 is greater than the resistivity of the first metal layer 170 and less than the resistivity of the fourth metal layer 184, when in the working condition of a large surge current, it is more difficult for the current to flow between the first dielectric layer 181 and the second dielectric layer 182, and between the first dielectric layer 181 and the third dielectric layer 183, so that the current can be more dispersed. That is, it is more difficult for the current to flow through the middle region, but to flow through both sides of the trench region. Therefore, it can effectively prevent the situation that heat is concentrated at the middle position of the trench region.

[0114] Based on the above implementation, the embodiment of the present application further provides a method for manufacturing a trench junction barrier Schottky diode for manufacturing the above-mentioned trench junction barrier Schottky diode. The method includes:

[0115] S120, providing an N-type epitaxial wafer;

[0116] S104, defining a terminal region and an active region based on the N-type epitaxial wafer; wherein, the active region includes a plurality of P posts, the plurality of P posts are arranged at intervals, and an ohmic contact layer, a barrier metal layer and a first metal layer are arranged in the trench region. The ohmic contact layer is in contact with the bottom and side walls of the trench region, and the barrier metal layer is located between the ohmic contact layer and the first metal layer; a current dispersion structure is arranged inside and on the surface of the first metal layer, and the current dispersion structure is used to disperse the surge current to both sides of the trench region when a surge current appears;

[0117] S106, manufacturing a passivation protection layer based on the surface of the terminal region;

[0118] S108, manufacturing a second metal layer based on the surface of the active region, and the first metal layer and the second metal layer are made of the same material;

[0119] S110, manufacturing a third metal layer based on the back surface of the epitaxial wafer.

[0120] Among them, the steps of S104 are exemplarily described below in conjunction with the drawings:

[0121] Please refer to Figure 6, first, etch a plurality of first trenches based on epitaxial etch, wherein the plurality of first trenches are arranged at intervals. It should be noted that the number of first trenches is not limited in this application, and 3 first trenches are taken as an example for illustration in the figure.

[0122] Perform P-type ion implantation based on the positions of the first trenches;

[0123] Perform terminal region ion implantation;

[0124] Anneal in a high-temperature furnace tube; the structure after annealing is as Figure 7 shown.

[0125] Deposit ohmic contact metal on the surfaces of the first trenches and etch after annealing to form an ohmic contact layer;

[0126] Deposit a barrier metal layer on the surface of the ohmic contact layer and etch. The structure after depositing the ohmic contact layer and the barrier metal layer is as Figure 8 shown. Among them, the etching described in this application means removing the redundant parts through an etching process.

[0127] Please refer to Figure 9 , deposit a first sub-layer on the surface of the barrier metal layer and etch. The first sub-layer is used to fill the second dielectric layer and the third dielectric layer. Therefore, the thickness of the deposited first sub-layer can be determined based on the heights of the second dielectric layer and the third dielectric layer.

[0128] Etch two second trenches arranged at intervals based on the first sub-layer;

[0129] Please refer to Figure 10 , fill the two second trenches with an insulating dielectric and etch to form the second dielectric layer and the third dielectric layer;

[0130] Deposit a second sub-layer on the surfaces of the first sub-layer, the second dielectric layer, and the third dielectric layer and etch. The purpose of depositing the second sub-layer is to fabricate the first dielectric layer. Therefore, the thickness of the second sub-layer can be adjusted based on the height of the first dielectric layer.

[0131] Etch a third trench based on the second sub-layer, wherein the third trench is located between the two second trenches;

[0132] Please refer to Figure 11 , fill the third trench with an insulating dielectric and etch to form the first dielectric layer;

[0133] After that, deposit a third sub-layer on the surfaces of the second sub-layer and the first dielectric layer and etch. The first sub-layer, the second sub-layer, and the third sub-layer form the first metal layer;

[0134] Etch a fourth trench based on the third sub-layer, wherein the bottom of the fourth trench exposes the first dielectric layer;

[0135] Deposit a fourth metal layer on the fourth trench and etch it; the surface of the fourth metal layer is flush with the surface of the first metal layer;

[0136] Finally, deposit and etch an insulating dielectric on the surface of the fourth metal layer to form a fourth dielectric layer. By adjusting the lithography and etching process parameters, the surface of the fourth dielectric layer can be made arc-shaped.

[0137] In summary, the embodiments of the present application provide a trench junction barrier Schottky diode and a manufacturing method thereof. The trench junction barrier Schottky diode includes: an N-type epitaxial wafer; a terminal region and an active region located on the surface layer of the N-type epitaxial wafer; wherein, the active region includes a plurality of P posts, the plurality of P posts are spaced apart from each other, and a trench region is provided on the surface of each P post. An ohmic contact layer, a barrier metal layer, and a first metal layer are provided in the trench region. The ohmic contact layer contacts the bottom and side walls of the trench region, and the barrier metal layer is located between the ohmic contact layer and the first metal layer; a current dispersion structure located in and on the surface of the first metal layer, the current dispersion structure is used to disperse the surge current to both sides of the trench region when a surge current occurs; a passivation protection layer located on the surface of the terminal region; a second metal layer located on the surface of the active region and a third metal layer located on the back surface of the epitaxial wafer, and the materials of the first metal layer and the second metal layer are the same. On the one hand, since a barrier metal layer is provided in the trench junction barrier Schottky diode provided by the present application, it can prevent the reaction between the first metal layer and the ohmic contact layer at high temperatures, greatly improving the metal-semiconductor contact electrical performance, surge performance, thermal performance, and mechanical performance of the device, and thus greatly improving the electrical performance, reliability, and robustness of the device. On the other hand, by providing a current dispersion structure, it can play a role in dispersing current under abnormal working conditions such as large surge currents, reducing the large amount of heat generated by the excessive concentration of current in the middle region and the too high current density, reducing the probability of thermal failure, effectively improving the forward surge current IFSM of the device, and greatly improving the reliability and robustness of the device.

[0138] The foregoing is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

[0139] It will be apparent to those skilled in the art that the present application is not limited to the details of the above-described exemplary embodiments, and that the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, in all respects, the embodiments should be regarded as exemplary and non-limiting. The scope of the present application is defined by the appended claims rather than the above description. Accordingly, all changes that fall within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present application. Any reference signs in the claims should not be construed as limiting the claims concerned.

Claims

1. A trench junction barrier Schottky diode, characterized in that, The trench junction barrier Schottky diode includes: An N-type epitaxial wafer; A terminal region and an active region located on the surface layer of the N-type epitaxial wafer; wherein, the active region includes a plurality of P pillars, the plurality of P pillars are arranged at intervals, and a trench region is provided on the surface of each P pillar, and an ohmic contact layer, a barrier metal layer and a first metal layer are provided in the trench region, the ohmic contact layer is in contact with the bottom and side walls of the trench region, and the barrier metal layer is located between the ohmic contact layer and the first metal layer; A current dispersion structure located inside and on the surface of the first metal layer, the current dispersion structure is used to disperse the surge current to both sides of the trench region when a surge current occurs; A passivation protection layer located on the surface of the terminal region; A second metal layer located on the surface of the active region and a third metal layer located on the back surface of the epitaxial wafer, and the materials of the first metal layer and the second metal layer are the same; The current dispersion structure includes a first dielectric layer, a second dielectric layer, a third dielectric layer, a fourth metal layer and a fourth dielectric layer, the first dielectric layer, the second dielectric layer and the third dielectric layer are arranged at intervals and are all located inside the first metal layer, the second dielectric layer and the third dielectric layer are located on both sides of the first dielectric layer, and the heights of the second dielectric layer and the third dielectric layer are both less than the height of the first dielectric layer; The fourth metal layer is located on the surface of the first dielectric layer, the fourth dielectric layer is located on the surface of the fourth metal layer, and the surface of the fourth metal layer is flush with the surface of the first metal layer; The materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are different from the material of the fourth dielectric layer; and the materials for making the first dielectric layer, the second dielectric layer and the third dielectric layer are low dielectric constant and high thermal conductivity materials.

2. The trench junction barrier Schottky diode according to claim 1, wherein The surface of the fourth dielectric layer is set to be arc-shaped.

3. The grooved junction barrier Schottky diode according to claim 1, characterized in that, The current dispersion structure is symmetrically arranged about the vertical center line.

4. The trench junction barrier Schottky diode according to claim 1, characterized in that, The structures of the second dielectric layer and the third dielectric layer are the same, and the parameters of the first dielectric layer, the second dielectric layer and the third dielectric layer satisfy the formula: H2 < H3; L2 > L3; a > b; Wherein, H2 represents the height of the second dielectric layer and the third dielectric layer, H3 represents the height of the first dielectric layer; L2 represents the width of the second dielectric layer and the third dielectric layer, L3 represents the width of the first dielectric layer; a represents the distance between the second dielectric layer, the third dielectric layer and the surface, side wall and bottom of the first metal layer, and b represents the distance between the second dielectric layer, the third dielectric layer and the first dielectric layer.

5. The trench junction barrier Schottky diode according to claim 1, characterized in that, The current dispersion structure further includes a fifth metal layer and a sixth metal layer, the fifth metal layer is located between the first dielectric layer and the second dielectric layer, and the sixth metal layer is located between the first dielectric layer and the third dielectric layer; The resistivity of the fifth metal layer and the sixth metal layer is greater than the resistivity of the first metal layer and less than the resistivity of the fourth metal layer.

6. The trench junction barrier Schottky diode according to claim 1, characterized in that, The parameters of the trench region satisfy the formula: L1 > A = B; A = B < H1 < 1 / 2H; Wherein, L1 represents the width of the trench region; A represents the distance between the left edge of the P pillar and the left sidewall of the trench, B represents the distance between the right edge of the P pillar and the right sidewall of the trench, H1 represents the depth of the trench region, and H represents the depth of the P pillar.

7. A manufacturing method of a trench junction barrier Schottky diode, characterized in that, A method for manufacturing a trench junction barrier Schottky diode as described in any one of claims 1 to 6, the method comprising: Providing an N-type epitaxial wafer; Defining a terminal region and an active region based on the N-type epitaxial wafer; wherein, the active region includes a plurality of P pillars, the plurality of P pillars are spaced apart from each other, and a trench region is provided on the surface of each P pillar, and an ohmic contact layer, a barrier metal layer, and a first metal layer are provided in the trench region, the ohmic contact layer is in contact with the bottom and sidewalls of the trench region, and the barrier metal layer is located between the ohmic contact layer and the first metal layer; a current dispersion structure is provided inside and on the surface of the first metal layer, and the current dispersion structure is used to disperse the surge current to both sides of the trench region when a surge current occurs; Fabricating a passivation protection layer on the surface of the terminal region; Fabricating a second metal layer on the surface of the active region, and the first metal layer and the second metal layer are made of the same material; Fabricating a third metal layer on the back surface of the epitaxial wafer.

8. The manufacturing method of the trench junction barrier Schottky diode as described in claim 7, characterized in that, The step of defining a terminal region and an active region based on the N-type epitaxial wafer includes: Etching a plurality of first trenches based on the epitaxial wafer, wherein the plurality of first trenches are spaced apart from each other; Performing P-type ion implantation based on the positions of the first trenches; Performing ion implantation on the terminal region; Annealing in a high-temperature furnace tube; Depositing ohmic contact metal on the surface of the first trench and etching after annealing to form an ohmic contact layer; Depositing and etching a barrier metal layer on the surface of the ohmic contact layer; Depositing and etching a first sub-layer on the surface of the barrier metal layer; Etching two second trenches spaced apart from each other based on the first sub-layer; Filling and etching insulating media in the two second trenches to form a second dielectric layer and a third dielectric layer; Depositing and etching a second sub-layer on the surfaces of the first sub-layer, the second dielectric layer, and the third dielectric layer; Etching a third trench based on the second sub-layer, wherein the third trench is located between the two second trenches; Filling and etching insulating media in the third trench to form a first dielectric layer; Depositing and etching a third sub-layer on the surfaces of the second sub-layer and the first dielectric layer, wherein the first sub-layer, the second sub-layer, and the third sub-layer form the first metal layer; Etching a fourth trench based on the third sub-layer, wherein the bottom of the fourth trench exposes the first dielectric layer; Depositing and etching a fourth metal layer in the fourth trench; the surface of the fourth metal layer is flush with the surface of the first metal layer; Depositing and etching insulating media on the surface of the fourth metal layer to form a fourth dielectric layer.

Images