Cell structure, manufacturing method thereof, semiconductor device, electronic device, and vehicle

Abstract

The invention discloses a cellular structure and a preparation method thereof, a semiconductor device, electronic equipment and a vehicle, and the cellular structure comprises at least one trench gate structure, a first well region of a first conductive type and a second well region of a second conductive type, and each trench gate structure extends along the longitudinal direction of the cellular structure; the first well region wraps the bottom of each trench gate structure in the longitudinal direction and the transverse direction of the cellular structure, and the longitudinal direction of the cellular structure is perpendicular to the transverse direction of the cellular structure; the second well region wraps the bottom of the first well region and the side face of the first well region in the transverse direction of the cellular structure and the longitudinal direction of the cellular structure. According to the cellular structure, the overlapping area of the bottom of the trench gate structure and the collector region is reduced, and Miller capacitance of a device is reduced, so that the switching speed of the device is improved, and the energy loss of the device in the switching process is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a cellular structure, a method for preparing the cellular structure, a semiconductor device, an electronic device and a vehicle. Background Art

[0002] In the related art, the bottom of the trench gate of the trench IGBT (Insulated Gate Bipolar Transistor) structure is completely contained in the drift region of the N-type semiconductor material, and there is a large overlap area between it and the collector region. This structure increases the Miller capacitance of the device. The high Miller capacitance increases the charge that needs to be charged and discharged during the switching process, thereby extending the switching time, reducing the overall switching speed, and increasing the energy loss of the device during the switching process, thereby limiting the further optimization of the device performance. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to propose a cell structure that reduces the overlap area between the bottom of the trench gate structure and the collector region, reduces the Miller capacitance of the device, thereby increasing the switching speed of the device and reducing the energy loss of the device during the switching process.

[0004] The second object of the present invention is to provide a method for preparing a cellular structure.

[0005] A third object of the present invention is to provide a semiconductor device.

[0006] A fourth objective of the present invention is to provide an electronic device.

[0007] A fifth object of the present invention is to provide a vehicle.

[0008] In order to achieve the above-mentioned purpose, the cellular structure of an embodiment of the first aspect of the present invention includes: at least one trench gate structure, each of the trench gate structures extends along the longitudinal direction of the cellular structure; a first well region of the first conductivity type, the first well region wraps the bottom of each of the trench gate structures along the longitudinal direction of the cellular structure and the lateral direction of the cellular structure, wherein the longitudinal direction of the cellular structure and the lateral direction of the cellular structure are perpendicular to each other; a second well region of the second conductivity type, the second well region wraps the bottom and the side of the first well region along the lateral direction of the cellular structure and the longitudinal direction of the cellular structure.

[0009] According to the cellular structure of the embodiment of the present invention, the first well region of the first conductivity type is wrapped around the bottom of each trench gate structure along the longitudinal and transverse directions of the cellular structure, and the second well region of the second conductivity type is wrapped around the bottom and side surfaces of the first well region along the transverse and longitudinal directions. This means that the first well region and the second well region form a barrier at the bottom of the trench gate structure to reduce the overlapping area between the bottom of the trench gate structure and the collector region, thereby reducing the Miller capacitance formed between the trench gate and the collector region due to charge accumulation. Due to the reduction of the Miller capacitance, the charging and discharging time of the device during the switching process is shortened, the switching speed of the IGBT is improved, and the energy loss of the device during the switching process is reduced, thereby improving the overall performance of the device.

[0010] In some embodiments, the second well region extends along the side of the first well region in the longitudinal direction of the cellular structure, the second well region extends to the side of the edge-distributed trench gate structure in the longitudinal direction of the cellular structure, and the second well region contacts the side of the edge-distributed trench gate structure.

[0011] In some embodiments, the cellular structure further includes: a drift region of the first conductivity type, and in a longitudinal direction of the cellular structure, the second well region is located on a front side of the drift region.

[0012] In some embodiments, the cellular structure further includes: a buffer zone of a first conductivity type, which is located on the back side of the drift region away from the first well region in the longitudinal direction of the cellular structure; and a collector zone of a second conductivity type, which is located on a side of the buffer zone away from the drift region in the longitudinal direction of the cellular structure.

[0013] In some embodiments, the cellular structure further includes: a base region of a second conductivity type, wherein the base region is located on the first well region in a longitudinal direction of the cellular structure.

[0014] In some embodiments, the cellular structure includes: a first trench gate structure and a second trench gate structure, the first trench gate structure and the second trench gate structure are arranged at intervals along the lateral direction of the cellular structure, and the first trench gate structure and the second trench gate structure both extend along the longitudinal direction of the cellular structure and extend into the first well region.

[0015] In some embodiments, the base region is located between the first trench gate structure and the second trench gate structure.

[0016] In some embodiments, at least one protrusion is formed on a surface of the drift region facing the second well region in a longitudinal direction of the cellular structure.

[0017] In some embodiments, the drift region is formed with at least one first protrusion, and each of the first protrusions extends along a longitudinal direction of the cellular structure and penetrates the second well region and extends into the first well region.

[0018] In some embodiments, the first protrusion is located in the middle of the drift region, and a portion of each of the first protrusions extending into the first well region is located between the first trench gate structure and the second trench gate structure.

[0019] In some embodiments, the drift region is formed with a plurality of the first protrusions, and the plurality of the first protrusions are arranged at intervals along a lateral direction of the cellular structure.

[0020] In some embodiments, the drift region further forms a second protrusion, the second protrusion and the first protrusion are arranged at intervals in the lateral direction of the cellular structure, the second protrusion extends along the longitudinal direction of the cellular structure and matches and connects with the first corner of the second well region.

[0021] In some embodiments, the drift region also forms a third protrusion, and the third protrusion, the second protrusion and the first protrusion are arranged at intervals in the lateral direction of the cellular structure, the second protrusion and the third protrusion are located on both sides of the first protrusion, and the third protrusion extends along the longitudinal direction of the cellular structure and is matched and connected with the second corner of the second well region.

[0022] In some embodiments, the second protrusion is located on a side of the first trench gate structure away from the second trench gate structure, and the third protrusion is located on a side of the second trench gate structure away from the first trench gate structure.

[0023] In some embodiments, the cellular structure also includes: a first emitter of a first conductive type, the first emitter being located on a side of the first trench gate structure away from the second trench gate structure in a lateral direction of the cellular structure, and the first emitter being located on a portion of the second well region connected to the first trench gate structure in a longitudinal direction of the cellular structure.

[0024] In some embodiments, the cellular structure also includes: a second emitter of the first conductivity type, the second emitter being located on a side of the second trench gate structure away from the first trench gate structure in a lateral direction of the cellular structure, and the second emitter being located on a portion of the second well region connected to the second trench gate structure in a longitudinal direction of the cellular structure.

[0025] In some embodiments, the cellular structure also includes: a first ohmic contact region, the first ohmic contact region is located on a side of the first emitter away from the second trench gate structure in a lateral direction of the cellular structure, the first ohmic contact region is connected to the first emitter, and the first ohmic contact region is located on the second well region in a longitudinal direction of the cellular structure.

[0026] In some embodiments, the cellular structure also includes: a second ohmic contact region, the second ohmic contact region is located on a side of the second emitter away from the second trench gate structure in the lateral direction of the cellular structure, the second ohmic contact region is connected to the second emitter, and the second ohmic contact region is located on the second well region in the longitudinal direction of the cellular structure.

[0027] In some embodiments, the cell structure also includes: a first insulating layer, the first insulating layer is located on a portion of the first emitter, the first trench gate structure, the second trench gate structure and a portion of the second emitter; a first emitter metal layer, the first emitter metal layer covers the first insulating layer and is connected to the first ohmic contact region, the first emitter, the second emitter and the second ohmic contact region.

[0028] In some embodiments, the cellular structure further includes: a third emitter, the third emitter being located on a side of the first trench gate structure close to the second trench gate structure in a lateral direction of the cellular structure, and the third emitter being located on the base region in a longitudinal direction of the cellular structure; and a fourth emitter, the fourth emitter being located on a side of the second trench gate structure close to the first trench gate structure in a lateral direction of the cellular structure, and the fourth emitter being located on the base region in a longitudinal direction of the cellular structure.

[0029] In some embodiments, the cell structure further includes: a third ohmic contact region, the third ohmic contact region is located on the base region in a longitudinal direction of the cell structure, and the third ohmic contact region is connected to the third emitter and the fourth emitter.

[0030] In some embodiments, the cell structure also includes: a second insulating layer, the second insulating layer covers the upper surface of the first trench gate structure, a portion of the upper surface of the first emitter and a portion of the upper surface of the third emitter; a third insulating layer, the third insulating layer covers the upper surface of the second trench gate structure, a portion of the upper surface of the second emitter and a portion of the upper surface of the fourth emitter; a second emitter metal layer, the second emitter metal layer covers the upper surface of the second insulating layer and the upper surface of the third insulating layer, and the second emitter metal layer is connected to the first ohmic contact region, the first emitter, the second emitter, the second ohmic contact region, the third emitter, the fourth emitter and the third ohmic contact region.

[0031] In some embodiments, the cellular structure also includes: a fifth emitter region, the fifth emitter is located on a side of the first trench gate structure close to the second trench gate structure in a lateral direction of the cellular structure, and the fifth emitter is located on the base region in a longitudinal direction of the cellular structure; a sixth emitter, the sixth emitter is located on a side of the second trench gate structure close to the first trench gate structure in a lateral direction of the cellular structure, and the sixth emitter is located on the base region in a longitudinal direction of the cellular structure.

[0032] In some embodiments, the cell structure further includes: a fourth ohmic contact region, the fourth ohmic contact region is located on the base region in a longitudinal direction of the cell structure, and the fourth ohmic contact region is connected to the fifth emitter and the sixth emitter.

[0033] In some embodiments, the cell structure includes: a fourth insulating layer, the fourth insulating layer covering the upper surface of the first trench gate structure, a portion of the upper surface of the first emitter and a portion of the upper surface of the fifth emitter; a fifth insulating layer, the fifth insulating layer covering the upper surface of the second trench gate structure, a portion of the upper surface of the second emitter and a portion of the upper surface of the sixth emitter; a third emitter metal layer, the third emitter metal layer covering the upper surface of the fourth insulating layer and the upper surface of the fifth insulating layer, the third emitter metal layer being connected to the first emitter, the fifth emitter, the fourth ohmic contact region, the sixth emitter and the second emitter.

[0034] In some embodiments, the second protrusion extends along the longitudinal direction of the cellular structure until it is flush with an upper surface of a portion of the second well region connected to the first trench gate structure.

[0035] In some embodiments, the third protrusion extends along the longitudinal direction of the cellular structure until it is flush with an upper surface of a portion of the second well region connected to the second trench gate structure.

[0036] In some embodiments, the cellular structure also includes: a first planar gate insulation layer, the first planar gate insulation layer covers the upper surface of the second protrusion, the upper surface of the portion of the second well region connected to the first trench gate structure, and the upper surface of a portion of the first emitter; a first planar gate structure, the first planar gate structure is located on the upper surface of the first planar gate insulation layer in the longitudinal direction of the cellular structure.

[0037] In some embodiments, the cellular structure also includes: a second planar gate insulation layer, the second planar gate insulation layer covers the upper surface of the third protrusion, the upper surface of the portion of the second well region connected to the second trench gate structure, and the upper surface of a portion of the second emitter; a second planar gate structure, the second planar gate structure is located on the upper surface of the second planar gate insulation layer in the longitudinal direction of the cellular structure.

[0038] In some embodiments, the cellular structure further includes: a collector metal layer, wherein the collector metal layer is located on a side of the collector region away from the buffer region in a longitudinal direction of the cellular structure.

[0039] In order to achieve the above-mentioned purpose, the preparation method of the cellular structure of the second aspect of the embodiment of the present invention includes: providing a substrate; preparing at least one trench gate structure, a first well region of a first conductivity type, and a second well region of a second conductivity type on the substrate; wherein each of the trench gate structures extends in the longitudinal direction of the cellular structure, the first well region wraps the bottom of each trench gate structure in the longitudinal direction of the cellular structure and in the transverse direction of the cellular structure, the second well region wraps the bottom and the side of the first well region in the transverse direction of the cellular structure and in the longitudinal direction of the cellular structure, and the longitudinal direction of the cellular structure is perpendicular to the transverse direction of the cellular structure.

[0040] According to the method for preparing a cellular structure of an embodiment of the present invention, when preparing the cellular structure, the first well region of the first conductivity type is wrapped around the bottom of each trench gate structure along the longitudinal and transverse directions of the cellular structure, and the second well region of the second conductivity type is wrapped around the bottom and side surfaces of the first well region along the transverse and longitudinal directions. This means that the first well region and the second well region form a barrier at the bottom of the trench gate structure to reduce the overlapping area between the bottom of the trench gate structure and the collector region, thereby reducing the Miller capacitance formed between the trench gate and the collector region due to charge accumulation. Due to the reduction of the Miller capacitance, the charging and discharging time of the device during the switching process is shortened, the switching speed of the semiconductor device is improved, and the energy loss of the device during the switching process is reduced, thereby improving the overall performance of the device.

[0041] In some embodiments, the preparation method also includes: preparing a drift region of the first conductivity type on the substrate, wherein the second well region is located on the front side of the drift region in the longitudinal direction of the cellular structure; preparing a buffer region of the first conductivity type on the back side of the drift region away from the first well region; and preparing a collector region of the second conductivity type on the side of the buffer region away from the drift region.

[0042] In some embodiments, the preparation method further includes: preparing a base region of a second conductivity type on the first well region in a longitudinal direction of the cellular structure.

[0043] In some embodiments, the preparation method further includes: preparing at least one protrusion on a surface of the drift region facing the second well region, wherein the at least one protrusion extends along a longitudinal direction of the cellular structure.

[0044] In some embodiments, the preparation method further includes: preparing an emitter, an ohmic contact region and an emitter metal layer on the front side of the drift region; and preparing a collector metal layer on a side of the collector region away from the buffer zone.

[0045] In some embodiments, the preparation method further includes: preparing a planar gate structure on the front side of the cell structure, wherein a planar gate insulating layer is provided between the planar gate structure and the emitter, the second well region and the drift region.

[0046] In order to achieve the above object, a semiconductor device according to an embodiment of the third aspect of the present invention includes at least one cellular structure as described in the above embodiment.

[0047] According to the semiconductor device of the embodiment of the present invention, by adopting the cellular structure described in the above embodiment, the overlapping area between the bottom of the trench gate structure and the collector region can be reduced, the Miller capacitance of the device is reduced, the switching speed of the device is increased, and the energy loss of the device during the switching process is reduced, thereby improving the overall performance of the semiconductor device.

[0048] In order to achieve the above object, an electronic device according to an embodiment of the fourth aspect of the present invention includes at least one semiconductor device as described in the above embodiment.

[0049] According to the electronic device of the embodiment of the present invention, by adopting the semiconductor device described in the above embodiment, the overlapping area between the bottom of the trench gate structure and the collector region can be reduced, the Miller capacitance formed between the trench gate and the collector region due to charge accumulation is reduced, the switching speed of the semiconductor device is improved, and the energy loss of the device during the switching process is reduced, thereby improving the overall performance of the device.

[0050] In order to achieve the above-mentioned object, a vehicle according to a fifth embodiment of the present invention includes the electronic device described in the above embodiment.

[0051] According to the vehicle of the embodiment of the present invention, by adopting the electronic device described in the above embodiment, the overlapping area between the bottom of the trench gate structure and the collector region can be reduced, the Miller capacitance formed between the trench gate and the collector region due to charge accumulation is reduced, the switching speed of the device is improved, and the energy loss of the device during the switching process is reduced, thereby improving the overall performance of the vehicle.

[0052] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0054] Figure 1 is a schematic diagram of a cell structure according to an embodiment of the present invention;

[0055] Figure 2 is a schematic diagram of a cell structure according to yet another embodiment of the present invention;

[0056] Figure 3 is a schematic diagram of a cell structure according to another embodiment of the present invention;

[0057] Figure 4 is a flow chart of a method for preparing a cellular structure according to one embodiment of the present invention;

[0058] Figure 5 is a schematic diagram of forming a drift region of a first conductivity type according to an embodiment of the present invention;

[0059] Figure 6 is a schematic diagram of implanting boron ions once to prepare a second well region according to one embodiment of the present invention;

[0060] Figure 7 is a schematic diagram of implanting boron ions twice to prepare a second well region according to an embodiment of the present invention;

[0061] Figure 8 is a schematic diagram of preparing a protrusion to form a second well region according to one embodiment of the present invention;

[0062] Fig. 9 is a schematic diagram of forming a trench gate structure according to an embodiment of the present invention;

[0063] Fig.10 is a schematic diagram of implanting phosphorus ions once to prepare a first well region according to one embodiment of the present invention;

[0064] Fig.11 is a schematic diagram of implanting phosphorus ions twice to prepare a first well region according to an embodiment of the present invention;

[0065] Fig.12 is a schematic diagram of forming a base region of a second conductivity type according to an embodiment of the present invention;

[0066] Fig.13 is a schematic diagram of implanting phosphorus ions to prepare an emitter according to an embodiment of the present invention;

[0067] Fig.14 is a schematic diagram of forming an emitter according to an embodiment of the present invention;

[0068] Fig.15 is a schematic diagram of forming an ohmic contact region according to an embodiment of the present invention;

[0069] Fig.16 is a schematic diagram of forming an emitter metal layer according to an embodiment of the present invention;

[0070] Fig.17 is a schematic diagram of forming a buffer zone according to an embodiment of the present invention;

[0071] Fig.18 is a schematic diagram of forming a collector region according to an embodiment of the present invention;

[0072] Fig.19 is a block diagram of a semiconductor device according to an embodiment of the present invention;

[0073] Fig. 20 is a block diagram of an electronic device according to an embodiment of the present invention;

[0074] Fig.21 is a block diagram of a vehicle according to one embodiment of the present invention.

[0075] Reference numerals:

[0076] Vehicle 100;

[0077] Electronic device 110;

[0078] Semiconductor device 111;

[0079] Cell structure 1;

[0080] first well region 20; second well region 30; drift region 40; buffer region 50; collector region 60; base region 70; first emitter 80; second emitter 90;

[0081] first trench gate structure 11; second trench gate structure 12; first ohmic contact region 13; second ohmic contact region 14; first insulating layer 15; first emitter metal layer 16; third emitter 17; fourth emitter 18; third ohmic contact region 19; second insulating layer 21; third insulating layer 22; second emitter metal layer 23; fifth emitter 24; sixth emitter 25; fourth ohmic contact region 27; fourth insulating layer 28; fifth insulating layer 29; third emitter metal layer 31; first planar gate insulating layer 32; first planar gate structure 33; second planar gate insulating layer 34; second planar gate structure 35; collector metal layer 36;

[0082] A first protruding portion 41 ; a second protruding portion 42 ; and a third protruding portion 43 . DETAILED DESCRIPTION

[0083] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0084] Reference below Figure 1 A cell structure according to an embodiment of the present invention is described.

[0085] Figure 1 is a schematic diagram of a cell structure according to an embodiment of the present invention. Figure 1 As shown, the cell structure 1 includes: at least one trench gate structure, a first well region 20 of a first conductivity type, and a second well region 30 of a second conductivity type.

[0086] In some embodiments, the cell structure 1 is a basic unit structure in a semiconductor device. This structure can be repeatedly arranged in the design to achieve large-area current conduction and control. Each cell structure 1 may include multiple regions, such as an emitter region, a gate region, a drift region, a collector region, etc. The various regions in the cell structure 1 help to distribute and control the electric field inside the device, and through the cell structure 1, the current can effectively flow from the emitter region to the collector region.

[0087] In some embodiments, the cellular structure 1 enables the device to have consistent electrical and mechanical properties through its repeatability. It provides a standardized design, making large-scale manufacturing more efficient. At the same time, the design of the cellular structure 1 directly affects the performance of the device, such as on-state voltage drop, switching speed, and energy loss.

[0088] In some embodiments, the trench gate structure may be a gate structure formed in a trench etched in a semiconductor material. Such a structure may be implemented by filling the trench with multiple layers of materials (eg, a gate oxide layer and a polysilicon gate).

[0089] Among them, the gate oxide layer is the insulating layer between the polysilicon gate and the semiconductor material. It can be composed of high dielectric constant (High-K) oxide materials, such as SiO2 (silicon dioxide), HfO2 (hafnium oxide), Al2O3 (aluminum oxide), Si3N4 (silicon nitride), etc. These materials can be used to manufacture the gate oxide layer to improve the insulation performance and capacitance density of the device. The main function of the gate oxide layer is to act as an insulating layer to prevent the gate from directly contacting the carriers in the channel, prevent leakage current and charge accumulation, and thus improve the reliability and stability of the device.

[0090] In some embodiments, polysilicon can be the main material of the gate. Through its conductivity, the gate voltage can be applied to the gate oxide layer to form an electric field to control the conduction and shutdown of the channel. When a voltage is applied to the polysilicon gate, the gate oxide layer generates an electric field on the surface of the semiconductor material, regulating the carrier density in the channel to turn the channel on or off. In this way, the trench gate structure can accurately control the switching of the current. In addition, by adjusting the doping concentration and thickness of polysilicon, the gate's control ability over the channel can be further optimized, improving the overall performance of the device.

[0091] In some embodiments, at least one trench gate structure may include one trench gate structure, two trench gate structures, three trench gate structures, five trench gate structures, or other more trench gate structures. The number of trench gate structures may be set according to specific application requirements and design parameters. For example, for high-power semiconductor devices, more trench gate structures may be required to improve the current carrying capacity of the device and the switching speed of the device. Therefore, the number of trench gate structures is not specifically limited herein.

[0092] In some embodiments, each trench gate structure extends along the longitudinal direction of the cellular structure 1. This layout extending along the longitudinal direction of the cellular structure 1 enables the gate to more effectively control the electric field distribution in the channel, helps to optimize the current flow path, and thus helps to control the on and off process of the device.

[0093] In some embodiments, the first well region 20 of the first conductivity type may refer to a specific doped region formed using a semiconductor material of the first conductivity type, wherein the first conductivity type may represent a dominant electron type in a semiconductor device, which may be N-type (electrons are the main carriers) or P-type (holes are the main carriers), depending on the doping type of the material.

[0094] Specifically, if the first conductivity type is N-type, a high concentration of impurities (such as phosphorus, arsenic or antimony) can be added to the N-type semiconductor material to increase the electron concentration in the N-type semiconductor material, thereby forming a highly doped region, i.e., an N-type well region. If the first conductivity type is P-type, a high concentration of impurities (such as boron, indium or gallium) can be added to the P-type semiconductor material to increase the hole concentration in the P-type semiconductor material, thereby forming a highly doped region, i.e., a P-type well region. For example, Figure 1 As shown, the first well region 20 of the first conductivity type may be an N-type well region.

[0095] In some embodiments, the first well region 20 wraps the bottom of each trench gate structure along the longitudinal direction of the cell structure 1 and the lateral direction of the cell structure 1, wherein the longitudinal direction of the cell structure 1 and the lateral direction of the cell structure 1 are perpendicular to each other. This layout design isolates the trench gate structure from the collector region, effectively reducing the overlapping area between the bottom of the trench gate structure and the collector region, thereby reducing the Miller capacitance.

[0096] In some embodiments, the second well region 30 of the second conductivity type may refer to a specific doped region formed using a semiconductor material of the second conductivity type. The second conductivity type may represent the dominant electron type in the semiconductor device 111, which may also be N-type (electrons are the main carriers) or P-type (holes are the main carriers), depending on the doping type of the material.

[0097] Specifically, if the second conductivity type is N-type, a high concentration of impurities (such as phosphorus, arsenic or antimony) can be added to the N-type semiconductor material to increase the electron concentration in the N-type semiconductor material, thereby forming a highly doped region, namely, an N-type well region. If the second conductivity type is P-type, a high concentration of impurities (such as boron, indium or gallium) can be added to the P-type semiconductor material to increase the hole concentration in the P-type semiconductor material, thereby forming a highly doped region, namely, a P-type well region. For example, Figure 1 As shown, the second well region 30 of the second conductivity type may be a P-type well region.

[0098] In some embodiments, the second well region 30 wraps the bottom of the first well region 20 and the side of the first well region 20 along the lateral direction of the cell structure 1 and the longitudinal direction of the cell structure 1. The wrapping of the second well region 30 further enhances the protection of the trench gate structure, reduces the overlapping area between the bottom of the trench gate structure and the collector region, and thus reduces the Miller capacitance.

[0099] In some embodiments, the Miller capacitor is a capacitor formed between the input and output of the transistor. In an IGBT device, the Miller capacitor between the gate and the collector can amplify the effect of this capacitor through the feedback effect of voltage gain. Since the Miller capacitor can increase the amount of charge required for the gate voltage during the switching process, this causes the gate drive circuit to require more energy and time to change the gate voltage, thereby slowing down the switching speed. In addition, since the Miller capacitor increases the charge demand for the gate voltage change during the switching process, this means that the gate drive circuit needs to handle more charge during each switching process, thereby increasing switching losses.

[0100] According to the cellular structure 1 of the embodiment of the present invention, the first well region 20 of the first conductivity type is wrapped around the bottom of each trench gate structure along the longitudinal and transverse directions of the cellular structure 1, and the second well region 30 of the second conductivity type is wrapped around the bottom and side surfaces of the first well region 20 along the transverse and longitudinal directions. This means that the first well region 20 and the second well region 30 form a barrier at the bottom of the trench gate structure to reduce the overlapping area between the bottom of the trench gate structure and the collector region, thereby reducing the Miller capacitance formed between the trench gate and the collector region due to charge accumulation. Due to the reduction of the Miller capacitance, the charging and discharging time of the device during the switching process is shortened, the switching speed of the IGBT is improved, and the energy loss of the device during the switching process is reduced, thereby improving the overall performance of the device.

[0101] In some embodiments, Figure 1 As shown, the second well region 30 extends along the side of the first well region 20 in the longitudinal direction of the cell structure 1, and extends to the side of the trench gate structure distributed at the edge of at least one trench gate structure in the longitudinal direction of the cell structure, and the second well region 30 contacts the side of the trench gate structure distributed at the edge. By extending to and contacting the side of the trench gate structure distributed at the edge, the second well region 30 forms a continuous P-type region in the longitudinal and transverse directions of the device. This region can effectively regulate and uniformize the electric field distribution on both sides of the trench gate structure, and prevent the electric field from being concentrated at the edge of the trench gate. This layout design reduces the tip effect of the electric field at the edge of the trench gate, reduces the risk of breakdown, and improves the reliability of the device.

[0102] In addition, the second well region 30 affects the electric field distribution on both sides of the trench gate structure, allowing electrons to flow more smoothly in the channel. Specifically, the presence of the second well region 30 helps to form a more symmetrical and uniform electric field distribution, thereby optimizing the movement path of electrons in the channel.

[0103] like Figure 1As shown, the cell structure 1 also includes a drift region 40 of the first conductivity type. The main function of the drift region 40 is to provide a current path while supporting the electric field distribution under high voltage conditions. The drift region 40 of the first conductivity type can be an N-type doped region responsible for carrying current and delivering it to the collector region. Through N-type doping, the drift region 40 can provide a low resistance path in the on state and withstand high voltage in the off state.

[0104] In some embodiments, the structure of the drift region 40 may be an NPT (Non Punch Through) structure, a PT (Punch Through) structure, an SPT (Soft Punch Through) structure or a FS (Field Stop) structure, without specific limitation herein.

[0105] In some embodiments, the drift region 40 of the first conductivity type is in the longitudinal direction of the cell structure 1, and the second well region 30 is located on the front side of the drift region 40. The second well region 30 and the drift region 40 can form a reverse biased PN junction. The reverse biased PN junction can become the position where the longitudinal field intensity distribution is the strongest, and the longitudinal electric field intensity distribution of the semiconductor device 111 can be adjusted so that the peak area of ​​the longitudinal field intensity distribution is set in the area below the bottom of the trench gate structure, thereby forming an electric field protection for the bottom of the trench gate structure.

[0106] Specifically, reverse bias refers to the situation where the electric potential of the drift region 40 is higher than that of the second well region 30. In the reverse bias state, the electric field at both ends of the PN junction will cause the majority of carriers (electrons and holes) to move away from the junction region, forming an extended depletion layer. This extended depletion layer forms a high electric field region in the junction region, which can withstand higher voltages and improve the withstand voltage capability of the device. If the PN junction is in a forward bias state, the depletion layer disappears, the PN junction is turned on, which is equivalent to a turned-on diode and cannot play a withstand voltage role.

[0107] Therefore, in the IGBT device, the reverse biased PN junction between the second well region 30 and the drift region 40 is designed to be in the area with the largest electric field strength, so that the peak area of ​​the longitudinal field strength distribution is set below the bottom of the trench gate structure. This design can form electric field protection for the bottom of the trench gate structure. The electric field protection design effectively prevents the electric field from being concentrated at the bottom of the trench gate structure, reduces the risk of breakdown, and thus improves the reliability and stability of the device.

[0108] In some embodiments, the doping concentration and depth of the second well region 30 and the drift region 40 can be optimized to further improve the electric field protection effect. By precisely controlling the doping parameters of the second well region 30 and the drift region 40, the depletion layer of the PN junction can be made more stable, thereby enhancing the electric field protection of the bottom of the trench gate structure, and further improving the withstand voltage performance and stability of the device.

[0109] like Figure 1 As shown, the cell structure 1 further includes: a buffer region 50 of a first conductivity type and a collector region 60 of a second conductivity type. The buffer region 50 may be a semiconductor region having the same conductivity type as the drift region 40. For example, the buffer region 50 of the first conductivity type may also be an N-type buffer region 50. In an IGBT device, this buffer region 50 may be doped with a higher concentration of N-type dopants (such as phosphorus or arsenic) to improve its conductivity and ability to regulate the electric field.

[0110] In some embodiments, by controlling the doping concentration of the buffer region 50, the rate of decrease of the electric field from the drift region 40 to the collector region 60 can be accelerated. This is because a higher doping concentration can cause the electric field to decay rapidly within the buffer region 50. By accelerating the rate of decrease of the electric field, the thickness of the substrate can be reduced. A thinner substrate means that the resistance encountered by carriers when passing through the device is reduced, which reduces the conduction voltage drop and can pass through the device more quickly, thereby increasing the conduction speed of the device. In addition, the buffer region 50 can help to homogenize the electric field distribution inside the device, reduce the problem of excessive local electric field, and thus reduce the risk of device breakdown.

[0111] Therefore, by reducing the substrate thickness and optimizing the electric field distribution, the conduction speed and efficiency of the device are significantly improved. At the same time, the conduction voltage drop is reduced, which reduces the energy loss of the device during operation and improves the overall performance.

[0112] In some embodiments, the collector region 60 may be a semiconductor region having the same conductivity type as the second well region 30. Figure 1 As shown, the collector region 60 of the second conductivity type may be a P-type collector region 60. In an IGBT device, the P-type collector region 60 is doped with a relatively high concentration of a P-type dopant (such as boron) to provide good conductivity and current collection capability.

[0113] In some embodiments, the collector region 60 is the main current collection area. In an IGBT device, the collector region 60 may be a region connected to an external circuit and is responsible for conducting the current inside the device. By optimizing the doping concentration of the collector region 60, the collector region 60 may have good conductivity to ensure that the current can be efficiently transmitted and reduce energy loss during the current transmission process.

[0114] In some embodiments, after the IGBT device is turned on, the collector region 60, the buffer region 50, the drift region 40, the first well region 20 and the second well region 30 can form a complex PNPN structure, that is, a thyristor structure. This PNPN thyristor structure forms a low-impedance channel when the device is turned on, reducing the on-resistance, thereby reducing the on-voltage drop of the device. This is because the built-in electric field of the PNPN thyristor structure helps the rapid transmission of carriers, thereby improving the conduction performance and overall efficiency of the device.

[0115] In some embodiments, the buffer region 50 of the first conductivity type is located on the back side of the drift region 40 away from the first well region 20 in the longitudinal direction of the cell structure 1. The collector region 60 of the second conductivity type is located on the side of the buffer region 50 away from the drift region 40 in the longitudinal direction of the cell structure 1.

[0116] In some embodiments, the cell structure 1 further includes a base region 70 of the second conductivity type. The base region 70 of the second conductivity type may be a P-type base region 70. The base region 70 may be formed of a highly doped P-type material to enhance the response to the gate voltage.

[0117] In some embodiments, the P-type base region 70 is used as the main control region. By applying a voltage to the gate, the electron density in the channel can be controlled to control the opening and closing of the device. Specifically, when a forward voltage is applied, the electric field causes electrons to enter the channel region and the device is turned on. When a reverse voltage is applied, the electric field prevents electrons from entering the channel and the device is turned off. In addition, the base region 70 can also affect the electron channel on the side of the trench gate structure. By adjusting the gate voltage, the electrons can be controlled to enter the second well region 30 and the drift region 40 along the electron channel on the side of the trench gate structure.

[0118] In some embodiments, the base region 70 is located on the first well region 20 in the longitudinal direction of the cell structure 1. During the device conduction process, the PN junction formed by the first well region 20 and the base region 70 is in a reverse biased state. When the first well region 20 is completely depleted, the potential of the second well region 30 is "clamped" at a fixed value, which is conducive to maintaining the stability of the bottom potential of the trench gate structure, which is conducive to reducing the oscillation phenomenon during the device switching process.

[0119] Specifically, when the device is normally turned on, the potential of the first well region 20 is higher than the potential of the base region 70, forming a reverse biased PN junction. In the reverse biased state, an extended depletion layer is formed on both sides of the PN junction. That is, the electrons in the first well region 20 are depleted, and the holes in the base region 70 of the second conductivity type are depleted, forming fixed positive and negative charges. The fixed positive charge of the first well region 20 and the fixed negative charge of the base region 70 form a depletion layer, which does not contain free carriers and can therefore withstand high voltages.

[0120] In addition, the thickness of the depletion layer is related to the doping concentration of the first well region 20 and the base region 70. The higher the doping concentration, the slower the depletion layer expands and the smaller the thickness. The doping concentration of the first well region 20 is lower than the doping concentration of the base region 70. Therefore, the depletion layer at the first well region 20 expands faster and is thicker. The doping concentration of the base region 70 of the second conductivity type is higher, the depletion layer expands slower, and the thickness is thinner. When the first well region 20 is completely depleted, the base region 70 is partially depleted, and a high conductivity region can be formed between the first well region 20 and the base region 70, and the potential tends to be stable, that is, the potential of the first well region 20 no longer changes significantly, similar to being "clamped" at a fixed value. This stable potential distribution is conducive to maintaining the stability of the bottom potential of the trench gate structure, helping to reduce the oscillation phenomenon during the switching process and improving the turn-on speed and stability of the device.

[0121] like Figure 1 As shown, the cell structure 1 further includes: a first trench gate structure 11 and a second trench gate structure 12. The first trench gate structure 11 and the second trench gate structure 12 are arranged at intervals along the lateral direction of the cell structure 1. Such an interval arrangement helps to control the electric field distribution between the trench gates, reduce the electric field concentration phenomenon, thereby reducing the breakdown risk and improving the reliability and stability of the device.

[0122] In some embodiments, the first trench gate structure 11 and the second trench gate structure 12 both extend in the longitudinal direction of the cell structure 1 and extend into the first well region 20. The first well region 20 can reduce the overlapping area between the bottom of the trench gate structure and the collector region 60, thereby reducing the Miller capacitance of the device. By reducing the Miller capacitance, the overshoot phenomenon of the gate voltage of the device during the switching process can be reduced, and the control capability of the device gate resistance on the voltage change rate (dv / dt) and current change rate (di / dt) during the turn-on process can be enhanced, which helps to optimize the trade-off relationship between the loss and electromagnetic interference (EMI) noise during the turn-on process of the device.

[0123] In some embodiments, the base region 70 is located between the first trench gate structure 11 and the second trench gate structure 12. The location of the base region 70 helps connect the first trench gate structure 11 and the second trench gate structure 12 to form a continuous device structure. This connection helps optimize the current flow path and ensure effective control and regulation of the trench gate structure.

[0124] In some embodiments, the base region 70 also helps control the electric field distribution between the first trench gate structure 11 and the second trench gate structure 12. That is, by applying an appropriate voltage in the base region 70, the electric field distribution between the trench gate structures can be adjusted, thereby optimizing the on and off performance of the device.

[0125] In some embodiments, the drift region 40 has at least one protrusion formed on one side of the cell structure 1 facing the second well region 30 in the longitudinal direction. The design of the protrusion helps to increase the surface area of ​​the drift region 40, thereby optimizing the electric field distribution and increasing the withstand voltage capability of the device.

[0126] In some embodiments, at least one protrusion may be one protrusion, two protrusions, three protrusions, five protrusions, or more. The number of protrusions may be set according to the electric field distribution, device structure, and application requirements, and is not specifically limited here. For example, in high-voltage applications, multiple protrusions may be selected to further homogenize the electric field distribution and improve the voltage resistance.

[0127] In some embodiments, the protrusions can be in a variety of shapes, such as trapezoidal, rectangular, or other complex shapes, to meet different design requirements and application scenarios. In addition, simulation tools can be used to optimize the protrusions to determine the optimal shape, size, and position to achieve the best electric field distribution and current path. The protrusions can be implemented by selective ion implantation, doping diffusion, or other semiconductor manufacturing processes. Selecting the right materials and processes can ensure that the protrusions have the desired electrical properties and mechanical stability.

[0128] In some embodiments, Figure 1 As shown, the drift region 40 is formed with at least one first protrusion 41. Figure 1 Taking a first protrusion 41 as an example, each first protrusion 41 extends along the longitudinal direction of the cell structure 1 and penetrates the second well region 30 to extend into the first well region 20. The existence of the first protrusion 41 can form a preferential current flow path inside the device, so that the path of electrons and holes flowing in the device is more optimized, the resistance is reduced, and the conduction performance is improved.

[0129] In addition, the presence of the first protrusion 41 increases the surface area of ​​the drift region 40, which helps to optimize the electric field distribution in the longitudinal direction. By penetrating the second well region 30 and extending to the first well region 20, a continuous potential distribution can be formed in different regions. The first protrusion 41 can effectively homogenize the electric field in these regions, reduce local electric field concentration, thereby reducing the breakdown risk and improving the voltage resistance of the device.

[0130] In some embodiments, the first protrusion 41 is located in the middle of the drift region 40, and the portion of each first protrusion 41 extending into the first well region 20 is located between the first trench gate structure 11 and the second trench gate structure 12. This layout design can effectively balance the electric field distribution at the bottom of the two trench gate structures, which is beneficial to optimizing the electric field and current path and improving the overall performance of the device.

[0131] In an embodiment, Figure 1As shown, taking one first protrusion 41 as an example, in other embodiments, the drift region 40 is formed with a plurality of first protrusions 41 , and the plurality of first protrusions 41 are arranged at intervals along the lateral direction of the cellular structure 1 .

[0132] In some embodiments, the first protrusion 41 may be formed by selective ion implantation or doping process, and accurate doping concentration and process parameters are used to ensure that the shape and position of the first protrusion 41 meet the design requirements.

[0133] like Figure 1 As shown, the drift region 40 is also formed with a second protrusion 42 , which is arranged alternately with the first protrusion 41 in the lateral direction of the cellular structure 1 , and the second protrusion 42 extends in the longitudinal direction of the cellular structure 1 and is matched and connected with the first corner of the second well region 30 .

[0134] Among them, the second raised portion 42 and the first raised portion 41 are arranged at intervals in the lateral direction of the cellular structure 1, which means that the two raised portions are not arranged continuously, but have a certain interval. This layout helps to evenly distribute the electric field in the lateral direction and reduce the concentration of the electric field. The second raised portion 42 extends in the longitudinal direction of the cellular structure 1 and is matched and connected with the first corner of the second well region 30, which shows that the shape and position of the second raised portion 42 are precisely designed to ensure that it matches the geometric structure of the second well region 30, thereby optimizing the electric field and current path, and improving the voltage resistance and stability of the device. In addition, the presence of the second raised portion 42 increases the surface area of ​​the drift region 40, enhances the carrier transport capacity, and further improves the conduction performance of the device.

[0135] In some embodiments, the second protrusion 42 may be formed by a selective ion implantation or doping process to ensure that its shape and position accurately match the geometric structure of the second well region 30 .

[0136] like Figure 1 As shown, the drift region 40 is also formed with a third protrusion 43, and the third protrusion 43, the second protrusion 42 and the first protrusion 41 are arranged at intervals in the lateral direction of the cellular structure 1, the second protrusion 42 and the third protrusion 43 are located on both sides of the first protrusion 41, and the third protrusion 43 extends along the longitudinal direction of the cellular structure 1 and is matched and connected with the second corner of the second well region 30.

[0137] Among them, the second protrusion 42 and the third protrusion 43 are respectively located on both sides of the first protrusion 41 to form a symmetrical structure, which helps to evenly distribute the electric field in the lateral direction. The third protrusion 43 extends along the longitudinal direction of the cellular structure 1 and is matched and connected with the second corner of the second well region 30, which shows that the shape and position of the third protrusion 43 are precisely designed to ensure that it matches the geometric structure of the second well region 30, thereby optimizing the electric field and current path, and improving the voltage resistance and stability of the device.

[0138] As shown in the figure, the second protrusion 42 is located on a side of the first trench gate structure 11 away from the second trench gate structure 12, and the third protrusion 43 is located on a side of the second trench gate structure 12 away from the first trench gate structure 11. The extension lengths of the second protrusion 42 and the third protrusion 43 along the longitudinal direction of the cell structure 1 can be set based on specific structural requirements.

[0139] In addition, the presence of the third protrusion 43 further increases the surface area of ​​the drift region 40, enhances the carrier transport capacity, and further improves the conduction performance of the device. Therefore, the position design of the three protrusions forms multiple priority current paths, which helps to reduce conduction losses and improve conduction efficiency and device performance.

[0140] In some embodiments, the third protrusion 43 may be formed by a selective ion implantation or doping process to ensure that its shape and position accurately match the geometric structure of the second well region 30 .

[0141] like Figure 1 As shown, the cell structure 1 further includes: a first emitter 80 of the first conductivity type and a second emitter 90 of the first conductivity type. The first emitter 80 of the first conductivity type and the second emitter 90 of the first conductivity type may be N-type emitters, and these emitter regions are doped with elements such as phosphorus or arsenic to increase the number of electrons, thereby improving conductivity.

[0142] In some embodiments, the main function of the first emitter 80 and the second emitter 90 is to inject electrons into the cell structure 1. When the device is turned on, electrons are injected from the emitter, through the first well region 20, the second well region 30 and the drift region 40, to form a conduction channel. The first emitter 80 and the second emitter 90 are the main current injection points. By controlling the density and direction of the injected current, the current flow path can be optimized, the current crowding phenomenon can be reduced, and the device efficiency can be improved. Therefore, the position and design of the emitter directly affect the switching speed, conduction voltage drop and overall efficiency of the device. By optimizing the emitter, the electrical performance of the device can be improved.

[0143] In some embodiments, the first emitter 80 is located on a side of the first trench gate structure 11 away from the second trench gate structure 12 in the lateral direction of the cell structure 1, and the first emitter 80 is located on a portion of the second well region 30 connected to the first trench gate structure 11 in the longitudinal direction of the cell structure 1. The second emitter 90 is located on a side of the second trench gate structure 12 away from the first trench gate structure 11 in the lateral direction of the cell structure 1, and the second emitter 90 is located on a portion of the second well region 30 connected to the second trench gate structure 12 in the longitudinal direction of the cell structure 1.

[0144] Therefore, by respectively arranging the first emitter 80 and the second emitter 90 on both sides of the first trench gate structure 11 and the second trench gate structure 12, symmetrical current injection and balanced electric field distribution can be formed, which helps to balance the current distribution, so that electrons are uniformly injected from the two emitters and pass through the well region and the drift region 40, thereby improving the conduction performance of the device.

[0145] In some embodiments, the first emitter 80 and the second emitter 90 can be formed by an ion implantation process to ensure that their positions and shapes accurately match the design requirements of the second well region 30 and the trench gate structure. Therefore, through simulation and experiment, the optimal positions of the first emitter 80 and the second emitter 90 in the horizontal and vertical directions are determined to achieve the best current and electric field distribution effects.

[0146] like Figure 1 As shown, the cell structure 1 further includes: a first ohmic contact region 13 and a second ohmic contact region 14. The first ohmic contact region 13 and the second ohmic contact region 14 may refer to regions in the device structure for forming ohmic contact with the emitter. The first ohmic contact region 13 is located on a side of the first emitter 80 away from the second trench gate structure 12 in the lateral direction of the cell structure 1, the first ohmic contact region 13 is connected to the first emitter 80, and the first ohmic contact region 13 is located on the second well region 30 in the longitudinal direction of the cell structure 1. The second ohmic contact region 14 is located on a side of the second emitter 90 away from the second trench gate structure 12 in the lateral direction of the cell structure 1, the second ohmic contact region 14 is connected to the second emitter 90, and the second ohmic contact region 14 is located on the second well region 30 in the longitudinal direction of the cell structure 1.

[0147] In some embodiments, the first ohmic contact region 13 and the second ohmic contact region 14 may be heavily doped P-type ohmic contact regions, which function to reduce contact resistance and ensure good electrical contact performance, reduce energy loss, and ensure smooth current transmission. This can improve the conduction performance and efficiency of the device, while ensuring the reliability and stability of the device in high-voltage and high-frequency applications.

[0148] In some embodiments, the area and shape of the first ohmic contact region 13 and the second ohmic contact region 14 can be designed according to the specific size and current requirement of the cell structure 1 to ensure low contact resistance and uniform current distribution.

[0149] In some embodiments, the cell structure 1 further includes: a first insulating layer 15 and a first emitter metal layer 16. The first insulating layer 15 can be made of a variety of materials, including but not limited to phospho-silicate glass (BPSG), silicon dioxide (SiO2), etc. These materials have good insulation properties and can effectively isolate different regions. Therefore, the material and thickness of the first insulating layer 15 can be selected according to the requirements and design of the device to ensure good isolation and protection effects.

[0150] In some embodiments, the first insulating layer 15 is located on a portion of the first emitter 80, the first trench gate structure 11, the second trench gate structure 12, and a portion of the second emitter 90. The first insulating layer 15 is mainly used to provide isolation protection for the trench gate structure and the emitter and other regions to prevent electrical short circuit or breakdown between them, thereby improving the reliability and stability of the device.

[0151] In some embodiments, the first emitter metal layer 16 may be made of a metal material with good electrical conductivity, such as aluminum (Al), copper (Cu), etc. These metals have good electrical conductivity, can provide good electrical connection, and assume the functions of voltage application and current transmission during operation.

[0152] In some embodiments, the first emitter metal layer 16 covers the first insulating layer 15 and is connected to the first ohmic contact region 13, the first emitter 80, the second emitter 90, and the second ohmic contact region 14. The first emitter metal layer 16 is connected to the second well region 30 through the first ohmic contact region 13 and the second ohmic contact region 14. By connecting to these regions, it can draw current and transmit signals, thereby ensuring good electrical connection and transmission performance, and ensuring the normal operation of the device.

[0153] In some embodiments, Figure 1 The working principle process of the cell structure 1 in the figure may include the device turn-on and turn-off process. Specifically, the device conduction process: when a positive voltage is applied to the collector region 60 of the second conductivity type and the trench gate structure, and the first emitter 80 and the second emitter 90 are zero biased, the electron current flow path at the initial stage of device opening is: the first emitter 80 or the second emitter 90 - the base region 70 of the second conductivity type - the first well region 20 - the drift region 40 of the first conductivity type - the buffer region 50 of the first conductivity type. When the potential difference between the collector region 60 and the buffer region 50 is greater than the built-in potential of the PN junction of the collector region 60 and the buffer region, the PN junction is turned on, and electrons flow from the drift region 40 to the collector region 60, and at the same time, the holes in the collector region 60 begin to be injected into the drift region 40.

[0154] Furthermore, as the voltage of the collector region 60 increases, the depletion layer of the drift region 40 shrinks, and the reverse biased PN junction formed by the second well region 30 and the drift region 40 plays a major role in withstand voltage in this process. When the holes reach the drift region 40, a portion of them is swept to the second well region 30 under the action of a strong electric field, and then reaches the first well region 20. The other portion directly reaches the first well region 20 from the drift region 40 along the gap between the two trench gate structures and the second well region 30, and then flows out from the contact hole to reach the first emitter 80 or the second emitter 90.

[0155] During the device shutdown process, when a negative voltage is applied to the trench gate structure under the condition that the device is turned on, the electron channel is closed. The PNP transistor formed by the base region 70, the first well region 20 and the second well region 30 is turned off. The NPN transistor formed by the first well region 20, the second well region 30 and the drift region 40 is turned off.

[0156] Furthermore, as the electron current decreases, when the sum of the gains of the PNP transistor and the NPN transistor is less than 1, the PNP transistor formed by the collector region 60, the drift region 40, and the second well region 30 is turned off, and the IGBT device returns to the blocking state, which means that the device has been completely turned off and no longer conducts current. Therefore, through the description of the above process, the structure and working principle of the trench IGBT of the embodiment of the present invention, as well as the electron flow path and the switching process of the device under different working states can be clearly understood.

[0157] Figure 2 is a schematic diagram of a cell structure according to another embodiment of the present invention, Figure 2 As shown, the cell structure 1 further includes: a third emitter 17 and a fourth emitter 18. The third emitter 17 and the fourth emitter 18 may be N-type emitters, and these emitter regions are doped with elements such as phosphorus or arsenic to increase the number of electrons, thereby improving conductivity.

[0158] In some embodiments, the third emitter 17 and the fourth emitter 18 may also mainly function to inject electrons into the cell structure 1. When the device is turned on, electrons are injected from the emitter, passing through the first well region 20, the second well region 30 and the drift region 40 to form a conduction channel.

[0159] In some embodiments, Figure 1 The cell structure 1 in the embodiment only includes the first emitter 80 and the second emitter 90, and Figure 2 The cell structure 1 in the embodiment includes not only the first emitter 80 and the second emitter 90, but also the third emitter 17 and the fourth emitter 18. The increase in the number of emitters can increase the current carrying capacity of the device because each emitter can provide an additional current path. That is, more emitters mean more electron injection areas, which will increase the current density and enable the device to withstand a larger current. In addition, the increase in the number of emitters also enables the cell structure 1 to have a lower on-state voltage drop.

[0160] In some embodiments, the third emitter 17 is located on a side of the first trench gate structure 11 close to the second trench gate structure 12 in the lateral direction of the cell structure 1, and the third emitter 17 is located on the base region 70 in the longitudinal direction of the cell structure 1. The fourth emitter 18 is located on a side of the second trench gate structure 12 close to the first trench gate structure 11 in the lateral direction of the cell structure 1, and the fourth emitter 18 is located on the base region 70 in the longitudinal direction of the cell structure 1.

[0161] Therefore, by setting the first emitter 80 and the third emitter 17 on both sides of the first trench gate structure 11, and by setting the second emitter 90 and the fourth emitter 18 on both sides of the second trench gate structure 12, symmetrical current injection and balanced electric field distribution can be formed, which helps to balance the current distribution, so that electrons are uniformly injected from each emitter and pass through the well region and the drift region 40, thereby improving the conduction performance of the device.

[0162] In some embodiments, the third emitter 17 and the fourth emitter 18 may be formed by an ion implantation process to ensure that their positions and shapes precisely match the design requirements of the base region 70 and the trench gate structure.

[0163] like Figure 2 As shown, the cell structure 1 further includes a third ohmic contact region 19. The third ohmic contact region 19 may refer to a region in the device structure for forming an ohmic contact with the emitter. The third ohmic contact region 19 is located on the base region 70 in the longitudinal direction of the cell structure 1, and the third ohmic contact region 19 is connected to the third emitter 17 and the fourth emitter 18.

[0164] In some embodiments, the third ohmic contact region 19 may be a heavily doped P-type ohmic contact region, which is used to reduce contact resistance and ensure good electrical contact performance, reduce energy loss, and ensure smooth current transmission. This can improve the conduction performance and efficiency of the device, while ensuring the reliability and stability of the device in high-voltage and high-frequency applications.

[0165] In some embodiments, the area and shape of the third ohmic contact region 19 can be designed according to the specific size and current requirements of the cell structure 1 to ensure low contact resistance and uniform current distribution.

[0166] like Figure 2 As shown, the cell structure 1 also includes: a second insulating layer 21, a third insulating layer 22, and a second emitter metal layer 23. Among them, the second insulating layer 21 and the third insulating layer 22 can be made of a variety of materials, including but not limited to phospho-silicate glass (BPSG), silicon dioxide (SiO2), etc. These materials have good insulation properties and can effectively isolate different areas. Therefore, the material and thickness of the second insulating layer 21 and the third insulating layer 22 can be selected according to the requirements and design of the device to ensure good isolation and protection effects.

[0167] In some embodiments, the second insulating layer 21 covers the upper surface of the first trench gate structure 11, the upper surface of a portion of the first emitter 80, and the upper surface of a portion of the third emitter 17. The second insulating layer 21 is mainly used to provide isolation protection for the first trench gate structure 11, the portion of the first emitter 80, and the portion of the third emitter 17, etc., to prevent electrical short circuit or breakdown between them, thereby improving the reliability and stability of the device.

[0168] In some embodiments, the third insulating layer 22 covers the upper surface of the second trench gate structure 12, the upper surface of a portion of the second emitter 90, and the upper surface of a portion of the fourth emitter 18. The main function of the third insulating layer 22 is to provide isolation protection for the second trench gate structure 12, the second emitter 90, and the fourth emitter 18, etc., to prevent electrical short circuits or breakdowns between them, thereby improving the reliability and stability of the device. By connecting to these areas, it can draw current and transmit signals, thereby ensuring good electrical connection and transmission performance, and ensuring the normal operation of the device.

[0169] In some embodiments, the thickness and material selection of the second insulating layer 21 and the third insulating layer 22 can be adjusted according to the design requirements of a specific device to achieve optimal insulation effect and reliability.

[0170] In some embodiments, in some embodiments, the second emitter metal layer 23 can be made of a metal material with good electrical conductivity, such as aluminum (Al), copper (Cu), etc. These metals have good electrical conductivity, can provide good electrical connection, and assume the functions of voltage application and current transmission during operation.

[0171] In some embodiments, the second emitter metal layer 23 covers the upper surface of the second insulating layer 21 and the upper surface of the third insulating layer 22, and the second emitter metal layer 23 is connected to the first ohmic contact region 13, the first emitter 80, the second emitter 90, the second ohmic contact region 14, the third emitter 17, the fourth emitter 18, and the third ohmic contact region 19. By connecting with these regions, it can draw current and transmit signals, thereby ensuring good electrical connection and transmission performance, thereby ensuring the stability and reliability of the device.

[0172] Figure 3 is a schematic diagram of a cell structure according to another embodiment of the present invention. Figure 3 As shown, the cell structure 1 further includes: a fifth emitter 24 and a sixth emitter 25. The fifth emitter 24 and the sixth emitter 25 can be used to further adjust the current density distribution of the device, thereby improving the conduction performance and efficiency of the device.

[0173] In some embodiments, the fifth emitter 24 is located on a side of the first trench gate structure 11 close to the second trench gate structure 12 in the lateral direction of the cell structure 1, and the fifth emitter 24 is located on the base region 70 in the longitudinal direction of the cell structure 1. The sixth emitter 25 is located on a side of the second trench gate structure 12 close to the first trench gate structure 11 in the lateral direction of the cell structure 1, and the sixth emitter 25 is located on the base region 70 in the longitudinal direction of the cell structure 1. The fifth emitter 24 and the sixth emitter 25 expand the electrical connection options of the cell structure 1, so that the device has more current injection paths, so that the distribution and transmission of current can be more effectively controlled. In addition, the two emitters can also provide better current carrying capacity, thereby enhancing the conduction performance of the device and providing greater current handling capacity in high-power applications.

[0174] In some embodiments, the fifth emitter 24 and the sixth emitter 25 may be formed by an ion implantation process to ensure that their positions and shapes precisely match the design requirements of the base region 70 and the trench gate structure.

[0175] like Figure 3 As shown, the cell structure 1 further includes a fourth ohmic contact region 27. The fourth ohmic contact region 27 may refer to a region in the cell structure 1 for forming an ohmic contact with the emitter. The fourth ohmic contact region 27 is located on the base region 70 in the longitudinal direction of the cell structure 1, and the fourth ohmic contact region 27 is connected to the fifth emitter 24 and the sixth emitter 25.

[0176] In some embodiments, the fourth ohmic contact region 27 may be a heavily doped P-type ohmic contact region, which is used to reduce contact resistance and ensure good electrical contact performance, reduce energy loss, and ensure smooth current transmission. This can improve the conduction performance and efficiency of the device, while ensuring the reliability and stability of the device in high-voltage and high-frequency applications.

[0177] In some embodiments, the specific shape, area, and size of the fourth ohmic contact region 27 can be adjusted according to the size of the cell structure 1 , current density, and other factors to ensure low contact resistance and uniform current distribution.

[0178] like Figure 3 As shown, the cell structure 1 further includes: a fourth insulating layer 28, a fifth insulating layer 29 and a third emitter metal layer 31. Among them, the fourth insulating layer 28 and the fifth insulating layer 29 can be made of a variety of materials, including but not limited to phospho-silicate glass (BPSG), silicon dioxide (SiO2), etc. These materials have good insulation properties and can effectively isolate different areas. Therefore, the material and thickness of the fourth insulating layer 28 and the fifth insulating layer 29 can be selected according to the requirements and design of the device to ensure good isolation and protection effects.

[0179] In some embodiments, the fourth insulating layer 28 covers the upper surface of the first trench gate structure 11, the upper surface of a portion of the first emitter 80, and the upper surface of a portion of the fifth emitter 24. The fourth insulating layer 28 is mainly used to provide isolation protection for the first trench gate structure 11, the portion of the first emitter 80, and the portion of the fifth emitter 24, etc., to prevent electrical short circuit or breakdown between them, thereby improving the reliability and stability of the device.

[0180] In some embodiments, the fifth insulating layer 29 covers the upper surface of the second trench gate structure 12, the upper surface of a portion of the second emitter 90, and the upper surface of a portion of the sixth emitter 25. The fifth insulating layer 29 is mainly used to provide isolation protection for the second trench gate structure 12, the portion of the second emitter 90, and the portion of the sixth emitter 25, etc., to prevent electrical short circuit or breakdown between them, thereby improving the reliability and stability of the device.

[0181] In some embodiments, the thickness and material selection of the fourth insulating layer 28 and the fifth insulating layer 29 can be adjusted according to the design requirements of a specific device to achieve optimal insulation effect and reliability.

[0182] In some embodiments, the third emitter metal layer 31 may be made of a metal material with good electrical conductivity, such as aluminum (Al), copper (Cu), etc. These metals have good electrical conductivity, can provide good electrical connection, and assume the functions of voltage application and current transmission during operation.

[0183] In some embodiments, the third emitter metal layer 31 covers the upper surface of the fourth insulating layer 28 and the upper surface of the fifth insulating layer 29, and the third emitter metal layer 31 is connected to the first emitter 80, the fifth emitter 24, the fourth ohmic contact region 27, the sixth emitter 25, and the second emitter 90. By connecting to these regions, it can draw current and transmit signals, thereby ensuring good electrical connection and transmission performance, thereby ensuring the stability and reliability of the device.

[0184] In some embodiments, Figure 3 As shown, the second protrusion 42 extends along the longitudinal direction of the cell structure 1 to be flush with the upper surface of the portion of the second well region 30 connected to the first trench gate structure 11. The third protrusion 43 extends along the longitudinal direction of the cell structure 1 to be flush with the upper surface of the portion of the second well region 30 connected to the second trench gate structure 12. Through this layout design, the surface area of ​​the drift region 40 can be further increased, thereby improving the uniform distribution of the electric field, reducing the local electric field strength, and improving the withstand voltage of the device. In addition, the second protrusion 42 and the third protrusion 43 also help to provide a low-impedance current conduction path, thereby reducing the on-state voltage drop of the device.

[0185] like Figure 3As shown, the cell structure 1 further includes: a first planar gate insulating layer 32 and a first planar gate structure 33. The first planar gate insulating layer 32 may be made of various types of insulating materials, such as silicon dioxide (SiO2), silicon nitride (Si3N4) or phospho-silicate glass (BPSG), etc. The selection of the material and thickness thereof may be determined according to the design requirements and manufacturing process of the cell structure 1.

[0186] In some embodiments, the first planar gate insulating layer 32 covers the upper surface of the second protrusion 42, the upper surface of the portion of the second well region 30 connected to the first trench gate structure 11, and the upper surface of a portion of the first emitter 80. The main function of the first planar gate insulating layer 32 is to provide electrical isolation, which can isolate the potential of the first planar gate structure 33 from the semiconductor region of the lower layer to prevent electrical short circuit or breakdown of the device during operation.

[0187] In some embodiments, the first planar gate structure 33 is located on the upper surface of the first planar gate insulating layer 32 in the longitudinal direction of the cellular structure 1. The first planar gate structure 33 can use aluminum or copper as the planar gate material, and adjust its conductive properties through a doping process. The first planar gate structure 33 can form an electric field to control the switching state of the current channel by applying a control voltage. In the cellular structure 1, more precise current regulation can be achieved through the control of the first planar gate structure 33, thereby improving the switching speed and efficiency of the cellular structure 1.

[0188] like Figure 3 As shown, the cell structure 1 further includes: a second planar gate insulating layer 34 and a second planar gate structure 35. The second planar gate insulating layer 34 may also be made of various types of insulating materials, such as silicon dioxide (SiO2), silicon nitride (Si3N4) or phospho-silicate glass (BPSG), etc. The selection of the material and thickness thereof may be determined according to the design requirements and manufacturing process of the cell structure 1.

[0189] In some embodiments, the second planar gate insulating layer 34 covers the upper surface of the third protrusion 43, the upper surface of the portion of the second well region 30 connected to the second trench gate structure 12, and the upper surface of a portion of the second emitter 90. The second planar gate insulating layer 34 is mainly used to provide electrical isolation, which can isolate the potential of the second planar gate structure 35 from the semiconductor region of the lower layer to prevent electrical short circuit or breakdown of the device during operation.

[0190] In some embodiments, the second planar gate structure 35 is located on the upper surface of the second planar gate insulating layer 34 in the longitudinal direction of the cellular structure 1. The second planar gate structure 35 can use polysilicon as the planar gate material, and adjust its conductive properties through a doping process. The second planar gate structure 35 can form an electric field to control the switching state of the current channel by applying a control voltage. In the cellular structure 1, more precise current regulation can be achieved through the control of the second planar gate structure 35, thereby improving the switching speed and efficiency of the cellular structure 1.

[0191] In some embodiments, Figure 3 Compared with the cell structure 1 Figure 1 For the cell structure 1, the first planar gate structure 33 and the second planar gate structure 35 are mainly added. The purpose of adding the planar gate structure is to improve the conduction performance of the device and reduce the conduction loss. The conductive channel length of the planar gate structure is shorter, so in the early stage of device opening, electrons are more likely to flow from the electron conductive channel under the planar gate structure, thereby achieving rapid opening. In contrast, the conductive channel length of the trench gate structure is longer, and the conduction process may be slower. Therefore, by adding a planar gate structure, the turn-on speed of the device can be increased, the turn-on loss can be reduced, and the performance of the device can be improved.

[0192] like Figure 1-Figure 3 As shown, the cell structure 1 further includes a collector metal layer 36. The collector metal layer 36 is located on the side of the collector region 60 away from the buffer region 50 in the longitudinal direction of the cell structure 1. The collector metal layer 36 is an important part for collecting current, and its main function is to collect the current flowing through the device and output it to the external circuit. In the semiconductor device 111, the collector has the important task of outputting power, so the design and layout of the collector metal layer 36 are very important to the performance of the device.

[0193] In some embodiments, the collector metal layer 36 may be made of metal materials with good electrical conductivity and thermal stability, such as copper (Cu), aluminum (Al), etc. Selecting a suitable metal material can ensure good electrical conductivity and thermal conductivity, and improve the working efficiency and reliability of the device.

[0194] In some embodiments, a metal film may be deposited on the side of the collector region 60 away from the buffer region 50 by using techniques such as electron beam evaporation (EBD) or physical vapor deposition (PVD). The shape and size of the collector metal layer 36 may be adjusted by photolithography and etching processes.

[0195] In some embodiments, the thickness and shape design of the collector metal layer 36 directly affect the current carrying capacity and voltage tolerance. By optimizing the thickness and shape of the collector metal layer 36, the resistance loss can be reduced, the conductivity can be improved, and the influence of thermal effects on the device can be reduced.

[0196] In some embodiments, the longitudinal spacing between the emitter and the first well region 20 in the cell structure 1 and the doping concentration of the base region 70 can be adjusted according to the threshold value required by the device to meet the performance requirements in different application scenarios. By adjusting these parameters, the conduction characteristics and threshold voltage of the device can be accurately controlled, thereby optimizing the performance of the device.

[0197] In some embodiments, the junction depth and doping concentration of the second well region 30 and the doping concentration of the first well region 20 in the cell structure 1 can be adjusted according to the on-state voltage drop requirement of the device. Increasing the doping concentration of the second well region 30 is conducive to increasing the emission efficiency of the PNP transistor and reducing the on-state voltage drop of the device. Properly increasing the doping concentration of the first well region 20 is conducive to improving the emission efficiency of the NPN transistor composed of the first well region 20, the second well region 30 and the drift region 40, thereby reducing the on-state voltage drop of the device.

[0198] Reference below Figure 4 A method for preparing a cellular structure according to an embodiment of the present invention is described.

[0199] Figure 4 is a flow chart of a method for preparing a cellular structure according to an embodiment of the present invention. Figure 4 As shown, the method for preparing the cellular structure at least includes steps S1-S2, which are specifically as follows:

[0200] S1, providing a substrate.

[0201] Specifically, a substrate is required during the preparation process as the basis of the cellular structure. The substrate may be a silicon substrate or other suitable materials for supporting and growing subsequent layers.

[0202] S2, preparing at least one trench gate structure, a first well region of a first conductivity type, and a second well region of a second conductivity type on the substrate.

[0203] Among them, the trench gate structure is one of the key components of the cell structure and is used to control the flow of current. The trench gate structure can be realized by filling multiple layers of materials (such as gate oxide and polysilicon gate) in the trench. The gate oxide layer is an insulating layer between the polysilicon gate and the semiconductor material. It can be composed of high dielectric constant (High-K) oxide materials, such as SiO2 (silicon dioxide), HfO2 (hafnium oxide), Al2O3 (aluminum oxide), Si3N4 (silicon nitride), etc. The polysilicon filled in the trench gate structure can be N-type polysilicon or P-type polysilicon, which is not specifically limited here. By adjusting the doping concentration and thickness of polysilicon, the gate's control ability over the channel can be further optimized and the overall performance of the device can be improved.

[0204] In some embodiments, the preparation of the first well region involves depositing a material of a first conductivity type (such as an N-type semiconductor material) in a specific region to form a conductive region for controlling the flow path of current. A highly doped region is formed by doping the N-type semiconductor material with a high concentration of impurities (such as phosphorus, arsenic, or antimony) to increase the electron concentration in the N-type semiconductor material.

[0205] In some embodiments, the second well region can be composed of a second conductive type material (such as a P-type semiconductor material) by doping the P-type semiconductor material with a high concentration of impurities (such as boron, indium or gallium) to increase the hole concentration in the P-type semiconductor material, thereby forming a highly doped region.

[0206] In some embodiments, each trench gate structure extends along the longitudinal direction of the cellular structure, the first well region wraps around the bottom of each trench gate structure along the longitudinal direction and the lateral direction of the cellular structure, the second well region wraps around the bottom and the side of the first well region along the lateral direction and the longitudinal direction of the cellular structure, and the longitudinal direction of the cellular structure is perpendicular to the lateral direction of the cellular structure.

[0207] According to the method for preparing a cellular structure of an embodiment of the present invention, when preparing the cellular structure, the first well region of the first conductivity type is wrapped around the bottom of each trench gate structure along the longitudinal and transverse directions of the cellular structure, and the second well region of the second conductivity type is wrapped around the bottom and side surfaces of the first well region along the transverse and longitudinal directions. This means that the first well region and the second well region form a barrier at the bottom of the trench gate structure to reduce the overlapping area between the bottom of the trench gate structure and the collector region, thereby reducing the Miller capacitance formed between the trench gate and the collector region due to charge accumulation. Due to the reduction of the Miller capacitance, the charging and discharging time of the device during the switching process is shortened, the switching speed of the semiconductor device is improved, and the energy loss of the device during the switching process is reduced, thereby improving the overall performance of the device.

[0208] In some embodiments, the method for preparing the cellular structure further includes: preparing a drift region of the first conductivity type on the substrate, wherein the second well region is located on the front side of the drift region in the longitudinal direction of the cellular structure. Preparing a buffer region of the first conductivity type on the back side of the drift region away from the first well region. Preparing a collector region of the second conductivity type on the side of the buffer region away from the drift region.

[0209] Among them, the drift region can be prepared by ion implantation or diffusion technology, and dopants such as phosphorus (P) ions or arsenic (As) ions can be implanted on the surface of the silicon layer to make it an N-type semiconductor material. These dopants can replace some atoms in the silicon lattice to form free electrons, thereby achieving N-type doping. The sample is then heat-treated, and the dopants are diffused in the silicon lattice through high-temperature annealing to form a uniform doping distribution, thereby forming a drift region for carrying current and transporting it to the collector area.

[0210] In some embodiments, on the back side of the drift region away from the first well region, N-type dopants, such as phosphorus (P) ions or arsenic (As) ions, etc., can be injected using ion implantation or diffusion technology to make it an N-type semiconductor material. These dopants can form free electrons, thereby achieving N-type doping. Then, the sample is subjected to appropriate heat treatment to diffuse the dopants and form a uniform N-type doping distribution, thereby forming a buffer zone. By controlling the doping concentration of the buffer zone, the speed at which the electric field drops from the drift region to the collector region can be accelerated.

[0211] In some embodiments, on the side of the buffer away from the drift region, ion implantation or diffusion technology can also be used to implant P-type dopants, such as boron (B) ions, to make it a P-type semiconductor material. These dopants can form holes, thereby achieving P-type doping. Then, the sample is subjected to appropriate heat treatment to diffuse the dopants and form a uniform P-type doping distribution, thereby forming a collector region. By optimizing the doping concentration of the collector region, the collector region can have good conductivity to ensure that the current can be efficiently transmitted and reduce energy loss during current transmission.

[0212] In some embodiments, the second well region and the drift region may form a reverse biased PN junction. The reverse biased PN junction may become the position where the longitudinal field strength distribution is the strongest, and the longitudinal electric field strength distribution of the semiconductor device may be adjusted so that the peak area of ​​the longitudinal field strength distribution is set below the bottom of the trench gate structure, thereby forming electric field protection for the bottom of the trench gate structure.

[0213] In some embodiments, the method for preparing the cellular structure further includes: preparing a base region of the second conductivity type on the first well region in a longitudinal direction of the cellular structure.

[0214] Specifically, first, a dopant of the desired type (second conductivity type), such as boron ions (B+), is implanted into a specific region (on the first well region) of the cell structure through ion implantation or other techniques. The implantation of these dopants can increase the ion concentration in the region, thereby changing the conductive properties of the material.

[0215] Further, after implanting the dopant, a driving and diffusion step may be performed. Driving may refer to pushing the dopant into the material to increase the depth of doping, while diffusion may refer to diffusing the dopant in the crystal through heat treatment to form a desired dopant concentration profile.

[0216] Furthermore, after the dopant is injected, a heat treatment, i.e., annealing, can be performed. The annealing process can activate the injected dopant and help the dopant diffuse within the crystal to form the desired dopant distribution and concentration. After all steps are completed, the diffusion and activation of the dopant can form a P-type base region. In this region, the doped material will have P-type conductivity, i.e., holes become the main carriers.

[0217] In addition, in the process of preparing the base region, process parameters such as the implantation concentration of the dopant, annealing temperature and time need to be precisely controlled to ensure that the obtained base region has the desired electrical properties.

[0218] In some embodiments, the method for preparing the cellular structure further includes: preparing at least one protrusion on a side of the drift region facing the second well region, and the at least one protrusion extends in the longitudinal direction of the cellular structure. The design of these protrusions helps to increase the surface area of ​​the drift region, thereby optimizing the electric field distribution and increasing the withstand voltage capability of the device.

[0219] In some embodiments, the at least one protrusion may be one protrusion, two protrusions, three protrusions, five protrusions or more. The number of protrusions may be set according to electric field distribution, device structure and application requirements, and is not specifically limited here.

[0220] In some embodiments, the protrusions may be in various shapes, such as trapezoidal, rectangular or other complex shapes, to meet different design requirements and application scenarios. The preparation process of the protrusions may involve key steps such as photolithography, etching, ion implantation and deposition, through which the desired protrusions may be formed on the surface of the drift region of the device to increase the surface area of ​​the drift region.

[0221] In some embodiments, the method for preparing the cell structure further includes: preparing an emitter, an ohmic contact region and an emitter metal layer on the front side of the drift region; and preparing a collector metal layer on a side of the collector region away from the buffer region.

[0222] The emitter can be prepared by defining an emitter window on the front side of the drift region through photolithography, and then injecting phosphorus (P) ions or arsenic (As) ions into the window area to make it an N-type semiconductor material. After the injection, annealing is performed to activate the phosphorus ions and form a conductive channel. This method can form a P-type emitter.

[0223] In some embodiments, the ohmic contact region can be prepared by ion implantation, where a high concentration of boron (B) ions are implanted into a specific area on the semiconductor surface to form a high concentration P-type region for forming an ohmic contact with the emitter. Its function is to reduce contact resistance and ensure good electrical contact performance, reduce energy loss, and ensure smooth current transmission.

[0224] In some embodiments, the emitter metal layer may be prepared by depositing a metal film through physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form the emitter metal layer.

[0225] In some embodiments, the collector metal layer may also be prepared by depositing a layer of conductive metal on a side of the collector region away from the buffer region by methods such as physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form the collector metal layer.

[0226] In some embodiments, the method for preparing the cellular structure further includes: preparing a planar gate structure on the front side of the cellular structure, wherein a planar gate insulating layer is provided between the planar gate structure and the emitter, the second well region and the drift region.

[0227] Among them, the planar gate structure can be prepared by photolithography and metal deposition processes. First, the shape and size of the planar gate structure are defined on the target area using photolithography technology. Then, a layer of metal, such as aluminum, copper or silver, is deposited on or around the photolithography pattern by physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form a planar gate structure. These metals can have good conductivity and processability, enabling them to provide an appropriate gate control electric field.

[0228] In some embodiments, the planar gate insulating layer can be made of a material with good insulating properties, such as silicon dioxide (SiO2), silicon nitride (Si3N4) or aluminum oxide (Al2O3). These materials can be deposited around the gate by chemical vapor deposition (CVD) or physical vapor deposition (PVD) and other techniques. During the photolithography and etching process, these materials are retained around the gate to form a planar gate insulating layer. The planar gate insulating layer has good insulating properties and can effectively isolate the planar gate structure from other parts to prevent electrical short circuits or breakdowns during the operation of the device.

[0229] As Figure 1 Take the cell structure shown in the figure as an example. Figure 5-Figure 11 The preparation process of the cellular structure of the embodiment of the present invention is described. The preparation process of the cellular structure may include the following steps:

[0230] First, a lightly doped silicon wafer is selected as a substrate, and phosphorus (P) ions are implanted into the substrate to prepare a drift region of the first conductivity type. The resulting structure is as follows: Figure 5 shown.

[0231] Second, boron (B) ions are implanted into the substrate to prepare a second well region of the second conductivity type, and the junction depth of the second well region is about 12-15um. Figure 6 shown.

[0232] Third, if Figure 7 As shown, boron (B) ions are implanted again on the substrate to form a protrusion on the side of the drift region facing the second well region. The resulting structure is as shown in FIG. Figure 8 shown.

[0233] Fourth, photolithography is performed on the surface of the silicon wafer to form a window of the trench gate structure, and the trench is etched and the damaged layer is removed. Then, a gate oxide layer is grown, filled with polysilicon and etched to form a trench with a depth of about 5um. The resulting structure is as follows: Fig. 9 shown.

[0234] Fifth, a window of the first well region is prepared by photolithography, and then phosphorus (P) ions are implanted once, and the resulting structure is as follows: Fig.10 shown.

[0235] Sixth, a secondary implantation of phosphorus (P) ions is performed to form a first well region. The junction depth of the first well region is about 8um. The resulting structure is as follows: Fig.11 shown.

[0236] Seventh, by implanting, driving and annealing boron (B) ions in the active region, a base region of the second conductivity type is formed, and the junction depth of the base region is about 2um-3um. The resulting structure is as follows Fig.12 shown.

[0237] Eighth, a window of the emitter region is prepared by photolithography technology, and phosphorus (P) ions are implanted to form the emitter region. The resulting structure is as follows: Fig.13 and Fig.14 shown.

[0238] Ninth, first deposit phosphosilicate glass, then form contact holes by photolithography, and implant high-concentration boron (B) ions to form a heavily doped P-type ohmic contact area, and then perform surface metallization treatment. The resulting structure is as follows: Fig.15 and Fig.16 shown.

[0239] Tenth, flip the silicon wafer and thin the back side of the silicon wafer to the required thickness, and then implant phosphorus (P) ions to form a buffer zone of the first conductivity type. The resulting structure is as follows: Fig.17 shown.

[0240] Eleventh, by selectively implanting boron (B) ions, a heavily doped collector region of the second conductivity type is formed. The resulting structure is as follows Fig.18 shown.

[0241] Twelve, a collector metal layer is prepared on the side of the collector region away from the buffer zone to complete the preparation of the cell structure of the embodiment of the present invention. The obtained structure is as follows Figure 1 shown.

[0242] In general, the embodiments of the present invention can be realized through multiple photolithography, oxidation, ion implantation, annealing and deposition process steps. Figure 1 Preparation of cellular structures. In addition, Figure 2 and Figure 3 The preparation process of the cellular structure is similar to the above Figure 1 The preparation process of the cellular structure is similar, so it will not be described in detail.

[0243] In some embodiments, the first well region, the second well region, the base region and the emitter can be prepared before the trench gate structure is completed, which means that the doping and structure formation of key areas can be completed before the trench gate structure is formed, thereby better controlling the performance and characteristics of the device.

[0244] In some embodiments, the preparation of the buffer region of the first conductivity type can be performed before preparing the front structure of the IGBT (including the cellular MOS structure and the terminal structure), which can reduce interference with the buffer region when preparing the front structure and improve device performance and preparation efficiency.

[0245] In some embodiments, a double-layer epitaxial material having a buffer region of the first conductivity type and a drift region of the first conductivity type can be directly selected as the silicon wafer material for the process start. This method avoids the step of using hydrogen implantation to form a buffer region (field stop layer), simplifies the process flow, and improves the efficiency of preparation.

[0246] In some embodiments, the process steps and process conditions in the method for preparing the cellular structure of the embodiment of the present invention can be set according to actual needs.

[0247] Reference below Fig.19 A semiconductor device according to an embodiment of the present invention is described.

[0248] Fig.19 is a block diagram of a semiconductor device according to an embodiment of the present invention, Fig.19 As shown, the semiconductor device 111 includes at least one cell structure 1 as described in the above embodiments.

[0249] In some embodiments, the semiconductor device 111 may be an insulated gate bipolar transistor (IGBT) or a reverse conducting insulated gate bipolar transistor (RC-IGBT).

[0250] In some embodiments, the IGBT may be an n-channel IGBT device or a p-channel IGBT device. The method for preparing an n-channel IGBT device is also applicable to the preparation of a p-channel IGBT device.

[0251] In some embodiments, the semiconductor material of the IGBT device may be silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or other types of materials.

[0252] According to the semiconductor device 111 of the embodiment of the present invention, by adopting the cellular structure 1 described in the above embodiment, the overlapping area between the bottom of the trench gate structure and the collector region 60 can be reduced, the Miller capacitance of the device is reduced, the switching speed of the device is increased, and the energy loss of the device during the switching process is reduced, thereby improving the overall performance of the semiconductor device 111.

[0253] Reference below Fig. 20 An electronic device according to an embodiment of the present invention is described.

[0254] Fig. 20 is a block diagram of an electronic device according to an embodiment of the present invention, such as Fig. 20 As shown, the electronic device 110 includes at least one semiconductor device 111 described in the above embodiments.

[0255] In some embodiments, the electronic device 110 is widely used in various fields, including but not limited to: power management equipment, electric vehicles, industrial control equipment, home appliances, renewable energy equipment, etc.

[0256] According to the electronic device 110 of the embodiment of the present invention, by adopting the semiconductor device 111 described in the above embodiment, the overlapping area between the bottom of the trench gate structure and the collector region 60 can be reduced, the Miller capacitance formed between the trench gate and the collector region 60 due to charge accumulation is reduced, the switching speed of the semiconductor device 111 is improved, and the energy loss of the device during the switching process is reduced, thereby improving the overall performance of the device.

[0257] Reference below Fig.21 A vehicle according to an embodiment of the present invention will be described.

[0258] Fig.21 is a block diagram of a vehicle according to an embodiment of the present invention, Fig.19 As shown, the vehicle 100 includes the electronic device 110 described in the above embodiment.

[0259] In some embodiments, the electronic device 110 in the vehicle 100 may be a device using IGBT, such as a motor drive system, a charging and discharging circuit, an on-board charger, etc.

[0260] Among them, the motor drive system can use the motor as the power source. The motor drive system uses IGBT devices to achieve precise control of the motor current and voltage, thereby adjusting the motor speed and torque. The high switching speed and low conduction loss of IGBT devices enable them to efficiently handle large currents and high voltages, providing stable and reliable motor drive performance.

[0261] In some embodiments, the charge and discharge circuit can be used in a battery management system and a regenerative braking system. The battery management system can use IGBT devices to control the charging and discharging of the battery pack. By adjusting the gate voltage of the IGBT, the battery current can be accurately controlled to ensure that the battery operates in an optimal state. When the vehicle 100 decelerates or brakes, the regenerative braking system can use the IGBT device to operate the motor as a generator, convert mechanical energy into electrical energy, and feed it back to the battery for charging, thereby achieving the purpose of energy recovery.

[0262] In some embodiments, the on-board charger can achieve efficient power conversion through IGBT devices, converting the AC power provided by the external power grid into DC power to charge the battery pack. The efficient switching characteristics and high current handling capabilities of IGBT devices enable the on-board charger to charge electric vehicles quickly and efficiently.

[0263] According to the vehicle 100 of the embodiment of the present invention, by adopting the electronic device 110 described in the above embodiment, the overlapping area between the bottom of the trench gate structure and the collector area 60 can be reduced, the Miller capacitance formed between the trench gate and the collector area 60 due to charge accumulation is reduced, the switching speed of the device is improved, and the energy loss of the device during the switching process is reduced, thereby improving the overall performance of the vehicle 100.

[0264] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0265] Figure 1-Figure 3 Two trench gate structures are shown for illustrative purposes, but after reading the following technical solution, ordinary technicians can obviously understand that the solution can be applied to a technical solution with three or more trench gate structures, which also falls within the protection scope of the present invention.

[0266] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0267] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A cellular structure, characterized in that: include: at least one trench gate structure, each of the trench gate structures extending along the longitudinal direction of the cell structure; A first well region of a first conductivity type, wherein the first well region wraps around the bottom of each of the trench gate structures along a longitudinal direction of the cellular structure and a lateral direction of the cellular structure, wherein the longitudinal direction of the cellular structure and the lateral direction of the cellular structure are perpendicular to each other; A second well region of a second conductivity type, wherein the second well region wraps around a bottom of the first well region and a side surface of the first well region along a lateral direction of the cellular structure and a longitudinal direction of the cellular structure.

2. The cellular structure according to claim 1, characterized in that: The second well region extends along the side of the first well region in the longitudinal direction of the cellular structure, and the second well region extends to the side of the edge-distributed trench gate structure in the longitudinal direction of the cellular structure, and the second well region contacts the side of the edge-distributed trench gate structure.

3. The cellular structure according to claim 1 or 2, characterized in that: The cellular structure also includes: A drift region of a first conductivity type, wherein the second well region is located on a front side of the drift region in a longitudinal direction of the cellular structure.

4. The cellular structure according to claim 3, characterized in that: The cellular structure also includes: a buffer zone of a first conductivity type, the buffer zone being located on a back side of the drift region away from the first well region in a longitudinal direction of the cell structure; A collector region of a second conductivity type is located at a side of the buffer region away from the drift region in a longitudinal direction of the cellular structure.

5. The cellular structure according to claim 4, characterized in that: The cellular structure also includes: A base region of a second conductivity type is located on the first well region in a longitudinal direction of the cell structure.

6. The cellular structure according to claim 5, characterized in that: The cellular structure comprises: A first trench gate structure and a second trench gate structure, wherein the first trench gate structure and the second trench gate structure are arranged at intervals along the lateral direction of the cellular structure, and both the first trench gate structure and the second trench gate structure extend along the longitudinal direction of the cellular structure and extend into the first well region.

7. The cellular structure according to claim 6, characterized in that: The base region is located between the first trench gate structure and the second trench gate structure.

8. The cellular structure according to claim 6, characterized in that: At least one protrusion is formed on a surface of the drift region facing the second well region in the longitudinal direction of the cellular structure.

9. The cellular structure according to claim 8, characterized in that: The drift region is formed with at least one first protrusion, and each of the first protrusions extends along the longitudinal direction of the cellular structure and penetrates the second well region and extends into the first well region.

10. The cellular structure according to claim 9, characterized in that: The first protrusion is located in the middle of the drift region, and the portion of each first protrusion extending into the first well region (20) is located between the first trench gate structure and the second trench gate structure.

11. The cellular structure according to claim 10, characterized in that: The drift region is formed with a plurality of the first protrusions, and the plurality of the first protrusions are arranged at intervals along a lateral direction of the cellular structure.

12. The cellular structure according to claim 9, characterized in that: The drift region further forms a second protrusion, which is spaced apart from the first protrusion in the lateral direction of the cellular structure. The second protrusion extends in the longitudinal direction of the cellular structure and is matched and connected with a first corner of the second well region.

13. The cellular structure according to claim 12, characterized in that: The drift region also forms a third protrusion, and the third protrusion, the second protrusion and the first protrusion are arranged at intervals in the lateral direction of the cellular structure, the second protrusion and the third protrusion are located on both sides of the first protrusion, and the third protrusion extends along the longitudinal direction of the cellular structure and is matched and connected with the second corner of the second well region.

14. The cellular structure according to claim 13, characterized in that: The second protrusion is located on a side of the first trench gate structure away from the second trench gate structure, and the third protrusion is located on a side of the second trench gate structure away from the first trench gate structure.

15. The cellular structure according to claim 14, characterized in that: The cellular structure also includes: A first emitter of a first conductivity type, wherein the first emitter is located on a side of the first trench gate structure away from the second trench gate structure in a lateral direction of the cell structure, and the first emitter is located on a portion of the second well region connected to the first trench gate structure in a longitudinal direction of the cell structure.

16. The cellular structure according to claim 15, characterized in that: The cellular structure also includes: A second emitter of the first conductivity type, the second emitter is located on a side of the second trench gate structure away from the first trench gate structure in the lateral direction of the cell structure, and the second emitter is located on a portion of the second well region connected to the second trench gate structure in the longitudinal direction of the cell structure.

17. The cellular structure according to claim 16, characterized in that: The cellular structure also includes: A first ohmic contact region, wherein the first ohmic contact region is located on a side of the first emitter away from the second trench gate structure in a lateral direction of the cell structure, the first ohmic contact region is connected to the first emitter, and the first ohmic contact region is located on the second well region in a longitudinal direction of the cell structure.

18. The cellular structure according to claim 17, characterized in that: The cellular structure also includes: A second ohmic contact region, the second ohmic contact region is located on a side of the second emitter away from the second trench gate structure in the lateral direction of the cell structure, the second ohmic contact region is connected to the second emitter, and the second ohmic contact region is located on the second well region in the longitudinal direction of the cell structure.

19. The cellular structure according to claim 18, characterized in that: The cellular structure also includes: a first insulating layer, wherein the first insulating layer is located on a portion of the first emitter, the first trench gate structure, the second trench gate structure, and a portion of the second emitter; A first emitter metal layer covers the first insulating layer and is connected to the first ohmic contact region, the first emitter, the second emitter, and the second ohmic contact region.

20. The cellular structure according to claim 18, characterized in that: The cellular structure also includes: a third emitter, the third emitter being located on a side of the first trench gate structure close to the second trench gate structure in a lateral direction of the cell structure, and being located on the base region in a longitudinal direction of the cell structure; A fourth emitter, wherein the fourth emitter is located on a side of the second trench gate structure close to the first trench gate structure in a lateral direction of the cell structure, and the fourth emitter is located on the base region in a longitudinal direction of the cell structure.

21. The cellular structure according to claim 20, characterized in that: The cellular structure also includes: A third ohmic contact region is located on the base region in the longitudinal direction of the cell structure, and the third ohmic contact region is connected to the third emitter and the fourth emitter.

22. The cellular structure according to claim 21, characterized in that: The cellular structure also includes: a second insulating layer, wherein the second insulating layer covers an upper surface of the first trench gate structure, a portion of an upper surface of the first emitter, and a portion of an upper surface of the third emitter; a third insulating layer, wherein the third insulating layer covers an upper surface of the second trench gate structure, a portion of an upper surface of the second emitter, and a portion of an upper surface of the fourth emitter; A second emitter metal layer, the second emitter metal layer covers the upper surface of the second insulating layer and the upper surface of the third insulating layer, the second emitter metal layer is connected to the first ohmic contact area, the first emitter, the second emitter, the second ohmic contact area, the third emitter, the fourth emitter and the third ohmic contact area.

23. The cellular structure according to claim 16, characterized in that: The cellular structure also includes: a fifth emitter, wherein the fifth emitter is located on a side of the first trench gate structure close to the second trench gate structure in a lateral direction of the cell structure, and the fifth emitter is located on the base region in a longitudinal direction of the cell structure; A sixth emitter, wherein the sixth emitter is located on a side of the second trench gate structure close to the first trench gate structure in a lateral direction of the cell structure, and the sixth emitter is located on the base region in a longitudinal direction of the cell structure.

24. The cellular structure according to claim 23, characterized in that: The cellular structure also includes: A fourth ohmic contact region, wherein the fourth ohmic contact region is located on the base region in a longitudinal direction of the cell structure, and the fourth ohmic contact region is connected to the fifth emitter and the sixth emitter.

25. The cellular structure according to claim 24, characterized in that: The cellular structure comprises: a fourth insulating layer, wherein the fourth insulating layer covers an upper surface of the first trench gate structure, a portion of an upper surface of the first emitter, and a portion of an upper surface of the fifth emitter; a fifth insulating layer, wherein the fifth insulating layer covers an upper surface of the second trench gate structure, a portion of an upper surface of the second emitter, and a portion of an upper surface of the sixth emitter; A third emitter metal layer, the third emitter metal layer covers the upper surface of the fourth insulating layer and the upper surface of the fifth insulating layer, and the third emitter metal layer is connected to the first emitter, the fifth emitter, the fourth ohmic contact area, the sixth emitter and the second emitter.

26. The cellular structure according to any one of claims 23 to 25, characterized in that: The second protrusion extends along the longitudinal direction of the cellular structure until it is flush with an upper surface of a portion of the second well region connected to the first trench gate structure.

27. The cellular structure according to claim 26, characterized in that: The third protrusion extends along the longitudinal direction of the cellular structure until it is flush with an upper surface of a portion of the second well region connected to the second trench gate structure.

28. The cellular structure according to claim 26, characterized in that: The cellular structure also includes: a first planar gate insulating layer, wherein the first planar gate insulating layer covers an upper surface of the second protrusion, an upper surface of a portion of the second well region connected to the first trench gate structure, and an upper surface of a portion of the first emitter; A first planar gate structure is located on an upper surface of the first planar gate insulating layer in a longitudinal direction of the cell structure.

29. The cellular structure according to claim 27, characterized in that: The cellular structure also includes: a second planar gate insulating layer, wherein the second planar gate insulating layer covers an upper surface of the third protruding portion, an upper surface of a portion of the second well region connected to the second trench gate structure, and an upper surface of a portion of the second emitter; A second planar gate structure is located on an upper surface of the second planar gate insulating layer in a longitudinal direction of the cell structure.

30. The cellular structure according to claim 4, characterized in that: The cellular structure also includes: A collector metal layer is located at a side of the collector region away from the buffer region in the longitudinal direction of the cellular structure.

31. A method for preparing a cellular structure, characterized in that: include: providing a substrate; Preparing at least one trench gate structure, a first well region of a first conductivity type and a second well region of a second conductivity type on the substrate; Each of the trench gate structures extends along the longitudinal direction of the cellular structure, the first well region wraps around the bottom of each trench gate structure along the longitudinal direction of the cellular structure and the transverse direction of the cellular structure, the second well region wraps around the bottom and the side of the first well region along the transverse direction of the cellular structure and the longitudinal direction of the cellular structure, and the longitudinal direction of the cellular structure is perpendicular to the transverse direction of the cellular structure.

32. The preparation method according to claim 31, characterized in that: The preparation method further comprises: A drift region of the first conductivity type is prepared on the substrate, wherein the second well region is located on the front side of the drift region in the longitudinal direction of the cell structure; Preparing a buffer zone of a first conductivity type on the back side of the drift region away from the first well region; A collector region of a second conductivity type is prepared on a side of the buffer region away from the drift region.

33. The preparation method according to claim 32, characterized in that: The preparation method further comprises: In the longitudinal direction of the cellular structure, a base region of a second conductivity type is prepared on the first well region.

34. The preparation method according to claim 32, characterized in that: The preparation method further comprises: At least one protrusion is formed on a surface of the drift region facing the second well region, and the at least one protrusion extends along a longitudinal direction of the cellular structure.

35. The preparation method according to any one of claims 32 to 34, characterized in that: The preparation method further comprises: preparing an emitter, an ohmic contact region and an emitter metal layer on the front side of the drift region; and A collector metal layer is prepared on a side of the collector region away from the buffer region.

36. The preparation method according to claim 35, characterized in that: The preparation method further comprises: A planar gate structure is prepared on the front side of the cell structure, and a planar gate insulating layer is provided between the planar gate structure and the emitter, the second well region and the drift region.

37. A semiconductor device, characterized in that: Comprising at least one cellular structure according to any one of claims 1 to 30.

38. An electronic device, characterized in that: Comprising at least one semiconductor device as claimed in claim 37.

39. A vehicle, characterized in that: An electronic device comprising the electronic device described in claim 38.

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