Insulated gate bipolar transistor, preparation method, electronic equipment and vehicle
By introducing PMOS components and N+ barrier zones into the IGBT, the problem of potential floating in the floating P region is solved, the Miller capacitance is reduced, and the switching speed and reliability are improved.
Patent Information
- Application Number
- CN202411534021.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-04-18
AI Technical Summary
During the conduction process, the trench type insulated gate bipolar transistor (IGBT) affects the operation reliability of the device due to the floating potential floating in the P region.
The PMOS element is introduced into the IGBT, and the potential of the floating P region is clamped through the PMOS element in the trench emitter to ensure the stable distribution of the potential, and the hole current flows through the N+ barrier region to prevent the trench gate potential from floating.
It effectively reduces the Miller capacitance of the device, increases the switching speed, reduces the switching loss, and reduces the oscillation of the device during the switching process, improving reliability.
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Figure CN119855176A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to an insulated gate bipolar transistor, a method for preparing the insulated gate bipolar transistor, an electronic device and a vehicle. Background Art
[0002] In the current related technologies, trench insulated gate bipolar transistors (IGBTs) generally isolate the trench gate from the N-drift region by setting a floating P region with a depth greater than the trench to reduce the Miller capacitance of the IGBT device and enhance the withstand voltage characteristics of the IGBT device. However, during the conduction of the IGBT device, the potential of the floating P region will float with the collector voltage, which will have an adverse effect on the operating reliability of the device. Summary of the invention
[0003] The present application provides an insulated gate bipolar transistor, a method for manufacturing the insulated gate bipolar transistor, an electronic device and a vehicle.
[0004] The insulated gate bipolar transistor involved in the embodiment of the present application includes an emitter, a gate, a collector and a conductive region, wherein the conductive region includes a floating P region and a PMOS element;
[0005] The gate is provided with a trench gate, and the trench gate extends into the floating P region;
[0006] The emitter is provided with a trench emitter, the trench emitter extends into the floating P region and has a depth smaller than that of the trench gate;
[0007] The PMOS element is disposed at the trench emitter to clamp the potential of the floating P region.
[0008] In some embodiments, an N+ blocking region is provided in the conductive region, and the N+ blocking region is distributed at one end of the trench gate extending into the floating P region to suppress the hole current of the PMOS element from flowing at the trench gate.
[0009] In some embodiments, the PMOS element includes a source region and an N region, the source region is connected to the emitter, the source region is sequentially adjacent to the N region, and the N region is adjacent to the floating P region.
[0010] In some embodiments, the emitter includes an emitter element and an N+ emitter region, the emitter element and the N+ emitter region are adjacent to each other in sequence, and a first insulating dielectric layer is disposed between the emitter element and the gate.
[0011] In some embodiments, the conductive region includes a heavily doped P+ region and a P base region, the emitter element, the N+ emitter region and the heavily doped P+ region are adjacent to each other, and the N+ emitter region, the P base region and the heavily doped P+ region are adjacent to each other.
[0012] In some embodiments, a second insulating dielectric layer is disposed between the trench gate, the conductive region, and the emitter.
[0013] In some embodiments, a third insulating dielectric layer is disposed between the trench emitter, the floating P region, and the PMOS element.
[0014] In some embodiments, the collector includes a collector element and a P+ collector region, and the collector element and the P+ collector region are sequentially adjacent.
[0015] In some embodiments, the conductive region further includes an N-type field stop layer, and the collector element, the P+ collector region, and the N-type field stop layer are adjacent to each other in sequence.
[0016] In some embodiments, the conductive region further includes an N-drift region, and the collector, the N-drift region, and the floating P region are sequentially adjacent.
[0017] In some embodiments, the conductive region further includes a P-base region, and the P-base region, the N-drift region, and the trench gate are adjacent to each other.
[0018] In certain embodiments, the conductive region further includes a CS carrier storage layer, the CS carrier storage layer being adjacent to the P base region, the CS carrier storage layer being configured to enhance conductivity modulation during a turn-on phase of the insulated gate bipolar transistor.
[0019] In some embodiments, the PMOS element includes a source region, an N region, and a P region, the source region is connected to the emitter, the source region, the N region, and the P region are adjacent to each other in sequence, and the P region is adjacent to the floating P region.
[0020] In this way, the present application can firstly make the bottom of the trench gate surrounded by the floating P region, thereby reducing the overlapping area between the trench gate and the collector, reducing the Miller capacitance of the device, increasing the switching speed of the device, and reducing the switching loss of the device. Secondly, when the device is in the on state, the presence of the floating P region PMOS can clamp the floating P region potential at a fixed value, which is conducive to maintaining the stable distribution of the potential around the trench gate, thereby helping to reduce the oscillation phenomenon during the device switching process. Thirdly, the reverse biased PN junction formed by the floating P region and the N-drift region becomes the position with the strongest longitudinal field intensity distribution, and the longitudinal electric field intensity distribution is adjusted, and the electric field protection of the bottom structure of the trench gate is achieved by setting the peak area of the longitudinal field intensity distribution to the area below the bottom of the trench gate. In addition, the N+ blocking area at the bottom of the trench gate is used to block the hole current generated by the PMOS, preventing the hole current from flowing at the bottom of the trench and causing the trench gate potential to float, which is conducive to reducing the oscillation phenomenon during the device switching process.
[0021] The method for preparing the insulated gate bipolar transistor in the embodiment of the present application can be used to prepare the above-mentioned insulated gate bipolar transistor, and specifically comprises:
[0022] Taking a silicon wafer having a first doping level to form an N-drift region;
[0023] The silicon wafer is subjected to photolithography, ion implantation, etching, deposition and / or metallization treatment according to a preset process to form the emitter, the collector, the gate and the conductive region to manufacture the insulated gate bipolar transistor.
[0024] In some embodiments, performing photolithography, ion implantation, etching, deposition and / or metallization on the silicon wafer according to a preset process to form the emitter, the collector, the gate and the conductive region to manufacture the insulated gate bipolar transistor specifically includes:
[0025] implanting boron ions into the N-drift region at a predetermined junction depth at a first end of the N-drift region to form an original floating P region;
[0026] Performing photolithography, filling and etching processes in a preset manner in the original floating P region to form a trench gate and a trench emitter;
[0027] Performing photolithography at the trench gate, and sequentially injecting phosphorus ions and boron ions into the photolithography area to form an N+ blocking area;
[0028] Implanting phosphorus ions into the original floating P region at the trench gate to form a floating P region;
[0029] Performing photolithography at a third preset depth in the N-drift region, implanting boron ions into the photolithography region and annealing to form a P-base region;
[0030] Performing photolithography in the N-drift region and implanting phosphorus ions into the photolithography region to form an N+ emitter region;
[0031] Implanting boron ions with a preset concentration into the N-drift region to form a heavily doped P+ region;
[0032] Depositing phosphosilicate glass in the N-drift region and performing photolithography to form photolithography holes to provide a first insulating dielectric layer within the position range of the floating P region, the emitter, and the gate;
[0033] Perform ion implantation at the trench emitter in the floating P region in a preset manner to form a PMOS element;
[0034] Performing metallization at a first end of the N-drift region to form an emitter element;
[0035] Thinning the silicon wafer at the second end of the N-drift region and implanting phosphorus ions to form an N-type field stop layer;
[0036] Implanting boron ions into the N-type field stop layer to form a P+ collector region;
[0037] Metallization is performed at a second end of the N-drift region to form a collector element.
[0038] In some embodiments, performing photolithography, filling, and etching in a preset manner in the original floating P region to form a trench gate and a trench emitter includes:
[0039] Photolithography of a first trench at a first preset depth;
[0040] photolithography a second trench at a second predetermined depth;
[0041] providing a second insulating dielectric layer for the first trench;
[0042] providing a third insulating dielectric layer for the second trench;
[0043] Filling the first trench with polysilicon and performing etching to form the trench gate;
[0044] The second trench is filled with polysilicon and etched to form the trench emitter.
[0045] In some embodiments, the step of performing ion implantation at the trench emitter in the floating P region in a preset manner to form a PMOS element includes:
[0046] Phosphorus ions and boron ions are implanted successively at the trench emitter in the floating P region to respectively form an N region and a source region in a PMOS element.
[0047] In some embodiments, the performing of photolithography at a third preset depth in the N-drift region, implanting boron ions into the photolithography region, and annealing to form a P-base region also includes:
[0048] Photolithography is performed in the N-drift region, and phosphorus ions are implanted into the photolithography region to form a CS carrier storage layer.
[0049] In some embodiments, the step of sequentially implanting phosphorus ions and boron ions at the trench emitter in the floating P region to form an N region and a source region in a PMOS element, respectively, further comprises:
[0050] Boron ions are implanted at the trench emitter in the floating P region to form a P region with a different doping concentration from that of the floating P region.
[0051] The electronic device in the embodiment of the present application includes the above-mentioned insulated gate bipolar transistor.
[0052] The vehicle in the embodiment of the present application includes the above-mentioned insulated gate bipolar transistor, or includes the above-mentioned electronic device.
[0053] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0054] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0055] Figure 1 A schematic diagram of the structure of an insulated gate bipolar transistor in an embodiment of the present application;
[0056] Figure 2 A schematic diagram of the structure of an insulated gate bipolar transistor in an embodiment of the present application;
[0057] Figure 3 A schematic diagram of the structure of an insulated gate bipolar transistor in an embodiment of the present application;
[0058] Figure 4 It is an application scenario and a schematic diagram of the preparation process of the insulated gate bipolar transistor in the embodiment of the present application.
[0059] Among them: 1. emitter element; 2. first insulating dielectric layer; 3. N+ emitter region; 4. heavily doped P+ region; 5. P base region; 6. trench gate; 7. trench emitter; 8. second insulating dielectric layer and third insulating dielectric layer; 9. N+ barrier region; 10. floating P region; 11. source region; 12. N region; 13. N-drift region; 14. N-type field stop region; 15. P+ collector region; 16. collector element; 17. CS carrier storage layer; 18. P region. DETAILED DESCRIPTION
[0060] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions from beginning to end. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of the present application, and cannot be understood as limiting the embodiments of the present application.
[0061] See also Figure 1 The insulated gate bipolar transistor in the embodiment of the present application includes an emitter, a gate, a collector and a conductive region, the conductive region includes a floating P region 10 and a PMOS element; the gate is provided with a trench gate 6, and the trench gate extends into the floating P region 10; the emitter is provided with a trench emitter 7, and the trench emitter 7 extends into the floating P region 10 and has a depth less than the trench gate 6; the PMOS element is arranged at the trench emitter 7 to clamp the potential of the floating P region 10.
[0062] In some embodiments, an N+ barrier region 9 is disposed in the conductive region and is distributed at one end of the trench gate 6 extending into the floating P region 10 to suppress the hole current of the PMOS element from flowing at the trench gate 6 .
[0063] Specifically, see Figure 1 , Figure 1 The structure cross section of the insulated gate bipolar transistor (hereinafter referred to as IGBT) provided in the embodiment of the present application is schematically shown. In practical application, a plurality of IGBTs may be provided in an integrated circuit. Figure 1 The insulated gate bipolar transistors shown in the figure are connected in parallel to form an IGBT module to realize the corresponding circuit function. Each insulated gate bipolar transistor includes at least three terminals: an emitter, a gate, and a collector. In order to improve the overall stability of the IGBT, the above-mentioned IGBT also includes a conductive region, which is disposed as a whole between the emitter, the gate, and the collector, and has a connection relationship with the three terminals. It should be noted that, except that the boundaries of the trench gate 6 and the trench emitter 7 are formed by artificial etching, Figure 1 The solid lines in the figure represent the natural boundaries of each area due to the differences in ion composition and concentration, and are not artificially set boundaries.
[0064] Specifically, the gate includes a trench gate 6. It should be noted that since the gate and the emitter should be insulated, the trench gate 6 needs to be pre-processed to form an isolation layer around it, so that the end of the trench gate 6 close to the emitter is isolated from the emitter to avoid conduction. The conductive area includes a floating P region 10, which surrounds the end of the trench gate 6 away from the emitter, thereby reducing the overlapping area between the trench gate 6 and the collector, thereby reducing the Miller capacitance of the IGBT as a whole, thereby increasing the switching speed of the IGBT device as a whole and reducing the switching loss of the IGBT device. The emitter is also provided with a trench emitter 7 inside the floating P region 10, and the trench emitter 7 is arranged parallel to the trench gate 6. At the same time, a PMOS element is additionally provided on one side of the trench emitter 7 in the floating P region 10, and the PMOS element is directly connected to the emitter of the IGBT and the floating P region 10. When the IGBT device is turned on, the presence of the PMOS element can achieve a clamping effect, thereby clamping the overall potential of the floating P region 10 to a preset fixed value, thereby stabilizing the potential distribution around the trench gate 6 .
[0065] Furthermore, an N+ blocking region 9 is provided in the floating P region 10 around the end of the trench gate 6 away from the emitter. When the IGBT device is turned on, the N+ blocking region 9 will block the hole current generated by the PMOS element, thereby further preventing the hole current from flowing around the end of the trench gate 6 away from the emitter, avoiding the potential floating phenomenon of the trench gate 6, which is beneficial to reduce the potential oscillation occurring during the conduction and power-off process of the IGBT and improving the reliability of the IGBT device.
[0066] In some embodiments, the PMOS device includes a source region 11 and an N region 12 . The source region 11 is connected to the emitter. The source region 11 and the N region 12 are sequentially adjacent to each other. The N region 12 is adjacent to the floating P region 10 .
[0067] In some embodiments, the emitter includes an emitter element 1 and an N+ emitter region 3, the emitter element 1 and the N+ emitter region 3 are adjacent to each other in sequence, and a first insulating dielectric layer 2 is disposed between the emitter element 1 and the gate.
[0068] In some embodiments, the conductive region includes a heavily doped P+ region 4 and a P base region 5, the emitter element 1, the N+ emitter region 3 and the heavily doped P+ region 4 are adjacent to each other, and the N+ emitter region 3, the P base region 5 and the heavily doped P+ region 4 are adjacent to each other.
[0069] In some embodiments, a second insulating dielectric layer 8 is disposed between the trench gate 6 and the conductive region and the emitter.
[0070] In some embodiments, a third insulating dielectric layer 8 is disposed between the trench emitter 7 and the floating P region 10 and the PMOS element.
[0071] In some embodiments, the collector includes a collector element 16 and a P+ collector region 15 , and the collector element 16 and the P+ collector region 15 are sequentially adjacent.
[0072] In some embodiments, the conductive region further includes an N-type field stop layer 14 , and the collector element 16 , the P+ collector region 15 , and the N-type field stop layer 14 are sequentially adjacent.
[0073] In some embodiments, the conductive region further includes an N-drift region 13 , and the collector, the N-drift region 13 , and the floating P region 10 are sequentially adjacent.
[0074] In some embodiments, the conductive region further includes a P-base region 5 , and the P-base region 5 , the N-drift region 13 , and the trench gate 6 are adjacent to each other.
[0075] Specifically, based on the above embodiment, the PMOS element at least includes a source region 11 and an N region 12, wherein the source region 11 is directly short-circuited with the emitter, and the N region 12 is adjacent to the floating P region 10. When the IGBT is turned on, the source region 11, the N region 12 and the floating P region 10 together constitute a PNP type transistor structure, such as Figure 1 In the case shown, the above-mentioned PNP transistor structure will form an electron channel on the surface of the trench emitter 7, thereby achieving a clamping effect on the potential of the floating P region 10.
[0076] In addition, illustratively, the emitter specifically includes two parts, namely, the emitter element 1 and the N+ emitter region 3, and in coordination therewith, a heavily doped P+ region 4 and a P base region 5 are provided in the conductive region. The emitter element 1 is the emitter of the IGBT device as a whole, and is generally shown as an end plate or pin made of a conductor such as metal. In order to meet the effect in the above-mentioned embodiment, the emitter element 1 and the trench gate 6 should be insulated, and the emitter element 1 and the trench emitter 7 should be connected, so illustratively, please refer to Figure 1, a first insulating dielectric layer 2 is provided between the emitter element 1 and the trench gate 6. The above-mentioned first insulating dielectric layer 2 is generally an insulating layer of insulating materials such as phosphorus silicon glass. In terms of size, the size of the first insulating dielectric layer 2 should be able to completely isolate the trench gate 6 from the emitter element 1 on the one hand, and ensure that the trench emitter 7 and the emitter element 1, and the PMOS element and the emitter element 1 can be fully contacted on the other hand. In addition, the transistor structure composed of the N+ emitter region 3 in the emitter and the heavily doped P+ region 4 and P base region 5 in the conductive region can introduce electrons at the emitter into the N-drift region 13 in the conductive region after power is applied between the emitter and the collector of the IGBT device, thereby realizing the overall conduction of the IGBT device.
[0077] Furthermore, in order to enable the emitter and the PMOS tube to smoothly form an electron channel and ensure that the functions of the trench gate 6 and the trench emitter 7 are normal, an insulating layer should be provided around the trench gate 6 and the trench emitter 7. Therefore, by way of example, a second insulating dielectric layer 8 is provided around the trench gate 6, and a third insulating dielectric layer 8 is provided around the trench emitter 7. The second insulating dielectric layer 8 and the third insulating dielectric layer 8 are both pre-processed when etching the trench, and are generally in the form of a silicon dioxide crystal layer.
[0078] In addition, the collector includes a collector element 16 and a P+ collector region 15, and an N-type field stop layer 14 is provided in the conductive region in coordination therewith. The collector element 16 is the collector that the IGBT device as a whole shows to the outside, and is generally shown as an end plate or pin made of a conductor such as metal. The P+ collector region 15 is directly adjacent to the N-type field stop layer 14 in the conductive region, and the N-type field stop layer 14 is directly adjacent to the N-drift region 13 in the conductive region. When the IGBT device is turned on, the P+ collector region 15 of the collector and the N-type field stop layer 14 and the N-drift region 13 in the conductive region together form a PN junction transistor structure, the P+ collector region 15 injects holes into the N-drift region 13, and the electrons injected into the N-drift region 13 by the emitter are swept to the collector element 16 under the action of the external electric field to form a collector current. It should be noted that a reverse-biased PN junction is formed between the N-drift region 13 and the floating P region 10, and the longitudinal field strength distribution at the PN junction is the strongest among all positions inside the IGBT device. In this way, the peak area of the longitudinal field strength distribution is fixed near the end of the trench gate 6 away from the emitter, thereby providing electric field protection for the bottom structure of the trench gate 6.
[0079] See also Figure 2 In some embodiments, the conductive region further includes a CS carrier storage layer 17, the CS carrier storage layer 17 is adjacent to the P base region 5, and the CS carrier storage layer 17 is configured to enhance conductivity modulation during the conduction phase of the insulated gate bipolar transistor.
[0080] Specifically, on the basis of the above-mentioned embodiments, in order to reduce the overall on-state voltage drop of the IGBT device, in some examples, on the basis of the above-mentioned embodiments, the emitter further includes a CS carrier storage layer 17 (hereinafter referred to as the CS layer), the CS carrier storage layer 17 is generally N-type and adjacent to the P base region 5, and the interface between the P base region 5 and the CS carrier storage layer 17 is utilized to form an NPN-type transistor structure together with the N+ emitter region 3 in the emitter, the heavily doped P+ region 4 in the conductive region, and the P base region 5, which can block the holes in the N-drift region 13 from entering the P base region 5 during the on-state phase of the IGBT device, thereby inducing more emitter electrons to the N-drift region 13, increasing the carrier concentration of the N-drift region 13, and enhancing the overall conductivity modulation effect of the IGBT device, thereby reducing the on-state voltage drop of the IGBT device.
[0081] See also Figure 3 In some embodiments, the PMOS element includes a source region 11, an N region 12, and a P region 18, the source region 11 is connected to the emitter, the source region 11, the N region 12, and the P region 18 are adjacent to each other in sequence, and the P region 18 is adjacent to the floating P region.
[0082] Specifically, based on the above embodiment, in addition to the source region 11 and the N region 12, the PMOS element may also be provided with a P region 18, the emitter element 1, the source region 11, the N region 12, the P region 18 and the floating P region 10 are sequentially adjacent, wherein there is a concentration difference between the ions in the P region 18 and the floating P region 10, and the above concentration difference will affect the on-state voltage drop of the PMOS element. In the process of manufacturing the IGBT element, the on-state voltage drop of the PMOS element may be adjusted by adjusting the concentration of the ions in the P region 18, thereby adjusting the clamping effect of the PMOS element on the floating P region 10.
[0083] The conduction process of the above-mentioned IGBT device is as follows: when a positive voltage is applied to the collector and the gate and the emitter is zero biased, the flow path of electrons in the initial stage of the IGBT device is: emitter N+ emitter region 3—P base region 5 electron conductive channel—CS carrier storage layer 17—N-drift region 13—N-type field stop layer 14—collector P+ collector region 16. As the collector voltage increases, when the potential difference between the collector P+ collector region 16 and the N-type field stop layer 14 is greater than the built-in potential of the PN junction, the PN junction is turned on, and the holes in the P+ collector region 16 begin to be injected into the N-drift region 13, and the IGBT realizes a unipolar to bipolar conduction mode. The holes in the P+ collector region 16 reach the N-drift region 13 and are swept to the P base region 5 of the emitter under the action of a strong electric field, and reach the emitter element 1 through the transistor structure at the emitter.
[0084] In this way, the present application can firstly make the bottom of the trench gate 6 surrounded by the floating P region 10, thereby reducing the overlapping area between the trench gate 6 and the collector, reducing the Miller capacitance of the device, improving the switching speed of the device, and reducing the switching loss of the device. Secondly, when the device is in the on state, the presence of the PMOS element can clamp the potential of the floating P region 10 at a fixed value, which is conducive to maintaining the stable distribution of the potential around the trench gate 6, thereby helping to reduce the oscillation phenomenon during the device switching process. Thirdly, the reverse biased PN junction formed by the floating P region 10 and the N-drift region 13 becomes the position with the strongest longitudinal field intensity distribution, and the longitudinal electric field intensity distribution is adjusted. By setting the peak area of the longitudinal field intensity distribution to the area below the bottom of the trench gate 6, the electric field protection of the bottom structure of the trench gate 6 is achieved. In addition, the N+ blocking region 9 at the bottom of the trench gate 6 is used to block the hole current generated by the PMOS, prevent the hole current from flowing at the bottom of the trench and causing the trench gate 6 potential to float, which is conducive to reducing the oscillation phenomenon during the device switching process.
[0085] The method for preparing the insulated gate bipolar transistor in the embodiment of the present application can be used to prepare the above-mentioned insulated gate bipolar transistor, and specifically comprises:
[0086] Taking a silicon wafer with a first doping level to form an N-drift region 13;
[0087] The silicon wafer is subjected to photolithography, ion implantation, etching, deposition and / or metallization according to a preset process to form an emitter, a collector, a gate and a conductive region to manufacture an insulated gate bipolar transistor.
[0088] Specifically, for the preparation of the IGBT device in the above embodiment, illustratively, a silicon wafer with a relatively light doping degree is first selected, and the main part of the silicon wafer is used to construct the N-drift region 13 in the conductive region of the IGBT device, such as Figure 4 (a) shown.
[0089] On the basis of the above-mentioned silicon wafer, for each component of the IGBT device in the above-mentioned implementation mode, it is necessary to perform process treatments such as photolithography, etching, crystal deposition, ion implantation, and metallization on the above-mentioned silicon wafer. The specific process execution sequence needs to be based on the positional relationship of each component on the silicon wafer. For relevant process limitations, please refer to the following examples.
[0090] In some embodiments, the steps of performing photolithography, ion implantation, etching, deposition and / or metallization on a silicon wafer according to a preset process to form an emitter, a collector, a gate and a conductive region to manufacture an insulated gate bipolar transistor specifically include:
[0091] Injecting boron ions into the N-drift region 13 at a preset junction depth at a first end of the N-drift region 13 to form an original floating P region;
[0092] Performing photolithography, filling and etching processes in a preset manner in the original floating P region to form a trench gate 6 and a trench emitter 7;
[0093] Perform photolithography at the trench gate 6, and successively implant phosphorus ions and boron ions into the photolithography area to form an N+ blocking region 9;
[0094] Injecting phosphorus ions into the original floating P region at the trench gate 6 to form a floating P region 10;
[0095] Performing photolithography at a third preset depth in the N-drift region 13, implanting boron ions into the photolithography region and annealing to form a P-base region 5;
[0096] Perform photolithography in the N-drift region 13 and implant phosphorus ions into the photolithography area to form an N+ emitter region 3;
[0097] Injecting boron ions with a preset concentration into the N-drift region 13 to form a heavily doped P+ region 4;
[0098] Depositing phosphosilicate glass in the N-drift region 13 and performing photolithography to form photolithography holes, so as to set the first insulating dielectric layer 2 within the position range of the floating P region 10, the emitter, and the gate;
[0099] Performing ion implantation at the trench emitter 7 in the floating P region 10 in a predetermined manner to form a PMOS element;
[0100] Performing metallization at a first end of the N-drift region 13 to form an emitter element 1;
[0101] The thickness of the silicon wafer is reduced at the second end of the N-drift region 13 and phosphorus ions are implanted to form an N-type field stop layer 14;
[0102] Boron ions are implanted into the N-type field stop layer 14 to form a P+ collector region 15;
[0103] Metallization is performed at a second end of the N-drift region 13 to form a collector element 16 .
[0104] Further, in some embodiments, photolithography, filling and etching processes are performed in a preset manner in the original floating P region to form a trench gate 6 and a trench emitter 7, including:
[0105] Photolithography of a first trench at a first preset depth;
[0106] photolithography a second trench at a second predetermined depth;
[0107] Providing a second insulating dielectric layer 8 for the first trench;
[0108] Providing a third insulating dielectric layer 8 for the second trench;
[0109] Filling the first trench with polysilicon and performing etching to form a trench gate 6;
[0110] The second trench is filled with polysilicon and etched to form a trench emitter 7 .
[0111] Further, in some embodiments, ion implantation is performed in a preset manner at the trench emitter 7 in the floating P region 10 to form a PMOS element, including:
[0112] Phosphorus ions and boron ions are implanted successively at the trench emitter 7 in the floating P region 10 to respectively form the N region 12 and the source region 11 in the PMOS element.
[0113] Specifically, see Figure 4 (a)~ Figure 4 (f) The above-mentioned multiple figures collectively show the process of manufacturing an IGBT device.
[0114] Exemplarily, on the basis of the above-mentioned silicon wafer that has been selected, boron ions are injected into the silicon wafer from the front side of the silicon wafer to form an original floating P region, and the injected junction depth is generally 10 to 15 μm. Further, on this basis, photolithography is performed at two parallel positions in the original floating P region at different depths to obtain a first trench with a larger depth and a second trench with a shallower depth. Among them, the depth of the first trench is generally 5 μm, and the depth of the second trench is generally 3 μm. Then, oxidation treatment is performed at the first trench and the second trench to generate an oxide gate at the outer edge of the first trench and the outer edge of the second trench, thereby forming a second insulating dielectric layer 8 and a third insulating dielectric layer 8. Finally, polysilicon is injected into the first trench and the second trench and grid etching is performed to completely form a trench gate 6 and a trench emitter 7. As shown Figure 4 (b) as shown.
[0115] Next, phosphorus ions and boron ions are successively implanted into the original floating P region around the trench gate 6, so as to form an N+ blocking region 9 near the end of the trench gate 6 away from the emitter. Figure 4 On this basis, phosphorus ions are continuously injected into the trench gate 6 to correct the morphological distribution of the original floating P region 10 and form a complete floating P region 10, as shown in FIG. Figure 4 (d) as shown.
[0116] Furthermore, boron ions are injected into the junction of the N-drift region 13 and the floating P region 10 and annealing is performed to diffuse the boron ions to form a P base region 5 of the emitter, wherein the junction depth of the P base region 5 is generally 2 μm. Next, photolithography is performed in the same area to form a corresponding photolithography area, and phosphorus ions are injected into the corresponding photolithography area to form an N+ emitter region 3 of the emitter. In addition, boron ions with a higher concentration are injected into the same area to form a heavily doped P+ region 4. In addition, phosphorus ions and boron ions are respectively injected into the trench emitter 7 in the floating P region 10 to form a source region 11 and an N pole region, respectively. Finally, phosphosilicate glass is deposited in the range between the trench gate 6 and the trench emitter 7, and contact holes are photolithographically formed at the above-mentioned phosphosilicate glass to form a first insulating dielectric layer 2. Finally, metallization is performed on the front side of the silicon wafer to form an emitter element 1 on the front side of the silicon wafer. As shown Figure 4 (e) as shown.
[0117] Further, the silicon wafer is turned over to the back side and thinned until the thickness meets the preset requirements, phosphorus ions are further injected into the thinned area to form an N-type field stop layer 14, and then boron ions are further injected into the N-type field stop layer 14 to form a P+ collector region 15, and finally metallization is performed on the back side of the silicon wafer to form a collector element 16. Figure 4 (f) is shown. So far, the preparation process of the above IGBT device is completed.
[0118] In certain embodiments, see Figure 4 (g) performing photolithography at a third preset depth in the N-drift region 13, implanting boron ions into the photolithography region, and annealing to form a P-base region 5, which also includes:
[0119] Photolithography is performed in the N-drift region 13 , and phosphorus ions are implanted into the photolithography region to form a CS carrier storage layer 17 .
[0120] In certain embodiments, see Figure 4 (h) Phosphorus ions and boron ions are successively implanted into the trench emitter 7 in the floating P region 10 to form the N region 12 and the source region 11 in the PMOS element, respectively. The above also includes:
[0121] Boron ions are implanted at the trench emitter 7 in the floating P region 10 to form a P region 18 having a doping concentration different from that of the floating P region 10 .
[0122] It should be added that the above-mentioned IGBT may also be an RC-IGBT. The structure of the above-mentioned drift region may be one of the structures such as NPT, PT, SPT or FS. The polysilicon filled in the above-mentioned trench gate 6 and trench emitter 7 may be N-type or P-type.
[0123] In addition, the N+ emitter region 3, the heavily doped P+ region 4 and the P base region 5 in the emitter can be processed and prepared before the trench gate 6 is processed. The processing and preparation of the N-type field stop layer 14 in the above-mentioned preparation method can be carried out before the processing and preparation of the emitter and the PMOS element, or a double-layer epitaxial silicon wafer material having the N-type field stop layer 14 and the N-drift region 13 can be directly selected as the starting silicon wafer material of the preparation method, and the N-type field stop layer 14 can also be formed by replacing the hydrogen implantation method.
[0124] In addition, the electrical properties of each region in the IGBT device in the above scheme are N-type or P-type, which can be interchanged, and adaptive adjustments can be made according to different actual conditions during the preparation process.
[0125] The electronic device in the embodiment of the present application includes the above-mentioned insulated gate bipolar transistor.
[0126] The vehicle in the embodiment of the present application includes the above-mentioned insulated gate bipolar transistor, or includes the above-mentioned electronic device.
[0127] In the description of this specification, the descriptions with reference to the terms "certain embodiments", "in an example", "exemplarily", etc., mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.
[0128] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.
[0129] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.
Claims
1. An insulated gate bipolar transistor, characterized in that: The transistor includes an emitter, a gate, a collector and a conductive region, and the conductive region includes a floating P region and a PMOS element; The gate is provided with a trench gate, and the trench gate extends into the floating P region; The emitter is provided with a trench emitter, the trench emitter extends into the floating P region and has a depth smaller than that of the trench gate; The PMOS element is disposed at the trench emitter to clamp the potential of the floating P region.
2. The insulated gate bipolar transistor according to claim 1, characterized in that: An N+ blocking region is disposed in the conductive region and is distributed at one end of the trench gate extending into the floating P region to suppress hole current of the PMOS element from flowing at the trench gate.
3. The insulated gate bipolar transistor according to claim 1, wherein: The PMOS element includes a source region and an N region, the source region is connected to the emitter, the source region and the N region are sequentially adjacent to each other, and the N region is adjacent to the floating P region.
4. The insulated gate bipolar transistor according to claim 1, wherein: The emitter includes an emitter element and an N+ emitter region, the emitter element and the N+ emitter region are adjacent to each other in sequence, and a first insulating dielectric layer is arranged between the emitter element and the gate.
5. The insulated gate bipolar transistor according to claim 4, characterized in that: The conductive region includes a heavily doped P+ region and a P base region, the emitter element, the N+ emitter region and the heavily doped P+ region are adjacent to each other, and the N+ emitter region, the P base region and the heavily doped P+ region are adjacent to each other.
6. The insulated gate bipolar transistor according to claim 1, wherein: A second insulating dielectric layer is arranged between the trench gate, the conductive region and the emitter.
7. The insulated gate bipolar transistor according to claim 1, wherein: A third insulating dielectric layer is disposed between the trench emitter, the floating P region and the PMOS element.
8. The insulated gate bipolar transistor according to claim 1, wherein: The collector includes a collector element and a P+ collector region, and the collector element and the P+ collector region are adjacent to each other in sequence.
9. The insulated gate bipolar transistor according to claim 8, characterized in that: The conductive region further includes an N-type field stop layer, and the collector element, the P+ collector region, and the N-type field stop layer are adjacent to each other in sequence.
10. The insulated gate bipolar transistor according to claim 8, characterized in that: The conductive region further includes an N-drift region, and the collector, the N-drift region and the floating P region are adjacent to each other in sequence.
11. The insulated gate bipolar transistor according to claim 10, characterized in that: The conductive region further includes a P-base region, and the P-base region, the N-drift region and the trench gate are adjacent to each other.
12. The insulated gate bipolar transistor according to claim 5, characterized in that: The conductive region further includes a CS carrier storage layer adjacent to the P base region, the CS carrier storage layer being configured to enhance conductance modulation during a turn-on phase of the insulated gate bipolar transistor.
13. The insulated gate bipolar transistor according to claim 1, wherein: The PMOS element includes a source region, an N region, and a P region. The source region is connected to the emitter. The source region, the N region, and the P region are adjacent to each other in sequence. The P region is adjacent to the floating P region.
14. A method for preparing an insulated gate bipolar transistor, characterized in that: The method is used to prepare the insulated gate bipolar transistor according to any one of claims 1 to 13, and the method comprises: Taking a silicon wafer having a first doping level to form an N-drift region; The silicon wafer is subjected to photolithography, ion implantation, etching, deposition and / or metallization treatment according to a preset process to form the emitter, the collector, the gate and the conductive region to manufacture the insulated gate bipolar transistor.
15. The method according to claim 14, characterized in that The performing of photolithography, ion implantation, etching, deposition and / or metallization on the silicon wafer according to a preset process to form the emitter, the collector, the gate and the conductive region to manufacture the insulated gate bipolar transistor specifically includes: implanting boron ions into the N-drift region at a predetermined junction depth at a first end of the N-drift region to form an original floating P region; Performing photolithography, filling and etching processes in a preset manner in the original floating P region to form a trench gate and a trench emitter; Performing photolithography at the trench gate, and sequentially injecting phosphorus ions and boron ions into the photolithography area to form an N+ blocking area; Implanting phosphorus ions into the original floating P region at the trench gate to form a floating P region; Performing photolithography at a third preset depth in the N-drift region, implanting boron ions into the photolithography region and annealing to form a P-base region; Performing photolithography in the N-drift region and implanting phosphorus ions into the photolithography region to form an N+ emitter region; Implanting boron ions with a preset concentration into the N-drift region to form a heavily doped P+ region; Depositing phosphosilicate glass in the N-drift region and performing photolithography to form photolithography holes to provide a first insulating dielectric layer within the position range of the floating P region, the emitter, and the gate; Perform ion implantation at the trench emitter in the floating P region in a preset manner to form a PMOS element; Performing metallization at a first end of the N-drift region to form an emitter element; Thinning the silicon wafer at the second end of the N-drift region and implanting phosphorus ions to form an N-type field stop layer; Implanting boron ions into the N-type field stop layer to form a P+ collector region; Metallization is performed at a second end of the N-drift region to form a collector element.
16. The method according to claim 15, characterized in that The method of performing photolithography, filling and etching in a preset manner in the original floating P region to form a trench gate and a trench emitter includes: Photolithography of a first trench at a first preset depth; photolithography a second trench at a second predetermined depth; providing a second insulating dielectric layer for the first trench; providing a third insulating dielectric layer for the second trench; Filling the first trench with polysilicon and performing etching to form the trench gate; The second trench is filled with polysilicon and etched to form the trench emitter.
17. The method according to claim 15, characterized in that The step of performing ion implantation at the trench emitter in the floating P region in a preset manner to form a PMOS element comprises: Phosphorus ions and boron ions are implanted successively at the trench emitter in the floating P region to respectively form an N region and a source region in a PMOS element.
18. The method according to claim 15, characterized in that The method further comprises: performing photolithography at a third preset depth in the N-drift region, implanting boron ions into the photolithography region, and annealing to form a P-base region. Photolithography is performed in the N-drift region, and phosphorus ions are implanted into the photolithography region to form a CS carrier storage layer.
19. The method according to claim 15, characterized in that The step of successively implanting phosphorus ions and boron ions at the trench emitter in the floating P region to form an N region and a source region in the PMOS element, respectively, also includes: Boron ions are implanted at the trench emitter in the floating P region to form a P region with a different doping concentration from that of the floating P region.
20. An electronic device, characterized in that: The electronic device comprises the insulated gate bipolar transistor according to any one of claims 1 to 13.
21. A vehicle, characterized in that: The vehicle comprises the insulated gate bipolar transistor according to any one of claims 1 to 13, or comprises the electronic device according to claim 20.