RC-IGBT device compromising forward and reverse characteristics and preparation method thereof

Abstract

The invention provides an RC-IGBT device compromising forward and reverse characteristics and a preparation method thereof, and relates to the technical field of power semiconductors, the RC-IGBT device comprises an IGBT cellular area, an FRD cellular area and a terminal area which are integrated on the same chip, the FRD cellular area is located on one side of the IGBT cellular area, and the terminal area is located on the periphery of the IGBT cellular area and the periphery of the FRD cellular area; and an IGBT gate PAD region is arranged on one side, far away from the FRD cellular region, in the IGBT cellular region. The beneficial effects are that the FRD cellular area is arranged at one side of the IGBT cellular area, and the layout is easier to design; the IGBT cell area and the FRD cell area are independently designed, forward conduction voltage drop can be reduced by adjusting the IGBT cell area, reverse conduction voltage drop and reverse recovery time can be reduced through front design and local service life control of the FRD cell area, and therefore forward characteristics and reverse characteristics are compromised. And the two share the terminal area without increasing the chip area.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductors, and in particular to an RC-IGBT device with compromised forward and reverse characteristics and a preparation method thereof. Background Art

[0002] As the mainstream power switching device in the field of medium and high power power electronics, IGBT has become one of the most important power semiconductor devices. It is widely used in many fields with good comprehensive performance, such as transportation, motor control, traction drive, smart grid, household appliances, etc. Traditional IGBT cannot conduct in reverse. In practical applications, an additional FRD (Fast Recovery Diode) needs to be connected in anti-parallel to achieve reverse conduction, which increases the cost and volume of the system. With the continuous advancement of IGBT and FRD structures, in order to obtain higher power handling capabilities, IGBT and FRD are monolithically integrated to form RC-IGBT (reverse conducting IGBT, reverse conducting IGBT).

[0003] RC-IGBT integrates IGBT and FRD devices on the same chip, without the need for additional anti-parallel diodes, which can greatly save silicon wafer area. In addition, the monolithic integrated IGBT and FRD share one terminal, especially for high-voltage devices and small single chip area, the junction terminal area is large and the proportion of the active area is relatively small, and its advantages are very obvious. Since the two chips are combined into one die, the packaging processes such as chip bonding and lead sputtering are reduced, and the required DBC (Direct bonding copper) area is also reduced, thereby reducing the packaging cost. Compared with traditional IGBT, RC-IGBT has many advantages such as small size, low cost, high power density, small parasitic inductance, high reliability and simplified process.

[0004] In the prior art, RC-IGBT is based on the IGBT structure, and an N+ collector is added to the back to form a structure in which the P+ collector and the N+ collector are arranged alternately, that is, the IGBT cell region and the FRD cell region are arranged alternately, such as Figure 1 As shown. If the length LN of the N+ collector in this structure is too long, it will cause voltage rebound during the forward conduction of the RC-IGBT device, affecting the current sharing effect when the devices are used in parallel; if the length LN of the N+ collector is too short, the reverse conduction and reverse recovery characteristics will deteriorate. Therefore, how to take into account both the forward and reverse characteristics is a technical problem that needs to be solved urgently. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides an RC-IGBT device with a compromise forward and reverse characteristics, comprising an IGBT cell region, an FRD cell region and a terminal region integrated on the same chip, wherein the FRD cell region is located on one side of the IGBT cell region, and the terminal region is located on the periphery of the IGBT cell region and the FRD cell region; an IGBT gate PAD region is provided on one side of the IGBT cell region away from the FRD cell region; one or more IGBT cells are distributed in the IGBT cell region, and one or more FRD cells are distributed in the FRD cell region.

[0006] Preferably, a planar gate structure is adopted, which includes a substrate, the front side of the substrate is provided with the IGBT cell region and the FRD cell region distributed on the left and right; a P-type semiconductor region is provided in the substrate, an interlayer dielectric layer is formed above the P-type semiconductor region, a continuous first metal layer is formed above the interlayer dielectric layer, and the first metal layer is the emitter metal layer of the IGBT cell region and the anode metal layer of the FRD cell region; wherein an N+ emitter region is provided in the P-type semiconductor region in the IGBT cell region, and a gate oxide layer and a gate are respectively formed in the corresponding interlayer dielectric layer from bottom to top; a back side P+ collector region and a back side N+ cathode region are respectively formed on the back side of the substrate corresponding to the areas where the IGBT cell region and the FRD cell region are located, and a back side metal layer is formed on the side of the back side P+ collector region and the back side N+ cathode region away from the substrate.

[0007] Preferably, a trench gate structure is adopted, and the trench gate structure includes a substrate, and the front side of the substrate is provided with the IGBT cell region and the FRD cell region distributed on the left and right; a P-type semiconductor region is provided in the substrate, and an interlayer dielectric layer is formed above the P-type semiconductor region, and a continuous first metal layer is formed above the interlayer dielectric layer, and the first metal layer is the emitter metal layer of the IGBT cell region and the anode metal layer of the FRD cell region; wherein, an N+ emitter region is provided in the P-type semiconductor region in the IGBT cell region, and a gate oxide layer is formed, and the gate oxide layer is in a trench shape and passes through the N+ emitter region and the P-type semiconductor region in sequence, and a gate is formed in the gate oxide layer; the back side of the substrate corresponds to the area where the IGBT cell region and the FRD cell region are located, and a back side metal layer is formed on the side of the back side P+ collector region and the back side N+ cathode region away from the substrate.

[0008] Preferably, an isolation region is provided between the IGBT cell region and the FRD cell region.

[0009] Preferably, a planar gate structure is adopted, and the planar gate structure includes a substrate, and the front side of the substrate is provided with the IGBT cell region and the FRD cell region distributed on the left and right; a P-type semiconductor region is provided in the substrate, an interlayer dielectric layer is formed above the P-type semiconductor region, and a continuous first metal layer is formed above the interlayer dielectric layer, and the first metal layer is the emitter metal layer of the IGBT cell region and the anode metal layer of the FRD cell region; wherein the P-type semiconductor region in the IGBT cell region is provided with an N+ emitter region, and the corresponding interlayer dielectric layer is provided from bottom to top A gate oxide layer and a gate are formed respectively; at least one P-type isolation ring is also provided in the substrate as the isolation region, which is arranged at the boundary of the IGBT cell region and the FRD cell region, and is located between the P-type semiconductor region in the IGBT cell region and the P-type semiconductor region in the FRD cell region; a back P+ collector region and a back N+ cathode region are formed on the back side of the substrate corresponding to the areas where the IGBT cell region and the FRD cell region are located, and a back metal layer is formed on the side of the back P+ collector region and the back N+ cathode region away from the substrate.

[0010] Preferably, a trench gate structure is adopted, and the trench gate structure includes a substrate, and the front side of the substrate is provided with the IGBT cell region and the FRD cell region distributed on the left and right; a P-type semiconductor region is provided in the substrate, and an interlayer dielectric layer is formed above the P-type semiconductor region; wherein, an N+ emitter region is provided in the P-type semiconductor region in the IGBT cell region, and a gate oxide layer is formed, and the gate oxide layer is in a trench shape and passes through the N+ emitter region and the P-type semiconductor region in sequence, and a gate is formed in the gate oxide layer; a plurality of isolation grooves are formed at the boundaries of the IGBT cell region and the FRD cell region as the isolation region; a back side P+ collector region and a back side N+ cathode region are respectively formed on the back side of the substrate corresponding to the areas where the IGBT cell region and the FRD cell region are located, and a back side metal layer is formed on the side of the back side P+ collector region and the back side N+ cathode region away from the substrate.

[0011] Preferably, a continuous first metal layer is formed above the interlayer dielectric layer, and the first metal layer is an emitter metal layer of the IGBT cell region and an anode metal layer of the FRD cell region.

[0012] Preferably, an emitter metal layer is formed above the interlayer dielectric layer in the IGBT cell region, an anode metal layer is formed above the interlayer dielectric layer in the FRD cell region, and the emitter metal layer and the anode metal layer are connected via a jumper wire.

[0013] The present invention also provides a method for preparing an RC-IGBT device with a compromise between forward and reverse characteristics, which is used to prepare the above-mentioned RC-IGBT device, comprising: step S1, forming a gate of an IGBT cell region on one side of a substrate, and then using the region where the gate is located as a barrier layer, and forming a plurality of P-type semiconductor regions distributed in the IGBT cell region and the FRD cell region on the front side of the substrate by P-type implantation; step S2, performing photolithography to form an N+ ion implantation region in the P-type semiconductor region of the IGBT cell region and performing N-type ion implantation to form an N+ emitter region; step S3, depositing a N+ ion implantation region on the top of the substrate; and step S4, depositing a N+ ion implantation region on the top of the substrate. An interlayer dielectric layer is stacked, and then metal holes are formed on the interlayer dielectric layer by photolithography and metal is sputtered to form an emitter metal layer of the IGBT cell region and an anode metal layer of the FRD cell region; Step S4, after thinning the back side of the substrate, P+ collector region injection is performed on the back side of the IGBT cell region of the substrate, and N+ cathode region injection is performed on the back side of the FRD cell region; Step S5, gold plating is performed on the back side of the P+ collector region and the N+ cathode region to form a back metal layer, and the collector of the IGBT cell region and the cathode of the FRD cell region are led out from the back metal layer.

[0014] The present invention also provides a method for preparing an RC-IGBT device with a compromise forward and reverse characteristics, which is used to prepare the above-mentioned RC-IGBT device with an isolation region, comprising: step S1, forming a gate of an IGBT cell region on one side of a substrate, and forming an isolation region at the boundary between the IGBT cell region and the FRD cell region, and then using the region where the gate is located as a barrier layer, forming a plurality of P-type semiconductor regions distributed in the IGBT cell region and the FRD cell region on the front side of the substrate by P-type implantation; step S2, performing photolithography to form an N+ ion implantation region in the P-type semiconductor region of the IGBT cell region and performing N-type ion implantation to form an N+ emitter region; step S3, depositing an interlayer dielectric layer above the substrate, then photolithographically forming metal holes on the interlayer dielectric layer and sputtering metal to form an emitter metal layer of the IGBT cell region and an anode metal layer of the FRD cell region; step S4, after thinning the back side of the substrate, respectively injecting P+ collector region into the IGBT cell region on the back side of the substrate, and injecting N+ cathode region into the FRD cell region on the back side; step S5, gold-plating the back sides of the P+ collector region and the N+ cathode region to form a back metal layer, and the collector of the IGBT cell region and the cathode of the FRD cell region are led out from the back metal layer.

[0015] The above technical solution has the following advantages or beneficial effects: 1) The FRD cell area is set on one side of the IGBT cell area, making the layout easier to design; 2) The FRD cell area and the IGBT cell area are designed independently. The forward conduction voltage drop can be reduced by adjusting the IGBT cell area. The reverse conduction voltage drop and reverse recovery time can also be reduced by the positive design of the FRD cell area and the local life control, thereby compromising the forward and reverse characteristics. 3) The IGBT cell area and the FRD cell area share the terminal area, which will not increase the chip area; 4) Compared with the traditional structure, under the condition of the same chip area, it can not only suppress the voltage rebound phenomenon of forward conduction, but also greatly shorten the reverse recovery time, thereby improving the current sharing ability of the chip in parallel and reducing the switching loss; 5) The IGBT cell area and the FRD cell area are distributed separately, and the areas of the IGBT cell area and the FRD cell area can be adjusted separately according to the current level requirements of the end customers. Because the cell areas of the two devices are set independently, it is relatively easy to implement in design, and no additional process steps are required in process implementation. The forward characteristics are adjusted through the IGBT cell area, and the reverse characteristics are adjusted through the FRD cell area. The reverse characteristics are generally achieved through life control. If the life of the chip as a whole is controlled, it will affect the forward characteristics of the IGBT cell area. Therefore, the FRD cell area is locally controlled in terms of life. Since the FRD cell areas are concentrated together, the process of local life control is easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of the structure in which the IGBT cell area and the FRD cell area are alternately arranged in the traditional structure; Figure 2 This is a schematic diagram of a layout design of an RC-IGBT device with compromised forward and reverse characteristics in Embodiment 1 of the present invention; Figure 3 It is a schematic diagram of a planar gate structure of an RC-IGBT device that compromises forward and reverse characteristics in Embodiment 1 of the present invention; Figure 4 A schematic diagram of a trench gate structure of an RC-IGBT device with compromised forward and reverse characteristics in Embodiment 1 of the present invention; Figure 5 It is a schematic flow chart of a method for preparing an RC-IGBT device with compromised forward and reverse characteristics in Example 1 of the present invention; Figure 6 It is a schematic diagram of a gate formed when a planar gate structure is adopted in the preparation method of Example 1 of the present invention; Figure 7 It is a schematic diagram of a gate formed when a trench gate structure is adopted in the preparation method of Example 1 of the present invention; Figure 8It is a schematic diagram of a P-type semiconductor region and an N+ emitter region formed in a substrate in the preparation method of Example 1 of the present invention; Fig. 9 It is a schematic structural diagram of forming a first metal layer in the preparation method of Example 1 of the present invention; Fig.10 A schematic diagram of a layout design of an RC-IGBT device with compromised forward and reverse characteristics in Embodiment 2 of the present invention; Fig.11 A schematic diagram of a planar gate structure of an RC-IGBT device that compromises forward and reverse characteristics in Embodiment 2 of the present invention; Fig.12 A schematic diagram of a trench gate structure of an RC-IGBT device with compromised forward and reverse characteristics in Embodiment 2 of the present invention; Fig.13 This is a schematic diagram of a structure in which an emitter metal layer and an anode metal layer are connected via a jumper wire in Embodiment 2 of the present invention; Fig.14 It is a schematic flow chart of a method for preparing an RC-IGBT device with compromised forward and reverse characteristics in Example 2 of the present invention.

[0017] In the attached drawings: 1. terminal region; 2. IGBT cell region; 3. FRD cell region; 4. IGBT gate PAD region; 5. isolation region; 6. substrate; 7. P-type semiconductor region; 8. N+ emitter region; 9. gate oxide layer; 10. gate; 11. interlayer dielectric layer; 12. first metal layer; 13. back N+ cathode region; 14. back P+ collector region; 15. isolation groove; 16. P-type isolation ring; 17. back metal layer; 18. FRD cell region anode metal region; 19. IGBT cell region emitter metal region; 20. IGBT cell region gate metal region; 21. jumper. DETAILED DESCRIPTION

[0018] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment, and other embodiments may also fall within the scope of the present invention as long as they conform to the gist of the present invention.

[0019] Example 1 In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a RC-IGBT device with a compromise between forward and reverse characteristics is provided. Figure 2As shown, it includes an IGBT cell region 2, an FRD cell region 3 and a terminal region 1 integrated on the same chip, the FRD cell region 3 is located on one side of the IGBT cell region 2, and the terminal region 1 is located on the periphery of the IGBT cell region 2 and the FRD cell region 3; an IGBT gate PAD region 4 is provided on the side of the IGBT cell region 2 away from the FRD cell region 3; one or more IGBT cells are distributed in the IGBT cell region 2, and one or more FRD cells are distributed in the FRD cell region.

[0020] Specifically, in this embodiment, the IGBT cell area 2 and the FRD cell area 3 in the RC-IGBT device of the present invention that compromises forward and reverse characteristics are designed as left and right structures, rather than being arranged alternately. The IGBT cell area 2 and the FRD cell area 3 are designed separately, that is, when there are multiple IGBT devices and multiple FRD devices on the same chip, the IGBT cells of each IGBT device are concentrated in the IGBT cell area 2, and the FRD cells of each FRD device are concentrated in the FRD cell area 3. Therefore, the compromise between the forward and reverse characteristics can be achieved by adjusting the IGBT cell area 2 or the FRD cell area 3. In the case of the same chip area, this structure can not only suppress the voltage rebound phenomenon of forward conduction, but also greatly shorten the reverse recovery time, thereby improving the current sharing capability of the chip in parallel, and can also reduce the switching loss.

[0021] The RC-IGBT device with compromised forward and reverse characteristics of the present invention can adopt a planar gate structure. The cross-sectional schematic diagram of the planar gate structure is shown in FIG. Figure 3 As shown, it includes a substrate 6, and the front side of the substrate 6 is provided with an IGBT cell region 2 and an FRD cell region 3 distributed on the left and right; a P-type semiconductor region 7 is provided in the substrate 6, an interlayer dielectric layer 11 is formed above the P-type semiconductor region 7, and a continuous first metal layer 12 is formed above the interlayer dielectric layer 11, and the first metal layer 12 is the emitter metal layer of the IGBT cell region 2 and the anode metal layer of the FRD cell region 3; wherein, an N+ emitter region 8 is provided in the P-type semiconductor region 7 in the IGBT cell region 2, and a gate oxide layer 9 and a gate electrode 10 are respectively formed in the corresponding interlayer dielectric layer 11 from bottom to top; a back side P+ collector region 14 and a back side N+ cathode region 13 are respectively formed on the back side of the substrate 6 corresponding to the areas where the IGBT cell region 2 and the FRD cell region 3 are located, and a back side metal layer 17 is formed on the side of the back side P+ collector region 14 and the back side N+ cathode region 13 away from the substrate 6.

[0022] Specifically, in this embodiment, the substrate 6 is preferably an N-substrate, which has a P-type semiconductor region 7 built therein, and the ions injected into the P-type semiconductor region 7 are boron. An N+ emitter region 8 is provided on the upper surface of the P-type semiconductor region 7 to form the emitter of the IGBT cell region 2; the N+ emitter region 8 is not provided in the P-type semiconductor region 7 to form the anode of the FRD cell region 3. The emitter metal layer of the IGBT cell region 2 is shared with the anode metal layer of the FRD cell region 3.

[0023] A gate oxide layer 9 and a polysilicon layer are arranged from bottom to top on the upper surface of the P-type semiconductor region 7, and the gate oxide layer 9 and the polysilicon layer partially cover the upper surface of the P-type semiconductor region 7 to form a gate 10 of the IGBT cell region 2; a P+ collector region 14 is provided on the back of the IGBT cell region 2 to form a collector of the IGBT cell region 2. An N+ cathode region 13 is provided on the back of the FRD cell region 3 to form a cathode of the FRD cell region 3. The collector metal layer of the IGBT cell region 2 is shared with the cathode metal layer of the FRD cell region 3.

[0024] The RC-IGBT device with compromised forward and reverse characteristics of the present invention can adopt a trench gate structure. The cross-sectional schematic diagram of the trench gate structure is shown in FIG. Figure 4 As shown, it includes a substrate 6, and the front side of the substrate 6 is provided with an IGBT cell region 2 and an FRD cell region 3 distributed on the left and right; a P-type semiconductor region 7 is provided in the substrate 6, an interlayer dielectric layer 11 is formed above the P-type semiconductor region 7, and a continuous first metal layer 12 is formed above the interlayer dielectric layer 11, and the first metal layer 12 is the emitter metal layer of the IGBT cell region 2 and the anode metal layer of the FRD cell region 3; wherein, an N+ emitter region 8 is provided in the P-type semiconductor region 7 in the IGBT cell region 2, and a gate oxide layer 9 is formed, the gate oxide layer 9 is in a groove type and passes through the N+ emitter region 8 and the P-type semiconductor region 7 in sequence, and a gate 10 is formed in the gate oxide layer 9; a back side P+ collector region 14 and a back side N+ cathode region 13 are respectively formed on the back side of the substrate 6 corresponding to the areas where the IGBT cell region 2 and the FRD cell region 3 are located, and a back side metal layer 17 is formed on the side of the back side P+ collector region 14 and the back side N+ cathode region 13 away from the substrate 6.

[0025] Specifically, in this embodiment, the substrate 6 is preferably an N-substrate, which has a P-type semiconductor region 7 built therein, and the ions injected into the P-type semiconductor region 7 are boron. An N+ emitter region 8 is provided on the upper surface of the P-type semiconductor region 7 to form the emitter of the IGBT cell region 2; the N+ emitter region 8 is not provided in the P-type semiconductor region 7 to form the anode of the FRD cell region 3. The emitter metal layer of the IGBT cell region 2 is shared with the anode metal layer of the FRD cell region 3.

[0026] A trench structure is provided between the P-type semiconductor regions 7 of the IGBT cell region 2, in which a gate oxide layer 9 and a polysilicon layer are provided from bottom to top to form a gate 10 of the IGBT cell region 2; the trench design between the P-type semiconductor regions 7 of the FRD cell region 3 can be selected according to requirements.

[0027] The back side of the IGBT cell region 2 has a P+ collector region 14, which forms the collector of the IGBT cell region 2. The back side of the FRD cell region 3 has an N+ cathode region 13, which forms the cathode of the FRD cell region 3. The collector metal layer of the IGBT cell region 2 is shared with the cathode metal layer of the FRD cell region 3.

[0028] In this embodiment 1, the preparation method of the RC-IGBT device with compromised forward and reverse characteristics is as follows: Figure 5 As shown, the following steps are included: Step S1, forming a gate of an IGBT cell region on one side of the substrate, and then using the region where the gate is located as a barrier layer, forming a plurality of P-type semiconductor regions distributed in the IGBT cell region and the FRD cell region on the front side of the substrate by P-type implantation; wherein, according to the electrical performance requirements of the IGBT device, the crystal orientation is selected as <100> The N-substrate 6 has a resistivity of 200Ω*cm~250Ω*cm and a thickness of 500um~600um. After the substrate is selected, a local oxidation process is first performed on the N-substrate 6 to achieve LOCOS local oxidation isolation, and the thickness of the oxide layer is about 15000 angstroms~18000 angstroms.

[0029] Further, a gate oxide layer 9 is grown on the N-substrate 6, and a polysilicon layer is deposited thereon. The gate oxide layer 9 has a thickness of 1000 angstroms to 1500 angstroms, and the polysilicon layer has a thickness of 7000 angstroms to 12000 angstroms. The gate region is defined by a photolithography process using a gate photomask, and then the excess gate oxide layer 9 and polysilicon layer are removed by an etching process to form a gate 10 of the IGBT cell region 2, as shown in FIG. Figure 6 As shown in the figure, the trench structure is different from the planar structure in that a trench is first formed on the N-substrate 6, the depth of the trench is generally 4um~6um, and then a gate oxide layer 9 is grown and a polysilicon layer is deposited. After the polysilicon layer is etched back, the gate 10 of the IGBT cell region 2 is formed, as shown in FIG. Figure 7 shown.

[0030] Subsequently, the gate region of the IGBT cell region 2 is formed as a barrier layer, and a P-type semiconductor region is formed by P-type ion boron. The injection concentration of the P-type semiconductor region is 3.0E+13cm-2~4.5 E+13cm-2, and the injection energy is 50KeV~80KeV.

[0031] Step S2, photolithography is performed in the P-type semiconductor region of the IGBT cell region to form an N+ ion implantation region and perform N-type ion implantation to form an N+ emitter region; wherein, in the P-type semiconductor region 7 of the IGBT cell region 2, an N+ ion implantation region is formed by a self-aligned photolithography process using an N+ photomask, and N-type ions are implanted therein to form an N+ emitter region 8, which is the emitter of the IGBT cell region 2. The P-type semiconductor region 7 of the FRD cell region 3 can be completed simultaneously with the P-type semiconductor region 7 of the IGBT cell region 2, or can be formed by a separate process, such as Figure 8 As shown; Step S3, depositing an interlayer dielectric layer on the substrate, then photolithographically forming metal holes on the interlayer dielectric layer and sputtering metal to form an emitter metal layer of the IGBT cell region and an anode metal layer of the FRD cell region; wherein, an emitter metal contact hole is formed using a contact hole photomask, and metal AlSiCu or AlCu is sputtered with a thickness of 2.5um to 6um to form a first metal layer 12, i.e., the emitter metal layer of the IGBT cell region 2 and the anode metal layer of the FRD cell region 3, such as Fig. 9 shown.

[0032] Step S4, after thinning the back side of the substrate, respectively perform P+ collector region injection on the IGBT cell region on the back side of the substrate, and perform N+ cathode region injection on the FRD cell region on the back side; wherein, the back side of the wafer is thinned by the back side thinning process, and the thickness after thinning is 480um~550um. After the thinning process, the IGBT cell region 2 is injected with P+ collector region, and the FRD cell region 3 is injected with N+ cathode region.

[0033] Step S5, gold-plating the back of the P+ collector region and the N+ cathode region to form a back metal layer, and the collector of the IGBT cell region and the cathode of the FRD cell region are led out from the back metal layer.

[0034] The back of the wafer is plated with gold. The materials used for the gold plating are Ti / Ni / Ag. The thicknesses of the materials are 1 / 3 / 10 kiloangstroms respectively. The collector of the IGBT cell area 2 and the cathode of the FRD cell area 3 are led out from the metal layer on the back of the wafer. Figure 3 shown.

[0035] Example 2 In this embodiment, based on the structure of embodiment 1, Fig.10 As shown, an isolation region 5 is provided between the IGBT cell region 2 and the FRD cell region 3 .

[0036] Specifically, different from Example 1, an isolation region 5 is set between the IGBT cell region 2 and the FRD cell region 3 in the RC-IGBT device with compromise forward and reverse characteristics in this embodiment. The isolation region 5 is used for large current devices to prevent device damage due to current mismatch between the two IGBT cell regions 2 and the FRD cell region 3.

[0037] The RC-IGBT device of the present invention with compromised forward and reverse characteristics can be used as follows Fig.11 The planar gate structure shown in the figure comprises a substrate 6, and an IGBT cell region 2 and an FRD cell region 3 are arranged on the front of the substrate 6. A P-type semiconductor region 7 is arranged in the substrate 6, and an interlayer dielectric layer 11 is formed above the P-type semiconductor region 7. A continuous first metal layer 12 is formed above the interlayer dielectric layer 11, and the first metal layer 12 is an emitter metal layer of the IGBT cell region 2 and an anode metal layer of the FRD cell region 3. Among them, an N+ emitter region 8 is arranged in the P-type semiconductor region 7 in the IGBT cell region 2, and the corresponding interlayer dielectric layer 11 is respectively formed from bottom to top. A gate oxide layer 9 and a gate electrode 10 are formed in the substrate 6; at least one P-type isolation ring 16 is also provided in the substrate 6 as an isolation region 5, which is arranged at the boundary between the IGBT cell region 2 and the FRD cell region 3, and is located between the P-type semiconductor region 7 in the IGBT cell region 2 and the P-type semiconductor region 7 in the FRD cell region 3; a back side P+ collector region 14 and a back side N+ cathode region 13 are respectively formed on the back side of the substrate 6 corresponding to the areas where the IGBT cell region 2 and the FRD cell region 3 are located, and a back side metal layer 17 is formed on the side of the back side P+ collector region 14 and the back side N+ cathode region 13 away from the substrate 6.

[0038] Specifically, in this embodiment, the terminal area is mainly composed of a P-Ring field limiting ring, a field plate and a cut-off ring. The P-Ring field limiting ring is a P-type field ring, and the field plate is composed of a Poly field plate and a metal field plate, which are completed simultaneously with the Poly layer and the metal layer process; the cut-off ring is composed of a P-type semiconductor region, an N+ emitter region and a metal layer. The number of P-type field rings is mainly determined by the voltage resistance requirements of the device. The higher the voltage resistance, the more P-type field rings there are and the larger the area of ​​the terminal.

[0039] The above-mentioned P-type isolation ring 16 is formed simultaneously with the P-Ring field limiting ring of the terminal area 1, and no additional process is required. The number of P-type isolation rings 16 is ≥1, but the structure of the P-type isolation ring 16 is different from that of the terminal area 1. Under general applications, the number of P-type isolation rings is less than that of the terminal area, and the structure is relatively simpler than the terminal structure, the process is easy to implement, and the area of ​​the P-type isolation ring is much smaller than that of the terminal area, which relatively saves chip area.

[0040] The RC-IGBT device of the present invention with compromised forward and reverse characteristics can be used as follows Fig.12The trench gate structure shown in the figure comprises a substrate 6, and an IGBT cell region 2 and an FRD cell region 3 are arranged on the front side of the substrate 6 and are distributed on the left and right sides; a P-type semiconductor region 7 is arranged in the substrate 6, and an interlayer dielectric layer 11 is formed above the P-type semiconductor region 7; wherein, an N+ emitter region 8 is arranged in the P-type semiconductor region 7 in the IGBT cell region 2, and a gate oxide layer 9 is formed, and the gate oxide layer 9 is in a trench shape and passes through the N+ emitter region 8 and the P-type semiconductor region 7 in sequence, and a gate 10 is formed in the gate oxide layer 9; a plurality of isolation grooves 15 are formed at the boundaries of the IGBT cell region 2 and the FRD cell region 3 as isolation regions 5; a back P+ collector region 14 and a back N+ cathode region 13 are respectively formed on the back side of the substrate 6 corresponding to the areas where the IGBT cell region 2 and the FRD cell region 3 are located, and a back metal layer 17 is formed on the side of the back P+ collector region 14 and the back N+ cathode region 13 away from the substrate 6.

[0041] Specifically, in this embodiment, the isolation trench 15 and the trench-type gate are formed simultaneously, and ≥1 isolation trench 15 is provided.

[0042] Furthermore, since the isolation region 5 is provided between the IGBT cell region 2 and the FRD cell region 3, the metal layer above the isolation region 5 may or may not be provided according to design requirements. Therefore, if the isolation region is designed with a metal layer, a continuous first metal layer 12 is formed above the interlayer dielectric layer 11, and the first metal layer 12 is the emitter metal layer of the IGBT cell region 2 and the anode metal layer of the FRD cell region 3, that is, the emitter metal layer of the IGBT cell region 2 and the anode metal layer of the FRD cell region 3 are shared.

[0043] If the isolation region does not need to design a metal layer, an emitter metal layer 19 is formed on the interlayer dielectric layer 11 of the IGBT cell region 2, and an anode metal layer 18 is formed on the interlayer dielectric layer 11 of the FRD cell region 3. The emitter metal layer 19 and the anode metal layer 18 are connected by a jumper 21, that is, the emitter metal layer of the IGBT cell region 2 and the anode metal layer of the FRD cell region 3 are independently designed, wherein the IGBT cell region gate metal region 20 is located in the IGBT gate PAD region 4. However, during packaging, a common electrode can be achieved by wire bonding (the number of jumpers 21 is selected according to the actual application), such as Fig.13 shown.

[0044] In this embodiment, a method for preparing a RC-IGBT device with a compromise between forward and reverse characteristics is as follows: Fig.14As shown, the method comprises the following steps: step S1, forming a gate of an IGBT cell region on one side of a substrate, and forming an isolation region at the boundary between the IGBT cell region and the FRD cell region, and then using the region where the gate is located as a barrier layer, forming a plurality of P-type semiconductor regions distributed in the IGBT cell region and the FRD cell region on the front side of the substrate by P-type implantation; step S2, performing photolithography to form an N+ ion implantation region in the P-type semiconductor region of the IGBT cell region and performing N-type ion implantation to form an N+ emitter region; step S3, depositing a layer on the upper side of the substrate An interlayer dielectric layer is formed, and then metal holes are formed on the interlayer dielectric layer by photolithography and metal is sputtered to form an emitter metal layer of the IGBT cell region and an anode metal layer of the FRD cell region; step S4, after thinning the back side of the substrate, the P+ collector region of the IGBT cell region on the back side of the substrate is injected, and the N+ cathode region of the FRD cell region on the back side is injected; step S5, the back side of the P+ collector region and the N+ cathode region are gold-plated to form a back metal layer, and the collector of the IGBT cell region and the cathode of the FRD cell region are led out from the back metal layer.

[0045] It can be seen that the overall steps are basically the same as those in Example 1. The difference is that an isolation region is formed at the boundary between the IGBT cell region and the FRD cell region. When the isolation region is a P-type isolation ring, it is formed simultaneously with the P-Ring field limiting ring of the terminal region. When the isolation region is an isolation groove, it is formed simultaneously with the trench-type gate. The remaining steps will not be repeated.

[0046] The present invention is mainly applied to high voltage and high current RC-IGBT devices, wherein the structure of the power RC-IGBT device is not limited to the structure mentioned in the present invention, and may also be a super junction IGBT and the like.

[0047] The above description is only a preferred embodiment of the present invention, and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the contents of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. An RC-IGBT device with compromised forward and reverse characteristics, characterized in that: It includes an IGBT cell region, an FRD cell region and a terminal region integrated on the same chip, wherein the FRD cell region is located on one side of the IGBT cell region, and the terminal region is located on the periphery of the IGBT cell region and the FRD cell region; an IGBT gate PAD region is provided on one side of the IGBT cell region away from the FRD cell region; one or more IGBT cells are distributed in the IGBT cell region, and one or more FRD cells are distributed in the FRD cell region.

2. The RC-IGBT device according to claim 1, characterized in that: A planar gate structure is adopted, and the planar gate structure includes a substrate, and the front side of the substrate is provided with the IGBT cell region and the FRD cell region distributed on the left and right; a P-type semiconductor region is provided in the substrate, an interlayer dielectric layer is formed above the P-type semiconductor region, and a continuous first metal layer is formed above the interlayer dielectric layer, and the first metal layer is the emitter metal layer of the IGBT cell region and the anode metal layer of the FRD cell region; wherein, an N+ emitter region is provided in the P-type semiconductor region in the IGBT cell region, and a gate oxide layer and a gate are respectively formed in the corresponding interlayer dielectric layer from bottom to top; a back side P+ collector region and a back side N+ cathode region are respectively formed on the back side of the substrate corresponding to the areas where the IGBT cell region and the FRD cell region are located, and a back side metal layer is formed on the side of the back side P+ collector region and the back side N+ cathode region away from the substrate.

3. The RC-IGBT device according to claim 1, characterized in that: A trench gate structure is adopted, and the trench gate structure includes a substrate, and the front side of the substrate is provided with the IGBT cell region and the FRD cell region distributed on the left and right; a P-type semiconductor region is provided in the substrate, an interlayer dielectric layer is formed above the P-type semiconductor region, and a continuous first metal layer is formed above the interlayer dielectric layer, and the first metal layer is the emitter metal layer of the IGBT cell region and the anode metal layer of the FRD cell region; wherein, an N+ emitter region is provided in the P-type semiconductor region in the IGBT cell region, and a gate oxide layer is formed, the gate oxide layer is in a trench shape and passes through the N+ emitter region and the P-type semiconductor region in sequence, and a gate is formed in the gate oxide layer; a back P+ collector region and a back N+ cathode region are respectively formed on the back side of the substrate corresponding to the areas where the IGBT cell region and the FRD cell region are located, and a back metal layer is formed on the side of the back P+ collector region and the back N+ cathode region away from the substrate.

4. The RC-IGBT device according to claim 1, characterized in that: An isolation region is provided between the IGBT cell region and the FRD cell region.

5. The RC-IGBT device according to claim 4, characterized in that: A planar gate structure is adopted, and the planar gate structure includes a substrate, and the front side of the substrate is provided with the IGBT cell region and the FRD cell region distributed on the left and right; a P-type semiconductor region is provided in the substrate, an interlayer dielectric layer is formed above the P-type semiconductor region, and a continuous first metal layer is formed above the interlayer dielectric layer, and the first metal layer is an emitter metal layer of the IGBT cell region and an anode metal layer of the FRD cell region; wherein the P-type semiconductor region in the IGBT cell region is provided with an N+ emitter region, and the corresponding interlayer dielectric layer is respectively provided with an N+ emitter region from bottom to top. A gate oxide layer and a gate are formed; at least one P-type isolation ring is also provided in the substrate as the isolation region, which is arranged at the boundary of the IGBT cell region and the FRD cell region and is located between the P-type semiconductor region in the IGBT cell region and the P-type semiconductor region in the FRD cell region; a back P+ collector region and a back N+ cathode region are respectively formed on the back side of the substrate corresponding to the areas where the IGBT cell region and the FRD cell region are located, and a back metal layer is formed on the side of the back P+ collector region and the back N+ cathode region away from the substrate.

6. The RC-IGBT device according to claim 4, characterized in that: A trench gate structure is adopted, and the trench gate structure includes a substrate, the front side of the substrate is provided with the IGBT cell region and the FRD cell region distributed on the left and right; a P-type semiconductor region is provided in the substrate, and an interlayer dielectric layer is formed above the P-type semiconductor region; wherein, an N+ emitter region is provided in the P-type semiconductor region in the IGBT cell region, and a gate oxide layer is formed, the gate oxide layer is in a trench shape and passes through the N+ emitter region and the P-type semiconductor region in sequence, and a gate is formed in the gate oxide layer; a plurality of isolation grooves are formed at the boundaries of the IGBT cell region and the FRD cell region as the isolation region; a back P+ collector region and a back N+ cathode region are respectively formed on the back side of the substrate corresponding to the areas where the IGBT cell region and the FRD cell region are located, and a back metal layer is formed on the side of the back P+ collector region and the back N+ cathode region away from the substrate.

7. The RC-IGBT device according to claim 6, characterized in that: A continuous first metal layer is formed above the interlayer dielectric layer, and the first metal layer is an emitter metal layer of the IGBT cell region and an anode metal layer of the FRD cell region.

8. The RC-IGBT device according to claim 6, characterized in that: An emitter metal layer is formed above the interlayer dielectric layer in the IGBT cell region, and an anode metal layer is formed above the interlayer dielectric layer in the FRD cell region. The emitter metal layer and the anode metal layer are connected via a jumper wire.

9. A method for preparing a RC-IGBT device with a compromise between forward and reverse characteristics, characterized in that: For preparing the RC-IGBT device as claimed in any one of claims 1 to 3, comprising: step S1, forming a gate of an IGBT cell region on one side of a substrate, and then using the region where the gate is located as a barrier layer, and forming a plurality of P-type semiconductor regions distributed in the IGBT cell region and the FRD cell region on the front side of the substrate by P-type implantation; step S2, performing photolithography to form an N+ ion implantation region in the P-type semiconductor region of the IGBT cell region and performing N-type ion implantation to form an N+ emitter region; step S3, depositing an interlayer dielectric layer above the substrate, and then Metal holes are formed on the interlayer dielectric layer by photolithography and metal is sputtered to form an emitter metal layer of the IGBT cell region and an anode metal layer of the FRD cell region; step S4, after thinning the back side of the substrate, P+ collector region injection is performed on the IGBT cell region on the back side of the substrate, and N+ cathode region injection is performed on the FRD cell region on the back side; step S5, gold plating is performed on the back sides of the P+ collector region and the N+ cathode region to form a back metal layer, and the collector of the IGBT cell region and the cathode of the FRD cell region are led out from the back metal layer.

10. A method for preparing a RC-IGBT device with compromised forward and reverse characteristics, characterized in that: The method for preparing an RC-IGBT device as claimed in any one of claims 4 to 8 comprises: step S1, forming a gate of an IGBT cell region on one side of a substrate, and forming an isolation region at the boundary between the IGBT cell region and the FRD cell region, and then using the region where the gate is located as a barrier layer, and forming a plurality of P-type semiconductor regions distributed in the IGBT cell region and the FRD cell region on the front side of the substrate by P-type implantation; step S2, performing photolithography to form an N+ ion implantation region in the P-type semiconductor region of the IGBT cell region and performing N-type ion implantation to form an N+ emitter region; step S3, forming an N+ ion implantation region on the substrate; and An interlayer dielectric layer is deposited above the bottom, and then metal holes are formed by photolithography on the interlayer dielectric layer and metal is sputtered to form an emitter metal layer of the IGBT cell region and an anode metal layer of the FRD cell region; step S4, after thinning the back side of the substrate, the P+ collector region of the IGBT cell region on the back side of the substrate is injected, and the N+ cathode region of the FRD cell region on the back side is injected; step S5, gold-plating the back sides of the P+ collector region and the N+ cathode region to form a back metal layer, and the collector of the IGBT cell region and the cathode of the FRD cell region are led out from the back metal layer.

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