Semiconductor discharge tube and preparation method thereof

Abstract

The invention discloses a semiconductor discharge tube and a preparation method thereof. The semiconductor discharge tube comprises an N-type substrate which comprises a first surface and a second surface which are opposite to each other; the first P-type doped region, the second P-type doped region, the third P-type doped region and the N-type emitter region are located on one side of the first surface and one side of the second surface; the orthographic projection of the N-type emitter region on the N-type substrate is not overlapped with the orthographic projection of the third P-type doped region on the N-type substrate; the first P-type doped region, the second P-type doped region, the third P-type doped region and the N-type emitter region which are located on the first surface are symmetrical about the center of the N-type substrate respectively with the first P-type doped region, the second P-type doped region, the third P-type doped region and the N-type emitter region which are located on the second surface; wherein the orthographic projection of the third P-type doped region on the N-type substrate covers at least part of the orthographic projection of the first P-type doped region on the N-type substrate. According to the embodiment of the invention, the through-current capability of the semiconductor discharge tube can be improved, and the overvoltage protection capability is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor discharge tube and a preparation method thereof. Background Art

[0002] The semiconductor discharge tube is an overvoltage protection device. When the voltage exceeds the avalanche voltage of the semiconductor discharge tube, the semiconductor discharge tube will clamp the transient voltage within the transition voltage; when the voltage continues to increase, the semiconductor discharge tube enters the conduction state due to the negative resistance effect, and can discharge a large surge current or pulse current. When using a semiconductor discharge tube, the semiconductor discharge tube can be connected in parallel at both ends of the device, and within its breakdown voltage range, it plays a role in protecting the subsequent power receiving equipment. The current carrying capacity of the semiconductor discharge tube determines its overvoltage protection capability for the equipment. Summary of the invention

[0003] The present invention provides a semiconductor discharge tube and a preparation method thereof, so as to improve the current carrying capacity of the semiconductor discharge tube and enhance the overvoltage protection capability.

[0004] According to one aspect of the present invention, there is provided a semiconductor discharge tube, comprising:

[0005] An N-type substrate including a first surface and a second surface opposite to each other;

[0006] The first P-type doping region, the second P-type doping region, the third P-type doping region and the N-type emitter region are all located on one side of the first surface and one side of the second surface; wherein the second P-type doping region is located on a side of the first P-type doping region away from the N-type substrate, and the second P-type doping region is connected to the N-type substrate; the third P-type doping region and the N-type emitter region are located inside the second P-type doping region and away from a side of the first P-type doping region;

[0007] The orthographic projection of the N-type emitter region on the N-type substrate does not overlap with the orthographic projection of the third P-type doped region on the N-type substrate; the first P-type doped region, the second P-type doped region, the third P-type doped region, and the N-type emitter region located on the first surface are symmetrical with the first P-type doped region, the second P-type doped region, the third P-type doped region, and the N-type emitter region located on the second surface, respectively, about the center of the N-type substrate;

[0008] The orthographic projection of the third P-type doping region on the N-type substrate covers at least a portion of the orthographic projection of the first P-type doping region on the N-type substrate.

[0009] Optionally, an orthographic projection of the third P-type doping region on the N-type substrate completely overlaps with an orthographic projection of the first P-type doping region on the N-type substrate.

[0010] Optionally, the doping concentration of the third P-type doping region is much greater than the doping concentration of the first P-type doping region.

[0011] Optionally, a first preset depth exists between a side of the first P-type doping region close to the N-type substrate and a side of the second P-type doping region close to the N-type substrate;

[0012] A second preset depth exists between a side of the second P-type doping region close to the N-type substrate and a side of the third P-type doping region close to the N-type substrate;

[0013] The third P-type doping region has a third preset depth;

[0014] The first preset depth is greater than the second preset depth, and the second preset depth is greater than the third preset depth.

[0015] Optionally, the first preset depth ranges from 30 to 50 μm;

[0016] The second preset depth ranges from 15 to 30 μm;

[0017] The third preset depth ranges from 5 to 10 μm.

[0018] Optionally, a center position of the N-type emitter region located on the first surface corresponds to a center position of the first P-type doping region located on the second surface;

[0019] Along a thickness direction perpendicular to the N-type substrate, the N-type emitter region includes at least three sub-N-type emitter regions, and the sub-N-type emitter regions are arranged at intervals.

[0020] Optionally, the semiconductor discharge tube further comprises: an inner groove, wherein the inner wall of the inner groove is provided with a passivation layer;

[0021] In a thickness direction perpendicular to the N-type substrate, the inner groove is disposed on both sides of the second P-type doping region located on the first surface; and the inner groove is disposed on both sides of the second P-type doping region located on the second surface;

[0022] The preset depth of the inner trench is greater than the depth of the second P-type doping region.

[0023] Optionally, the semiconductor discharge tube further comprises: a metal layer;

[0024] On one side of the first surface of the N-type substrate, the metal layer is located on a side of the third P-type doping region away from the first surface;

[0025] Furthermore, on the second surface side of the N-type substrate, the metal layer is located on a side of the third P-type doping region away from the second surface.

[0026] According to another aspect of the present invention, there is provided a method for preparing a semiconductor discharge tube, comprising:

[0027] Providing an N-type substrate; the N-type substrate comprises a first surface and a second surface opposite to each other;

[0028] forming a first P-type doping region inwardly from the first surface and the second surface respectively;

[0029] A second P-type doping region is formed inwardly from the first surface and the second surface respectively; the second P-type doping region is located on a side of the first P-type doping region away from the N-type substrate, and the second P-type doping region is connected to the N-type substrate;

[0030] forming a third P-type doping region inwardly from the first surface and the second surface respectively;

[0031] An N-type emitter region is formed inwardly from the first surface and the second surface respectively;

[0032] The third P-type doping region and the N-type emitter region are located inside the second P-type doping region and away from the side of the first P-type doping region; the orthographic projection of the N-type emitter region on the N-type substrate does not overlap with the orthographic projection of the third P-type doping region on the N-type substrate; the first P-type doping region, the second P-type doping region, the third P-type doping region, and the N-type emitter region located on the first surface are symmetrical with the first P-type doping region, the second P-type doping region, the third P-type doping region, and the N-type emitter region located on the second surface, respectively, about the center of the N-type substrate;

[0033] The orthographic projection of the third P-type doping region on the N-type substrate covers at least a portion of the orthographic projection of the first P-type doping region on the N-type substrate.

[0034] Optionally, the method for preparing the semiconductor discharge tube further includes:

[0035] Etching the first surface and the second surface inward to form inner grooves respectively; wherein, in a direction perpendicular to the thickness of the N-type substrate, the inner grooves are respectively arranged on both sides of the second P-type doping region located on the first surface and the second surface;

[0036] Depositing a passivation material inside the inner groove to form a passivation layer;

[0037] A metal layer is formed on the first surface and the second surface.

[0038] The semiconductor discharge tube provided by the embodiment of the present invention has a bidirectional structure, and the first P-type doping region, the second P-type doping region, the third P-type doping region and the N-type emitter region are arranged on the first surface and the second surface of the semiconductor discharge tube, respectively, and are symmetrical about the center of the N-type substrate. The first P-type doping region has a deep push-in depth, which can reduce the distance between the second P-type doping region and the N-type emitter region located on the other side of the surface, thereby reducing the width of the base region, which is conducive to improving the current flow capacity of the semiconductor discharge tube. However, since the push-in depth of the first P-type doping region is deep, the doping concentration is low, so that the semiconductor discharge tube has limited ability to discharge surge current. By arranging a third P-type doping region with a shallow push-in depth at a surface position corresponding to at least part of the first P-type doping region, the surface carrier concentration of the semiconductor discharge tube in the third P-type doping region and the corresponding part of the first P-type doping region can be increased with little change to the overall structure of the semiconductor discharge tube. In this way, the flow capacity of the semiconductor discharge tube in the on state can be further improved, high surge current can be discharged, and the overvoltage protection capability of the semiconductor discharge tube can be improved.

[0039] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 is a schematic cross-sectional structure diagram of a semiconductor discharge tube provided according to an embodiment of the present invention;

[0042] Figure 2 is a schematic cross-sectional structure diagram of another semiconductor discharge tube provided according to an embodiment of the present invention;

[0043] Figure 3 is a schematic flow chart of a method for preparing a semiconductor discharge tube according to an embodiment of the present invention;

[0044] Figure 4 It is a schematic flow chart of another method for preparing a semiconductor discharge tube provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0047] An embodiment of the present invention provides a semiconductor discharge tube. Figure 1 The cross-sectional structure diagram of a semiconductor discharge tube provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the semiconductor discharge tube includes: an N-type substrate 10, including a first surface 11 and a second surface 12 opposite to each other; a first P-type doping region 21, a second P-type doping region 22, a third P-type doping region 23 and an N-type emitter region 24, all of which are located on one side of the first surface 11 and one side of the second surface 12; wherein the second P-type doping region 22 is located on a side of the first P-type doping region 21 away from the N-type substrate 10, and the second P-type doping region 22 is connected to the N-type substrate 10; the third P-type doping region 23 and the N-type emitter region 24 are located inside the second P-type doping region 22 and away from the side of the first P-type doping region 21.

[0048] The orthographic projection of the N-type emitter region 24 on the N-type substrate 10 does not overlap with the orthographic projection of the third P-type doping region 23 on the N-type substrate 10; the first P-type doping region 21, the second P-type doping region 22, the third P-type doping region 23, and the N-type emitter region 24 located on the first surface 11 are respectively symmetrical with the first P-type doping region 21, the second P-type doping region 22, the third P-type doping region 23, and the N-type emitter region 24 located on the second surface 12 about the center of the N-type substrate 10; wherein the orthographic projection of the third P-type doping region 23 on the N-type substrate 10 covers at least part of the orthographic projection of the first P-type doping region 21 on the N-type substrate 10.

[0049] Specifically, the same first P-type doping region 21, second P-type doping region 22, third P-type doping region 23 and N-type emitter region 24 are provided on both the first surface 11 and the second surface 12 of the N-type substrate 10. The first P-type doping region 21 located on one side of the first surface 11 and the first P-type doping region 21 located on one side of the second surface 12 are symmetrical about the center of the N-type substrate 10; the second P-type doping region 22 located on one side of the first surface 11 and the second P-type doping region 22 located on one side of the second surface 12 are symmetrical about the center of the N-type substrate 10; the third P-type doping region 23 located on one side of the first surface 11 and the third P-type doping region 23 located on one side of the second surface 12 are symmetrical about the center of the N-type substrate 10; and the N-type emitter region 24 located on one side of the first surface 11 and the N-type emitter region 24 located on one side of the second surface 12 are symmetrical about the center of the N-type substrate 10. Therefore, the semiconductor discharge tube provided in the embodiment of the present invention can achieve a bidirectional discharge effect, that is, no matter the semiconductor discharge tube is subjected to a positive surge or a negative surge, an avalanche breakdown can occur, thereby discharging the surge current.

[0050] By providing an N-type emitter region 24 and a second P-type doping region 22 on both the first surface 11 side and the second surface 12 side, the NPN triode structure formed by the N-type emitter region 24, the second P-type doping region 22 and the N-type substrate 10 can have a large negative resistance characteristic, which is conducive to improving the ability to discharge surge current. Since the structures located on the first surface 11 side are exactly the same as the structures located on the second surface 12 side, this embodiment is described with reference to the structures located on the first surface 11 side. The first P-type doping region 21 has a deep push-in junction depth, so that the distance between the first P-type doping region 21 located on the first surface 11 side and the second P-type doping region 22 and the N-type emitter region 24 located on the second surface 12 side is small, which is conducive to reducing the width of the base region. When the semiconductor discharge tube is in the on state, the current flows from the first P-type doping region 21 located on the first surface 11 side to the second P-type doping region 22 and the N-type emitter region 24 located on the second surface 12 side. By setting the first P-type doping region 21 to have a deeper junction pushing depth, the width of the base region can be reduced, which is beneficial to improving the current carrying capacity of the semiconductor discharge tube when it is in the on state, and realizing the discharge of surge current and overvoltage protection for the equipment.

[0051] However, due to the deep push-in depth and low doping concentration of the first P-type doping region 21, the semiconductor discharge tube has limited ability to discharge surge current. Therefore, a third P-type doping region 23 with a shallow push-in depth is provided at a position where the surface layer of the first surface 11 of the N-type substrate 10 corresponds at least partially to the first P-type doping region 21, that is, the third P-type doping region 23 corresponds at least partially to the first P-type doping region 21, so that the added third P-type doping region 23 can make little change to the overall structure of the semiconductor discharge tube. Since the doping concentration of the third P-type doping region 23 is higher than that of the first P-type doping region 21, it is beneficial to increase the surface carrier concentration of the semiconductor discharge tube in the corresponding part of the third P-type doping region 23 and the first P-type doping region 21, thereby further improving the flow capacity of the semiconductor discharge tube when it is in the on state, discharging high surge current, and improving the overvoltage protection capability of the semiconductor discharge tube.

[0052] The semiconductor discharge tube provided by the embodiment of the present invention has a bidirectional structure, and the first P-type doping region, the second P-type doping region, the third P-type doping region and the N-type emitter region are arranged on the first surface and the second surface of the semiconductor discharge tube, respectively, and are symmetrical about the center of the N-type substrate. The first P-type doping region has a deep push-in depth, which can reduce the distance between the second P-type doping region and the N-type emitter region located on the other side of the surface, thereby reducing the width of the base region, which is conducive to improving the current flow capacity of the semiconductor discharge tube. However, since the push-in depth of the first P-type doping region is deep, the doping concentration is low, so that the semiconductor discharge tube has limited ability to discharge surge current. By arranging a third P-type doping region with a shallow push-in depth at a surface position corresponding to at least part of the first P-type doping region, the surface carrier concentration of the semiconductor discharge tube in the third P-type doping region and the corresponding part of the first P-type doping region can be increased with little change to the overall structure of the semiconductor discharge tube. In this way, the flow capacity of the semiconductor discharge tube in the on state can be further improved, high surge current can be discharged, and the overvoltage protection capability of the semiconductor discharge tube can be improved.

[0053] Optionally, based on the above embodiment, continue to refer to Figure 1 , the orthographic projection of the third P-type doping region 23 on the N-type substrate 10 completely overlaps with the orthographic projection of the first P-type doping region 21 on the N-type substrate 10 .

[0054] Specifically, the width of the third P-type doping region 23 is set to be the same as the width of the first P-type doping region 21, that is, the orthographic projection of the third P-type doping region 23 on the N-type substrate 10 completely overlaps with the orthographic projection of the first P-type doping region 21 on the N-type substrate 10, so that the surface carrier concentration of the surface portion corresponding to the semiconductor discharge tube and the first P-type doping region 21 can be increased, and the flow capacity of the semiconductor discharge tube can be improved, so as to discharge high surge current and enhance the overvoltage protection of the equipment. It should be noted that if the width of the third P-type doping region 23 is set to be greater than the width of the first P-type doping region 21, the part of the third P-type doping region 23 that exceeds the first P-type doping region 21 in the width direction has a weak effect on improving the flow capacity of the semiconductor discharge tube, and will cause a significant change to the overall structure of the semiconductor discharge tube. Therefore, setting the width of the third P-type doping region 23 to be the same as the width of the first P-type doping region 21 is the best solution.

[0055] Optionally, based on the above embodiments, continue to refer to Figure 1 , the doping concentration of the third P-type doping region 23 is much greater than the doping concentration of the first P-type doping region 21 .

[0056] Specifically, the first P-type doping region 21, the second P-type doping region 22 and the third P-type doping region 23 are all heavily doped regions doped with group III elements, and can be, for example, heavily doped regions with boron, which are not limited here. In the surface region corresponding to the first P-type doping region 21, a third P-type doping region 23 with a shallower push-in depth is provided, while the first P-type doping region 21 has a deeper push-in depth. For example, there is a first preset depth between the side of the first P-type doping region 21 close to the N-type substrate 10 and the side of the second P-type doping region 22 close to the N-type substrate 10; there is a second preset depth between the side of the second P-type doping region 22 close to the N-type substrate 10 and the side of the third P-type doping region 23 close to the N-type substrate 10; the third P-type doping region 23 has a third preset depth; wherein the first preset depth is greater than the second preset depth, and the second preset depth is greater than the third preset depth. That is to say, the push-junction depth of the third P-type doping region 23 is the third preset depth, the push-junction depth of the second P-type doping region 22 is the sum of the second preset depth and the third preset depth, and the push-junction depth of the first P-type doping region 21 is the sum of the first preset depth, the second preset depth and the third preset depth. Exemplarily, the first preset depth ranges from 30 to 50 μm; the second preset depth ranges from 15 to 30 μm; and the third preset depth ranges from 5 to 10 μm. Thus, the push-junction depths of the first P-type doping region 21, the second P-type doping region 22 and the third P-type doping region 23 can be determined.

[0057] Optionally, Figure 2 FIG. 1 is a schematic cross-sectional view of another semiconductor discharge tube provided by an embodiment of the present invention. Figure 2As shown, the center position of the N-type emitter region 24 located on the first surface 11 corresponds to the center position of the first P-type doped region 21 located on the second surface 12; along the thickness direction perpendicular to the N-type substrate 10, the N-type emitter region 24 includes at least 3 sub-N-type emitter regions 241, and the sub-N-type emitter regions 241 are arranged at intervals.

[0058] Specifically, by setting the center position of the N-type emitter region 24 on one side of the first surface 11 to correspond to the center position of the first P-type doped region 21 on one side of the second surface 12, that is, the N-type emitter region 24 on one side of the first surface 11 and the first P-type doped region 21 on one side of the second surface 12 are axially symmetrically distributed about the straight line where the center of the N-type emitter region 24 is located or the straight line where the first P-type doped region 21 is located, the current conduction path between the first P-type doped region 21 and the N-type emitter region 24 can be made shortest, that is, the path of the breakdown current is shortest when the semiconductor discharge tube undergoes avalanche breakdown, and conduction is easiest to achieve, and the current conduction can be made uniform, which is beneficial to discharge high surge current and enhance the overvoltage protection effect on the equipment.

[0059] The N-type emitter region 24 may include at least three sub-N-type emitter regions 241, and each sub-N-type emitter region 241 is arranged at equal intervals along a thickness direction perpendicular to the N-type substrate 10. For example, Figure 2 2 shows that the N-type emitter region 24 includes four sub-N-type emitter regions 241. A short-circuit hole is provided between two adjacent sub-N-type emitter regions 241. If the short-circuit hole is not provided, the semiconductor discharge tube with a larger area will have a current concentrated in a certain part, while no current will flow through the other part. By providing multiple short-circuit holes, the anti-interference ability of the semiconductor discharge tube is improved.

[0060] Optionally, based on the above embodiments, continue to refer to Figure 2 The semiconductor discharge tube further includes an inner groove 30 , and a passivation layer 31 is disposed on the inner wall of the inner groove 30 .

[0061] In the thickness direction perpendicular to the N-type substrate 10, the inner groove 30 is arranged on both sides of the second P-type doping region 22 located on the first surface 11; and the inner groove 30 is arranged on both sides of the second P-type doping region 22 located on the second surface 12; the preset depth of the inner groove 30 is greater than the depth of the second P-type doping region 22.

[0062] Specifically, an inner groove 30 is provided at the intersection of the second P-type doping region 22 and the side of the N-type substrate 10 in the semiconductor discharge tube, and the inner groove 30 is U-shaped. A U-shaped inner groove 30 is provided on one side of the first surface 11 and one side of the second surface 12, and the bottom of the inner groove 30 exceeds the second P-type doping region 22, that is, the depth of the inner groove 30 is greater than the push-in depth of the second P-type doping region 22. Exemplarily, the size of the bottom of the inner groove 30 exceeding the second P-type doping region 22 can be set to 15 to 30 μm. A passivation layer 31 covering the inner wall is also provided inside the inner groove 30, and the passivation layer 31 can be prepared by glass powder, which is conducive to improving the withstand voltage of the semiconductor discharge tube, reducing high-temperature leakage current, and thus improving the reliability of the semiconductor discharge tube.

[0063] Optionally, based on the above embodiments, continue to refer to Figure 2 The semiconductor discharge tube further includes: a metal layer 40.

[0064] On the first surface 11 side of the N-type substrate 10 , the metal layer 40 is located on the side of the third P-type doping region 23 away from the first surface 11 ; and, on the second surface 12 side of the N-type substrate 10 , the metal layer 40 is located on the side of the third P-type doping region 23 away from the second surface 12 .

[0065] Specifically, a metal layer 40 is provided on the surface of the third P-type doping region 23 located on the first surface 11 and the surface of the third P-type doping region 23 located on the second surface 12, which serves as an electrode of the semiconductor discharge tube and is connected to the second P-type doping region 22, the third P-type doping region 23 and the N-type emitter region 24, thereby achieving a bidirectional discharge effect.

[0066] The embodiment of the present invention also provides a method for preparing a semiconductor discharge tube. Figure 3 FIG. 1 is a flow chart of a method for preparing a semiconductor discharge tube provided by an embodiment of the present invention. Figure 3 As shown, the method for preparing the semiconductor discharge tube specifically comprises the following steps:

[0067] S110, providing an N-type substrate; the N-type substrate comprises a first surface and a second surface opposite to each other.

[0068] S120, forming a first P-type doping region from the first surface and the second surface toward the inside.

[0069] For example, the first surface and the second surface are subjected to double-sided coating, exposure and development patterning processes, and the corresponding area is subjected to boron diffusion at 1000-1200°C for 50-100 minutes, so that the square resistance of the formed doped area is 3-10Ω / sq. Then, the formed doped area is subjected to boron oxidation at 1000-1300°C for 40-60 hours, and the thickness of the formed oxide layer is Thus, a first P-type doping region is formed.

[0070] S130, forming a second P-type doping region from the first surface and the second surface toward the inside; the second P-type doping region is located on a side of the first P-type doping region away from the N-type substrate, and the second P-type doping region is connected to the N-type substrate.

[0071] For example, the first surface and the second surface are subjected to double-sided coating, exposure and development patterning processes, and the corresponding area is subjected to boron diffusion at 1000-1200°C for 50-100 minutes, so that the square resistance of the formed doped area is 10-25Ω / sq. Then, the formed doped area is subjected to boron oxidation at 1000-1300°C for 15-20 hours, and the thickness of the formed oxide layer is Thus, a second P-type doping region is formed.

[0072] S140, forming a third P-type doping region from the first surface and the second surface toward the inside.

[0073] For example, the first surface and the second surface are subjected to double-sided coating, exposure and development patterning processes, and the corresponding area is subjected to boron diffusion at 1000-1200°C for 100-300 minutes, so that the square resistance of the formed doped area is 1-5Ω / sq. Then, the formed doped area is subjected to boron oxidation at 1000-1300°C for 100-200 minutes, and the thickness of the formed oxide layer is Thereby, a third P-type doping region is formed.

[0074] S150, forming an N-type emitter region from the first surface and the second surface toward the inside.

[0075] For example, the first surface and the second surface are subjected to double-sided glue coating, exposure and development patterning processes, and phosphorus diffusion is performed on the corresponding area at 1000-1100°C for 50-100 minutes, so that the square resistance of the formed doped area is 1-5Ω / sq. Then, the formed doped area is subjected to boron oxidation at 1000-1300°C for 100-200 minutes, and the thickness of the formed oxide layer is Thus, an N-type emitter region is formed.

[0076] Among them, the third P-type doping region and the N-type emitter region are located inside the second P-type doping region and away from one side of the first P-type doping region; the orthographic projection of the N-type emitter region on the N-type substrate does not overlap with the orthographic projection of the third P-type doping region on the N-type substrate; the first P-type doping region, the second P-type doping region, the third P-type doping region, and the N-type emitter region located on the first surface are respectively symmetrical with the first P-type doping region, the second P-type doping region, the third P-type doping region, and the N-type emitter region located on the second surface about the center of the N-type substrate; wherein the orthographic projection of the third P-type doping region on the N-type substrate covers at least part of the orthographic projection of the first P-type doping region on the N-type substrate.

[0077] In summary, the method for preparing a semiconductor discharge tube provided in an embodiment of the present invention is used to prepare a semiconductor discharge tube provided in any of the above embodiments, which has similar beneficial effects as the semiconductor discharge tube provided in any of the above embodiments, and will not be described in detail here.

[0078] Optionally, Figure 4 FIG. 1 is a flow chart of another method for preparing a semiconductor discharge tube provided by an embodiment of the present invention. Figure 4 As shown, the method for preparing the semiconductor discharge tube may further specifically include the following steps:

[0079] S210, providing an N-type substrate; the N-type substrate comprises a first surface and a second surface opposite to each other.

[0080] S220 , forming a first P-type doping region from the first surface and the second surface toward the inside.

[0081] S230, forming a second P-type doping region from the first surface and the second surface toward the inside; the second P-type doping region is located on a side of the first P-type doping region away from the N-type substrate, and the second P-type doping region is connected to the N-type substrate.

[0082] S240, forming a third P-type doping region from the first surface and the second surface toward the inside.

[0083] S250 , forming an N-type emitter region from the first surface and the second surface toward the inside.

[0084] S260, etching from the first surface and the second surface toward the inside to form an inner groove; wherein, in a thickness direction perpendicular to the N-type substrate, the inner groove is respectively arranged on both sides of the second P-type doping region located on the first surface and the second surface.

[0085] Exemplarily, the first surface and the second surface are subjected to double-sided coating, exposure and development patterning processes, and the corresponding areas on both sides of the second P-type doping region are etched with silicon etching solution to form an inner groove, wherein the bottom of the inner groove exceeds the second P-type doping region by 15 to 30 μm.

[0086] S270 , depositing a passivation material inside the inner trench to form a passivation layer.

[0087] For example, the passivation material may be glass powder. Glass powder is deposited inside the inner grooves on both sides, and a passivation layer of glass material is formed by high-temperature sintering to passivate and protect the semiconductor discharge tube.

[0088] S280 , forming a metal layer on the first surface and the second surface.

[0089] Exemplarily, metal materials are evaporated on both sides of the first surface and the second surface, and metal photolithography is performed on both sides. The metal film layer on both sides of the photolithography area is corroded by a metal etching solution, and an alloy layer is formed on the photolithography area under a vacuum environment.

[0090] Optionally, based on the above embodiments, before forming the first P-type doped region from the first surface and the second surface to the inside, the first surface and the second surface of the N-type substrate need to be double-sided oxidized, and the thickness of the formed oxide layer is

[0091] In forming the first P-type doped region in step S220, forming the second P-type doped region in step S230, forming the third P-type doped region in step S240, and forming the N-type emitter region in step S250, after performing the double-sided patterning process, a buffered oxide etchant (BOE) is required to remove the surface oxide layer of the photolithography area.

[0092] Furthermore, in forming the inner trench in step S260 , after the double-sided patterning process, a BOE solution is also required to remove the surface oxide layer of the photolithography area.

[0093] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor discharge tube, characterized in that: include: An N-type substrate including a first surface and a second surface opposite to each other; The first P-type doping region, the second P-type doping region, the third P-type doping region and the N-type emitter region are all located on one side of the first surface and one side of the second surface; wherein the second P-type doping region is located on a side of the first P-type doping region away from the N-type substrate, and the second P-type doping region is connected to the N-type substrate; the third P-type doping region and the N-type emitter region are located inside the second P-type doping region and away from a side of the first P-type doping region; The orthographic projection of the N-type emitter region on the N-type substrate does not overlap with the orthographic projection of the third P-type doped region on the N-type substrate; the first P-type doped region, the second P-type doped region, the third P-type doped region, and the N-type emitter region located on the first surface are symmetrical with the first P-type doped region, the second P-type doped region, the third P-type doped region, and the N-type emitter region located on the second surface, respectively, about the center of the N-type substrate; The orthographic projection of the third P-type doping region on the N-type substrate covers at least a portion of the orthographic projection of the first P-type doping region on the N-type substrate.

2. The semiconductor discharge tube according to claim 1, characterized in that: The orthographic projection of the third P-type doping region on the N-type substrate completely overlaps with the orthographic projection of the first P-type doping region on the N-type substrate.

3. The semiconductor discharge tube according to claim 2, characterized in that: The doping concentration of the third P-type doping region is much greater than the doping concentration of the first P-type doping region.

4. The semiconductor discharge tube according to claim 2, characterized in that: A first preset depth exists between a side of the first P-type doping region close to the N-type substrate and a side of the second P-type doping region close to the N-type substrate; A second preset depth exists between a side of the second P-type doping region close to the N-type substrate and a side of the third P-type doping region close to the N-type substrate; The third P-type doping region has a third preset depth; The first preset depth is greater than the second preset depth, and the second preset depth is greater than the third preset depth.

5. The semiconductor discharge tube according to claim 4, characterized in that: The first preset depth ranges from 30 to 50 μm; The second preset depth ranges from 15 to 30 μm; The third preset depth ranges from 5 to 10 μm.

6. The semiconductor discharge tube according to claim 1, characterized in that: The center position of the N-type emitter region located on the first surface corresponds to the center position of the first P-type doping region located on the second surface; Along a thickness direction perpendicular to the N-type substrate, the N-type emitter region includes at least three sub-N-type emitter regions, and the sub-N-type emitter regions are arranged at intervals.

7. The semiconductor discharge tube according to claim 1, characterized in that: Also includes: An inner groove, wherein an inner wall of the inner groove is provided with a passivation layer; In a thickness direction perpendicular to the N-type substrate, the inner groove is disposed on both sides of the second P-type doping region located on the first surface; and the inner groove is disposed on both sides of the second P-type doping region located on the second surface; The preset depth of the inner trench is greater than the depth of the second P-type doping region.

8. The semiconductor discharge tube according to claim 1, characterized in that: Also includes: Metal layer; On one side of the first surface of the N-type substrate, the metal layer is located on a side of the third P-type doping region away from the first surface; Furthermore, on the second surface side of the N-type substrate, the metal layer is located on a side of the third P-type doping region away from the second surface.

9. A method for preparing a semiconductor discharge tube, characterized in that: include: Providing an N-type substrate; The N-type substrate comprises a first surface and a second surface opposite to each other; forming a first P-type doping region inwardly from the first surface and the second surface respectively; A second P-type doping region is formed inwardly from the first surface and the second surface respectively; the second P-type doping region is located on a side of the first P-type doping region away from the N-type substrate, and the second P-type doping region is connected to the N-type substrate; forming a third P-type doping region inwardly from the first surface and the second surface respectively; An N-type emitter region is formed inwardly from the first surface and the second surface respectively; The third P-type doping region and the N-type emitter region are located inside the second P-type doping region and away from the side of the first P-type doping region; the orthographic projection of the N-type emitter region on the N-type substrate does not overlap with the orthographic projection of the third P-type doping region on the N-type substrate; the first P-type doping region, the second P-type doping region, the third P-type doping region, and the N-type emitter region located on the first surface are symmetrical with the first P-type doping region, the second P-type doping region, the third P-type doping region, and the N-type emitter region located on the second surface, respectively, about the center of the N-type substrate; The orthographic projection of the third P-type doping region on the N-type substrate covers at least a portion of the orthographic projection of the first P-type doping region on the N-type substrate.

10. The method for preparing a semiconductor discharge tube according to claim 9, characterized in that: Also includes: Etching the first surface and the second surface inward to form inner grooves respectively; wherein, in a direction perpendicular to the thickness of the N-type substrate, the inner grooves are respectively arranged on both sides of the second P-type doping region located on the first surface and the second surface; Depositing a passivation material inside the inner groove to form a passivation layer; A metal layer is formed on the first surface and the second surface.

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