Ferroelectric field effect transistor, memory device and neural network device

Abstract

The invention relates to a ferroelectric field effect transistor, a memory device and a neural network device. A ferroelectric field effect transistor includes a channel, a gate electrode disposed to face the channel, a ferroelectric layer disposed between the channel and the gate electrode, an interface layer disposed between the channel and the ferroelectric layer, and a diffusion barrier layer disposed between the ferroelectric layer and the gate electrode, in which the diffusion barrier layer includes SiON, the diffusion barrier layer has an oxygen concentration gradient that gradually decreases from a first surface of the diffusion barrier layer facing the gate electrode toward a second surface of the diffusion barrier layer facing the ferroelectric layer, and the diffusion barrier layer may have a nitrogen concentration gradient that gradually increases from the first surface toward the second surface.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0137981 filed in the Korean Intellectual Property Office on October 16, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to ferroelectric field effect transistors, memory devices, and neural network devices. Background Art

[0004] Ferroelectrics are materials with ferroelectricity, which means that they maintain spontaneous polarization by arranging (aligning) their internal electric dipole moments even when no electric field is applied from an external electric field source. Therefore, when a predetermined voltage is applied to the ferroelectric, the polarization remains semi-permanent in the ferroelectric even when the applied voltage returns to 0V. Research has been conducted on applying these ferroelectric properties to logic devices and / or memory devices. For example, in the case of a ferroelectric field effect transistor using a ferroelectric, the threshold voltage of the field effect transistor may vary with the direction of polarization in the ferroelectric. The threshold voltage variation characteristics of such a ferroelectric field effect transistor can be used to implement a logic device or a memory device. Summary of the invention

[0005] A ferroelectric field effect transistor is provided, which includes a diffusion barrier layer (barrier layer) for increasing a memory window (memory window), which is a difference between two different threshold voltages.

[0006] In addition, a memory device and a neural network device including the diffusion barrier layer are provided.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0008] According to one aspect of the embodiment, a ferroelectric field effect transistor includes a channel, a gate electrode facing the channel, a ferroelectric layer between the channel and the gate electrode, an interface layer between the channel and the ferroelectric layer, and a diffusion barrier layer between the ferroelectric layer and the gate electrode, wherein the diffusion barrier layer includes SiON, having an oxygen concentration gradient that decreases from a first surface of the diffusion barrier layer facing the gate electrode toward a second surface of the diffusion barrier layer facing the ferroelectric layer, and having a nitrogen concentration gradient that increases from the first surface toward the second surface.

[0009] The oxygen concentration is highest on the first surface of the diffusion barrier layer and lowest on the second surface of the diffusion barrier layer, such that the oxygen concentration on the first surface of the diffusion barrier layer may be higher than the oxygen concentration on the second surface of the diffusion barrier layer by a ratio of about 10% or more.

[0010] The nitrogen concentration is lowest on the first surface of the diffusion barrier layer and highest on the second surface of the diffusion barrier layer, such that the nitrogen concentration on the second surface of the diffusion barrier layer may be higher than the nitrogen concentration on the first surface of the diffusion barrier layer by a ratio of about 10% or more.

[0011] The diffusion barrier layer may have a silicon concentration gradient that increases from the first surface toward the second surface.

[0012] The silicon concentration is lowest on the first surface of the diffusion barrier layer and highest on the second surface of the diffusion barrier layer, such that the silicon concentration on the second surface of the diffusion barrier layer may be higher than the silicon concentration on the first surface of the diffusion barrier layer by a ratio of about 10% or more.

[0013] A ratio of a silicon concentration to a nitrogen concentration on a first surface of the diffusion barrier layer and a ratio of a silicon concentration to a nitrogen concentration on a second surface of the diffusion barrier layer may be the same.

[0014] The diffusion barrier layer may include an amorphous structure.

[0015] The ferroelectric field effect transistor may further include a tunnel barrier layer between the diffusion barrier layer and the gate electrode and / or between the ferroelectric layer and the diffusion barrier layer.

[0016] The interface layer may include, for example, SiO 2 , AlN or Si 3 N 4 At least one of.

[0017] The interfacial layer may include, for example, SiON.

[0018] The interface layer may have an oxygen concentration gradient that increases from a third surface of the interface layer facing the ferroelectric layer toward a fourth surface of the interface layer facing the channel.

[0019] The interface layer may have a nitrogen concentration gradient and a silicon concentration gradient decreasing from the third surface toward the fourth surface.

[0020] In the interface layer, the oxygen concentration may be lowest on the third surface of the interface layer and highest on the fourth surface of the interface layer, so that the oxygen concentration on the fourth surface of the interface layer may be higher than the oxygen concentration on the third surface of the interface layer by a ratio of about 10% or more.

[0021] In the interface layer, the nitrogen concentration may be highest on the third surface of the interface layer and lowest on the fourth surface of the interface layer, so that the nitrogen concentration on the third surface of the interface layer may be higher than the nitrogen concentration on the fourth surface of the interface layer by a ratio of about 10% or more.

[0022] In the interface layer, the silicon concentration may be highest on the third surface of the interface layer and lowest on the fourth surface of the interface layer, so that the silicon concentration on the third surface of the interface layer may be higher than the silicon concentration on the fourth surface of the interface layer by a ratio of about 10% or more.

[0023] A ratio of a silicon concentration to a nitrogen concentration on a third surface of the interface layer and a ratio of a silicon concentration to a nitrogen concentration on a fourth surface of the interface layer may be the same.

[0024] The interface layer may include an amorphous structure.

[0025] The ferroelectric layer may include a plurality of first material layers and at least one second material layer disposed between two of the plurality of first material layers facing each other, and the plurality of first material layers may include a ferroelectric material, and the second material layer may include a paraelectric material.

[0026] According to another aspect of the embodiment, the memory device includes: a plurality of gate electrodes and a plurality of spacers (spacers) alternately arranged in a first direction, a channel spaced apart from the plurality of gate electrodes and the plurality of spacers in a second direction perpendicular to the first direction, the channel extending in the first direction; a ferroelectric layer between the channel and the plurality of gate electrodes and extending in the first direction; an interface layer between the ferroelectric layer and the channel and extending in the first direction; and a diffusion barrier layer between the ferroelectric layer and the plurality of gate electrodes and extending in the first direction, wherein the diffusion barrier layer may have an oxygen concentration gradient that decreases from a first surface of the diffusion barrier layer facing the plurality of gate electrodes toward a second surface of the diffusion barrier layer facing the ferroelectric layer, and the diffusion barrier layer has a nitrogen concentration gradient that increases from the first surface toward the second surface.

[0027] According to another aspect of the embodiment, a neural network device includes: an array of multiple synaptic elements arranged in two dimensions, wherein the multiple synaptic elements each include an access transistor (access transistor) and a ferroelectric field effect transistor, wherein the ferroelectric field effect transistor includes a channel, a gate electrode facing the channel, a ferroelectric layer between the channel and the gate electrode, an interface layer between the channel and the ferroelectric layer, and a diffusion barrier layer between the ferroelectric layer and the gate electrode, the diffusion barrier layer includes SiON, the diffusion barrier layer has an oxygen concentration gradient that decreases from a first surface of the diffusion barrier layer facing the gate electrode toward a second surface of the diffusion barrier layer facing the ferroelectric layer, and the diffusion barrier layer has a nitrogen concentration gradient that increases from the first surface toward the second surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects, features and advantages of some embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 A cross-sectional view schematically showing the structure of a ferroelectric field effect transistor according to at least one example embodiment;

[0030] Figure 2 To display Figure 1 A graph of an oxygen concentration gradient in a diffusion barrier layer of a ferroelectric field effect transistor shown in;

[0031] Figure 3 To display Figure 1 A graph of silicon concentration gradient and nitrogen concentration gradient in a diffusion barrier layer of a ferroelectric field effect transistor shown in;

[0032] Figure 4 A cross-sectional view schematically showing the structure of a ferroelectric field effect transistor according to at least one example embodiment;

[0033] Figure 5 A cross-sectional view schematically showing the structure of a ferroelectric field effect transistor according to at least one example embodiment;

[0034] Figure 6 To display Figure 5 A graph of an oxygen concentration gradient in an interfacial layer of a ferroelectric field effect transistor shown in;

[0035] Figure 7 To display Figure 5 A graph of a nitrogen concentration gradient in an interfacial layer of a ferroelectric field effect transistor shown in;

[0036] Figure 8 A cross-sectional view schematically showing the structure of a ferroelectric field effect transistor according to at least one example embodiment;

[0037] Fig. 9 A cross-sectional view schematically illustrating a structure of a memory cell string of a memory device according to at least one example embodiment;

[0038] Fig.10 A cross-sectional view schematically illustrating a structure of a memory cell string of a memory device according to at least one example embodiment;

[0039] Fig.11 A cross-sectional view schematically illustrating a structure of a memory cell string of a memory device according to at least one example embodiment;

[0040] Fig.12 A diagram illustrating an equivalent circuit of a memory device according to at least one example embodiment;

[0041] Fig.13 is a schematic circuit diagram of a neural network device according to at least one example embodiment; and

[0042] Fig.14 A schematic block diagram showing an example configuration of an electronic device including a neural network device. DETAILED DESCRIPTION

[0043] Embodiments will now be described in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the following only describes the embodiment to illustrate aspects by reference to the accompanying drawings. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. When before or after the list of elements, statements such as "at least one (kind) of ... " modify the entire list of elements, and do not modify the individual elements of the list. In addition, numerical terms such as "first", "second", etc. can be used to describe and / or distinguish various parts (components), but are only used to distinguish one part (component) from another. The above terms are not intended to limit the differences in the material or structure of the parts (components).

[0044] Hereinafter, a ferroelectric field effect transistor, a memory device, and a neural network device will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals represent the same components, and the sizes of the components in the drawings may be exaggerated for clarity and convenience of description. In addition, the embodiments described below are merely exemplary, and various modifications are possible from these embodiments.

[0045] Hereinafter, the term "upper portion" or "on..." may also include "existing in a non-contacting manner" and "in direct contact with..." In addition, it will also be understood that spatially relative terms, such as "above...", "top", etc., in addition to the orientation shown in the figures, are intended to cover different orientations of the device in use or operation, and the device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative terms used herein are interpreted accordingly. Unless the context clearly implies otherwise, a singular expression includes a plural expression. In addition, when a part "includes" a component, this means that it may further include additional components, rather than excluding additional components, unless otherwise specified.

[0046] The use of the term "said" and similar indicative terms may correspond to both the singular and the plural. If there is no explicit description of the order in which the steps of a method are constituted or vice versa, the steps may be performed in a suitable order and are not necessarily limited to the order described.

[0047] In addition, the terms "unit", "module", etc. mean a unit that processes at least one function or operation, which can be implemented by a processing circuit system such as hardware, software, and / or a combination of hardware and software. For example, the processing circuit system may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. The processing circuit system may include at least one of electrical components such as transistors, resistors, capacitors, etc., and / or an electronic circuit including the components.

[0048] The line connections or connecting members between the components shown in the drawings exemplarily represent functional connections and / or physical or circuit connections, and in actual devices, they may be replaceable or represented as various other functional connections, physical connections or circuit connections. In addition, when the term "about" or "substantially" is used in conjunction with numerical values ​​and / or geometric terms in this specification, it is intended that the relevant numerical values ​​and / or geometric shapes include manufacturing tolerances (e.g., ±10%) around the stated numerical values ​​and / or geometric shapes. In addition, regardless of whether the numerical values ​​and / or geometric terms are modified to "about" or "substantially", it will be understood that these numerical values ​​and / or geometric shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the stated numerical values ​​and / or geometric shapes.

[0049] All examples or exemplary terms are used only to describe the technical ideas in detail, and the scope is not limited by these examples or exemplary terms unless the scope is limited by the claims.

[0050] Figure 1FIG. 1 is a cross-sectional view schematically showing the structure of a ferroelectric field effect transistor according to at least one example embodiment. Figure 1 The ferroelectric field effect transistor 100 according to at least one example embodiment may include a source region 103, a drain region 104, a channel 102 disposed between the source region 103 and the drain region 104, a gate electrode 109 disposed facing the channel 102, a ferroelectric layer (ferroelectric layer) 106 disposed between the channel 102 and the gate electrode 109, an interface layer 105 disposed between the channel 102 and the ferroelectric layer 106, and a diffusion barrier layer 107 disposed between the ferroelectric layer 106 and the gate electrode 109. In addition, the ferroelectric field effect transistor 100 may further include a tunnel barrier layer 108 disposed between the diffusion barrier layer 107 and the gate electrode 109. In other words, the ferroelectric field effect transistor 100 may include a gate stack arranged such that the interface layer 105 may be disposed on the upper surface of the channel 102, the ferroelectric layer 106 may be disposed on the upper surface of the interface layer 105, the diffusion barrier layer 107 may be disposed on the upper surface of the ferroelectric layer 106, the tunnel barrier layer 108 may be disposed on the upper surface of the diffusion barrier layer 107, and the gate electrode 109 may be disposed on the upper surface of the tunnel barrier layer 108.

[0051] The ferroelectric field effect transistor 100 may further include a substrate (base plate) 101. In at least one embodiment, a source region 103 and a drain region 104 may be respectively disposed on both sides of an upper portion of the substrate 101 and / or on opposite sides of a partial region of an upper portion of the substrate 101. The channel 102 may be a partial region of an upper portion of the substrate 101. Although not shown, the ferroelectric field effect transistor 100 may further include a source electrode and a drain electrode disposed above the source region 103 and the drain region 104 and electrically connected to the source region 103 and the drain region 104, respectively.

[0052] In at least one embodiment, the source region 103 and the drain region 104 may be doped with a first conductivity type at a first concentration, and the substrate 101 may be doped with a second conductivity type electrically opposite to the first conductivity type at a second concentration. For example, the substrate 101 may include a p-type semiconductor and the source region 103 and the drain region 104 may include an n-type semiconductor, or the substrate 101 may include an n-type semiconductor and the source region 103 and the drain region 104 may include a p-type semiconductor. The substrate 101 may be approximately 10 16 Up to 10 17 cm -3 The source region 103 and the drain region 104 may be doped at a relatively low concentration. 19 Up to 10 21 cm -3The substrate 101 may be doped with a relatively high concentration to obtain low resistance. The source region 103 and the drain region 104 may be formed by doping a portion of the upper portion of the substrate 101, respectively. The upper region of the substrate 101 between the source region 103 and the drain region 104 becomes the channel 102. Therefore, the channel 102 may be disposed between the source region 103 and the drain region 104 in the upper region of the substrate 101. However, this is only an example, and embodiments are not limited thereto. For example, in at least one embodiment, at least one of the channel 102, the source region 103 and / or the drain region 104 may be deposited and / or transferred onto the substrate 101.

[0053] In this way, the substrate 101, the channel 102, the source region 103 and the drain region 104 may include at least one semiconductor material such as a group IV semiconductor (such as silicon (Si), germanium (Ge) and SiGe), a group III-V compound semiconductor (such as GaAs and GaP), a group II-VI compound semiconductor, an oxide semiconductor, a two-dimensional material semiconductor and / or the like as a base material. When the substrate 101, the channel 102, the source region 103 and the drain region 104 include Si, Ge, SiGe, etc., the substrate 101 and the channel 102 may be doped with at least one dopant such as B, Al, Ga and In, and the source region 103 and the drain region 104 may be doped with at least one dopant such as P, As and Sb. Thus, the ferroelectric field effect transistor 100 becomes an n-channel metal oxide semiconductor (NMOS) field effect transistor. Alternatively, the substrate 101 and the channel 102 may be doped with at least one dopant such as P, As, and Sb, and the source region 142 and the drain region 143 may be doped with at least one dopant such as B, Al, Ga, and In. In this case, the ferroelectric field effect transistor 100 becomes a p-channel metal oxide semiconductor (PMOS) field effect transistor.

[0054] The ferroelectric layer 106 may include a ferroelectric material. A ferroelectric is a material having ferroelectricity that maintains spontaneous polarization by arranging (aligning) internal electric dipole moments without applying an electric field from an external electric field source. The threshold voltage of the ferroelectric field effect transistor 100 may change depending on the polarization direction of the ferroelectric layer 106 (e.g., the direction from the gate electrode 109 to the channel 102, or vice versa). In at least one embodiment, the ferroelectric material may be (or include) a material having a non-centrosymmetric (NCS) material phase.

[0055] The ferroelectric layer 106 may include, for example, a ferroelectric having at least one of a fluorite structure, a perovskite structure, and a wurtzite structure. The ferroelectric having a fluorite structure may include, for example, hafnium oxide (HfO 2). For example, the hafnium oxide may be doped with at least one element of zirconium (Zr), lanthanum (La), aluminum (Al), silicon (Si), yttrium (Y), gadolinium (Gd), and / or the like; and / or the ferroelectric layer 106 may include hafnium and zirconium (e.g., Hf) in substantially the same elemental ratio. 0.5 Zr 0.5 O 2 ), and in addition, at least one element of lanthanum (La), aluminum (Al), silicon (Si), yttrium (Y), gadolinium (Gd) and / or the like may be doped at a ratio of less than about 10 atomic percent (atomic %). In addition, the ferroelectric having a perovskite structure may include, for example, lead zirconatetitanate (PZT). The ferroelectric having a wurtzite structure may include, for example, zinc oxide (zinc oxide) (ZnO), aluminum nitride (AlN) and / or the like. Such a wurtzite structured ferroelectric may be doped with at least one element such as boron (B), scandium (Sc) and / or the like. The thickness of the ferroelectric layer 106 may be, for example, from about 5 nanometers (nm) to about 20 nm.

[0056] In at least one embodiment, the ferroelectric layer 106 may further include an antiferroelectric material. For example, the antiferroelectric material may include zirconium oxide (zirconium oxide). For example, the zirconium oxide may be doped with at least one element of hafnium (Hf), lanthanum (La), aluminum (Al), silicon (Si), yttrium (Y), gadolinium (Gd), and / or the like.

[0057] The gate electrode 109 may include one or more metals, metal nitrides, metal carbides, polysilicon, and / or combinations thereof. For example, the metal may include aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), and / or the like, the metal nitride may include titanium nitride (TiN), tantalum nitride (TaN), and / or the like, and the metal carbide may include aluminum or silicon doped (or containing aluminum or silicon) metal carbides, such as TiAlC, TaAlC, TiSiC, TaSiC, and / or the like.

[0058] In at least one embodiment, the gate electrode 109 may have a structure in which a plurality of materials are stacked. For example, the gate electrode 109 may have a stacked structure of a metal nitride layer / metal layer such as TiN / Al, and / or a stacked structure of a metal nitride layer / metal carbide layer / metal layer such as TiN / TiAlC / W. The gate electrode 109 may include a titanium nitride (TiN) layer or molybdenum (Mo), and the examples may be used with various modifications.

[0059] In addition, in addition to and / or as an alternative to the materials described above, the gate electrode 109 may include a conductive two-dimensional material. For example, the conductive two-dimensional material may include at least one of graphene, black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, and / or the like.

[0060] The interface layer 105 may be formed by natural oxidation of the semiconductor material of the channel 102 during the process of manufacturing the ferroelectric field effect transistor 100. Therefore, in these examples, the interface layer 105 may include an oxide of the semiconductor material. For example, when the channel 102 includes Si, Ge, SiGe, etc., the interface layer 105 may include SiO 2 ,GeO 2 SiGeO 4 The thickness of the interface layer 105 may be about 0.1 nm to 5 nm, or about 0.1 nm to about 2 nm.

[0061] When oxygen that passes through the ferroelectric layer 106 and permeates into the interface layer 105 increases during the process of manufacturing the ferroelectric field effect transistor 100, the thickness of the interface layer 105 may excessively increase. In addition, the layer quality of the interface layer 105 may deteriorate, thereby increasing defects in the interface layer 105. For this reason, the memory window, which represents the difference between two different threshold voltages of the ferroelectric field effect transistor 100, may decrease.

[0062] The memory window MW of the ferroelectric field effect transistor 100 can be expressed by Equation 1 below.

[0063] [Equation 1]

[0064]

[0065] In the above equation 1, ΔP is the polarization of the ferroelectric layer 106, ΔQ it is the amount of charge captured (trapped) at the interface of the ferroelectric layer 106 facing the channel 102, ΔQ' it is the amount of charge trapped at the interface of the ferroelectric layer 106 facing the gate electrode 109, C FE is the capacitance of the ferroelectric layer 106, and C TD is the capacitance of the layer between the ferroelectric layer 106 and the gate electrode 109. In other words, ΔQ it is the amount of charge trapped at the interface between the ferroelectric layer 106 and the interface layer 105 .

[0066] As the thickness of the interface layer 105 increases and the defects in the interface layer 105 increase, ΔQ it As can be seen from Equation 1, as ΔQ it As θ increases, the memory window of the ferroelectric field effect transistor 100 decreases, so that the performance of the ferroelectric field effect transistor 100 may be degraded.

[0067] The diffusion barrier layer 107 can prevent and / or minimize the increase in thickness of the interface layer 105 and the degradation of the layer quality by preventing and / or reducing oxygen from passing through the gate electrode 109 and the ferroelectric layer 106 and penetrating into the interface layer 105 during the process of manufacturing the ferroelectric field effect transistor 100. The thickness of the diffusion barrier layer 107 may have a thickness of about 1 nm or more to prevent the penetration of oxygen. In addition, the thickness of the diffusion barrier layer 107 may be about 5 nm or less, or about 3 nm or less, so that the distance between the ferroelectric layer 106 and the gate electrode 109 does not become too large.

[0068] Furthermore, when the diffusion barrier layer 107 is additionally present between the gate electrode 109 and the ferroelectric layer 106, the capacitance C of the layer between the gate electrode 109 and the ferroelectric layer 106 TD As can be seen from Equation 1, when the capacitance C of the layer between the gate electrode 109 and the ferroelectric layer 106 TD When Q is reduced, the storage window can be increased. In addition, the diffusion barrier layer 107 can increase the amount of charge Q' trapped at the interface of the ferroelectric layer 106 facing the gate electrode 109. it To further increase the storage window.

[0069] In order to prevent or reduce the penetration of oxygen, the diffusion barrier layer 107 may include a material having a relatively low oxygen permeability. In addition, the diffusion barrier layer 107 may include a material having a relatively low dielectric constant to reduce the capacitance C TD . For example, the diffusion barrier layer 107 may include silicon oxynitride (SiON) having an amorphous structure. When the diffusion barrier layer 107 has an amorphous structure, the penetration of other materials may be effectively suppressed. In addition, due to the capture of oxygen in the process of manufacturing the ferroelectric field effect transistor 100 and / or intentionally to prevent the penetration of oxygen, the concentration of oxygen elements in the diffusion barrier layer 107 may increase toward the gate electrode 109. Therefore, a concentration gradient of oxygen elements may appear in the diffusion barrier layer 107.

[0070] Figure 2 To display Figure 1 FIG. 1 is a graph of an oxygen concentration gradient in a diffusion barrier layer 107 of a ferroelectric field effect transistor 100 shown in FIG. Figure 2 In the figure, the horizontal axis is the unitless distance from the upper surface (or first surface) of the diffusion barrier layer 107 facing the gate electrode 109 to the lower surface (or second surface) of the diffusion barrier layer 107 facing the ferroelectric layer 106, and the vertical axis is the unitless concentration of the oxygen element in the diffusion barrier layer 107. Figure 2As shown in , the diffusion barrier layer 107 may have an oxygen concentration gradient that gradually decreases from the upper surface toward the lower surface. In other words, due to the gradual decrease in oxygen concentration toward the lower surface of the diffusion barrier layer 107, the oxygen concentration may be highest on the upper surface of the diffusion barrier layer 107, and the oxygen concentration may be lowest on the lower surface of the diffusion barrier layer 107.

[0071] For example, the oxygen concentration on the upper surface of the diffusion barrier layer 107 may be higher than the oxygen concentration on the lower surface of the diffusion barrier layer 107 by a ratio of about 10% or more, about 50% or more, about 100% or more, or about 300% or more. In other words, the ratio of the oxygen concentration on the upper surface of the diffusion barrier layer 107 to the oxygen concentration on the lower surface of the diffusion barrier layer 107 may be about 1.1 or more, about 1.5 or more, about 2 or more, or about 4 or more. For example, the difference between the oxygen concentration on the upper surface of the diffusion barrier layer 107 and the oxygen concentration on the lower surface of the diffusion barrier layer 107 (oxygen concentration on the upper surface of the diffusion barrier layer 107 - oxygen concentration on the lower surface of the diffusion barrier layer 107) may be about 5 atomic % or more, about 10 atomic % or more, or about 20 atomic % or more. If the oxygen concentration difference between the upper and lower surfaces of the diffusion barrier layer 107 is about 5 atomic % or more, the maximum oxygen concentration difference between the upper and lower surfaces of the diffusion barrier layer 107 need not be limited because the diffusion barrier layer 107 can sufficiently prevent or reduce oxygen from penetrating into the interface layer 105. However, considering the amount of oxygen that can be coupled (bonded) to the diffusion barrier layer 107, the difference between the oxygen concentration on the upper surface of the diffusion barrier layer 107 and the oxygen concentration on the lower surface of the diffusion barrier layer 107 may be less than or equal to about 60 atomic %.

[0072] In addition, the concentration of the silicon (Si) element and the concentration of the nitrogen (N) element may be changed according to the change in the concentration of the oxygen element in the diffusion barrier layer 107 . Figure 3 To display Figure 1 FIG. 1 is a graph showing a silicon concentration gradient and a nitrogen concentration gradient in the diffusion barrier layer 107 of the ferroelectric field effect transistor 100 shown in FIG. Figure 3 , the diffusion barrier layer 107 may have a silicon concentration gradient and a nitrogen concentration gradient that gradually increase from the upper surface to the lower surface. In other words, the silicon concentration is lowest on the upper surface of the diffusion barrier layer 107, and the silicon concentration gradually increases toward the lower surface of the diffusion barrier layer 107, so that the silicon concentration may be the largest on the lower surface of the diffusion barrier layer 107. Similarly, the nitrogen concentration is lowest on the upper surface of the diffusion barrier layer 107, and the nitrogen concentration gradually increases toward the lower surface of the diffusion barrier layer 107, so that the nitrogen concentration may be the largest on the lower surface of the diffusion barrier layer 107. Therefore, in at least some embodiments, in the diffusion barrier layer 107, the concentration of oxygen may be said to be inversely proportional to the concentration of silicon and / or nitrogen.

[0073] For example, the silicon concentration on the lower surface of the diffusion layer 107 may be higher by a ratio of about 10% or more, about 20% or more, about 50% or more, or about 100% or more than the silicon concentration on the upper surface of the diffusion layer 107. The difference between the silicon concentration on the lower surface of the diffusion barrier layer 107 and the silicon concentration on the upper surface of the diffusion barrier layer 107 may be about 5 atomic % or more, about 10 atomic % or more, or about 20 atomic % or more, and less than or equal to about 60 atomic %. In addition, the nitrogen concentration on the lower surface of the diffusion layer 107 may be higher by a ratio of about 10% or more, about 20% or more, about 50% or more, or about 100% or more than the nitrogen concentration on the upper surface of the diffusion layer 107. The difference between the nitrogen concentration on the lower surface of the diffusion barrier layer 107 and the nitrogen concentration on the upper surface of the diffusion barrier layer 107 may be about 5 atomic % or more, about 10 atomic % or more, or about 20 atomic % or less, and less than or equal to about 60 atomic %.

[0074] Meanwhile, the ratio of silicon concentration to nitrogen concentration in the diffusion barrier layer 107 may be constant. In other words, the ratio of silicon concentration to nitrogen concentration may not vary in all regions of the diffusion barrier layer 107. For example, the ratio of silicon concentration to nitrogen concentration on the lower surface of the diffusion barrier layer 107, and the ratio of silicon concentration to nitrogen concentration on the upper surface of the diffusion barrier layer 107 may be identical to each other. Here, the term "identical" does not mean "completely consistent", and if the deviation of the ratio of silicon concentration to nitrogen concentration on the upper and lower surfaces of the diffusion barrier layer 107 is within about 5%, the ratio of silicon concentration to nitrogen concentration on the lower surface of the diffusion barrier layer 107, and the ratio of silicon concentration to nitrogen concentration on the upper surface of the diffusion barrier layer 107 may be considered to be identical to each other.

[0075] According to the concentration gradient of the elements described above, due to the increased oxygen concentration from the ferroelectric layer 106 toward the upper surface of the diffusion barrier layer 107, the dielectric constant of the diffusion barrier layer 107 is reduced, and thus, the capacitance can be reduced. In addition, due to the increased nitrogen concentration toward the lower surface of the diffusion barrier layer 107 close to the ferroelectric layer 106, charge trapping can be increased. Therefore, charge trapping can be additionally formed near the interface with the ferroelectric layer 106, and the storage window can be further increased. In addition, oxygen and nitrogen can be present in excess in stoichiometry compared to silicon in the diffusion barrier layer 107. As a result, defects such as oxygen vacancies and / or nitrogen vacancies can be almost absent inside the diffusion barrier layer 107.

[0076] Return to reference Figure 1, when a sufficiently high voltage (e.g., a write voltage or an erase voltage) is applied to the gate electrode 109, the tunnel barrier layer 108 disposed between the diffusion barrier layer 107 and the gate electrode 109 can transfer charges from the gate electrode 109 to the ferroelectric layer 106 through a tunnel effect. In addition, when no voltage is applied to the gate electrode 109 and / or a low voltage (e.g., a standby voltage or a read voltage) is applied to the gate electrode 109, the tunnel barrier layer 108 can prevent charges trapped at the interface of the ferroelectric layer 106 from leaking through the gate electrode 109. The tunnel barrier layer 108 can also further reduce the capacitance C of the layer between the gate electrode 109 and the ferroelectric layer 106. TD The tunnel barrier layer 108 may include, for example, SiO 2 、Al 2 O 3 MgO 2 The thickness of the tunnel barrier layer 108 may be about 1 nm to about 5 nm or about 3 nm.

[0077] When the ferroelectric layer 106 includes HZO (HfZrO x ), the diffusion barrier layer 107 includes SiON having a thickness of about 4 nm and having the oxygen and nitrogen concentration gradients as described above, and the tunnel barrier layer 108 includes SiO having a thickness of about 3 nm. 2 , the memory window of the ferroelectric field effect transistor 100 according to the embodiment may be, for example, about 6.0V or greater, about 6.5V or greater, and / or 7.0V or greater. In order to measure the memory window, the first threshold voltage of the ferroelectric field effect transistor 100 in a relatively low threshold voltage state may be measured, and a voltage higher than or equal to the coercive voltage may be applied to the gate electrode 109 of the ferroelectric field effect transistor 100 to switch the polarization direction of the ferroelectric layer 106. Thereafter, the second threshold voltage of the ferroelectric field effect transistor 100 in a relatively high threshold voltage state may be measured, and the difference between the second threshold voltage and the first threshold voltage may be calculated. The threshold voltage of the ferroelectric field effect transistor 100 may be a voltage at which the current flowing between the source region 103 and the drain region 104 is saturated while gradually increasing the gate voltage applied to the gate electrode 109. Meanwhile, according to the ferroelectric field effect transistor of the comparative example (which does not include a diffusion barrier layer and includes only a HZO ferroelectric layer and a 7nm thick SiO 2 The memory window of the tunnel barrier layer 107 may be, for example, about 1.0 V or less, or about 1.5 V or less. Therefore, it can be seen that by using the diffusion barrier layer 107, the memory window of the ferroelectric field effect transistor 100 is greatly increased.

[0078] Figure 4 FIG. 1 is a cross-sectional view schematically showing the structure of a ferroelectric field effect transistor according to at least one example embodiment. Figure 1In the ferroelectric field effect transistor 100 shown in FIG. 1 , the tunnel barrier layer 108 is disposed between the gate electrode 109 and the diffusion barrier layer 107 , but the position of the diffusion barrier layer 107 and the position of the tunnel barrier layer 108 may be interchanged. Figure 4 , the ferroelectric field effect transistor 100a may include a diffusion barrier layer 107 disposed between a gate electrode 109 and a tunnel barrier layer 108. The tunnel barrier layer 108 may be disposed between the ferroelectric layer 106 and the diffusion barrier layer 107. In other words, the tunnel barrier layer 108 may be disposed on the upper surface of the ferroelectric layer 106, the diffusion barrier layer 107 may be disposed on the tunnel barrier layer 108, and the gate electrode 109 may be disposed on the upper surface of the diffusion barrier layer 107. In other aspects, the configuration of the ferroelectric field effect transistor 100a other than the positions of the diffusion barrier layer 107 and the tunnel barrier layer 108 may be the same as Figure 1 The configuration of the ferroelectric field effect transistor 100 shown in FIG. 1 is the same (and / or substantially similar), and thus a repeated description thereof has been omitted.

[0079] Figure 5 FIG. 1 is a cross-sectional view schematically showing the structure of a ferroelectric field effect transistor according to at least one example embodiment. Figure 1 In the ferroelectric field effect transistor 100 shown in FIG. 1 , the interface layer 105 is described as being formed by spontaneous oxidation of the semiconductor material of the channel 102. At the same time (on the other hand), Figure 5 The ferroelectric field effect transistor 100b may include an interface layer 105a intentionally disposed between the channel 102 and the ferroelectric layer 106 to prevent oxidation of the ferroelectric layer 106. In at least one embodiment, the interface layer 105a may include a material that is the same as (and / or similar to) the diffusion barrier layer 107. In other words, the interface layer 105a may include SiON having an amorphous structure. The configuration of the ferroelectric field effect transistor 100b other than the interface layer 105a may be the same as the configuration of the ferroelectric field effect transistor 100 and / or 100a shown above.

[0080] Like the diffusion barrier layer 107, the concentration of oxygen elements in the interface layer 105a may increase toward the channel 102 due to oxygen capture during the manufacturing process of the ferroelectric field effect transistor 100b and / or intentionally to prevent oxygen penetration. Therefore, a concentration gradient of oxygen elements may occur in the interface layer 105a.

[0081] Figure 6 To display Figure 5 FIG. 1 is a graph showing an oxygen concentration gradient in the interface layer 105a of the ferroelectric field effect transistor 100b shown in FIG. Figure 6In the figure, the horizontal axis is the unitless distance from the upper surface (or third surface) of the interface layer 105a facing the ferroelectric layer 106 to the lower surface (or fourth surface) of the interface layer 105a facing the channel 102, and the vertical axis is the unitless concentration of the oxygen element in the interface layer 105a. Figure 6 As shown in , the interface layer 105a may have an oxygen concentration gradient that gradually increases from the upper surface toward the lower surface. In other words, the oxygen concentration may be lowest on the upper surface of the interface layer 105a, and the oxygen concentration may gradually increase toward the lower surface of the interface layer 105a, so that the oxygen concentration may be highest on the lower surface of the interface layer 105a that contacts the channel 102.

[0082] For example, the oxygen concentration on the lower surface of the interface layer 105a may be higher than the oxygen concentration on the upper surface of the interface layer 105a by a ratio of about 10% or more, about 50% or more, about 100% or more, or about 300% or more. The difference between the oxygen concentration on the lower surface of the interface layer 105a and the oxygen concentration on the upper surface of the interface layer 105a may be about 5 atomic % or more, about 10 atomic % or more, or about 20 atomic % or more, and less than or equal to about 60 atomic %. Therefore, the oxygen concentration gradient in the interface layer 105a and the oxygen concentration gradient in the diffusion barrier layer 107 may be opposite to each other.

[0083] In addition, the concentration of the silicon (Si) element and the concentration of the nitrogen (N) element may be changed according to the change in the concentration of the oxygen element in the interface layer 105 a . Figure 7 To display Figure 5 FIG. 1 is a diagram showing an example of a nitrogen concentration gradient in the interface layer 105a of the ferroelectric field effect transistor 100b shown in FIG. Figure 7 As shown in , the interface layer 105a may have a nitrogen concentration gradient that gradually decreases from the upper surface toward the lower surface. In other words, the nitrogen concentration is highest on the upper surface of the interface layer 105a, and the nitrogen concentration gradually decreases toward the lower surface of the interface layer 105a, thereby minimizing the nitrogen concentration on the lower surface of the interface layer 105a. For example, compared with the nitrogen concentration on the lower surface of the interface layer 105a, the nitrogen concentration on the upper surface of the interface layer 105a may be higher by a ratio of about 10% or more, about 20% or more, about 50% or more, or about 100% or more. The difference between the nitrogen concentration on the upper surface of the interface layer 105a and the nitrogen concentration on the lower surface of the interface layer 105a may be about 5 atomic % or more, about 10 atomic % or more, or about 20 atomic % or more, and less than or equal to about 60 atomic %.

[0084] Despite Figure 7105a. Although not shown in the figure, the change of silicon concentration in the interface layer 105a may have the same trend as the nitrogen concentration therein. In other words, the interface layer 105a may have a silicon concentration gradient that gradually decreases from the upper surface toward the lower surface. For example, compared with the silicon concentration on the lower surface of the interface layer 105a, the silicon concentration on the upper surface of the interface layer 105a may be higher by a ratio of about 10% or more, about 20% or more, about 50% or more, or about 100% or more. The difference between the silicon concentration on the upper surface of the interface layer 105a and the silicon concentration on the lower surface of the interface layer 105a may be about 5 atomic % or more, about 10 atomic % or more, or about 20 atomic % or more, and less than or equal to about 60 atomic %. Therefore, the concentration gradient of nitrogen and silicon in the interface layer 105a and the concentration gradient of nitrogen and silicon in the diffusion barrier layer 107 may be opposite to each other.

[0085] The ratio of silicon concentration to nitrogen concentration in the interface layer 105a may be constant. In other words, the ratio of silicon concentration to nitrogen concentration may not change in all regions within the interface layer 105a. For example, the ratio of silicon concentration to nitrogen concentration on the lower surface of the interface layer 105a and the ratio of silicon concentration to nitrogen concentration on the upper surface of the interface layer 105a may be the same as each other.

[0086] In at least one example embodiment, in order to reduce the trapping concentration between the channel 102 and the ferroelectric layer 106 (eg, to reduce the amount of charge ΔQ trapped at the interface of the ferroelectric layer 106 facing the channel 102), it ), other materials other than SiON may be intentionally deposited on the channel 102 to form the interface layer 105a. For example, in at least one embodiment, the interface layer 105a may include AlN, Si 3 N 4 , or other high dielectric constant materials except SiON. Including AlN, Si 3 N 4 , or other high dielectric material interfacial layer 105a does not prevent oxygen from penetrating from channel 102, but can increase the storage window by reducing the capture concentration between channel 102 and ferroelectric layer 106. In addition, when interfacial layer 105a has a relatively high dielectric constant, the voltage applied to interfacial layer 105a can be reduced, and the voltage applied to ferroelectric layer 106 can be increased.

[0087] Figure 8 FIG. 1 is a cross-sectional view schematically showing the structure of a ferroelectric field effect transistor according to at least one example embodiment. Figure 8 The ferroelectric layer 106' of the ferroelectric field effect transistor 100c according to at least one example embodiment may include a plurality of first material layers 106a and at least one second material layer 106b between two first material layers 106a facing each other. Figure 8, three first material layers 106a and two second material layers 106b are shown, but the number of the first material layers 106a and the second material layers 106b is not limited thereto. For example, the ferroelectric layer 106′ may include two first material layers 106a and one second material layer 106b, or the ferroelectric layer 106′ may include four first material layers 106a and three second material layers 106b. In addition to the ferroelectric layer 106′, Figure 8 The remaining configuration of the ferroelectric field effect transistor 100c shown in FIG. 1 may be the same as the configuration of the ferroelectric field effect transistors 100, 100a, and / or 100b described above.

[0088] The first material layer 106a may include a reference Figure 1 The ferroelectric material of the ferroelectric layer 106 described above. For example, the first material layer 106a may include at least one of the ferroelectrics having a fluorite structure, a perovskite structure, and a wurtzite structure. The second material layer 106b may include a paraelectric material. For example, the second material layer 106b may include Al 2 O 3 、SiO 2 ,La 2 O 3 and Y 2 O 3 At least one paraelectric.

[0089] In the case of the above-mentioned ferroelectric material, when the thickness is about 10 nm or more, the ferroelectric properties may gradually deteriorate as the thickness increases, and may be lost at a thickness of 20 nm or more. Figure 1 The ferroelectric layer 106 is formed as a single layer having a thickness of about 20 nm or more. Figure 8 As shown in , by stacking a plurality of first material layers 106a including ferroelectric materials, a ferroelectric layer 106′ can be formed to have a thickness of 20nm or more without degrading the ferroelectric properties. The thickness of each of the first material layers 106a can be, for example, about 5nm to about 10nm. In addition, the thickness of the second material layer 106b can be small enough not to degrade the ferroelectric properties of the ferroelectric layer 106′. For example, the thickness of the second material layer 106b can be about 0.1nm to about 1nm.

[0090] Until now, a ferroelectric field effect transistor having a horizontal planar channel has been described, but the above-described diffusion barrier layer 107 can also be applied to a memory device having a vertical NOT-AND (VNAND) structure as a three-dimensional (or vertical) NAND.

[0091] Fig. 9 2 is a cross-sectional view schematically illustrating a structure of a memory cell string of a memory device according to at least one example embodiment. Fig. 9, a memory cell string 200 of a memory device according to at least one embodiment may include a plurality of gate electrodes 206 and a plurality of spacers 207 alternately arranged in a first direction (e.g., a Z-axis direction), a channel 201 facing the plurality of gate electrodes 206 and the plurality of spacers 207 in a second direction (e.g., an X-axis direction) perpendicular to the first direction and spaced apart from the plurality of gate electrodes 206 and the plurality of spacers 207 and extending continuously in the first direction, a ferroelectric layer 203 extending continuously in the first direction and disposed between the channel 201 and the plurality of gate electrodes 206, an interface layer 202 extending continuously in the first direction and disposed between the ferroelectric layer 203 and the channel 201, and a diffusion barrier layer 204 extending continuously in the first direction and disposed between the ferroelectric layer 203 and the plurality of gate electrodes 206. In addition, the memory cell string 200 may further include a tunnel barrier layer 205 extending continuously in the first direction and disposed between the plurality of gate electrodes 206 and the diffusion barrier layer 204. For example, the tunnel barrier layer 205 , the diffusion barrier layer 204 , the ferroelectric layer 203 , the interface layer 202 , and the channel 201 may be sequentially disposed in the second direction from the plurality of gate electrodes 206 and the plurality of spacers 207 .

[0092] Each of the plurality of spacers 207 may include silicon oxide (SiO 2 ), but not limited thereto. The ferroelectric layer 203 may include Figure 1 The ferroelectric layer 106 is the same and / or substantially similar ferroelectric material. In addition, the interface layer 202 and the tunnel barrier layer 205 can be the same as the reference Figure 1 The interface layer 105 and tunnel barrier layer 108 are depicted as being the same and / or substantially similar.

[0093] In addition, the diffusion barrier layer 204 may have a Figure 1The diffusion barrier layer 204 may have the same characteristics as described above for the diffusion barrier layer 107. For example, the diffusion barrier layer 204 may include SiON having an amorphous structure. In addition, concentration gradients of oxygen, silicon, and nitrogen may appear in the diffusion barrier layer 204. For example, the oxygen concentration may gradually decrease from a first surface of the diffusion barrier layer 204 facing the plurality of gate electrodes 206 toward a second surface of the diffusion barrier layer 204 facing the ferroelectric layer 203. In other words, in at least some embodiments, the oxygen concentration may be highest on the first surface of the diffusion barrier layer 204 facing the gate electrodes 206, and the oxygen concentration may be lowest on the second surface of the diffusion barrier layer 204 facing the ferroelectric layer 203. In addition, the silicon concentration and the nitrogen concentration may gradually increase from the first surface of the diffusion barrier layer 204 facing the gate electrodes 206 toward the second surface of the diffusion barrier layer 204 facing the ferroelectric layer 203. Therefore, the silicon and nitrogen concentrations may be lowest on the first surface of the diffusion barrier layer 204 facing the gate electrodes 206, and the silicon and nitrogen concentrations may be highest on the second surface of the diffusion barrier layer 204 facing the ferroelectric layer 203. The ratio of silicon concentration to nitrogen concentration in the diffusion barrier layer 204 may be constant. Therefore, the ratio of silicon concentration to nitrogen concentration on the first surface of the diffusion barrier layer 204 and the ratio of silicon concentration to nitrogen concentration on the second surface of the diffusion barrier layer 204 may be the same as each other.

[0094] Fig.10 1 is a cross-sectional view schematically illustrating a structure of a memory cell string of a memory device according to at least one example embodiment. Fig. 9 In the memory cell string 200 of the memory device shown in , the tunnel barrier layer 205 is disposed between the gate electrode 206 and the diffusion barrier layer 204, but the position of the diffusion barrier layer 204 and the position of the tunnel barrier layer 205 may be interchanged. Fig.10 , the memory cell string 200a of the memory device may include a diffusion barrier layer 204 disposed between the gate electrode 206 and the tunnel barrier layer 205. In other words, in the memory cell string 200a of the memory device, the diffusion barrier layer 204, the tunnel barrier layer 205, the ferroelectric layer 203, the interface layer 202, and the channel 201 may be sequentially arranged in the second direction from the plurality of gate electrodes 206 and the plurality of spacers 207. The configuration of the memory cell string 200a except for the positions of the diffusion barrier layer 204 and the tunnel barrier layer 205 may be the same as Fig. 9 The configuration of the memory cell string 200 shown in FIG. 2 is the same.

[0095] Fig.11 1 is a cross-sectional view schematically illustrating a structure of a memory cell string of a memory device according to at least one example embodiment. Fig. 9 In the memory cell string 200 shown in FIG. 1 , the interface layer 202 can be formed by naturally oxidizing the semiconductor material of the channel 201. At the same time (on the other hand), Fig.11The memory cell string 200b may include an interface layer 202a intentionally disposed between the channel 201 and the ferroelectric layer 203 to prevent oxidation of the ferroelectric layer 203. The interface layer 202a may include the same material as the diffusion barrier layer 204. In other words, the interface layer 202a may include SiON having an amorphous structure. Except for the interface layer 202a, the configuration of the memory cell string 200b may be the same as the configuration of the memory cell string 200 and / or 200a described above.

[0096] The interface layer 202a may have the same Figure 5 The interface layer 202a may have the same characteristics as the interface layer 105a described above. For example, the interface layer 202a may include SiON having an amorphous structure. In addition, concentration gradients of oxygen, silicon, and nitrogen may appear in the interface layer 202a. For example, the interface layer 202a may have an oxygen concentration gradient that gradually increases from the third surface of the interface layer 202a facing the ferroelectric layer 203 toward the fourth surface of the interface layer 202a facing the channel 201, and may have a silicon concentration gradient and a nitrogen concentration gradient that gradually decrease from the third surface toward the fourth surface.

[0097] Therefore, the oxygen concentration may gradually increase from the third surface of the interface layer 202a facing the ferroelectric layer 203 toward the fourth surface of the interface layer 202a facing the channel 201. In other words, the oxygen concentration may be the lowest on the third surface of the interface layer 202a, and the oxygen concentration may be the highest on the fourth surface of the interface layer 202a. In addition, the silicon concentration and the nitrogen concentration may gradually decrease from the third surface of the interface layer 202a toward the fourth surface of the interface layer 202a. Therefore, the silicon concentration and the nitrogen concentration may be the highest on the third surface of the interface layer 202a, and the silicon concentration and the nitrogen concentration may be the lowest on the fourth surface of the interface layer 202a. The ratio of the silicon concentration to the nitrogen concentration in the interface layer 202a may be constant. Therefore, the ratio of the silicon concentration to the nitrogen concentration on the third surface of the interface layer 202a and the ratio of the silicon concentration to the nitrogen concentration on the fourth surface of the interface layer 202a may be the same as each other.

[0098] In at least one example embodiment, in order to reduce the trapping concentration between the channel 201 and the ferroelectric layer 203, a material different from SiON may be intentionally deposited between the channel 201 and the ferroelectric layer 203 to form an interface layer 202a. For example, the interface layer 202a may include AlN, Si 3 N 4 Or other high dielectric constant materials except SiON.

[0099] exist Figures 9 to 11In the memory cell strings 200, 200a and 200b shown in the figure, a gate electrode 206 and a tunnel barrier layer 205, a diffusion barrier layer 204, a ferroelectric layer 203, an interface layer 202 and a channel 201 adjacent to the gate electrode 206 can form a memory cell in the second direction. Therefore, it can be considered that the memory cell strings 200, 200a and 200b include a plurality of memory cells stacked in the first direction. In addition, a memory device having a VNAND structure may include a plurality of memory cell strings 200, 200a and 200b arranged in two dimensions.

[0100] Fig.12 FIG. 2 is a diagram showing an equivalent circuit of a memory device according to at least one example embodiment. Fig.12 , the memory device may include a plurality of memory cell strings CS11 to CSkn. The plurality of memory cell strings CS11 to CSkn may be arranged two-dimensionally in the row direction and the column direction to form rows and columns. The memory cell strings CS11 to CSkn may each include a plurality of memory cells MC and a plurality of string selection transistors SST. The memory cells MC and the string selection transistors SST of each of the memory cell strings CS11 to CSkn may be stacked in the height direction. The memory cells MC in each of the memory cell strings CS11 to CSkn may each correspond to a circuit in which a transistor and a resistor are connected in parallel. For example, each of the memory cell strings CS11 to CSkn may be Figures 9 to 11 One of the memory cell strings 200, 200a and 200b shown in FIG.

[0101] The rows of the plurality of memory cell strings CS11 to CSkn may be connected to the plurality of string selection lines SSL1 to SSLk, respectively. For example, the string selection transistors SST of the memory cell strings CS11 to CS1n may be commonly connected to the string selection line SSL1. The string selection transistors SST of the memory cell strings CSk1 to CSkn may be commonly connected to the string selection line SSLk.

[0102] In addition, the columns of the plurality of memory cell strings CS11 to CSkn may be connected to the plurality of bit lines BL1 to BLn, respectively. For example, the memory cells MC and the string selection transistors SST of the memory cell strings CS11 to CSk1 may be commonly connected to the bit line BL1, and the memory cells MC and the string selection transistors SST of the memory cell strings CS1n to CSkn may be commonly connected to the bit line BLn.

[0103] In addition, the rows of the plurality of memory cell strings CS11 to CSkn may be connected to the plurality of common source lines CSL1 to CSLk, respectively. For example, the string selection transistors SST of the plurality of memory cell strings CS11 to CS1n may be commonly connected to the common source line CSL1, and the string selection transistors SST of the plurality of memory cell strings CSk1 to CSkn may be commonly connected to the common source line CSLk.

[0104] Memory cells MC at the same height from the substrate (or string selection transistors SST) may be commonly connected to one word line WL, and memory cells MC at different heights from the substrate (or string selection transistors SST) may be respectively connected to a plurality of word lines WL1 to WLn.

[0105] In such a structure, writing and reading can be performed in units of rows of memory cell strings CS11 to CSkn. For example, memory cell strings CS11 to CSkn can be selected for each row through common source lines CSLs, and memory cell strings CS11 to CSkn can be selected for each row through string selection lines SSL. In addition, writing and reading operations can be performed on each page in the selected row of memory cell strings CS11 to CSkn. For example, the page can be a row of memory cells MC connected to one word line WL. In the selected row of memory cell strings CS11 to CSkn, memory cells MC can be selected for each page through word lines WL.

[0106] Fig.13 is a schematic circuit diagram of a neural network device according to at least one example embodiment. Fig.13 According to at least one example embodiment, a neural network device 300 may include an array of a plurality of synaptic elements 310 arranged in two dimensions. Each of the plurality of synaptic elements 310 may include an access transistor 311 and a ferroelectric field effect transistor 312. The ferroelectric field effect transistor 312 may be Figures 1 to 8 The access transistor 311 may be used as a selection element for turning on / off the synapse element 310.

[0107] The neural network device 300 may also include a plurality of word lines WL, a plurality of bit lines BL, a plurality of input lines IL, and a plurality of output lines OL. The gate of the access transistor 311 may be electrically connected to any one of the plurality of word lines WL, the source thereof may be electrically connected to any one of the plurality of bit lines BL, and the drain thereof may be connected to the gate of the ferroelectric field effect transistor 312. In addition, the source of the ferroelectric field effect transistor 312 may be electrically connected to the input line of any one of the plurality of input lines IL, and the drain thereof may be electrically connected to the output line of any one of the plurality of output lines OL.

[0108] During the learning operation of the neural network device 300, the access transistor 311 is individually turned on through the individual word line WL, and the program pulse can be applied to the gate of the ferroelectric field effect transistor 312 through the bit line BL. The signal of the training data can be applied through the input line IL. Through this process, the weight can be stored in each ferroelectric field effect transistor 312.

[0109] During the inference operation of the neural network device 300, all access transistors 311 may be turned on through the entire word line WL, and a read voltage Vread may be applied through the bit line BL. Then, the current from the synaptic element 310 connected in parallel to the output line OL is added to and flows in each output line OL. The output circuit is connected to the plurality of output lines OL to convert the current flowing through each output line OL into a digital signal.

[0110] Fig.14 A schematic block diagram showing an example configuration of an electronic device including a neural network device. Fig.14 , the electronic device 400 may analyze input data in real time based on a neural network to extract effective information, determine a situation based on the extracted information, or control the configuration of a device equipped with the electronic device 400. For example, the electronic device 400 may be applied to a robot device (e.g., a drone, an advanced driver assistance system (ADAS)), a smart TV, a smart phone, a medical device, a mobile device, an image display device, a measuring device, an IoT device, and / or the like, and / or may be installed on at least one of various types of devices.

[0111] The electronic device 400 may include a processor 410, a random access memory (RAM) 420, a neural network device 430, a memory 440, a sensor module 450, and a communication (Tx / Rx) module 460. The electronic device 400 may further include an input / output module, a security module, a power control device, etc. Some of the hardware components of the electronic device 400 may be mounted on at least one semiconductor chip.

[0112] The processor 410 controls the overall operation of the electronic device 400. The processor 410 may include one processor core or multiple processor cores (i.e., multi-core). The processor 410 may process or execute programs and / or data stored in the memory 440. In some embodiments, the processor 410 may control the functions of the neural network device 430 by executing the programs stored in the memory 440. The processor 410 may be implemented as a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), and / or the like.

[0113] The RAM 420 may temporarily store programs, data, or instructions. For example, the programs and / or data stored in the memory 440 may be temporarily stored in the RAM 420 according to the control or boot code of the processor 410. The RAM 420 may be implemented as a memory such as a dynamic RAM (DRAM), a static RAM (SRAM), and / or the like.

[0114] The neural network device 430 may perform neural network operations based on received input data, and generate information signals based on the execution results. The neural network may include, but is not limited to, CNN, RNN, FNN, long short-term memory (LSTM), stacked neural network (SNN), state space dynamic neural network (SSDNN), deep belief network (DBN), restricted Boltzmann machine (RBM), etc. The neural network device 430 may be a hardware accelerator dedicated to the neural network itself or a device including the same. The neural network device 430 may perform read or write operations as well as neural network operations. In at least one embodiment, the neural network device 430 may correspond to Fig.13 A neural network device 300 according to an embodiment is shown in FIG.

[0115] The information signal may include one of the following: various types of recognition signals, such as a voice recognition signal, an object recognition signal, an image recognition signal, a biometric information recognition signal, etc. For example, the neural network device 430 may receive frame data included in a video stream as input data, and generate a recognition signal for an object included in an image represented by the frame data from the frame data. However, the neural network device is not limited thereto, and the neural network device 430 may receive various types of input data, and generate a recognition signal according to the input data according to the type or function of the device on which the electronic device 400 is installed.

[0116] The neural network device 430 may execute, for example, machine learning models such as linear regression, logistic regression, statistical clustering, Bayesian classification, decision trees, principal component analysis and / or expert systems, and / or machine learning models of integrated techniques such as random forests, etc. The machine learning models may be used to provide a variety of services, such as image classification services, user authentication services based on biometric information or biometric data, advanced driver assistance systems (ADAS), voice assistant services, automatic speech recognition (ASR) services, etc.

[0117] The memory 440 is a storage location for storing data and may store an operating system (OS), various programs, and various data. In at least one example embodiment, the memory 440 may store intermediate results generated during the operation of the neural network device 430.

[0118] The memory 440 may be a DRAM, but is not limited thereto. The memory 440 may include at least one of a volatile memory and a non-volatile memory. The non-volatile memory includes a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change ROM (PROM), a magnetic ROM (MROM), a resistive ROM (RROM), a ferroelectric ROM (FROM), and the like. The volatile memory includes a dynamic RAM (DRAM), a static RAM (SRAM), a synchronous DRAM (SDRAM), a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a ferroelectric RAM (FeRAM). In at least one example embodiment, the memory 440 may include at least one of a hard disk drive (HDD), a solid state drive (SSD), a compact flash (CF), a secure digital (SD), a micro secure digital (Micro-SD), a mini secure digital (Mini-SD), and a memory stick. In at least one embodiment, the memory 440 may correspond to Fig.12 A memory device according to an embodiment is shown in FIG.

[0119] The sensor module 450 may collect information around the device on which the electronic device 400 is installed. The sensor module 450 may sense or receive a signal (e.g., an image signal, a voice signal, a magnetic signal, a bio-signal, a touch signal, etc.) from the outside of the electronic device 400, and convert the sensed or received signal into data. To this end, the sensor module 450 may include at least one of the following: a plurality of types of sensing devices, such as a microphone, an imaging device, an image sensor, a light detection and ranging (LIDAR) sensor, an ultrasonic sensor, an infrared sensor, a biosensor, and a touch sensor.

[0120] The sensor module 450 may provide the converted data as input data to the neural network device 430. For example, the sensor module 450 may include an image sensor, generate a video stream by photographing the external environment of the electronic device 400, and sequentially provide continuous data frames of the video stream as input data to the neural network device 430. However, the embodiment is not limited thereto, and the sensor module 450 may provide various types of data to the neural network device 430.

[0121] The communication module 460 may include various wired or wireless interfaces and be configured to communicate with external devices. For example, the communication module 460 may include a wired local area network (LAN), a wireless local area network (WLAN) such as wireless fidelity (Wi-Fi), a wireless personal area network (WPAN) such as Bluetooth, a wireless universal serial bus (USB), Zigbee, near field communication (NFC), radio frequency identification (RFID), power line communication (PLC), and a communication interface capable of connecting to a mobile cellular network, such as a third generation (3G), a fourth generation (4G), a long term evolution (LTE) and / or the like.

[0122] The above-mentioned ferroelectric field effect transistor, memory device and neural network device have been described with reference to the embodiments shown in the accompanying drawings.

[0123] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should typically be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. Ferroelectric field effect transistor, including: Channel; a gate electrode facing the channel; a ferroelectric layer between the channel and the gate electrode; an interface layer between the channel and the ferroelectric layer; as well as a diffusion barrier layer between the ferroelectric layer and the gate electrode, wherein the diffusion barrier layer comprises SiON, the diffusion barrier layer has an oxygen concentration gradient that decreases from a first surface of the diffusion barrier layer facing the gate electrode toward a second surface of the diffusion barrier layer facing the ferroelectric layer, and The diffusion barrier layer has a nitrogen concentration gradient that increases from the first surface toward the second surface.

2. The ferroelectric field effect transistor of claim 1 , wherein the oxygen concentration is highest on the first surface of the diffusion barrier layer and lowest on the second surface of the diffusion barrier layer, such that the oxygen concentration on the first surface of the diffusion barrier layer is higher than the oxygen concentration on the second surface of the diffusion barrier layer by a ratio of about 10% or more.

3. The ferroelectric field effect transistor of claim 1 , wherein the nitrogen concentration is lowest on the first surface of the diffusion barrier layer and highest on the second surface of the diffusion barrier layer, such that the nitrogen concentration on the second surface of the diffusion barrier layer is higher than the nitrogen concentration on the first surface of the diffusion barrier layer by a ratio of approximately 10% or more. 4 . The ferroelectric field effect transistor according to claim 1 , wherein the diffusion barrier layer has a silicon concentration gradient that increases from the first surface toward the second surface.

5. The ferroelectric field effect transistor of claim 4 , wherein the silicon concentration is lowest on the first surface of the diffusion barrier layer and highest on the second surface of the diffusion barrier layer, such that the silicon concentration on the second surface of the diffusion barrier layer is higher than the silicon concentration on the first surface of the diffusion barrier layer by a ratio of about 10% or more. 6 . The ferroelectric field effect transistor according to claim 1 , wherein a ratio of silicon concentration to nitrogen concentration on the first surface of the diffusion barrier layer and a ratio of silicon concentration to nitrogen concentration on the second surface of the diffusion barrier layer are the same. 7 . The ferroelectric field effect transistor according to claim 1 , wherein the diffusion barrier layer comprises an amorphous structure.

8. The ferroelectric field effect transistor according to claim 1, further comprising: A tunnel barrier layer is provided between the diffusion barrier layer and the gate electrode and / or between the ferroelectric layer and the diffusion barrier layer.

9. The ferroelectric field effect transistor of claim 1, wherein the interface layer comprises at least one of SiO2, AlN or Si3N4.

10. The ferroelectric field effect transistor of claim 1, wherein the interface layer comprises SiON. 11 . The ferroelectric field effect transistor according to claim 10 , wherein the interface layer has an oxygen concentration gradient increasing from a third surface of the interface layer facing the ferroelectric layer toward a fourth surface of the interface layer facing the channel. 12 . The ferroelectric field effect transistor according to claim 11 , wherein the interface layer has a nitrogen concentration gradient and a silicon concentration gradient that decrease from the third surface toward the fourth surface.

13. The ferroelectric field effect transistor according to claim 11, wherein: In the interface layer, the oxygen concentration is lowest on the third surface of the interface layer and highest on the fourth surface of the interface layer, so that the oxygen concentration on the fourth surface of the interface layer is higher than the oxygen concentration on the third surface of the interface layer by a ratio of about 10% or more.

14. The ferroelectric field effect transistor according to claim 12, wherein: In the interface layer, the nitrogen concentration is highest on the third surface of the interface layer and lowest on the fourth surface of the interface layer, so that the nitrogen concentration on the third surface of the interface layer is higher than the nitrogen concentration on the fourth surface of the interface layer by a ratio of about 10% or more.

15. The ferroelectric field effect transistor according to claim 12, wherein: In the interface layer, the silicon concentration is highest on the third surface of the interface layer and lowest on the fourth surface of the interface layer, so that the silicon concentration on the third surface of the interface layer is higher than the silicon concentration on the fourth surface of the interface layer by a ratio of about 10% or more. 16 . The ferroelectric field effect transistor according to claim 12 , wherein a ratio of silicon concentration to nitrogen concentration on the third surface of the interface layer and a ratio of silicon concentration to nitrogen concentration on the fourth surface of the interface layer are the same.

17. The ferroelectric field effect transistor of claim 10, wherein the interface layer comprises an amorphous structure.

18. The ferroelectric field effect transistor according to claim 1, wherein The ferroelectric layer includes a plurality of first material layers, and at least one second material layer disposed between two of the plurality of first material layers facing each other, and The plurality of first material layers include ferroelectric material, and the second material layer includes paraelectric material.

19. Memory devices, comprising: a plurality of gate electrodes and a plurality of spacers alternately arranged in a first direction; a channel spaced apart from the plurality of gate electrodes and the plurality of spacers in a second direction perpendicular to the first direction, the channel extending in the first direction; a ferroelectric layer between the channel and the plurality of gate electrodes and extending in the first direction; an interface layer between the ferroelectric layer and the channel and extending in the first direction; as well as a diffusion barrier layer extending in the first direction between the ferroelectric layer and the plurality of gate electrodes, wherein the diffusion barrier layer has an oxygen concentration gradient that decreases from a first surface of the diffusion barrier layer facing the plurality of gate electrodes toward a second surface of the diffusion barrier layer facing the ferroelectric layer, and The diffusion barrier layer has a nitrogen concentration gradient that increases from the first surface toward the second surface.

20. Neural network devices, including: An array of multiple synaptic elements arranged in two dimensions, wherein the synaptic elements each include an access transistor and a ferroelectric field effect transistor, The ferroelectric field effect transistor is as defined in any one of claims 1-18.

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