High-reliability power device and manufacturing method thereof

Abstract

The invention provides a high-reliability power device and a manufacturing method thereof. The power device comprises a first conductive type epitaxial layer, a cellular region and first metal. Wherein the cell region is located in the first conductive type epitaxial layer and comprises a plurality of cells; the cell comprises a trench gate, a second conductive type grounding shielding region and a Schottky region. The trench gate includes a trench. The second conductive type grounding shielding region covers one side of the groove and at least one part of the bottom. The Schottky region is located on the side, away from the groove, of the second conductive type grounding shielding region. The first metal is over the first conductivity type epitaxial layer. The first metal is electrically connected with the second conductive type grounding shielding region and is in Schottky contact with the Schottky region. Due to the arrangement of the second conductive type grounding shielding region in the power device, the high reliability of the power device can be realized. And the Schottky diode is integrated in the cell, so that the switching loss of the power device can be reduced. The manufacturing method is simple in process and easy to implement.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuits and manufacturing, and relates to a high-reliability power device and a method for manufacturing the same. Background Art

[0002] Wide bandgap semiconductor material SiC is an ideal material for preparing high-voltage power electronic devices. Compared with Si materials, SiC materials have a higher breakdown electric field strength (4×10 6 V / cm), high saturation drift velocity (2×10 7 cm / s), high thermal conductivity, good thermal stability, etc., and are suitable for making high-power, high-voltage, high-temperature, radiation-resistant electronic devices. For example, SiC vertical double-diffused metal oxide semiconductor (VDMOS) as a SiC power device has better frequency characteristics and lower switching losses due to the absence of charge storage effect.

[0003] However, the planar SiC VDMOS has the following problems: the JFET region is dense and the Miller capacitance is large, which increases the dynamic loss of the device. Compared with the planar SiC VDMOS, the trench VDMOS does not have a JFET region. After the electrons leave the channel, they directly enter the open drift region, which can improve the dynamic loss of the device. However, the trench SiC VDMOS has the problem of electric field concentration in the gate oxide layer at the bottom of the trench, which can easily cause device reliability problems.

[0004] Therefore, how to provide a high-reliability power device and a manufacturing method thereof to improve the reliability of the power device has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a high-reliability power device and a manufacturing method thereof, so as to solve the problem that the reliability of trench power devices in the prior art needs to be improved.

[0007] To achieve the above objectives and other related objectives, in a first aspect, a high reliability power device is provided, comprising:

[0008] a first conductivity type epitaxial layer;

[0009] A cell region, located in the first conductive type epitaxial layer, the cell region includes a plurality of cells, the cells include a trench gate, a second conductive type ground shielding region and a Schottky region, the trench gate includes a trench, the second conductive type ground shielding region covers one side of the trench and at least a portion of the bottom of the trench, and the Schottky region is located on a side of the second conductive type ground shielding region away from the trench;

[0010] The first metal is located above the first conductive type epitaxial layer, and the first metal is connected to both the second conductive type ground shielding region and the Schottky region.

[0011] Optionally, the cell also includes a source doping region, which is adjacent to a side of the groove away from the second conductive type grounding shielding region, and the first metal is also electrically connected to the source doping region, wherein there is a distance between the source doping region and the second conductive type grounding shielding region between any two adjacent grooves, and the Schottky region is located between the source doping region and the second conductive type grounding shielding region.

[0012] Optionally, the source doping region includes a second conductivity type well region and a first conductivity type source region, the first conductivity type source region is located in the second conductivity type well region, and the first conductivity type source region includes a connected first extension region and multiple second extension regions, the first extension region extends along the length direction of the trench, the second extension region extends along the width direction of the trench, and the first metal is electrically connected to the first extension region.

[0013] Optionally, the trench gate also includes a gate dielectric and a gate electrode, the gate dielectric covers the inner wall of the trench and a portion of the surface of the first extension region, and the gate electrode is located above the gate dielectric; wherein, a horizontal channel formation region is formed based on a portion of the second conductive type well region located outside the first extension region, and a vertical channel formation region is formed based on an area of ​​the second conductive type well region adjacent to the trench.

[0014] Optionally, the source doping region also includes multiple second conductivity type contact regions, the second conductivity type contact regions are located on the upper surface layer of the second conductivity type well region, and there are two second conductivity type contact regions on both sides of the second extension region in the first direction, and the first metal is electrically connected to the second conductivity type contact regions.

[0015] Optionally, the second conductive type ground shielding region includes a first doping region and a second doping region, the first doping region is connected to the second doping region, the first doping region covers at least a portion of the bottom of the trench, and the second doping region covers one side of the trench.

[0016] Optionally, a ratio of a thickness of the first doping region to a depth of the trench is in a range of 1 / 30 to 1 / 3; a ratio of a width of the second doping region to a width of the trench is in a range of 1 / 10 to 1.

[0017] In a second aspect, a method for manufacturing a high-reliability power device is provided, comprising the following steps:

[0018] forming a first conductivity type epitaxial layer;

[0019] A cell region is formed in the first conductive type epitaxial layer, the cell region includes a plurality of cells, the cell includes a trench gate, a second conductive type ground shielding region and a Schottky region, the trench gate includes a trench, the second conductive type ground shielding region covers one side of the trench and at least a portion of the bottom of the trench, and the Schottky region is located on a side of the second conductive type ground shielding region away from the trench;

[0020] A first metal is formed on the first conductive type epitaxial layer, and the first metal is connected to both the second conductive type ground shielding region and the Schottky region.

[0021] Optionally, forming a cell region in the first conductivity type epitaxial layer comprises the following steps:

[0022] forming a trench in the first conductivity type epitaxial layer;

[0023] forming a first doped region below the trench, wherein the first doped region covers at least a portion of a bottom of the trench;

[0024] A second doping region is formed on one side of the trench, the second doping region covers one side of the trench, and the second doping region is connected to the first doping region to form a second conductive type grounding shielding region.

[0025] Optionally, the cell also includes a source doping region, which is adjacent to a side of the trench away from the second conductive type contact region; the Schottky region between any two adjacent trenches is located between the source region and the second conductive type grounding shielding region; the source doping region includes a second conductive type contact region, and the second conductive type contact region and the second doping region are formed in the same step.

[0026] As described above, the high reliability power device of the present application is provided with a second conductive type grounding shielding area in the cell of the power device. The second conductive type grounding shielding area covers one side of the groove in the groove gate and at least a part of the bottom, and the second conductive type grounding shielding area is electrically connected to the first metal for grounding, which can play a good role in electric field protection for the groove gate, and helps to achieve high reliability of the power device. In addition, based on the structure in which the first conductive type epitaxial layer is located on the side of the second conductive type grounding shielding area away from the groove, a Schottky region is formed, and the first metal has a Schottky contact with the Schottky region, so as to integrate a Schottky diode in the cell structure of the power device, realize alternative optimization of the low-performance body diode of the power device, reduce the turn-on voltage of the device body diode, and reduce the switching loss of the power device. Furthermore, by designing the structure of the source region in the cell, the source region includes a first extension region and a plurality of second extension regions, and a horizontal channel formation region is added on the basis of forming a vertical channel formation region in the second conductive type well region, so that both the horizontal channel and the vertical channel are provided under working conditions, thereby compensating for the channel density lost due to the setting of the second conductive ground shielding region and ensuring the on-current capability of the device. In addition, based on the above structural design of the source region, the contact area between the first metal and the Schottky region is further increased, thereby improving the current output capability of the device.

[0027] The manufacturing method of the high-reliability power of the present application can form a second conductive type ground shielding area in the cell and integrate a Schottky diode to realize a power device with high reliability, low switching loss, and high current output capability. Among them, the local structure of the second conductive type ground shielding area (for example, the second doping area) can be formed in the same step as the local structure of the source doping area (for example, the second conductive type contact area), which is conducive to saving process. The overall process steps are simple and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of a top view of a high reliability power device provided in an embodiment of the present application;

[0029] Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure of the A-A' portion;

[0030] Figure 3 for Figure 1 Schematic diagram of the cross-sectional structure of the B-B' portion;

[0031] Figure 4 for Figure 1 Schematic diagram of the cross-sectional structure of the C-C' portion;

[0032] Figure 5 A schematic diagram of the structure of a high-reliability power device provided in an embodiment of the present application before a gate dielectric is formed;

[0033] Figure 6 A flowchart of the steps of a method for manufacturing a high-reliability power device provided in an embodiment of the present application;

[0034] Figure 7 is a schematic cross-sectional view of a structure obtained after forming a first conductivity type epitaxial layer in the manufacturing method;

[0035] Figure 8 is a schematic cross-sectional view of the structure obtained after forming the first conductive type source region in the manufacturing method at the AA' portion;

[0036] Fig. 9 It is a cross-sectional schematic diagram of the structure obtained after forming the first conductivity type source region in the manufacturing method at the BB' portion;

[0037] Fig.10 is a schematic cross-sectional view of the structure obtained after the grooves are formed in the manufacturing method at the AA' portion;

[0038] Fig.11 is a schematic cross-sectional view of a portion BB' of the structure obtained after the groove is formed in the manufacturing method;

[0039] Fig.12 is a schematic cross-sectional view of the structure obtained after forming the second conductive type ground shielding region in the manufacturing method at the AA' portion;

[0040] Fig.13 It is a cross-sectional schematic diagram of the structure obtained after forming the second conductive type ground shielding region in the manufacturing method at the CC' portion;

[0041] Fig.14 is a schematic cross-sectional view of the structure obtained after forming the gate dielectric in the manufacturing method at the AA' portion;

[0042] Fig.15 is a schematic cross-sectional view of the structure obtained after forming the gate electrode in the manufacturing method at the AA' portion;

[0043] Fig.16 is a schematic cross-sectional view of the structure obtained after forming the gate electrode in the manufacturing method at the BB' portion;

[0044] Fig.17 is a schematic cross-sectional view of the structure obtained after forming the isolation dielectric layer in the manufacturing method at the AA' portion;

[0045] Fig.18 It is a cross-sectional schematic diagram of the structure obtained by forming the isolation dielectric layer in the manufacturing method at the BB' portion.

[0046] Description of reference numerals:

[0047] 10-first conductive type epitaxial layer, 11-Schottky region; 20-trench gate, 21-trench, 22-gate dielectric, 23-gate electrode, 231-vertical extension, 232-horizontal extension; 30-second conductive type ground shielding region, 31-first doped region, 32-second doped region; 40-source doped region, 41-second conductive type well region, 42-first conductive type source region, 421-first extension region, 422-second extension region, 43-second conductive type contact region; 50-first metal; 60-isolation dielectric layer; 70-first conductive type substrate; 80-first conductive type buffer layer; 90-second metal; I-region; S1~S3-steps. DETAILED DESCRIPTION

[0048] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application.

[0049] See also Figures 1 to 18 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner, and the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0050] In addition to the problem of high dynamic loss due to the high density of JFET area, planar SiC VDMOS also has the problem of too high conduction voltage drop of parasitic body diode. Since the parasitic body diode is a bipolar device, the reverse recovery current is large, and the conduction voltage drop of the parasitic body diode will continue to increase due to bipolar degradation. In addition, the presence of base plane dislocation (BDP) common in SiC materials affects the reverse recovery characteristic mode of the device. Therefore, the body diode of SiC VDMOS is not suitable as a reverse recovery diode. This problem also exists in trench SiC VDMOS.

[0051] In order to solve the problems of high body diode turn-on voltage and bipolar degradation, Schottky barrier diodes (SBDs) can be integrated in the SiC VDMOS cell, and the performance of the device can be improved by taking advantage of the SBD's low turn-on voltage and the absence of bipolar degradation. For example, the source well region in the cell can be disconnected to reserve an area for integrating the SBD. In order to obtain an SBD with better current flow capacity, the area between the source well regions needs to have a certain width, which will increase the cell size, and then increase the overall size of the SiC VDMOS device, which is not conducive to practical applications.

[0052] The present application provides a high reliability power device (hereinafter referred to as "power device"), see Figure 1 , Figure 1 The power device includes a first conductive type epitaxial layer 10, a cell region (not labeled) and a first metal 50 ( Figure 1 Please refer to Figures 2 to 4 ,in, Figure 2 Shows Figure 1 A schematic cross-sectional view of the A-A' region. Figure 3 Shows Figure 1 The cross-sectional diagram of the B-B' part, Figure 4 Shows Figure 1 Schematic diagram of the cross-section of the C-C' region.

[0053] Specifically, Figures 2 to 4As shown, the cell region is located in the first conductive type epitaxial layer 10. The cell region includes a plurality of cells (not labeled). The cell includes a trench gate 20, a second conductive type ground shielding region 30 and a Schottky region 11. The trench gate 20 includes a trench 21. The second conductive type ground shielding region 30 covers one side of the trench 21 and at least a portion of the bottom of the trench 21. The Schottky region 11 is located on a side of the second conductive type ground shielding region 30 away from the trench 21. The first metal 50 is located above the first conductive type epitaxial layer 10. The first metal 50 is electrically connected to the second conductive type ground shielding region 30 to achieve electrical extraction and grounding of the second conductive type ground shielding region 30. The first metal 50 also has a Schottky contact with the Schottky region 11 to form a Schottky diode. It should be noted that, since a plurality of cells are connected in parallel in the power device, the division boundary between the plurality of cells is not completely clear. For example, the plurality of cells may be divided based on the edge of one side of the second conductive type ground shielding area 30 away from the groove 31. In this case, the Schottky area 11 is located on the side of the groove 21 away from the second conductive type ground shielding area 30. Alternatively, the plurality of cells may also be divided based on the edge of one side of the trench gate 20 away from the second conductive type ground shielding area 30. In this case, the Schottky area 11 is located on the side of the second conductive type ground shielding area 30 away from the groove 21. This division boundary is used as an example for explanation herein.

[0054] In the embodiment of the present application, any cell in the power device includes a second conductive type ground shielding region 30 and a Schottky region 11. On the one hand, the second conductive type ground shielding region 30 can reduce the electric field strength at the bottom of the trench gate 20, thereby achieving effective protection of the trench gate 20 and increasing the withstand voltage and reliability of the power device. On the other hand, the Schottky region 11 is provided to integrate a Schottky diode in the power device, thereby reducing the turn-on voltage of the body diode in the power device, reducing the turn-on loss of the device, and improving the working performance of the device.

[0055] In an optional embodiment, if Figures 2 to 4As shown, the cell further includes a source doping region 40, the source doping region 40 is adjacent to the side of the groove 21 away from the second conductive type ground shielding region 30, and the first metal 50 is also electrically connected to the source doping region 40, wherein there is a distance between the source doping region 40 and the second conductive type ground shielding region 30 between any two adjacent grooves 21, and the Schottky region 11 is located between the source doping region 40 and the second conductive type ground shielding region 30. That is, a local structure of the undoped first conductive type epitaxial layer 10 is included between any two adjacent grooves 21, and the local structure is located between the source doping region 40 and the second conductive type ground shielding region 30, and the Schottky region 11 is formed based on the local structure.

[0056] In an optional embodiment, if Figures 2 to 4 As shown, the source doping region 40 includes a second conductive type well region 41 and a first conductive type source region 42. The first conductive type source region 42 is located in the second conductive type well region 41. One side of the first conductive type source region 42 is adjacent to the trench 21. And one side of the second conductive type well region 41 is also adjacent to the trench 21. A portion of the other side of the first conductive type source region 42 is at a distance from the other side of the second conductive type well region 41 (a channel is subsequently formed based on the surface inversion of this region).

[0057] Further, to clearly describe the structure of the source doping region, please refer to Figure 5 , Figure 5 Schematic diagram of the structure before the gate dielectric is formed in the power device is shown. The first conductive type source region 42 includes a first extension region 421 and a plurality of second extension regions 422 connected. The first extension region 421 extends along the length direction of the groove 21, and the second extension region 422 extends along the width direction of the groove 21. The first metal 50 is electrically connected to the first extension region 421. It is easy to understand that the length direction of the groove is perpendicular to the width direction of the groove.

[0058] It should be noted that, in the embodiment of the present application, the first metal 50 is an integrally formed structure. In order to achieve Schottky contact between the first metal 50 and the Schottky region 11 to form a Schottky diode, the first metal 50 needs to select a metal material with a work function higher than that of the Schottky region 11, such as Ni, Ti, etc. In other embodiments, the first metal 50 may be a split connection structure. For example, the first metal 50 may include a first metal portion (not shown) and a second metal portion (not shown). Among them, the first metal portion is in direct contact with the Schottky region 11, the second metal portion is in direct contact with the first extension region 421, and the second metal portion also covers or connects the first metal portion to form the first metal 50. At this time, compared with the first metal 50 being an integrally formed structure, although the manufacturing steps will be increased. However, different metal materials can be selected according to the properties or functions of the area to be contacted to form the first metal 50. For example, a metal material (for example, Al) that can form a good ohmic contact with the first extension region 421 can be selected as the second metal portion, thereby reducing the contact resistance and improving the device conduction capability.

[0059] In an optional embodiment, if Figures 2 to 4 As shown, the trench gate 20 further includes a gate dielectric 22 and a gate electrode 23. The gate dielectric 22 covers the inner wall of the trench 21 and a portion of the surface of the first extension region 421. The gate electrode 23 is located above the gate dielectric 22. A horizontal channel forming region is formed based on a portion of the second conductive type well region 41 located outside the first extension region 421. A vertical channel forming region is formed based on a region of the second conductive type well region 41 adjacent to the trench 21.

[0060] In an optional embodiment, the doping concentration of the vertical channel forming region is the same as the doping concentration of the planar channel forming region to ensure the consistency of opening the horizontal channel and the vertical channel in the cell and the working stability of the power device. The doping concentration of the vertical channel forming region and the planar channel forming region is not higher than the doping concentration of other regions in the second conductive type well region 41, which is conducive to inversion to form a channel.

[0061] In an optional embodiment, the doping concentration range of the vertical channel formation region is 5e16 cm -3 ~2e17cm -3 (including the endpoint value), the doping concentration range of the planar channel formation region is 5e16 cm -3 ~2e17cm -3 (including endpoint values). For example, the vertical channel formation area may be 8e16 cm -3 or 1e17 cm-3 , and the doping concentration of the planar channel formation region can be 8e16 cm -3 or 1e17 cm -3 .

[0062] In the embodiment of the present application, the cell of the power device has the second conductive type ground shielding area 30, which improves the voltage resistance and reliability of the device. However, since the second conductive type ground shielding area 30 covers one side of the groove 21, the vertical channel formation area formed based on the side wall of the groove 21 is sacrificed, which will increase the on-resistance of the device to a certain extent. In the embodiment of the present application, based on the structure of the first conductive type source area 42 (including the first extension area 421 and the second extension area 422), the structure of the trench gate 20 is adjusted so that the gate dielectric 22 covers a part of the surface of the first extension area 421, and the horizontal channel formation area is formed based on the part of the second conductive type well area 41 located outside the first extension area 421. When the gate voltage is greater than the threshold voltage, the horizontal channel formation area forms an inversion layer close to the side of the gate dielectric 22, thereby forming a horizontal channel. The formation of the horizontal channel helps to increase the channel density of the power device, thereby compensating for the device conduction capability weakened by the provision of the second conductive type ground shielding area 30, and achieving high reliability of the power device without substantially affecting the operating performance of the power device.

[0063] In addition, in the embodiment of the present application, through the structural setting of the first conductive type source region 42, that is, the first conductive type source region 42 includes the first extension region 421 and multiple second extension regions 422, and the multiple second extension regions 422 are arranged at intervals in the length direction of the groove 21, so that the formed horizontal channel is arranged in an interval manner along the arrangement of the second extension portion. Such a layout design can effectively increase the contact area between the first metal 50 and the Schottky region 11, thereby increasing the conduction current capability of the Schottky diode and improving the current output capability of the power device.

[0064] In an optional embodiment, if Figures 2 to 4As shown, the power device further includes an isolation dielectric layer 60, the isolation dielectric layer 60 covers the trench gate 20 (covers the exposed surface in the trench gate 20 structure), and the first metal 50 is embedded in the isolation dielectric layer 60 to connect with the first extension area 421, the Schottky area 11 and the second conductive type ground shielding area 30 in the first conductive type epitaxial layer 10. The gate electrode 23 includes a connected vertical extension portion 231 and a horizontal extension portion 232. The vertical extension portion 231 is filled in the trench 21. The horizontal extension portion 232 extends from above the trench 21 to above the first extension area 421. The distance between the horizontal extension portion 232 and the side of the trench 21 adjacent to the second conductive type ground shielding area 30 is smaller than the distance between the vertical extension portion 231 and the side of the trench 21 adjacent to the second conductive type ground shielding area 30. That is, a partial surface of the vertical extension portion 231 is not covered by the horizontal extension portion 232.

[0065] In the embodiment of the present application, through the structural design of the gate electrode 23, that is, the gate electrode 23 includes a vertical extension portion 231 and a horizontal extension portion 232, and the vertical extension portion 231 is not completely covered by the horizontal extension portion 232, so that a gap (such as Figure 1 Thus, under the premise that the isolation dielectric layer 60 completely covers the trench gate 20, the isolation dielectric layer 60 is prevented from covering the surface of the second conductive type ground shielding area 30 located on one side of the trench 21, so that the first metal 50 formed subsequently can be in good contact with the second conductive type ground shielding area 30.

[0066] In an optional embodiment, if Figures 2 to 4 As shown, the second conductive type ground shielding region 30 includes a first doping region 31 and a second doping region 32. The first doping region 31 is connected to the second doping region 32. The first doping region 31 covers at least a portion of the bottom of the trench 21, for example, the first doping region 31 completely covers the bottom of the trench 21 to achieve all-round protection of the bottom of the trench 21. The second doping region 32 covers one side of the trench 21.

[0067] In the embodiment of the present application, for the second conductive type ground shielding region 30, the first doping region 31 is mainly used to reduce the electric field concentration at the bottom of the trench gate 20, and the second doping region 32 is mainly used to achieve the grounding of the first doping region 31. Based on this, on the basis of satisfying the grounding effect of the first doping region 31, the width of the second doping region 32 can be relatively small, for example, the width of the second doping region 32 is smaller than the width of the second conductive type well region 21. Compared with the cell structure in the related art in which a region for integrating Schottky diodes is reserved between source well regions, in the embodiment of the present application, since the width of the second doping region 32 is small, correspondingly, the width of the Schottky region 11 between the second conductive type ground shielding region 30 and the source doping region 40 between any two adjacent trenches 21 can be set to be relatively wide, which will not increase the cell area and the overall area of ​​the power device while improving the performance of the Schottky diode, and is suitable for practical miniaturization applications.

[0068] In an optional embodiment, if Figure 2 As shown, the ratio between the thickness a of the first doping region 31 and the depth b of the groove 21 ranges from 1 / 30 to 1 / 3 (including the endpoint values). For example, the ratio between the thickness a of the first doping region 31 and the depth b of the groove 21 can be 1 / 15 or 1 / 5. The ratio between the width c of the second doping region 32 and the width d of the groove 21 ranges from 1 / 10 to 1 (including the endpoint values). For example, the ratio between the width c of the second doping region 32 and the width d of the groove 21 can be 3 / 10 or 3 / 5.

[0069] In an optional embodiment, the depth b of the groove 21 ranges from 1.5μm to 3μm (including endpoint values). For example, the depth b of the groove 21 may be 1.8μm, 2.2μm or 2.6μm. The width d of the groove 21 ranges from 0.3μm to 1μm (including endpoint values). For example, the width d of the groove 21 may be 0.5μm or 0.8μm. The depth c and width a of the groove 21 are selected and adjusted based on the application scenario and cell size of the power device. Herein, "depth" refers to the dimension in the direction from the first metal 50 to the first conductive type epitaxial layer 10 (i.e., the height direction of the cell), and "width" refers to the dimension perpendicular to the arrangement direction of the plurality of cells (i.e., the width direction of the cell).

[0070] In an optional embodiment, the thickness (or doping depth) a of the first doping region 31 is in the range of 0.1 μm to 0.5 μm (including the endpoint values). For example, the thickness a of the first doping region 31 may be 0.2 μm or 0.4 μm. The width c of the second doping region 32 is in the range of 0.1 μm to 0.3 μm (including the endpoint values), for example, the width c of the second doping region 32 may be 0.15 μm or 0.25 μm. The thickness a of the first doping region 31 may be adjusted based on actual needs, provided that the second conductive type grounding shielding region 30 can achieve the electric field protection effect on the trench gate 20. The width c of the second doping region 32 needs to ensure that the second doping region 32 has a sufficiently large area to be in good contact with the first metal 50, so as to achieve the grounding effect of the second conductive type grounding shielding region 30, and the width c of the second doping region 32 also needs to be reduced as much as possible to avoid occupying too much effective area of ​​the cell.

[0071] In an optional embodiment, the source doping region 40 also includes a plurality of second conductive type contact regions 43, the second conductive type contact regions 43 are located on the upper surface layer of the second conductive type well region 41, and there are two second conductive type contact regions 43 arranged on both sides of the second extension region 422 in the first direction, and the first metal 50 is electrically connected to the second conductive type contact regions 43.

[0072] In an optional embodiment, the second conductive type contact region 43 and the second doped region 32 in the second conductive type ground shielding region 30 are formed based on the same step, which is helpful to simplify the process steps.

[0073] In an optional embodiment, the power device further includes a first conductive type substrate 70 and a first conductive type buffer layer 80. The first conductive type substrate 70, the first conductive type buffer layer 80 and the first conductive type epitaxial layer 10 are stacked in sequence. The cell is located on a side of the first conductive type epitaxial layer 10 away from the buffer layer. The doping concentration of the first conductive type buffer layer 80 is between the first conductive type substrate 70 and the first conductive type epitaxial layer 10. The materials of the first conductive type substrate 70, the first conductive type buffer layer 80 and the first conductive type epitaxial layer 10 all include silicon carbide.

[0074] In an optional embodiment, the power device further includes a second metal 90 , and the second metal 90 is located on a side of the first conductive type substrate 70 away from the buffer layer, and the second metal 90 serves as a drain metal of the power device.

[0075] In an optional embodiment, the first conductivity type is N-type and the second conductivity type is P-type. Alternatively, the first conductivity type is P-type and the second conductivity type is N-type. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type for illustration. That is, in this embodiment, the power device is an N-type device, and the power device includes an N-type epitaxial layer, a P-type well region, an N-type source region, a P-type ground shielding region and a P-type contact region.

[0076] In an embodiment of the present application, a second conductive type ground shielding area is provided in a cell of a power device. The second conductive type ground shielding area covers one side and at least a portion of the bottom of the trench in the trench gate, and the second conductive type ground shielding area is electrically connected to the first metal, which can provide good electric field protection for the trench gate, and help achieve high reliability of the power device. In addition, based on the structure in which the first conductive type epitaxial layer is located on the side of the second conductive type ground shielding area away from the trench, a Schottky region is formed, and the first metal has a Schottky contact with the Schottky region, so as to integrate a Schottky diode in the cell structure of the power device, thereby realizing alternative optimization of the low-performance body diode of the power device, reducing the turn-on voltage of the device body diode, and reducing the switching loss of the power device. Furthermore, by designing the structure of the source region in the cell, the source region includes a first extension region and a plurality of second extension regions. On the basis of forming a vertical channel forming region in the second conductive type well region, a horizontal channel forming region is added to simultaneously have a horizontal channel and a vertical channel under working conditions, thereby compensating for the channel density lost due to the setting of the second conductive ground shielding region and ensuring the on-current capability of the device. In addition, based on the above structural design of the source region, the contact area between the first metal and the Schottky region is further increased, thereby improving the current output capability of the device.

[0077] In a second aspect, a method for manufacturing a high-reliability power device (hereinafter referred to as "manufacturing method") is provided. The manufacturing method can be used to manufacture the above-mentioned power device or other suitable power devices. Figure 6 , Figure 6 The process flow chart of the manufacturing method is shown. The manufacturing method comprises the following steps:

[0078] S1: forming a first conductivity type epitaxial layer;

[0079] S2: forming a cell region in the first conductive type epitaxial layer, the cell region comprising a plurality of cells, the cell comprising a trench gate, a second conductive type ground shielding region and a Schottky region, the trench gate comprising a trench, the second conductive type ground shielding region covering one side of the trench and at least a portion of the bottom of the trench, and the Schottky region being located on a side of the second conductive type ground shielding region away from the trench;

[0080] S3: forming a first metal on the first conductive type epitaxial layer, wherein the first metal is electrically connected to the second conductive type grounding shielding region, and the first metal has a Schottky contact with the Schottky region.

[0081] First, see Figure 7 , Figure 7 The schematic cross-sectional view of the structure obtained after forming the first conductive type epitaxial layer in the manufacturing method is shown. Step S1 is performed to form the first conductive type epitaxial layer 10 .

[0082] In an optional embodiment, step S1 includes the following steps: providing a first conductive type substrate 70 ; and sequentially forming a first conductive type buffer layer 80 and a first conductive type epitaxial layer 10 on the first conductive type substrate 70 .

[0083] Next, see Figures 8 to 18 , perform step S2 to form a cell region in the first conductive type epitaxial layer 10, the cell region includes a plurality of cells, the cell includes a trench gate 20, a second conductive type ground shielding region 30 and a Schottky region 11, the trench gate 20 includes a trench 21, the second conductive type ground shielding region 30 covers one side of the trench 21 and at least a portion of the bottom of the trench 21, and the Schottky region 11 is located on a side of the second conductive type ground shielding region 30 away from the trench 21.

[0084] In an optional embodiment, if Figures 8 to 18 As shown, forming a cell region in the first conductive type epitaxial layer 10 includes the following steps:

[0085] like Figures 8 to 11 As shown, a trench 21 is formed in the first conductive type epitaxial layer 10. The trench 21 can be formed by etching.

[0086] like Figure 12 to Figure 13 As shown, a first doping region 31 is formed below the trench 21, and the first doping region 31 covers at least a portion of the bottom of the trench 21;

[0087] like Figure 12 to Figure 13 As shown, a second doping region 32 is formed on one side of the groove 21, the second doping region 32 covers one side of the groove 21, and the second doping region 32 is connected to the first doping region 31 to form a second conductive type grounding shielding region 30, and the first doping region 31 and the second doping region 32 can be formed by ion implantation.

[0088] In the embodiment of the present application, the second conductive type ground shielding area 30 is formed by two ion implantation steps, which can, on the one hand, avoid insufficient ion implantation at the bottom corner of the groove 21 close to the second conductive type ground shielding area 30, thereby affecting the protection effect of the second conductive type ground shielding area 30. On the other hand, the precise control of the structural parameters of the second conductive type ground shielding area 30 can also be ensured.

[0089] In an optional embodiment, the ion implantation angle range when the second doping region 32 is formed by ion implantation is 0 to 15 degrees. For example, the ion implantation angle when the second doping region 32 is formed by ion implantation can be 5°, 7°, and 12°. The specific ion implantation angle is adjusted based on the aspect ratio value of the trench 21.

[0090] In an optional embodiment, if Figure 8 and Fig. 9 As shown, Figure 8 and Fig. 9 The schematic cross-sectional views of the structure obtained after forming the first conductive type source region in the manufacturing method at the A-A' position and the B-B' position are respectively shown. The step of forming the cell region in the first conductive type epitaxial layer 10 also includes the step of forming a source doping region 40. The source doping region 40 includes a second conductive type well region 41 and a first conductive type source region 42 located in the second conductive type well region 41. Then, as Fig.10 and Fig.11 As shown, Fig.10 and Fig.11 The cross-sectional schematic diagrams of the structure obtained after the groove is formed in the manufacturing method at the A-A' position and the B-B' position are respectively shown. The first conductive type epitaxial layer 10 is etched to form the groove 21, and the formed groove is adjacent to one side of the source doping region 40. In the case where the cell includes the source doping region 40, as Figure 12 to Figure 13 As shown, Fig.12 and Fig.13 The cross-sectional schematic diagrams of the structure obtained by forming the second conductive type ground shielding region in the manufacturing method at the AA' and BB' portions are respectively shown. The Schottky region 11 between any two adjacent trenches 21 is located between the source region and the second conductive type ground shielding region 30 .

[0091] In an optional embodiment, if Fig.13 As shown, the source doping region 40 further includes a second conductive type contact region 43 , and the second conductive type contact region 43 and the second doping region 32 are formed in the same step.

[0092] In an optional embodiment, if Figures 14 to 16As shown, the trench gate 20 further includes a gate dielectric 22 and a gate electrode 23, and forming a plurality of cells in the first conductive type epitaxial layer 10 further includes the step of forming the gate dielectric 22 and the gate electrode 23, and the gate dielectric 22 and the gate electrode 23 are formed after the second conductive type ground shielding region 30. For example, Fig.14 As shown, Fig.14 The schematic cross-sectional view of the structure obtained after the gate dielectric is formed in the manufacturing method at the A-A' position is shown. The gate dielectric 22 is formed on the inner wall of the trench 21 and a part of the surface of the source doping region 40, such as Fig.15 and Fig.16 As shown, Fig.15 and Fig.16 The schematic cross-sectional views of the structure obtained after the gate electrode is formed in the manufacturing method at the A-A' portion and the B-B' portion are respectively shown. A gate electrode material layer is formed on the gate dielectric 22, and etching is performed to form the gate electrode 23. The material of the gate dielectric 22 includes silicon oxide, and the material of the gate electrode material layer includes polysilicon. In one embodiment, before forming the gate dielectric 22, a step of performing a sacrificial oxidation process is also included to oxidize the grown oxide layer on the inner wall of the groove 21 and remove the oxide layer. This step can effectively avoid the problem of the rough surface of the inner surface of the groove 21 and the residual etching ions affecting the quality of the gate dielectric 22, thereby improving the reliability of the gate dielectric 22.

[0093] In an optional embodiment, if Figure 17 to Figure 18 As shown, Fig.17 and Fig.18 The schematic cross-sectional views of the structure obtained after forming the isolation dielectric layer in the manufacturing method at the A-A' position and the B-B' position are respectively shown. After forming the cell, the step of forming the isolation dielectric layer 60 is also included. For example, the step of forming the isolation dielectric layer 60 includes: forming an isolation dielectric material layer on the first conductive type epitaxial layer 10; etching the isolation dielectric material layer to obtain the isolation dielectric layer 60 and a contact hole (for example, a source contact hole), the isolation dielectric layer 60 covers the trench gate 20 (covers the exposed surface in the trench gate 20 structure), and the contact hole exposes a part of the surface of the first conductive type epitaxial layer 10, for example, the contact hole exposes at least a part of the surface of the first extension region 421, the second conductive type ground shielding region 30, the second conductive type contact region 43, and the Schottky region 11, etc.

[0094] Next, execute step S3, see Figure 2 and Figure 4, a first metal 50 is formed on the first conductive type epitaxial layer 10, the first metal 50 is electrically connected to the second conductive type ground shielding region 30, and the first metal 50 has a Schottky contact with the Schottky region 11. In the case where the manufacturing method includes the step of forming an isolation dielectric layer 60, the first metal 50 is filled into the contact hole to connect with the exposed surface of the first conductive type epitaxial layer 10.

[0095] In an optional embodiment, if Figures 2 to 4 As shown, the manufacturing method further includes the step of forming a second metal 90, the second metal 90 is located on a side of the first conductive type substrate 70 away from the buffer layer, and the second metal 90 serves as the drain metal of the power device. For example, the step of forming the second metal 90 can be performed after forming the first metal 50. In addition, before forming the second metal 90, the step of thinning the first conductive type substrate 70 can also be included.

[0096] The manufacturing method of the embodiment of the present application can form a second conductive type ground shielding area in the cell and integrate a Schottky diode to realize a power device with high reliability, low switching loss, and high current output capability. Among them, the local structure of the second conductive type ground shielding area (for example, the second doping area) can be formed in the same step as the local structure of the source doping area (for example, the second conductive type contact area), which is conducive to saving process. The overall process steps are simple and easy to implement.

[0097] In summary, the high reliability power device of the present application can provide good electric field protection for the trench gate by setting a second conductive type grounding shielding area in the cell of the power device, the second conductive type grounding shielding area covers one side of the trench in the trench gate and at least a part of the bottom, and the second conductive type grounding shielding area is electrically connected to the first metal for grounding, which helps to achieve high reliability of the power device. In addition, based on the first conductive type epitaxial layer on the side of the second conductive type grounding shielding area away from the trench, a Schottky region is formed, and the first metal has a Schottky contact with the Schottky region, so as to integrate a Schottky diode in the cell structure of the power device, realize alternative optimization of the low-performance body diode of the power device, reduce the turn-on voltage of the device body diode, and reduce the switching loss of the power device. Furthermore, by designing the structure of the source region in the cell, the source region includes a first extension region and a plurality of second extension regions, and on the basis of forming a vertical channel forming region in the second conductive type well region, a horizontal channel forming region is added to simultaneously have a horizontal channel and a vertical channel under working conditions, thereby compensating for the channel density lost due to the setting of the second conductive grounding shielding region, and ensuring the on-current capability of the device. In addition, based on the above structural design of the source region, the contact area between the first metal and the Schottky region is further increased, and the current output capability of the device is improved. The manufacturing method of the high-reliability power of the present application can form a second conductive type grounding shielding region in the cell and integrate a Schottky diode to realize a power device with high reliability, low switching loss and large current output capability. Among them, the local structure of the second conductive type grounding shielding region (for example, the second doping region) can be formed in the same step as the local structure of the source doping region (for example, the second conductive type contact region), which is conducive to saving the process. The overall process steps are simple and easy to implement. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0098] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A high reliability power device, characterized in that: include: a first conductivity type epitaxial layer; A cell region, located in the first conductive type epitaxial layer, the cell region includes a plurality of cells, the cells include a trench gate, a second conductive type ground shielding region and a Schottky region, the trench gate includes a trench, the second conductive type ground shielding region covers one side of the trench and at least a portion of the bottom of the trench, and the Schottky region is located on a side of the second conductive type ground shielding region away from the trench; The first metal is located above the first conductive type epitaxial layer, the first metal is electrically connected to the second conductive type grounding shielding region, and the first metal has a Schottky contact with the Schottky region.

2. The high reliability power device according to claim 1, characterized in that: The cell also includes a source doping region, which is adjacent to a side of the groove away from the second conductive type grounding shielding region, and the first metal is also electrically connected to the source doping region, wherein there is a distance between the source doping region and the second conductive type grounding shielding region between any two adjacent grooves, and the Schottky region is located between the source doping region and the second conductive type grounding shielding region.

3. The high reliability power device according to claim 2, characterized in that: The source doping region includes a second conductive type well region and a first conductive type source region, the first conductive type source region is located in the second conductive type well region, and the first conductive type source region includes a connected first extension region and multiple second extension regions, the first extension region extends along the length direction of the groove, and the second extension region extends along the width direction of the groove, and the first metal is electrically connected to the first extension region.

4. The high reliability power device according to claim 3, characterized in that: The trench gate also includes a gate dielectric and a gate electrode, the gate dielectric covers the inner wall of the trench and a portion of the surface of the first extension region, and the gate electrode is located above the gate dielectric, wherein a horizontal channel formation region is formed based on a portion of the second conductive type well region located outside the first extension region, and a vertical channel formation region is formed based on an area of ​​the second conductive type well region adjacent to the trench.

5. The high reliability power device according to claim 3, characterized in that: The source doping region also includes multiple second conductive type contact regions, which are located on the upper surface layer of the second conductive type well region, and there are two second conductive type contact regions on both sides of the second extension region in the first direction, and the first metal is electrically connected to the second conductive type contact regions.

6. The high reliability power device according to claim 1, characterized in that: The second conductive type grounding shielding region includes a first doping region and a second doping region, the first doping region is connected to the second doping region, the first doping region covers at least a portion of the bottom of the trench, and the second doping region covers one side of the trench.

7. The high reliability power device according to claim 6, characterized in that: The ratio of the thickness of the first doping region to the depth of the groove is in the range of 1 / 30 to 1 / 3; the ratio of the width of the second doping region to the width of the groove is in the range of 1 / 10 to 1.

8. A method for manufacturing a high reliability power device, characterized in that: The following steps are involved: forming a first conductivity type epitaxial layer; A cell region is formed in the first conductive type epitaxial layer, the cell region includes a plurality of cells, the cell includes a trench gate, a second conductive type ground shielding region and a Schottky region, the trench gate includes a trench, the second conductive type ground shielding region covers one side of the trench and at least a portion of the bottom of the trench, and the Schottky region is located on a side of the second conductive type ground shielding region away from the trench; A first metal is formed on the first conductive type epitaxial layer, the first metal is electrically connected to the second conductive type ground shielding region, and the first metal has a Schottky contact with the Schottky region.

9. The method for manufacturing a high-reliability power device according to claim 8, characterized in that: Forming a cell region in the first conductive type epitaxial layer includes the following steps: forming a trench in the first conductivity type epitaxial layer; forming a first doped region below the trench, wherein the first doped region covers at least a portion of a bottom of the trench; A second doping region is formed on one side of the trench, the second doping region covers one side of the trench, and the second doping region is connected to the first doping region to form a second conductive type grounding shielding region.

10. The method for manufacturing a high reliability power device according to claim 9, characterized in that: The cell also includes a source doping region, which is adjacent to a side of the trench away from the second conductive type contact region; the Schottky region between any two adjacent trenches is located between the source region and the second conductive type grounding shielding region; the source doping region includes a second conductive type contact region, and the second conductive type contact region and the second doping region are formed in the same step.

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