Preparation method of self-layering addressable three-dimensional stacked nanowire integration and CFET structure and preparation method of logic device

Abstract

The invention relates to the technical field of microelectronic manufacturing. According to the invention, the self-stratified addressable three-dimensional stacked nanowire integration is realized by utilizing the stepped laminated groove preparation and IPSLS nanowire growth mode, the preparation of an addressable three-dimensional integrated device is facilitated, the integration density can be greatly improved, and the performance of the device is improved. Meanwhile, a preparation mode of a CFET structure is provided based on the stepped three-dimensional stacked nanowires, different types of nanowires are grown in different stepped layers by adopting different catalytic metals, then photoetching definition is performed on each step, source and drain metals are prepared, and a gate dielectric layer and a gate thin film layer are deposited, so that the CFET structure is obtained. According to the invention, a multi-layer channel can be prepared through one-time growth, so that multi-layer stacking and addressing of the CFET are realized in a three-dimensional direction, the integration density of the device is greatly improved, the preparation process is simplified, and the process stability and reliability are improved.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics technology. Specifically, it relates to a self-layered addressable three-dimensional stacked nanowire integration based on stepped stacked grooves, which can be used in three-dimensional stacked high-density integrated devices, and in particular, it relates to a method for preparing a CFET device structure and a logic device based on a self-layered addressable three-dimensional nanowire with stepped stacked grooves, which can be applied to three-dimensional stacked logic device integration and new generation chip manufacturing. Background Art

[0002] Semiconductor nanowires (Nanowires) are the core materials of modern microelectronics technology because of their high ultra-high specific surface area, carrier mobility, high efficiency, stability and reliable doping process. The inventors of this application first proposed a planar solid-liquid-solid (IPSLS) growth mode: in which low-melting-point metal nanoparticles absorb amorphous precursor films and then grow crystalline nanowire structures. At the same time, the inventors of this application have also proposed a method of using positive photoresist technology to prepare a multi-step guide structure through a cycle of anisotropic etching and isotropic shrinking etching to grow a positionable planar nanowire array. The nanowires obtained by the previous research results of this team based on the "planar solid-liquid-solid" growth method have the advantages of planar or three-dimensional positionability, programmable morphology, controllable diameter and low cost, and can easily obtain three-dimensional nanowires based on various structures.

[0003] As the requirements for computing power, storage density, and energy efficiency in fields such as artificial intelligence, big data, and 5G communications rise sharply, the size of in-plane devices continues to shrink to the physical limit, and Moore's Law is difficult to continue. As the feature size shrinks to the nanometer level, interconnection delay and power consumption increase significantly, becoming a key factor restricting performance improvement. In order to continue Moore's Law, shorten the interconnection path to reduce delay and power consumption, and achieve higher integration density, it is necessary to move towards three-dimensional integration, that is, to continuously stack devices in the vertical direction. Technologies such as through silicon vias (TSV) and hybrid bonding have been developed, and concepts such as stacked complementary transistors (CFET) have been proposed for the development of three-dimensional device integration. However, the current technology has a low integration density, a complex preparation process, and low reliability and stability.

[0004] In order to solve the above problems, our team proposed a new technical path and complementary method for the existing three-dimensional integration based on the stacked etching technology and IPSLS growth technology. That is, they designed a new structure and preparation method for three-dimensional stacked nanowire integration and realized the addressability of the device. Summary of the invention

[0005] The present application provides a method for preparing a self-stratified addressable three-dimensional stacked nanowire integration and CFET based on stepped stacked grooves, which can prepare multi-layer nanowires based on a single growth, and the nanowires can be guided by the stepped grooves to gradually achieve self-stratification from parallel growth, thereby achieving an addressable effect, simplifying the preparation method and improving the integration density; in addition, the present invention also proposes a method for preparing a CFET and an inverter based on nanowires grown with stepped stacked grooves, realizing the integration of N-type field effect transistors (NFET) and P-type field effect transistors (PFET) in a three-dimensional direction, improving the integration density of CFET, and is expected to be applied to three-dimensional logic, storage, sensing and other devices.

[0006] The present application provides a method for preparing a self-stratified addressable three-dimensional stacked nanowire integration, comprising the following steps: 1) Using positive photolithography process, the mask channel pattern is transferred to a substrate with a periodic heterogeneous stacked structure deposited alternately and cyclically; 2) etching the heterogeneous stacked structure into a step-type or slope-type stacked structure by cyclic anisotropic etching and isotropic shrinkage etching or angled plasma etching; 3) selectively etching one of the dielectric layers to form a stepped guide trench structure; 4) depositing a strip-shaped catalytic metal layer at the end of the side surface of the guide groove structure having the largest number of grooves in the vertical direction; 5) In a PECVD system, the temperature is raised to above the melting point of the catalytic metal, and a reducing gas is used for plasma treatment to remove the oxide layer on the surface of the catalytic metal and form metal nanoparticles; 6) The temperature is lowered to below the melting point of the catalytic metal particles, and the amorphous semiconductor precursor film is covered on the entire surface of the sample; then annealing is performed, and the front end of the catalytic metal droplet begins to absorb the amorphous semiconductor precursor film layer, and the rear end deposits crystalline doped nanowires. When the catalytic metal moves to the step corner on the side of the guide groove structure, the catalytic metal ball turns to continue absorbing the amorphous semiconductor precursor film, thereby achieving self-stratification of the crystalline doped nanowires; 7) After removing the remaining amorphous semiconductor precursor film layer on the sample surface, the surface of the crystalline doped nanowires is passivated; 8) A gate dielectric layer is deposited on the entire sample surface, and a hole is opened at each step and then metal is injected to achieve connection with the crystalline doped nanowires, thereby achieving integration and addressability of the nanowire devices on each step.

[0007] Furthermore, in step 1), the material used for the substrate is crystalline silicon, glass, aluminum foil, silicon nitride, silicon oxide, silicon carbide, sapphire or polyimide, etc.; the heterogeneous stacked structure is a dielectric layer with different etching selectivity ratios such as silicon nitride / silicon oxide, aluminum oxide / silicon oxide, zinc oxide / silicon oxide, hafnium oxide / silicon nitride, etc.

[0008] Furthermore, in step 1), the photolithography is contact photolithography, laser direct writing, electron beam lithography, deep ultraviolet lithography, extreme ultraviolet lithography, etc., which is also applicable to the photolithography in subsequent steps.

[0009] Furthermore, in step 2), the anisotropic etching gas is CF4, C4F8, CHF3, SF6, Ar, Cl2, BCl3, etc. for physical or chemical etching, and the isotropic shrinking gas is O2, O3, SO2, etc. for shrinking the size of the photoresist. The step width and height are determined by the power and time of the plasma, which are used to control the number of nanowires in each step and the horizontal projection spacing between the nanowires; the inclination angle θ of the sloped stack is determined by the angle of plasma etching.

[0010] Furthermore, in step 3), the step-type guide groove etching method is dry etching with gases such as CF4, C4F8, CHF3, SF6, Cl2, BCl3, or wet etching with acid-base solutions such as HCl, HF, H3PO4, HNO3, NaOH, NH4OH, TMAH, etc. Parameters such as etching power, concentration and time jointly determine the depth of the groove. The etching method must have a high etching selectivity for the two dielectric layer structures, and the selectivity is greater than 5:1.

[0011] Furthermore, in step 1), the heterogeneous stacked structure is a dielectric layer B and a dielectric layer A with different etching selectivities, the etching selectivity of the dielectric layer B to the dielectric layer A is greater than 5:1, and the thickness of the dielectric layer A is d A , the thickness of dielectric layer B is d B .

[0012] Furthermore, in step 2), the step of preparing the stepped laminated structure includes: 1) Anisotropic etching, define the height h of each step, h is the thickness of the stack of n periods, that is, h = n·(d A +d B ), which is subsequently used to grow nanowires, and each step height h corresponds to n nanowires; 2) Isotropic shrinkage is used to shrink the size of the photoresist to expose the required step width w of the etching, and the step width w corresponds to the horizontal projection spacing of the nanowires in different steps.

[0013] Furthermore, the slope-type stack is obtained by angled plasma etching, the etched slope angle is θ, and the horizontal projection spacing between adjacent homogeneous dielectric layers is arctanθ·(dA+dB), which is used to define the horizontal projection spacing between subsequent adjacent nanowires. The use of angled plasma etching can further increase the step density, that is, increase the density of subsequent addressable nanowire devices.

[0014] Furthermore, in step 4), the catalytic metal layer is evaporated on the side of the stepped guide groove structure away from the end of the step, and the catalytic metal is one of In, Sn, Bi, Ga metals or their metal alloys. The catalytic metal can also be evaporated to the side by angled evaporation.

[0015] Furthermore, in step 6), the amorphous semiconductor precursor film is amorphous silicon a-Si, amorphous germanium a-Ge, amorphous carbon aC or a-Ge / a-Si heterogeneous stacked structure, etc.

[0016] Furthermore, in step 7), the amorphous semiconductor precursor film layer is removed by etching processes such as hydrogen plasma, RIE dry etching or wet etching; the wet etching solution is an alkaline corrosion system such as potassium hydroxide (KOH), ammonia (NH4OH), tetramethylammonium hydroxide (TMAH), etc., and the RIE dry etching gas is a fluorine-containing gas such as carbon tetrafluoride (CF4) and carbon tetrafluoride octafluoride (C4F8); the passivation method can be passivation with a strongly oxidizing solution such as HNO3, H2O2, KMnO4, passivation with an oxidizing plasma such as low-temperature O2, O3, or high-temperature (>750°C) passivation.

[0017] Furthermore, in step 8), the gate dielectric layer is aluminum oxide, hafnium oxide, silicon nitride, silicon oxide, titanium oxide, lanthanum oxide or a heterostructure; the hole opening method is RIE, DRIE, ICP, wet etching, laser drilling, etc.; the metal injection method is physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, chemical plating, Damascus process, metal reflow process, etc.

[0018] The present invention also provides a method for preparing a CFET structure by integrating the self-layered addressable three-dimensional stacked nanowires, which is characterized by comprising the following steps: 1) Using positive photolithography process, the mask channel pattern is transferred to a substrate with periodic heterogeneous stacked structures deposited alternately and cyclically. Theoretically, the number of steps is unlimited; 2) etching the stacked structure into a step-type or slope-type stacked structure by cyclic anisotropic etching and isotropic shrinkage etching or angled plasma etching; 3) selectively etching one of the dielectric layers to form a stepped guide trench structure; 4) Photolithographically define and evaporate different catalytic metals at the connection between one end and the side of each step in turn. The same catalytic metal can be photolithographically defined and evaporated at different step positions at one time; 5) In a PECVD system, the temperature is simultaneously raised to above the melting point of the catalyst metal with the highest melting point value, and a reducing gas is used for plasma treatment to remove the surface oxide layer and form metal nanoparticles of the catalyst metal; 6) Then, the temperature is simultaneously lowered to below the melting point of the catalytic metal particles with the lowest melting point value, and the amorphous semiconductor precursor film is covered on the entire sample surface; then, annealing is performed, and the front end of the catalytic metal droplet begins to absorb the amorphous semiconductor precursor film layer. Due to the self-doping effect of the catalytic metal, some catalytic metal atoms will enter the nanowires, and crystalline doped nanowires will be deposited at the rear end. Since the catalytic metal grows simultaneously in different steps, the self-stratification of the crystalline doped nanowires is automatically achieved. The nanowires generated here will automatically turn when they encounter the corners of the side and the step, thereby changing from layered growth in different steps to parallel growth in the same vertical plane, realizing vertical three-dimensional stacking of different types of nanowires; 7) After removing the remaining amorphous semiconductor precursor film layer on the sample surface, the surface of the crystalline doped nanowires is passivated; 8) Photolithography defines the source and drain metal patterns on each step’s independent vertical surface, removes the surface oxide layer and evaporates separate source and drain metals to connect different types of nanowires; 9) Deposit a gate dielectric layer on the entire sample surface, define the gate pattern by photolithography, and deposit a separate gate film on each step's independent vertical surface. After the device is fully prepared, perform vacuum low-temperature annealing to improve contact and eliminate interface defects to complete the preparation of the CFET structure as needed.

[0019] Preferably, in step 4), the type of catalytic metal is t, t ≥ 2, different catalytic metals are evaporated separately on the vertical surface of each step end, and at least one catalytic metal acts as a donor impurity to provide electrons to generate N-type nanowires that become the channel of NFET, and at least one catalytic metal acts as an acceptor impurity to provide holes to generate P-type nanowires that become the channel of PFET.

[0020] Preferably, the catalytic metal used as donor impurities is Bi, Sr, Na or K and their metal alloys, which can provide electrons to make the nanowire become the channel of NFET; the catalytic metal used as acceptor impurities is In, Ga, Al, Cu or Au metal and their metal alloys, which can provide holes to make the nanowire become P-type nanowire and become the channel of PFET.

[0021] Preferably, the source and drain metals described in step 8) need to form a relatively small Schottky barrier with the nanowires, the metal connected to the N-type nanowires is a metal or metal alloy such as Ti, Al, Ag, Pb or Ga, and the metal connected to the P-type nanowires is a metal or metal alloy such as Pt, Au, Ni, Pd, or Co; different types of nanowires can change the channel length according to the distance between the source and drain metals, thereby adjusting the performance of different types of devices to match.

[0022] Preferably, in step 9), the gate film is Al, Ni, Ti, Au, Pt or Cr and metal alloys, or polysilicon.

[0023] The present invention also provides a logic device, which is composed of the CFET structure prepared by the above method, and is characterized in that it includes an NMOS composed of the NFET and a PMOS composed of the PFET, the NMOS and the PMOS are provided with a common gate constituting the input end of the logic device, the NMOS is provided with a first separate electrode for grounding, the PMOS is provided with a second separate electrode for connecting to a power supply, and a common electrode for the output end of the logic device is provided between the NMOS and the PMOS.

[0024] The present invention also provides a method for preparing the above logic device, which is characterized by: 1) Prepare a CFET structure with 2 steps and 2 catalyst types; 2) The same type of nanowires in the same step are connected with separate electrodes, and the sides of different steps are connected with different types of crystalline doped nanowires with common electrodes to form the output end of the logic device; Alternatively, separate electrodes are formed by photolithographically defining and evaporating separation metal at each step and side corner, and common electrodes are formed by photolithographically defining and evaporating metal at the parallel stacking of all nanowires on the step side, which is beneficial to reducing the horizontal projection area of ​​the device and improving the integration density of the device; 3) Deposit a gate dielectric layer on the entire sample surface, define the gate patterns connected on all steps through photolithography, and evaporate metal to form a common gate for the input end of the logic device.

[0025] The various technical solutions provided in this application have at least the following technical effects or advantages: 1. The present invention adopts modern micro-machining technology to prepare a stepped stack, and uses IPSLS and other methods to grow a groove-guided ultra-fine doped crystalline nanowire three-dimensional stacked array at low temperature (< 350°C) without a wafer substrate, wherein the size of the nanowire is determined by the thickness d of the deposited dielectric layer B. B and the etched trench depth t jointly limit the thickness d BBoth the size and depth t can be controlled at the nanometer level, and ultra-fine crystalline nanowire channels can be prepared without relying on high-precision lithography.

[0026] 2. The present invention realizes self-stratified addressable three-dimensional stacked silicon nanowire integration, which can improve the integration density. Initially, all nanowires are stacked in parallel in the same plane, and turn when encountering a step-shaped corner, thereby realizing self-stratification of the nanowires. The vertical projection spacing between adjacent nanowires is determined by the thickness d of the deposited dielectric layer A. A The horizontal projection spacing of the nanowires between adjacent steps is defined by the step width w, and the number of nanowires in each step is defined by the step height h. These parameters can be controlled at the order of tens of nanometers, which greatly improves the integration density of the device. The stepped groove obtained by slope-type stacking etching, the horizontal projection spacing of the nanowires between adjacent steps is defined by spacing, and the number of nanowires in each step is 1, which can further improve the integration density of three-dimensional stacked nanowires and the density of addressable devices.

[0027] 3. The CFET preparation method proposed in the present invention can adjust the device performance in different steps to meet different needs by controlling the number of nanowires, channel length, source and drain metal types, and gate film types in each step. At the same time, by adjusting the deposition cycle of the stack and the etching of the stepped stack grooves, it can make full use of the three-dimensional space to achieve the stacking of PFET and NFET, further improving the number and device density of CFET in three-dimensional integration.

[0028] 4. The inverter prepared based on CFET of the present invention can realize the preparation of the inverter in the same vertical plane, reducing the occupied projected area, simplifying the preparation process, and greatly improving the integration density and reducing power consumption.

[0029] 5. The present invention is conducive to the realization of monolithic three-dimensional integration. Whether it is the preparation of CFET or various three-dimensional integrated devices prepared based on self-layered addressable three-dimensional stacked nanowires, different types of channels of all devices can be grown and prepared at one time in PECVD, so as to realize multi-layer stacking of CFET in the three-dimensional direction and achieve addressability. Since the channels of all devices can be prepared and passivated at one time, there is no need to bond different chips / wafers through hybrid bonding and other technologies to increase the number of stacking layers, and there is no need to transfer or cyclically deposit dielectric layers to prepare devices layer by layer, which effectively avoids the influence of the thermal effect of the upper device on the bottom device, reduces the thermal budget, and greatly simplifies the preparation process, greatly improves the stability and reliability of the process, and can be used as an efficient way for monolithic three-dimensional integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 It is a schematic diagram of a process and structure for forming a stepped stacked groove based on step etching and realizing self-layered addressability of three-dimensional stacked nanowires in one embodiment of the present invention; Figure 2 It is a schematic diagram of the process and structure of forming a stepped stacked groove based on slope etching and realizing self-layered addressability of three-dimensional stacked nanowires in one embodiment of the present invention; Figure 3 It is a schematic diagram of the process and structure of preparing CFET and inverter devices based on stepped stacked trenches in one embodiment of the present invention; Figure 4 It is a schematic diagram and a side structural diagram of an inverter prepared by integrating NFET and PFET in a vertical plane in one embodiment of the present invention; In the figure: 101, substrate; 102, silicon oxide; 103, silicon nitride; 104, etched silicon nitride guide groove; 105, catalytic metal indium ball; 106, crystalline nanowire; 107, silicon oxide gate dielectric layer; 108, metal connection for addressing; 201, catalytic metal bismuth for growth of N-type nanowire; 202, catalytic metal indium for growth of P-type nanowire; 203, N-type nanowire; 204, P-type nanowire; 205, source and drain metal for connecting nanowires; 206, gate dielectric layer; 207, gate film; 208, common electrode; 209, separated electrode. DETAILED DESCRIPTION

[0032] The present invention aims at the insufficiency or disadvantage of the prior art, and utilizes the preparation of the stepped stacked groove and the nanowire growth method of IPSLS to realize the integration of self-layered addressable three-dimensional stacked nanowires and facilitate the preparation of addressable three-dimensional integrated devices, which can greatly improve the integration density and enhance the device performance. At the same time, the present invention proposes a preparation method of CFET based on the stepped three-dimensional stacked nanowires, using different catalytic metals to grow different types of nanowires in different step layers, and then photolithographically define and prepare the source and drain metals for each step, and deposit the gate dielectric layer and the gate film layer, which can prepare multi-layer channels through one growth, thereby realizing the multi-layer stacking of CFET in the three-dimensional direction and achieving addressability, greatly improving the integration density of the device, simplifying the preparation process, process stability and reliability. Further, by connecting the source and drain metals and the gate film layer on the same side of the adjacent upper and lower steps, an inverter device based on CFET can be prepared; further, the inverter can be prepared where all the nanowires are stacked in parallel on the side of the step, that is, where the number of grooves is the largest in the vertical direction, which is conducive to reducing the projection area of ​​the device in the horizontal direction and improving the integration density of the device.

[0033] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods. Example

[0034] This embodiment provides a self-layered addressable three-dimensional stacked nanowire integration based on stepped stacked grooves, including a method for preparing CFET, such as Figure 1 As shown, it includes the following steps: In the first step, a stack of silicon oxide 102 and silicon nitride 103 is alternately deposited in sequence on a silicon oxide wafer substrate 101 using a plasma enhanced chemical vapor deposition (PECVD) technique. This embodiment takes 6 cycles as an example, i.e., there are 6 layers of silicon oxide 102 and 6 layers of silicon nitride 103 from top to bottom (excluding the silicon oxide deposited at the bottom layer).

[0035] In this embodiment, in order to obtain nanowires with a diameter less than 20 nm, the thickness d of the silicon nitride 103 is B The thickness of silicon oxide 102 is set to 20 nm. A Set to 20nm according to the preparation requirements, such as Figure 1 As shown in Figure (a).

[0036] In the second step, the mask pattern is transferred to the stack by photolithography technology, and C4F8 is used to anisotropically etch the heterogeneous stack by reactive coupled plasma (ICP). The etching depth each time includes 2 stacking cycles, and the step height is about 80nm. O2 is used to isotropically shrink the photoresist to make the photoresist etch back. Each etching is about 50nm, that is, the step width is 50nm. After 3 cycles, the photoresist is removed to form a step-type silicon oxide and silicon nitride stack and expose the side structure, such as Figure 1 As shown in Figure (b); In the third step, the obtained step-type stacked structure is placed in a hot phosphoric acid solution, the phosphoric acid content is >85%, the temperature of the hot phosphoric acid is 140°C, the etching ratio of hot phosphoric acid to silicon nitride and silicon oxide is about 50:1, and after being placed in the hot phosphoric acid solution for 5 minutes, the etched groove depth t is about 30nm, and the etched silicon nitride guide groove 104 is obtained, thereby obtaining a step-type stacked groove, such as Figure 1 Figure (c) in .

[0037] In the fourth step, the catalytic metal region is positioned at one end of the side of the stepped stacked groove (the side with the largest number of grooves in the vertical direction) by using photolithography technology, and a 5 nm catalytic metal indium In film is deposited by thermal evaporation; the temperature is raised to above the melting point of the catalytic metal in PECVD, and a reducing hydrogen plasma is introduced for treatment to transform the metal indium In film into separated catalytic metal indium balls 105, as shown in FIG. Figure 1 As shown in Figure (d); In the fifth step, the temperature is lowered to below the melting point of the catalytic metal particles in the PECVD system, and a 10 nm thick amorphous silicon (a-Si) film layer is covered on the entire surface of the structure; then the temperature is raised to above the eutectic point of the catalytic metal and the amorphous film layer, and the catalytic metal droplets begin to absorb amorphous silicon at their front end, and crystalline nanowires 106 are deposited at the rear end. Since the catalytic metal indium balls need to absorb the amorphous silicon in the grooves, the catalytically grown crystalline silicon nanowires are also confined in the grooves. When encountering the corners of the stepped stacked grooves, the nanowires will turn and enter the grooves of each step to continue growing, realizing the self-stratification of the nanowires, which is convenient for the subsequent discrete connection and addressing of the nanowires and devices of each step, such as Figure 1 As shown in Figure (e), the arrow in the figure indicates the growth direction of the nanowires.

[0038] In the sixth step, carbon tetrafluoride (CF4) in RIE is used for dry etching to remove amorphous silicon, and then annealed at 850 ° C for 8 min in an O2 atmosphere in a tubular annealing furnace to passivate the crystalline nanowires with high quality.

[0039] In the seventh step, the nanowires on each step can be used to prepare devices. The steps of preparing devices are shown in the subsequent embodiments and are omitted here. A 300nm silicon oxide gate dielectric layer 107 is covered on the entire sample surface, and a metal connection 108 for addressing is prepared by TSV silicon through-holes and metal injection to connect the nanowires in each step, so as to achieve the addressability of the nanowires and devices on each step, such as Figure 1 As shown in Figure (f), it can be used in high-density three-dimensional integrated devices such as logic, sensing, and storage. Example

[0040] This embodiment provides a self-layered addressable three-dimensional stacked nanowire integration based on stepped stacked grooves, including a method for preparing CFET, such as Figure 2 As shown, it includes the following steps: In the first step, a stack of silicon oxide 102 and silicon nitride 103 is alternately deposited in sequence on a substrate 101 (such as a silicon oxide wafer) using a plasma enhanced chemical vapor deposition (PECVD) technique. In this embodiment, six cycles are taken as an example, i.e., there are six layers of silicon oxide 102 and six layers of silicon nitride 103 from top to bottom (excluding the silicon oxide deposited at the bottom layer).

[0041] In this embodiment, in order to obtain nanowires with a diameter less than 20 nm, the thickness d of the silicon nitride 103 is B The thickness of silicon oxide 102 is set to 20 nm. A It is set to 20nm according to the preparation requirements.

[0042] In the second step, the mask pattern is transferred to the stack by photolithography technology, and ion beam etching (IBE) is performed using Ar plasma to perform angled etching to form a sloped stack and expose the side structure, such as Figure 2 As shown in Figure a) in the figure; the angle of ion beam etching is θ, and the horizontal projection spacing between adjacent homogeneous dielectric layers (i.e., the horizontal projection spacing between adjacent nanowires) is arctanθ·(d A +d B ),like Figure 2 (b) shows a side view of the slope type stack; In the third step, the obtained sloped stacked structure is placed in a hot phosphoric acid solution, the phosphoric acid content is >85%, the temperature of the hot phosphoric acid is 140°C, the etching ratio of hot phosphoric acid to silicon nitride and silicon oxide is about 50:1, and after being placed in the hot phosphoric acid solution for 5 minutes, the etched groove depth t is about 30nm, and the etched silicon nitride guide groove 104 is obtained, thereby obtaining a stepped stacked groove, such as Figure 2As shown in Figure (c), Figure 2 Figure (d) shows a side view of a stepped sidewall trench structure obtained by slope stack etching.

[0043] The fourth step is to use photolithography technology to locate the catalytic metal area at one end of the side of the stepped stacked groove (the side with the largest number of grooves in the vertical direction), and use thermal evaporation to deposit a 5nm thick catalytic metal indium In film; raise the temperature to above the melting point of the catalytic metal in PECVD, and introduce reducing hydrogen plasma for treatment to transform the In film into separated catalytic metal indium balls.

[0044] In the fifth step, the temperature is lowered to below the melting point of the catalytic metal particles in the PECVD system, and a 10 nm thick amorphous silicon (a-Si) film layer is covered on the entire surface of the structure; then the temperature is raised to above the eutectic point of the catalytic metal and the amorphous film layer, and the catalytic metal indium ball droplets begin to absorb amorphous silicon at their front end, and crystalline nanowires 106 are deposited at the rear end. Since the catalytic metal indium balls need to absorb the amorphous silicon in the grooves, the catalytically grown crystalline nanowires are also confined in the grooves. When encountering the corners of the stepped stacked grooves, the nanowires will turn and enter the grooves of each step to continue growing, thereby realizing self-stratification of the nanowires, which is convenient for subsequent discrete connection and addressing of the nanowires and devices on each step, such as Figure 2 As shown in Figure (e), the arrow in the figure indicates the growth direction of the nanowires.

[0045] In the sixth step, carbon tetrafluoride (CF4) in RIE is used for dry etching to remove amorphous silicon, and then annealed at 850 ° C for 8 min in an O2 atmosphere in a tubular annealing furnace to passivate the crystalline nanowires with high quality.

[0046] In the seventh step, the nanowires on each step can be used to prepare devices. The steps of preparing devices will be shown in the subsequent embodiments and are omitted here. A 300nm silicon oxide gate dielectric layer 107 is covered on the entire sample surface, and TSV silicon through holes and metal injection are used to connect the nanowires in each step, so as to achieve addressability of the nanowires and devices on each step, such as Figure 2 As shown in Figure (f), the self-stratified addressable three-dimensional stacked nanowire integration based on slope-type lamination can greatly improve the integration density of the device and can be used in high-density three-dimensional integrated devices such as logic, sensing, and storage. Example

[0047] This embodiment provides a CFET preparation method based on a stepped stacked trench, the structure of which is as follows Figure 3 As shown, this embodiment adopts a step-type trench preparation method similar to that in Embodiment 1, which specifically includes the following steps: 1) The number of steps of the step-shaped groove prepared in this embodiment is 2, and each step contains 3 periods of stacking, that is, the step height is 3·(d A +d B ), the step width is set to 200nm, such as Figure 3 As shown in Figure (a), the hot phosphoric acid etching method is also used to prepare a two-layer stepped stacked trench, such as Figure 3 As shown in Figure (b); 2) Photolithography is performed to define the catalytic metal area at each step protrusion (the side and the step corner) and different catalytic metals are evaporated in batches. The catalytic metal indium 202 for the growth of P-type nanowires is evaporated at the corner between the first step and the side, and the catalytic metal bismuth 201 for the growth of N-type nanowires is evaporated at the corner between the second step and the side. The temperature is raised to above the melting point of bismuth metal in PECVD, and a reducing hydrogen plasma is introduced for treatment to transform the catalytic metal into separated metal droplets, such as Figure 3 As shown in Figure (c); 3) In the PECVD system, the temperature is lowered to below the melting point of indium metal, and a 10 nm thick amorphous silicon (a-Si) thin film layer is covered on the entire surface of the structure; then the temperature is raised so that the catalytic metal droplets begin to absorb amorphous silicon at their front end, and crystalline silicon nanowires are deposited at the rear end; due to the self-doping effect of the catalytic metal in the nanowires, indium acts as an acceptor impurity in the silicon nanowires, so the catalytic metal In balls will grow P-type nanowires 204 in the sidewall grooves, and the metal bismuth Bi acts as a donor impurity in the silicon nanowires, so the catalytic metal Bi balls will grow N-type nanowires 203 in the sidewall grooves, and when encountering the corners of the stepped stacked grooves, they turn, thereby transforming from layered growth in different steps to parallel growth in the same vertical plane, realizing vertical three-dimensional stacking of different types of nanowires, such as Figure 3 As shown in Figure (d), P-type silicon nanowires are grown in the three grooves of the lower step, and N-type silicon nanowires are grown in the three grooves of the upper step. The arrows in the figure indicate the growth direction of the nanowires.

[0048] 4) The amorphous silicon was removed by dry etching using carbon tetrafluoride (CF4) in RIE, and then the nanowires were passivated with high quality by annealing at 850 °C for 8 min in an O2 atmosphere in a tubular annealing furnace.

[0049] 5) Photolithography is performed at each step to define the source and drain metal patterns, and BOE or HF solution of appropriate concentration (such as 4%) is used to remove the surface oxide layer and evaporate the source and drain metal 205 used to connect the nanowires to connect different types of nanowires, such as Figure 3As shown in Figure (e); the source and drain metals 205 used to connect the nanowires here are just unified labels for the source and drain metals. If different metals need to be evaporated to reduce the Schottky barrier in contact with the nanowires, photolithography, oxide layer removal, and metal evaporation can be performed in batches; in this embodiment, 12nm thick Ti and 40nm thick Al can be used to connect the N-type nanowires in the three grooves of the upper step, so that NFET can be prepared on the upper step, and 12nm thick Pt and 40nm thick Au can be used to connect the P-type nanowires in the three grooves of the lower step, so that PFET can be prepared on the lower step, realizing three-dimensional stacking of NFET and PFET, which is beneficial to the integration of CFET.

[0050] 6) A gate dielectric layer 206 is covered on the entire sample surface, and a gate pattern is defined by photolithography at each step, and a separate gate film 207 is locally deposited by evaporation or sputtering process. The gate dielectric layer 206 and the gate film 207 here are just unified labels for the gate dielectric and the gate film. In this embodiment, a 3nm aluminum oxide and 8nm hafnium oxide heterostructure can be used as the gate dielectric, and a 60nm Al or Ni metal film can be used as the gate. Figure 3 As shown in Figure (f).

[0051] This embodiment utilizes differently doped nanowires in different step layers to prepare NFET and PFET respectively on the steps, realizing the stacked integration of CFET in three-dimensional directions. At the same time, different types of nanowires will turn at the corners of the steps and gather in the same vertical plane, which is beneficial to improve the integration density and further improve the device performance of CFET, and is expected to be applied to three-dimensional logic devices and the manufacturing of new generation chips. Example

[0052] This embodiment provides a method for preparing an inverter based on a stepped stacked CFET, such as Figure 3 Figure (g), Figure (h) and Figure 4 As shown: In this embodiment, an inverter is prepared at the side of the stepped stacked trench, and the nanowires grown in layers in different steps are transformed into parallel growth in the same vertical plane, which is beneficial to reduce the horizontal projection area of ​​the device and improve the integration density of the device. Based on the different types of nanowires prepared and grown in Example 3.

[0053] In this embodiment, in step 5) of embodiment 3, the metal on one side of the upper and lower steps is connected to form a common electrode 208, and the other side is still connected with separate metal to form a separate electrode 209. Figure 3 As shown in Figure (g).

[0054] Then, in step 6) of embodiment 3, the gate pattern connected to the side is defined by photolithography and the gate film 207 is evaporated to form a common gate used as the input end of the inverter, such as Figure 3 As shown in Figure (h).

[0055] Figure 4 Figure (a) shows a simplified schematic diagram of the inverter prepared in this embodiment, which is used for comparison with Figure (b) on the right. Figure (b) is a side view of the inverter prepared in this embodiment, wherein the PFET of the lower step is used as the PMOS in the schematic diagram of Figure (a), and the NFET of the upper step is used as the NMOS in the schematic diagram of Figure (a). The separated electrode in the PFET is used as the operating voltage VDD of the inverter, the separated electrode in the NFET is used as the ground terminal GND of the inverter, the common electrode in the CFET is used as the output terminal Vout of the inverter, and the common gate in the CFET is used as the input terminal Vin of the inverter.

[0056] For example, the use of a Gate all around (GAA) structure can further improve the performance of nanowire devices in the stepped layer, but this is not the core idea and innovation of the present invention. It is only a structural improvement based on the present invention. The description of the above embodiments is used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope, and these improvements should also be regarded as the protection scope of the present invention.

Claims

1. A method for preparing a self-stratified addressable three-dimensional stacked nanowire integration, characterized in that: The steps include: 1) Using positive photolithography process, the mask channel pattern is transferred to a substrate with a periodic heterogeneous stacked structure deposited alternately and cyclically; 2) etching the heterogeneous stacked structure into a step-type or slope-type stacked structure by cyclic anisotropic etching and isotropic shrinkage etching or angled plasma etching; 3) selectively etching one of the dielectric layers to form a stepped guide trench structure; 4) depositing a strip-shaped catalytic metal layer at the end of the side surface of the guide groove structure having the largest number of grooves in the vertical direction; 5) In a PECVD system, the temperature is raised to above the melting point of the catalytic metal, and a reducing gas is used for plasma treatment to remove the oxide layer on the surface of the catalytic metal and form metal nanoparticles; 6) The temperature is lowered to below the melting point of the catalytic metal particles, and the amorphous semiconductor precursor film is covered on the entire surface of the sample; then annealing is performed, and the front end of the catalytic metal droplet begins to absorb the amorphous semiconductor precursor film layer, and the rear end deposits crystalline doped nanowires. When the catalytic metal moves to the step corner on the side of the guide groove structure, the catalytic metal ball turns to continue absorbing the amorphous semiconductor precursor film, thereby achieving self-stratification of the crystalline doped nanowires; 7) After removing the remaining amorphous semiconductor precursor film layer on the sample surface, the surface of the crystalline doped nanowires is passivated; 8) A gate dielectric layer is deposited on the entire sample surface, and a hole is opened at each step and then metal is injected to achieve connection with the crystalline doped nanowires, thereby achieving integration and addressability of the nanowire devices on each step.

2. The method for preparing a self-layered addressable three-dimensional stacked nanowire integration according to claim 1, characterized in that: In step 1), the heterogeneous stacked structure is a dielectric layer B and a dielectric layer A with different etching selectivities, the etching selectivity of the dielectric layer B to the dielectric layer A is greater than 5:1, and the thickness of the dielectric layer A is d A , the thickness of dielectric layer B is d B .

3. The method for preparing a self-layered addressable three-dimensional stacked nanowire integration according to claim 2, characterized in that: In step 2), the steps of preparing the step-type stacked structure include: 1) Anisotropic etching, define the height h of each step, h is the thickness of the stack of n periods, that is, h = n·(d A +d B ), used for the subsequent growth of nanowires, each step height h corresponds to n nanowires; 2) Isotropic shrinkage is used to shrink the size of the photoresist to expose the required step width w of the etching, and the step width w corresponds to the horizontal projection spacing of the nanowires in different steps.

4. The method for preparing a self-layered addressable three-dimensional stacked nanowire integration according to claim 1, characterized in that: In step 4), the catalytic metal layer is evaporated on the side of the stepped guide groove structure away from the end of the step, and the catalytic metal is one of In, Sn, Bi, Ga metals or metal alloys thereof.

5. The method for preparing a self-layered addressable three-dimensional stacked nanowire integration according to claim 1, characterized in that: In step 6), the amorphous semiconductor precursor film is amorphous silicon a-Si, amorphous germanium a-Ge, amorphous carbon aC or a-Ge / a-Si heterogeneous stacked structure.

6. A method for preparing a CFET structure by integrating the self-layered addressable three-dimensional stacked nanowires according to claim 1, characterized in that: The following steps are involved: 1) Using positive photolithography process, the mask channel pattern is transferred to a substrate with a periodic heterogeneous stacked structure deposited alternately and cyclically; 2) etching the heterogeneous stacked structure into a step-type or slope-type stacked structure by cyclic anisotropic etching and isotropic shrinkage etching or angled plasma etching; 3) selectively etching one of the dielectric layers to form a stepped guide trench structure; 4) performing photolithographic definition and evaporating different catalytic metals step by step at the connection between one end and the side of each step; 5) In a PECVD system, the temperature is simultaneously raised to above the melting point of the catalyst metal with the highest melting point value, and a reducing gas is used for plasma treatment to remove the surface oxide layer and form metal nanoparticles of the catalyst metal; 6) Then, the temperature is simultaneously lowered to below the melting point of the catalytic metal particles with the lowest melting point value, and the amorphous semiconductor precursor film is covered on the entire sample surface; then, annealing treatment is performed, and the front end of the catalytic metal droplet begins to absorb the amorphous semiconductor precursor film layer. Due to the self-doping effect of the catalytic metal, some catalytic metal atoms enter the nanowires, and crystalline doped nanowires are deposited at the rear end. Since the catalytic metal grows simultaneously in different steps, the self-stratification of the crystalline doped nanowires is automatically achieved. When the catalytic metal moves to the end of the step and the side corner, the catalytic metal ball turns to achieve the parallel stacking growth of different types of crystalline doped nanowires on the same side; 7) After removing the remaining amorphous semiconductor precursor film layer on the sample surface, the surface of the crystalline doped nanowires is passivated; 8) Photolithography defines the source and drain metal patterns on each step’s independent vertical surface, removes the surface oxide layer and evaporates separate source and drain metals to connect different types of crystalline doped nanowires; 9) A gate dielectric layer is deposited on the entire sample surface, and the gate pattern is defined by photolithography and a separate gate film is deposited on each step independently vertically to complete the preparation of the CFET structure.

7. The method for preparing a CFET structure by integrating self-layered addressable three-dimensional stacked nanowires according to claim 6, characterized in that: In step 4), the type of catalytic metal is t, t ≥ 2, and different catalytic metals are evaporated separately on the vertical surface of each step end, and at least one catalytic metal acts as a donor impurity to provide electrons to generate an N-type nanowire that becomes a channel of an NFET, and at least one catalytic metal acts as an acceptor impurity to provide holes to generate a P-type nanowire that becomes a channel of a PFET.

8. The method for preparing a CFET structure by integrating self-layered addressable three-dimensional stacked nanowires according to claim 7, characterized in that: The source and drain metals are electrically connected to the external circuit by injecting metal after opening holes, so as to achieve addressability of the device on each step; different source and drain metal distances are set to adjust the channel lengths of different types of crystalline doped nanowires, so as to adjust the performance of different types of devices to match.

9. A logic device, comprising the CFET structure prepared according to claim 7, characterized in that: It includes an NMOS composed of the NFET and a PMOS composed of the PFET, wherein the NMOS and the PMOS are provided with a common gate constituting the input terminal of the logic device, the NMOS is provided with a first separate electrode for grounding, the PMOS is provided with a second separate electrode for connecting to a power supply, and a common electrode for the output terminal of the logic device is provided between the NMOS and the PMOS.

10. A method for preparing a logic device, applicable to the logic device according to claim 9, characterized in that: 1) Prepare a CFET structure with 2 steps and 2 catalyst types; 2) The same type of nanowires in the same step are connected with separate electrodes, and the sides of different steps are connected with different types of crystalline doped nanowires with common electrodes to form the output end of the logic device; Alternatively, separate electrodes are formed by photolithographically defining and evaporating separation metals at the corners of each step and the side, and common electrodes are formed by photolithographically defining and evaporating metals at the parallel stacking locations of all nanowires on the side of the step; 3) Deposit a gate dielectric layer on the entire sample surface, define the gate patterns connected on all steps through photolithography, and evaporate metal to form a common gate for the input end of the logic device.

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