Radio frequency germanium-on-insulator wafer and manufacturing method thereof

Abstract

The invention belongs to the technical field of semiconductors, and discloses a radio frequency germanium-on-insulator wafer and a manufacturing method thereof. The method comprises the steps of forming a donor substrate, wherein the donor substrate comprises a silicon substrate, an etching barrier layer, a germanium layer and a negative capacitance material layer which are stacked in sequence; forming an acceptor substrate, wherein the acceptor substrate comprises an RF-SOI substrate and a silicon dioxide layer which are stacked in sequence; performing wafer bonding on the negative capacitance material layer of the donor substrate and the silicon dioxide layer of the acceptor substrate; removing the silicon substrate; and removing the etching barrier layer to obtain the germanium wafer on the radio frequency insulator. The radio frequency germanium-on-insulator wafer prepared by the method has excellent signal transmission performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a radio frequency germanium-on-insulator wafer and a method for manufacturing the same. Background Art

[0002] With the rapid development of information technology, the performance requirements for semiconductor materials are increasing. As a new type of substrate material, Germanium-on-Insulator (GOI) material has shown great application prospects because it combines the dual advantages of germanium (Ge) material and silicon-on-insulator (SOI) material. GOI material can not only significantly improve the mobility of channel electrons and holes, reduce parasitic capacitance, thereby improving device performance, but also show good uniformity over a large area, effectively reduce manufacturing costs and improve production efficiency. These characteristics make GOI materials have significant advantages in the manufacture of optoelectronic integrated chips, providing a solid foundation for large-scale production and wide application. However, although GOI materials have many advantages in theory, in practical applications, GOI optoelectronic integrated chips prepared based on existing GOI wafer technology have some technical challenges. In terms of signal transmission performance, GOI optoelectronic integrated chips perform poorly, and are prone to signal distortion and signal attenuation. Especially in high-frequency environments, the integrity of the signal is difficult to guarantee, and it cannot meet the stringent requirements of radio frequency communication for signal quality. In addition, when transmitting RF signals, GOI optoelectronic integrated chips will produce high insertion loss, which hinders the improvement of the performance of the entire communication system. At the same time, when processing large signals, the linearity of GOI optoelectronic integrated chips is poor, resulting in the inability to accurately restore the signal, which in turn affects the reliability and stability of the communication system. These problems have largely limited the expansion of GOI optoelectronic integrated chips in high-speed data transmission and multi-band communication applications in new generation communication technologies such as 5G.

[0003] In summary, although GOI materials have significant advantages in theory, they still face many technical challenges in practical applications, especially in terms of signal transmission performance, RF signal transmission loss and linearity. Solving these problems is crucial for the application of GOI optoelectronic integrated chips in 5G communication technology, and is also the focus of current research and development work. Summary of the invention

[0004] To this end, an embodiment of the present application provides a radio frequency germanium-on-insulator wafer and a method for manufacturing the same. The radio frequency germanium-on-insulator wafer prepared by the method has excellent signal transmission performance.

[0005] In a first aspect, the present application provides a method for manufacturing a radio frequency germanium-on-insulator wafer.

[0006] This application is achieved through the following technical solutions:

[0007] A method for manufacturing a radio frequency germanium-on-insulator wafer, comprising:

[0008] forming a donor substrate, wherein the donor substrate comprises a silicon substrate, an etching stop layer, a germanium layer and a negative capacitance material layer stacked in sequence;

[0009] forming a receptor substrate, the receptor substrate comprising an RF-SOI substrate and a silicon dioxide layer stacked in sequence;

[0010] Wafer bonding the negative capacitance material layer of the donor substrate to the silicon dioxide layer of the acceptor substrate;

[0011] removing the silicon substrate;

[0012] The etching stop layer is removed to obtain a radio frequency germanium-on-insulator wafer.

[0013] In a preferred example of the present application, it can be further configured that the material of the etch stop layer is at least one of heavily doped Si, heavily doped SiGe, heavily doped Si / SiGe composite material, heavily doped Si multilayer stack material, heavily doped SiGe multilayer stack material or heavily doped Si / SiGe multilayer stack material.

[0014] In a preferred example of the present application, it can be further configured that the material of the etch stop layer is at least one of SiGeC, SiGeCB, SiGeC / SiGeCB composite material, SiGeC multilayer material, and SiGeCB multilayer material.

[0015] In a preferred example of the present application, it can be further configured that the thickness of the etching stop layer is 0.01 μm to 0.5 μm.

[0016] In a preferred example of the present application, it can be further configured that the material of the negative capacitance material layer includes Hf 0.5 Zr 0.5 At least one of O2, BaTiO3, PZT, LiNbO3, SrRuO3, SrTiO3, PbTiO3, (Pb, Sr)TiO3 / SrTiO3 (PST / STO) superlattice or (Ba, Sr)TiO3 / LaAlO3 superlattice.

[0017] In a preferred example of the present application, it can be further configured that the thickness of the negative capacitance material layer is 0.01 μm to 1.0 μm.

[0018] In a preferred example of the present application, it can be further configured that the method of removing the silicon substrate includes one or a combination of mechanical thinning, dry etching, chemical mechanical polishing, wet etching and oxidation.

[0019] In a preferred example of the present application, it can be further configured that removing the etching stop layer includes:

[0020] The etch stop layer is removed by chemical mechanical polishing.

[0021] In a second aspect, the present application provides a radio frequency germanium-on-insulator wafer.

[0022] This application is achieved through the following technical solutions:

[0023] A radio frequency germanium-on-insulator wafer is prepared by the method for manufacturing a radio frequency germanium-on-insulator wafer according to the first aspect, comprising:

[0024] RF-SOI substrate;

[0025] A silicon dioxide layer is disposed on the surface of the RF-SOI substrate;

[0026] A negative capacitance material layer, wherein the negative capacitance material layer is bonded to the silicon dioxide layer;

[0027] The germanium layer is arranged on the surface of the negative capacitance material layer.

[0028] In a preferred example of the present application, it can be further configured that the material of the negative capacitance material layer includes Hf 0.5 Zr 0.5 At least one of O2, BaTiO3, PZT, LiNbO3, SrRuO3, SrTiO3, PbTiO3, (Pb, Sr)TiO3 / SrTiO3 (PST / STO) superlattice or (Ba, Sr)TiO3 / LaAlO3 superlattice.

[0029] In a preferred example of the present application, it can be further configured that the thickness of the negative capacitance material layer is 0.01 μm to 1.0 μm.

[0030] In summary, compared with the prior art, the technical solution provided in the embodiment of the present application has at least the following beneficial effects:

[0031] The present application provides a method for manufacturing a radio frequency germanium-on-insulator wafer, the method comprising forming a donor substrate, the donor substrate comprising a silicon substrate, an etch barrier layer, a germanium layer and a negative capacitance material layer stacked in sequence; forming an acceptor substrate, the acceptor substrate comprising an RF-SOI substrate and a silicon dioxide layer stacked in sequence; wafer bonding the negative capacitance material layer of the donor substrate to the silicon dioxide layer of the acceptor substrate; removing the silicon substrate; and removing the etch barrier layer to obtain the radio frequency germanium-on-insulator wafer. Since the RF-SOI substrate has good RF signal transmission performance, lower insertion loss, higher signal integrity and excellent linearity, the RF germanium-on-insulator wafer made on this basis has better signal transmission performance; introducing a negative capacitance material layer between the top germanium layer and the SiO2 buried oxide layer can enhance the overall capacitance characteristics, help to further reduce signal transmission delay in high-frequency environments, improve signal response speed, and enable signals to be processed more quickly, thereby improving the high-frequency performance of the entire germanium wafer; the presence of negative capacitance can compensate for nonlinear changes to a certain extent and improve the linearity of the RF-GOI chip. The negative capacitance material can help maintain the linear working state of the device, so that the output signal can more accurately reflect the changes in the input signal, thereby improving the fidelity of the signal; in addition, introducing an etching barrier layer during the manufacturing process can increase the tolerance of the etching process, improve the surface uniformity of the wafer, and thereby improve the transmission performance of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic flow chart of a method for manufacturing a radio frequency germanium-on-insulator wafer provided in one embodiment of the present application;

[0033] Figure 2 A schematic diagram of the structure of a donor substrate and an acceptor substrate provided in an embodiment of the present application;

[0034] Figure 3 A schematic diagram of the structure of a radio frequency germanium-on-insulator wafer during the manufacturing process provided by an embodiment of the present application;

[0035] Figure 4 A schematic diagram of the structure of a radio frequency germanium-on-insulator wafer provided in one embodiment of the present application;

[0036] Description of reference numerals:

[0037] Donor substrate 1, silicon substrate 11, etch stop layer 12, germanium layer 13, negative capacitance material layer 14, acceptor substrate 2, RF-SOI substrate 21, silicon dioxide layer 22. DETAILED DESCRIPTION

[0038] This specific embodiment is merely an explanation of the present application and is not a limitation of the present application. After reading this specification, those skilled in the art may make modifications to the present embodiment without any creative contribution as needed, but such modifications are protected by the patent law as long as they are within the scope of the claims of the present application.

[0039] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0040] In addition, the term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application, unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0041] In this application, the terms "first", "second", etc. are used to distinguish identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there any limitation on quantity and execution order.

[0042] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0043] The embodiments of the present application are further described in detail below in conjunction with the drawings in the specification.

[0044] like Figure 1 As shown, a method for manufacturing a radio frequency germanium-on-insulator wafer provided by a first exemplary embodiment of the present application includes:

[0045] S1: forming a donor substrate, wherein the donor substrate comprises a silicon substrate, an etching stop layer, a germanium layer and a negative capacitance material layer stacked in sequence.

[0046] Reference Figure 2 a. In the embodiment of the present application, the donor substrate 1 includes, from bottom to top, a silicon substrate 11, an etching stop layer 12, a germanium layer 13 and a negative capacitance material layer 14.

[0047] Specifically, the silicon substrate 11 is the basis of the donor substrate 1, and provides a platform for the subsequent deposition of the etching stop layer 12, the germanium layer 13, and the negative capacitance material layer 14. The silicon substrate 11 is selected from high-purity single crystal silicon.

[0048] The etching stopper layer 12 plays a protective role in the manufacturing process of the germanium wafer on RF insulator to prevent damage to the underlying material during the etching process. The etching stopper material can be deposited on the surface of the silicon substrate 11 by low pressure chemical vapor deposition technology (LPCVD). During the deposition process, the thickness and uniformity of the etching stopper layer 12 are adjusted by controlling process parameters such as deposition time, deposition rate, gas flow rate and ratio, and temperature.

[0049] Exemplarily, the thickness of the etch stop layer may be 0.01 μm to 0.5 μm. For example, it may be 10 nm, 50 nm, 100 nm, 200 nm, 400 nm, or 500 nm. The above values ​​are only for illustration and are not intended to limit the thickness of the etch stop layer.

[0050] The germanium layer 13 is a key layer in the donor substrate, and can be formed on the surface of the etch stop layer 12 by epitaxial growth technology or deposition method of high-purity germanium material. For example, a high-quality germanium layer 13 can be deposited on the surface of the etch stop layer 12 by CVD (chemical vapor deposition). Similarly, a high-quality germanium layer 13 can also be epitaxially grown on the etch stop layer 12 by MBE (molecular beam epitaxy).

[0051] The negative capacitance material layer 14 is made of a material with a dielectric constant to achieve negative capacitance benefits. In specific implementation, the negative capacitance material layer 14 can be deposited on the surface of the germanium layer 13 by atomic layer deposition (ALD) technology. The atomic layer deposition (ALD) technology can accurately control the thickness of the negative capacitance material layer 14, and can make the negative capacitance material layer 14 better attached to the surface of the germanium layer 13.

[0052] S2: forming a receptor substrate, wherein the receptor substrate comprises an RF-SOI substrate and a silicon dioxide layer stacked in sequence.

[0053] Reference Figure 2 b. In the embodiment of the present application, the acceptor substrate 2 includes, from bottom to top, an RF-SOI substrate 21 and a silicon dioxide layer 22 .

[0054] In the present application, a commercial RF-SOI substrate 21 is used; silicon dioxide is deposited on the surface of the RF-SOI substrate 21 to form a silicon dioxide film as a silicon dioxide layer 22. Specifically, the silicon dioxide layer 22 can be deposited on the surface of the RF-SOI substrate 21 by low pressure CVD (LPCVD), or by plasma enhanced CVD, or by atomic layer deposition (ALD). The precursor gas used includes, but is not limited to, TEOS (tetraethoxysilane) and SiH4 (silane).

[0055] The thickness and uniformity of the silicon dioxide layer 22 are adjusted by controlling process parameters such as deposition time, deposition rate, gas flow rate and ratio, and temperature during the deposition process.

[0056] The thickness of the silicon dioxide layer 22 can be set to be 10 nm to 2000 nm. The thickness of the silicon dioxide layer depends on the specific application requirements and performance targets. In practical applications, the most suitable thickness can be determined according to the device design and performance requirements.

[0057] The RF-SOI substrate has good RF signal transmission performance, lower insertion loss, higher signal integrity and excellent linearity. The RF germanium-on-insulator wafer prepared using it has high-speed data transmission performance.

[0058] S3: Wafer bonding the negative capacitance material layer of the donor substrate to the silicon dioxide layer of the acceptor substrate.

[0059] Reference Figure 3 a. The donor substrate 1 is flipped upside down, and the negative capacitance material layer 14 of the donor substrate 1 and the silicon dioxide layer 22 of the acceptor substrate 2 are bonded together by direct wafer bonding.

[0060] Exemplarily, before starting bonding, the surface of the negative capacitance material layer 14 and the surface of the silicon dioxide layer 22 are cleaned to remove pollutants such as organic matter, particles, oxide layers, to ensure that both surfaces that need to be bonded are flat and undamaged. Use a precise alignment system to accurately align the negative capacitance material layer 14 of the donor substrate 1 and the silicon dioxide layer 22 of the acceptor substrate 2, and apply a certain pressure and temperature to promote the formation of chemical bonds between the atoms of the two bonding interfaces. After bonding is completed, annealing is required. Adopting a direct wafer bonding method without adhesive, the two bonding surfaces can be closely combined to achieve a firm combination.

[0061] S4: removing the silicon substrate.

[0062] Reference Figure 3 b. After bonding is completed, the silicon substrate 11 is removed.

[0063] The method of removing the silicon substrate 11 includes one or a combination of mechanical thinning, dry etching, chemical mechanical polishing, wet etching and oxidation.

[0064] In the embodiment of the present application, a portion of the silicon substrate 11 is first removed by mechanical thinning, and then the remaining silicon substrate 11 is removed by dry etching, so that an etching stop layer 12 with good surface uniformity can be obtained.

[0065] In the process of removing the silicon substrate 11, the etching barrier layer 12 disposed under the silicon substrate 11 can increase the tolerance of the etching process. In the manufacturing process, the process parameters (such as etching gas flow, etching time, etching temperature, etc.) may fluctuate to a certain extent. The etching barrier layer can compensate for the influence of these fluctuations to a certain extent, so that even if there is a small deviation in the process parameters, the accuracy of etching can be guaranteed, which is beneficial to improving the surface uniformity of the wafer and reducing the difficulty of the RF-GOI wafer manufacturing process.

[0066] S5: removing the etching stop layer, obtaining a germanium layer of target thickness, and obtaining a radio frequency germanium-on-insulator wafer.

[0067] Reference Figure 3 c. Remove the etching stop layer 12 by chemical mechanical polishing (CMP) to expose the germanium layer 13. At the same time, the chemical mechanical polishing (CMP) can be used to etch the germanium layer 13 to reach a preset target thickness.

[0068] The thickness of the germanium layer 13 is in the range of 10 nm to 2000 nm.

[0069] Optionally, the material of the etch stop layer is at least one of heavily doped Si, heavily doped SiGe, heavily doped Si / SiGe composite material, heavily doped Si multilayer stack material, heavily doped SiGe multilayer stack material or heavily doped Si / SiGe multilayer stack material.

[0070] The doping element in the heavily doped Si, heavily doped SiGe, heavily doped Si / SiGe composite material, heavily doped Si multilayer stacked material, heavily doped SiGe multilayer stacked material or heavily doped Si / SiGe multilayer stacked material may be an n-type doping element, such as at least one of the P element and the As element; the doping element may also be a p-type doping element, such as the B element. The Ge content in the heavily doped SiGe does not exceed 10%.

[0071] Optionally, the material of the etch stop layer is at least one of SiGeC, SiGeCB, SiGeC / SiGeCB composite material, SiGeC multilayer material, and SiGeCB multilayer material.

[0072] Optionally, the material of the negative capacitance material layer includes Hf 0.5 Zr 0.5 At least one of O2, BaTiO3, PZT, LiNbO3, SrRuO3, SrTiO3, PbTiO3, (Pb, Sr)TiO3 / SrTiO3 (PST / STO) superlattice or (Ba, Sr)TiO3 / LaAlO3 superlattice.

[0073] The above negative capacitance material layers all have high dielectric constants. Introducing a negative capacitance material layer between the germanium layer and the SiO2 layer can significantly improve the capacitance characteristics and high-frequency performance of the chip. The introduction of the negative capacitance material layer enhances the overall capacitance characteristics of the chip. Better capacitance performance can reduce the lag of the signal during transmission, which helps to reduce the delay of signal transmission in high-frequency environments. This means that the response speed of the signal is improved, and the signal can be processed faster, thereby improving the high-frequency performance of the entire system and enabling the signal to maintain integrity at higher frequencies.

[0074] The introduction of negative capacitance materials can also improve the linearity of RF-GOI chips. Negative capacitance can compensate for the nonlinear changes of the device when it works at high frequencies to a certain extent. When the input signal amplitude is large, negative capacitance materials can help maintain the linear working state of the device. This ensures that the output signal can more accurately reflect the changes in the input signal, thereby improving the fidelity of the signal.

[0075] Reference Figure 4 As shown, another exemplary embodiment of the present application provides a radio frequency germanium-on-insulator wafer, which includes:

[0076] RF-SOI substrate 21;

[0077] A silicon dioxide layer 22 is provided on the surface of the RF-SOI substrate 21;

[0078] A negative capacitance material layer 14, wherein the negative capacitance material layer 14 is bonded to the silicon dioxide layer 22;

[0079] The germanium layer 13 is disposed on the surface of the negative capacitance material layer 14 .

[0080] Optionally, the material of the negative capacitance material layer 14 includes Hf 0.5 Zr 0.5 At least one of O2, BaTiO3, PZT, LiNbO3, SrRuO3, SrTiO3, PbTiO3, (Pb, Sr)TiO3 / SrTiO3 (PST / STO) superlattice or (Ba, Sr)TiO3 / LaAlO3 superlattice.

[0081] Optionally, the thickness of the negative capacitance material layer 14 is 0.01 μm to 1.0 μm.

[0082] Optionally, the thickness of the silicon dioxide layer 22 is 10 nm to 2000 nm.

[0083] Optionally, the germanium layer 13 has a thickness of 10 nm to 2000 nm.

[0084] The specific definition of the RF germanium-on-insulator wafer provided in this embodiment can be found in the embodiment of the method for manufacturing the RF germanium-on-insulator wafer described above, and will not be repeated here.

[0085] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the structural embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. Ordinary technicians in this field can understand and implement it without paying creative work.

[0086] The above is only a preferred implementation of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.

Claims

1. A method for manufacturing a radio frequency germanium-on-insulator wafer, characterized in that: The method comprises: forming a donor substrate, wherein the donor substrate comprises a silicon substrate, an etching stop layer, a germanium layer and a negative capacitance material layer stacked in sequence; forming a receptor substrate, the receptor substrate comprising an RF-SOI substrate and a silicon dioxide layer stacked in sequence; Wafer bonding the negative capacitance material layer of the donor substrate to the silicon dioxide layer of the acceptor substrate; removing the silicon substrate; The etching stop layer is removed to obtain a radio frequency germanium-on-insulator wafer.

2. The method for manufacturing a radio frequency germanium-on-insulator wafer according to claim 1, characterized in that: The material of the etch stop layer is at least one of heavily doped Si, heavily doped SiGe, heavily doped Si / SiGe composite material, heavily doped Si multilayer stacked material, heavily doped SiGe multilayer stacked material or heavily doped Si / SiGe multilayer stacked material.

3. The method for manufacturing a radio frequency germanium-on-insulator wafer according to claim 1, characterized in that: The material of the etch stop layer is at least one of SiGeC, SiGeCB, SiGeC / SiGeCB composite material, SiGeC multilayer material, and SiGeCB multilayer material.

4. The method for manufacturing a radio frequency germanium-on-insulator wafer according to claim 2 or 3, characterized in that: The thickness of the etching stop layer is 0.01 μm to 0.5 μm.

5. The method for manufacturing a radio frequency germanium-on-insulator wafer according to claim 1, characterized in that: The negative capacitance material layer includes Hf 0.5 Zr 0.5 At least one of O2, BaTiO3, PZT, LiNbO3, SrRuO3, SrTiO3, PbTiO3, (Pb, Sr)TiO3 / SrTiO3 (PST / STO) superlattice or (Ba, Sr)TiO3 / LaAlO3 superlattice.

6. The method for manufacturing a radio frequency germanium-on-insulator wafer according to claim 5, characterized in that: The thickness of the negative capacitance material layer is 0.01 μm to 1.0 μm.

7. The method for manufacturing a radio frequency germanium-on-insulator wafer according to claim 1, characterized in that: The method of removing the silicon substrate includes one or a combination of mechanical thinning, dry etching, chemical mechanical polishing, wet etching and oxidation.

8. The method for manufacturing a radio frequency germanium-on-insulator wafer according to claim 1, characterized in that: Removal of etch stop layers, including: The etch stop layer is removed by chemical mechanical polishing.

9. A radio frequency germanium-on-insulator wafer, characterized in that: include: RF-SOI substrate; A silicon dioxide layer is disposed on the surface of the RF-SOI substrate; A negative capacitance material layer, wherein the negative capacitance material layer is bonded to the silicon dioxide layer; The germanium layer is arranged on the surface of the negative capacitance material layer.

10. The radio frequency germanium-on-insulator wafer according to claim 9, characterized in that: The negative capacitance material layer includes Hf 0.5 Zr 0.5 At least one of O2, BaTiO3, PZT, LiNbO3, SrRuO3, SrTiO3, PbTiO3, (Pb, Sr)TiO3 / SrTiO3 (PST / STO) superlattice or (Ba, Sr)TiO3 / LaAlO3 superlattice.

11. The radio frequency germanium-on-insulator wafer according to claim 9, characterized in that: The thickness of the negative capacitance material layer is 0.01 μm to 1.0 μm.

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