Tbc solar cell and method of manufacturing the same

Abstract

The present disclosure discloses a TBC solar cell and a preparation method thereof. The preparation method of the TBC solar cell comprises the following steps: cleaning and polishing an N-type silicon substrate; depositing a first tunneling oxide layer and a first intrinsic polysilicon layer on the back surface; boron diffusion; laser grooving, etching and cleaning; depositing a second tunneling layer and a second intrinsic polysilicon layer on the back surface; phosphorus diffusion; laser grooving, etching and cleaning; depositing an aluminum oxide film and an anti-reflection film on both surfaces; and preparing a metal electrode. The present disclosure adds a phosphorus-doped polysilicon layer on the boron-doped polysilicon layer, and the second tunneling layer of the interlayer can form a secondary gettering effect, thereby improving the passivation level of the boron-doped polysilicon layer. The built-in electric field formed by the two PN junctions generates more carriers, forcing more holes to gather and horizontally transmit at the boron-doped polysilicon layer, and the holes are more easily collected by the metal electrode. On the basis of not increasing the process flow, the back surface is roughened, and the carrier collection optimization structure is increased.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic manufacturing, and in particular to a TBC solar cell and a preparation method thereof. Background Art

[0002] The existing TBC (Top-Contact Back-Contact) battery backside passivation contact structure can significantly improve the carrier collection efficiency of the backside grid lines. The key lies in providing a suitable passivation layer on the backside to reduce carrier recombination, thereby improving the efficiency of the battery. However, the implementation of this structure usually requires the use of a polysilicon (Poly-Silicon) layer with a high doping concentration on the backside, while ensuring a high passivation level. This is because the higher doping concentration helps improve the contact performance between the backside grid lines and the carriers, thereby improving the carrier collection ability.

[0003] However, the back P region is typically made of boron-doped polysilicon (Poly-Si:B). This results in high doping concentrations but also introduces a significant problem. The boron doping process causes boron atoms to form recombination centers within the silicon lattice. These recombination centers accelerate the recombination of electrons and holes, thereby reducing the cell's passivation effectiveness. This phenomenon not only affects the back region's passivation level but also leads to a decrease in cell efficiency. Summary of the Invention

[0004] In order to solve the technical problems mentioned in the prior art, the present disclosure proposes a TBC solar cell and a preparation method thereof.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A TBC solar cell, characterized in that the TBC solar cell includes a silicon substrate, the silicon substrate having a front surface and a back surface opposite to each other, the back surface of the silicon substrate having first regions and second regions alternately arranged along a first direction, a spacer region being provided between the first regions and the second regions, and the first direction being perpendicular to a thickness direction of the silicon substrate;

[0007] The first region includes a first PN junction, a first tunneling layer, and a first doped polysilicon layer sequentially arranged in a direction away from the back surface of the substrate;

[0008] The surface of the first doped polysilicon layer comprises a first sub-region and a second sub-region arranged at both ends of the first sub-region along a first direction, wherein the first sub-region comprises a suede structure and a passivation layer arranged in sequence in a direction away from the back surface of the substrate; and the second sub-region comprises a dielectric layer, a second doped polysilicon layer, and a passivation layer arranged in sequence in a direction away from the back surface of the substrate;

[0009] The spacer region includes a velvet structure and a passivation layer sequentially arranged in a direction away from the back surface of the substrate;

[0010] The second region includes a second PN junction, a second tunneling layer, a second doped polysilicon layer, and a passivation layer sequentially arranged in a direction away from the back surface of the substrate;

[0011] The front surface of the silicon substrate comprises a textured structure and a passivation layer sequentially arranged in a direction away from the front surface of the substrate;

[0012] The TBC solar cell further includes a first electrode and a second electrode, wherein the first electrode is located in the first sub-region and the first electrodes respectively pass through the passivation layer and contact the first doped polysilicon layer; the second electrode is located in the second region and the second electrodes respectively pass through the passivation layer and contact the second doped polysilicon layer;

[0013] The dielectric layer is a silicon oxide layer containing a first doping element and a second doping element.

[0014] Preferably, the doping element of the first doped polysilicon layer or the second doped polysilicon layer is a Group III or Group V element, wherein the doping element of the second doped polysilicon layer has opposite conductivity to that of the first doped polysilicon layer.

[0015] Preferably, the passivation layer is a stack of an aluminum oxide film and a silicon nitride film, wherein the thickness of the aluminum oxide film is 3 nm to 5 nm.

[0016] Preferably, the first tunneling layer is a tunneling oxide layer, the thickness of the first tunneling layer is 1 nm to 2.5 nm, and the thickness of the first doped polysilicon layer is 320 nm to 340 nm.

[0017] Preferably, the thickness of the second tunneling layer is 1 nm to 1.5 nm, and the thickness of the second doped polysilicon layer is 300 nm to 320 nm.

[0018] The present invention also seeks to protect a method for preparing a TBC solar cell, comprising the following steps:

[0019] Step S1: cleaning and polishing the N-type silicon substrate;

[0020] Step S2: depositing a first tunneling layer and a first intrinsic polysilicon layer in sequence on the back side of the N-type silicon substrate;

[0021] Step S3: performing boron diffusion on the first intrinsic polysilicon layer to form a boron-doped polysilicon layer and a BSG layer, and then diffusing toward the N-type silicon substrate to form a first PN junction;

[0022] Step S4: using a laser to remove the BSG layer in the N region and the Gap region on the back side of the N-type silicon substrate; etching and cleaning the BSG layer on the front side of the N-type silicon substrate, etching and cleaning the N region and the Gap region on the back side of the N-type silicon substrate, and the boron-doped polysilicon layer, the first tunneling layer, and the first PN junction on the front side; the area not removed is the P region;

[0023] Step S5: depositing a second tunneling layer and a second intrinsic polysilicon layer in sequence on the back side of the N-type silicon substrate;

[0024] Step S6: performing phosphorus diffusion on the second intrinsic polysilicon layer to form a phosphorus-doped polysilicon layer and a PSG layer, and then diffusing toward the N-type silicon substrate to form a second PN junction;

[0025] Step S7: using a laser to remove the PSG layer in the Gap region on the back side of the N-type silicon substrate and the first sub-region of the P region, while retaining the PSG layer in the second sub-region of the P region located on both sides of the first sub-region; etching and cleaning the PSG layer on the front side of the N-type silicon substrate, etching and cleaning the first sub-region, the Gap region on the back side of the N-type silicon substrate, and the phosphorus-doped polysilicon layer, the second tunneling layer, and the second PN junction on the front side, and forming a textured surface in the Gap region, the first sub-region, and the front side of the N-type silicon substrate;

[0026] Step S8: depositing an aluminum oxide film and an anti-reflection film on the front and back surfaces of the N-type silicon substrate;

[0027] Step S9: preparing metal electrodes in the first sub-region and the N region on the back side of the N-type silicon substrate, and sintering and solidifying them.

[0028] In some embodiments, the thickness of the first tunneling layer is 2 nm to 2.5 nm, and the thickness of the boron-doped polysilicon layer is 320 nm to 340 nm.

[0029] In certain embodiments, the BSG layer has a thickness of 70 nm to 80 nm.

[0030] In some embodiments, in step S4, the BSG layer on the front surface of the N-type silicon substrate is cleaned by wet chain etching, and the reagent used is an acid solution composed of HF and H2O in a volume ratio of 3:2;

[0031] The N region and Gap region on the back side of the N-type silicon substrate and the boron-doped polysilicon layer, the first tunnel oxide layer and the first PN junction on the front side are cleaned by alkaline bath etching. The reagent used is an alkaline solution composed of H2O, NaOH and polishing additives in a volume ratio of 300:20:3, wherein the NaOH concentration is 3%.

[0032] In some embodiments, the second tunneling layer has a thickness of 1 nm to 1.5 nm, and the phosphorus-doped polysilicon layer has a thickness of 300 nm to 320 nm.

[0033] In certain embodiments, the thickness of the PSG layer is 70 nm to 80 nm.

[0034] In some embodiments, in step S7, the PSG layer on the front surface of the N-type silicon substrate is cleaned by wet chain etching, and the reagent used is an acid solution composed of HF and H2O in a volume ratio of 3:2;

[0035] The first sub-region, the Gap region on the back side of the N-type silicon substrate and the phosphorus-doped polysilicon layer, the second tunneling layer and the second PN junction on the front side are cleaned by alkaline bath etching, and a velvet surface is formed on the Gap region, the first sub-region and the front side of the N-type silicon substrate. The reagent used is an alkaline solution composed of H2O, NaOH and polishing additives in a volume ratio of 300:12:5, wherein the NaOH concentration is 3%.

[0036] In certain embodiments, the aluminum oxide film has a thickness of 3 nm to 5 nm.

[0037] In some embodiments, the antireflection film includes five silicon nitride layers.

[0038] Due to the application of the above technical solution, the beneficial effects of the present disclosure compared with the prior art are:

[0039] (1) By adding a phosphorus-doped polysilicon layer on the boron-doped polysilicon layer, the second tunneling layer of the interlayer will form a secondary impurity gettering effect, thereby improving the passivation level of the boron-doped polysilicon layer.

[0040] (2) The boron-doped polysilicon layer and the phosphorus-doped polysilicon layer form two PN junctions. The built-in electric field formed by the two PN junctions generates more carriers, forcing more holes to gather in the boron-doped polysilicon layer and transmit laterally, making them easier to be collected by the metal electrode.

[0041] (3) Without increasing the process flow, a back velvet structure and a carrier collection optimization structure are added. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1 Schematic diagram of the cross-sectional structure of a TBC solar cell in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present disclosure.

[0045] It should be noted that the terms "first," "second," and the like in the specification and claims of the present disclosure and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present disclosure described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products, or apparatus.

[0046] In this disclosure, terms such as "upper," "lower," "left," "right," "front," "back," "top," "bottom," "inner," "outer," "center," "vertical," "horizontal," "transverse," and "longitudinal" indicate positions or locations based on the positions or locations shown in the accompanying drawings. These terms are primarily intended to better describe this disclosure and its embodiments and are not intended to limit the devices, elements, or components indicated to having a specific orientation, or to being constructed or operated in a specific orientation.

[0047] Furthermore, some of the above terms may be used to express other meanings besides indicating a position or location. For example, the term "on" may also be used to express a dependency or connection in certain circumstances. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0048] Furthermore, the terms "installed," "disposed," "provided with," "connected," "connected," and "socketed" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral structures; mechanical connections or electrical connections; direct connections, indirect connections through an intermediary, or internal communication between two devices, elements, or components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0049] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0050] An embodiment of the present disclosure provides a method for preparing a TBC solar cell, comprising the following steps:

[0051] Step S1: cleaning and polishing the N-type silicon substrate;

[0052] Step S2: depositing a first tunneling oxide layer and a first intrinsic polysilicon layer in sequence on the back side of the N-type silicon substrate;

[0053] Specifically, a cleaned and polished N-type silicon substrate is placed in an LPCVD device, and a first tunneling oxide layer with a thickness of 2nm to 2.5nm is grown at 600℃ to 650℃. A first intrinsic polysilicon layer with a thickness of 320nm to 340nm is grown at 550℃ to 650℃ for 10,000s.

[0054] Step S3: performing boron diffusion on the first intrinsic polysilicon layer to form a boron-doped polysilicon layer and a BSG layer, and then diffusing toward the N-type silicon substrate to form a first PN junction;

[0055] Specifically, an N-type silicon substrate is placed in a tubular diffusion device for boron diffusion at 830°C for 150s and 850°C for 500s, then heated to 970°C for 800s, and oxidized at 970°C for 850s to form a 70nm-80nm BSG layer, which is then expanded inward to form the first PN junction.

[0056] Step S4: using a laser to remove the BSG layer in the N region and the Gap region on the back side of the N-type silicon substrate; etching and cleaning the BSG layer on the front side of the N-type silicon substrate, etching and cleaning the N region and the Gap region on the back side of the N-type silicon substrate, and the boron-doped polysilicon layer, the first tunnel oxide layer, and the first PN junction on the front side; the area not removed is the P region;

[0057] Specifically, the BSG layer on the front side of the N-type silicon substrate was cleaned by wet chain etching using an acid solution consisting of HF and H2O in a volume ratio of 3:2. The pickling time was 60 seconds and the acid solution temperature was 30°C.

[0058] The N-type silicon substrate's backside N region and gap region, as well as the frontside boron-doped polysilicon layer, first tunnel oxide layer, and first PN junction, are cleaned using an alkaline bath etchant consisting of a 300:20:3 volume ratio of H2O, NaOH, and polishing additive, with a NaOH concentration of approximately 3%. The bath temperature is 50°C to 75°C, and the process takes 300 seconds.

[0059] Step S5: depositing a second tunneling layer and a second intrinsic polysilicon layer in sequence on the back side of the N-type silicon substrate;

[0060] Specifically, an N-type silicon substrate is placed in an LPCVD device, and a second tunneling layer with a thickness of 1 nm to 1.5 nm is grown at 600°C to 650°C. A second intrinsic polysilicon layer with a thickness of 300 nm to 320 nm is grown at 600°C to 650°C for 3500 seconds.

[0061] Step S6: performing phosphorus diffusion on the second intrinsic polysilicon layer to form a phosphorus-doped polysilicon layer and a PSG layer, and then diffusing toward the N-type silicon substrate to form a second PN junction;

[0062] Specifically, an N-type silicon substrate is placed in a tubular diffusion device for phosphorus diffusion at 860°C for 1350 seconds, then heated to 880°C for 300 seconds, and oxidized at 900°C for 500 seconds to form a 70nm to 80nm PSG layer, which is then expanded inward to form a second PN junction. Simultaneously, a boron- and phosphorus-containing silicon oxide layer is formed in the second tunneling layer located in the P region.

[0063] Step S7: using a laser to remove the PSG layer in the Gap region on the back side of the N-type silicon substrate and the first sub-region of the P region, while retaining the PSG layer in the second sub-region of the P region located on both sides of the first sub-region; etching and cleaning the PSG layer on the front side of the N-type silicon substrate, etching and cleaning the first sub-region, the Gap region on the back side of the N-type silicon substrate, and the phosphorus-doped polysilicon layer, the second tunneling layer, and the second PN junction on the front side, and forming a textured surface in the Gap region, the first sub-region, and the front side of the N-type silicon substrate;

[0064] Specifically, the PSG layer on the front side of the N-type silicon substrate was cleaned by wet chain etching using an acid solution consisting of HF and H2O in a volume ratio of 3:2. The pickling time was 40 seconds and the acid solution temperature was 30°C.

[0065] The first sub-region and gap region on the back side of the N-type silicon substrate, as well as the phosphorus-doped polysilicon layer, second tunneling layer, and second PN junction on the front side, are cleaned by alkaline etching. A textured surface is then formed on the back side of the N-type silicon substrate, along with the gap region, second sub-region, and front side. The etching solution used is an alkaline solution consisting of H2O, NaOH, and a polishing additive in a volume ratio of 300:12:5, with a NaOH concentration of approximately 3%. The bath temperature is 50°C to 75°C, and the process takes 450 seconds.

[0066] Step S8: depositing an aluminum oxide film and an anti-reflection film on the front and back surfaces of the N-type silicon substrate;

[0067] The details are as follows: Aluminum oxide film is deposited on both sides by single-insert double-sided ALD, and then an anti-reflection film is deposited on both sides by PECVD. The anti-reflection film consists of five layers of silicon nitride. The ALD process temperature is 200°C, the process time is 400 seconds, and the aluminum oxide film thickness is 3nm to 5nm. The PECVD coating process temperature is 500°C, the process time for each silicon nitride layer is 180 seconds, and the thickness of the five silicon nitride layers is 80nm.

[0068] Step S9: preparing metal electrodes in the first sub-region and the N region on the back side of the N-type silicon substrate, and sintering and solidifying them.

[0069] See Figure 1 The present disclosure also relates to a TBC solar cell manufactured by the above-mentioned manufacturing method, wherein the TBC solar cell includes an N-type silicon substrate 4, wherein the N-type silicon substrate 4 has a front surface and a back surface opposite to each other, and wherein the back surface of the N-type silicon substrate 4 has first regions and second regions alternately arranged along a first direction, with a spacer region between the first regions and the second regions, and wherein the first direction is perpendicular to the thickness direction of the N-type silicon substrate 4;

[0070] The first region includes a first PN junction 5, a first tunnel oxide layer 6, and a boron-doped polysilicon layer 7 arranged in sequence in a direction away from the back surface of the substrate;

[0071] The surface of the boron-doped polysilicon layer 7 has a first sub-region and second sub-regions arranged at both ends of the first sub-region along a first direction. The first sub-region includes a textured structure 3, an aluminum oxide film 2, and an anti-reflection film 1 arranged in sequence in a direction away from the back surface of the substrate. The second sub-region includes a boron-phosphorus-containing silicon oxide layer 8, a phosphorus-doped polysilicon layer 9, the aluminum oxide film 2, and the anti-reflection film 1 arranged in sequence in a direction away from the back surface of the substrate.

[0072] The spacer region includes a suede structure 3, an aluminum oxide film 2, and an anti-reflection film 1 arranged in sequence in a direction away from the back surface of the substrate;

[0073] The second region includes a second PN junction 11, a second tunneling layer 12, a phosphorus-doped polysilicon layer 9, an aluminum oxide film 2, and an anti-reflection film 1, which are sequentially arranged in a direction away from the back surface of the substrate;

[0074] The front surface of the N-type silicon substrate 4 includes a textured structure 3, an aluminum oxide film 2, and an anti-reflection film 1 arranged in sequence in a direction away from the front surface of the substrate;

[0075] The TBC solar cell also includes a first electrode 10 and a second electrode 13. The first electrode 10 is located in the first sub-area, and the first electrode 10 passes through the anti-reflection film 1, the aluminum oxide film 2, and the velvet structure 3 to contact the boron-doped polysilicon layer 7; the second electrode 13 is located in the second area, and the second electrode 13 passes through the anti-reflection film 1 and the aluminum oxide film 2 to contact the phosphorus-doped polysilicon layer 9.

[0076] Finally, it should be noted that the above are only preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or make equivalent replacements for some of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A TBC solar cell, characterized in that: The TBC solar cell includes a silicon substrate having a front surface and a back surface opposite to each other, wherein the back surface of the silicon substrate has first regions and second regions alternately arranged along a first direction, with a spacer region between the first regions and the second regions, and the first direction is perpendicular to a thickness direction of the silicon substrate; The first region includes a first PN junction, a first tunneling layer, and a first doped polysilicon layer sequentially arranged in a direction away from the back surface of the substrate; The surface of the first doped polysilicon layer comprises a first sub-region and a second sub-region arranged at both ends of the first sub-region along a first direction, wherein the first sub-region comprises a suede structure and a passivation layer arranged in sequence in a direction away from the back surface of the substrate; and the second sub-region comprises a dielectric layer, a second doped polysilicon layer, and a passivation layer arranged in sequence in a direction away from the back surface of the substrate; The spacer region includes a velvet structure and a passivation layer sequentially arranged in a direction away from the back surface of the substrate; The second region includes a second PN junction, a second tunneling layer, a second doped polysilicon layer, and a passivation layer sequentially arranged in a direction away from the back surface of the substrate; The front surface of the silicon substrate comprises a textured structure and a passivation layer sequentially arranged in a direction away from the front surface of the substrate; The TBC solar cell further includes a first electrode and a second electrode, wherein the first electrode is located in the first sub-region, and the first electrodes respectively pass through the passivation layer and contact the first doped polysilicon layer; The second electrodes are located in the second region, and the second electrodes respectively pass through the passivation layer and contact the second doped polysilicon layer; The dielectric layer is a silicon oxide layer containing a first doping element and a second doping element.

2. The TBC solar cell according to claim 1, wherein: The doping element of the first doped polysilicon layer or the second doped polysilicon layer is a Group III or Group V element, wherein the doping element of the second doped polysilicon layer has opposite conductivity to that of the first doped polysilicon layer.

3. The TBC solar cell according to claim 1, wherein: The passivation layer is a stack of aluminum oxide film and silicon nitride, wherein the thickness of the aluminum oxide film is 3nm~5nm.

4. The TBC solar cell according to claim 1, wherein: The first tunneling layer is a tunneling oxide layer, the thickness of the first tunneling layer is 1 nm to 2.5 nm, and the thickness of the first doped polysilicon layer is 320 nm to 340 nm.

5. The TBC solar cell according to claim 1, wherein: The thickness of the second tunneling layer is 1 nm to 1.5 nm, and the thickness of the second doped polysilicon layer is 300 nm to 320 nm.

6. A method for preparing a TBC solar cell according to any one of claims 1 to 5, characterized in that: The following steps are involved: Step S1: cleaning and polishing the N-type silicon substrate; Step S2: depositing a first tunneling layer and a first intrinsic polysilicon layer in sequence on the back side of the N-type silicon substrate; Step S3: performing boron diffusion on the first intrinsic polysilicon layer to form a boron-doped polysilicon layer and a BSG layer, and then diffusing toward the N-type silicon substrate to form a first PN junction; Step S4: using laser to remove the BSG layer in the back N region and Gap region of the N-type silicon substrate; Etch and clean the BSG layer on the front of the N-type silicon substrate, and etch and clean the N region, Gap region, and boron-doped polysilicon layer, first tunneling layer, and first PN junction on the back of the N-type silicon substrate. The area not removed is the P region. Step S5: depositing a second tunneling layer and a second intrinsic polysilicon layer in sequence on the back side of the N-type silicon substrate; Step S6: performing phosphorus diffusion on the second intrinsic polysilicon layer to form a phosphorus-doped polysilicon layer and a PSG layer, and then diffusing toward the N-type silicon substrate to form a second PN junction; Step S7: using a laser to remove the backside Gap region of the N-type silicon substrate and the PSG layer of the first sub-region of the P region, and retaining the PSG layers of the second sub-regions of the P region located on both sides of the first sub-region; Etching and cleaning the PSG layer on the front side of the N-type silicon substrate, etching and cleaning the first sub-region, the Gap region, and the phosphorus-doped polysilicon layer, the second tunneling layer, and the second PN junction on the back side of the N-type silicon substrate, and forming a textured surface on the Gap region, the first sub-region, and the front side of the N-type silicon substrate; Step S8: depositing an aluminum oxide film and an anti-reflection film on the front and back surfaces of the N-type silicon substrate; Step S9: preparing metal electrodes in the first sub-region and the N region on the back side of the N-type silicon substrate, and sintering and solidifying them.

7. The method for preparing a TBC solar cell according to claim 6, wherein: The thickness of the BSG layer is 70 nm to 80 nm.

8. The method for preparing a TBC solar cell according to claim 6, wherein: In step S4, the BSG layer on the front side of the N-type silicon substrate is cleaned by wet chain etching, and the reagent used is an acid solution composed of HF and H2O in a volume ratio of 3:2; The N region and Gap region on the back side of the N-type silicon substrate and the boron-doped polysilicon layer, the first tunneling layer and the first PN junction on the front side are cleaned by alkaline bath etching. The reagent used is an alkaline solution composed of H2O, NaOH and polishing additives in a volume ratio of 300:20:3, wherein the NaOH concentration is 3%.

9. The method for preparing a TBC solar cell according to claim 6, wherein: In step S7, the PSG layer on the front side of the N-type silicon substrate is cleaned by wet chain etching, and the reagent used is an acid solution composed of HF and H2O in a volume ratio of 3:2; The first sub-region, the Gap region on the back side of the N-type silicon substrate and the phosphorus-doped polysilicon layer, the second tunneling layer and the second PN junction on the front side are cleaned by alkaline bath etching, and a velvet surface is formed on the Gap region, the first sub-region and the front side of the N-type silicon substrate. The reagent used is an alkaline solution composed of H2O, NaOH and polishing additives in a volume ratio of 300:12:5, wherein the NaOH concentration is 3%.

Images