Light emitting diode with improved metal delamination and method of making the same

Abstract

The present disclosure provides a light-emitting diode with improved metal peeling and a preparation method thereof, and belongs to the technical field of optoelectronic manufacturing. The light-emitting diode comprises an epitaxial layer, a passivation layer, a first reflective layer and a second reflective layer. The passivation layer is located on the surface of the epitaxial layer, and the passivation layer has a first through hole penetrating through the passivation layer. The first reflective layer is located on the surface of the passivation layer away from the epitaxial layer, and the first reflective layer is electrically connected with the epitaxial layer through the first through hole. The second reflective layer is located in the passivation layer and between the surface of the passivation layer away from the epitaxial layer and the surface of the passivation layer close to the epitaxial layer. The surface of the first reflective layer away from the epitaxial layer has a recess hole exposing the passivation layer. The orthographic projection of the second reflective layer on the surface of the epitaxial layer overlaps with the orthographic projection of the recess hole on the surface of the epitaxial layer. The embodiment of the present disclosure can improve the adhesion of the silver mirror reflective layer, prevent the silver mirror reflective layer from peeling off from the passivation layer, and improve the reliability of the light-emitting diode.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of optoelectronic manufacturing, and particularly relates to a light-emitting diode with improved metal peeling and a preparation method thereof. BACKGROUND

[0002] Light-emitting diodes (LED) are common products. LEDs are usually formed by cutting a substrate after various film layers are manufactured on the substrate and are patterned.

[0003] In the related art, a light-emitting diode usually includes an epitaxial layer, a transparent conductive layer, a passivation layer, a silver mirror reflection layer, and a protective layer. The epitaxial layer, the transparent conductive layer, and the passivation layer are sequentially stacked, and the silver mirror reflection layer is located on a surface of the passivation layer away from the epitaxial layer. Since the metal Ag of the silver mirror reflection layer is prone to migration, a protective layer is formed on the surface of the passivation layer to cover the silver mirror reflection layer to prevent the migration of the metal Ag.

[0004] Since the adhesion between the metal Ag and the passivation layer is poor, the silver mirror reflection layer is prone to be detached from the passivation layer. Although the silver mirror reflection layer is also covered by the protective layer, and the adhesion between the protective layer and the passivation layer is good. Since most of the surface of the protective layer is connected with the silver mirror reflection layer, only a small amount of the surface of the periphery edge is connected with the passivation layer, and thus the protective layer is also difficult to stabilize the silver mirror reflection layer on the passivation layer, which leads to the problem of peeling of the silver mirror reflection layer from the passivation layer, and affects the reliability of the light-emitting diode. SUMMARY

[0005] The present disclosure provides a light-emitting diode with improved metal peeling and a preparation method thereof, which can improve the adhesion of the silver mirror reflection layer, prevent the silver mirror reflection layer from peeling from the passivation layer, and improve the reliability of the light-emitting diode. The technical solution is as follows:

[0006] In one aspect, the present disclosure provides a light-emitting diode, which includes an epitaxial layer, a passivation layer, a first reflection layer, and a second reflection layer. The passivation layer is located on a surface of the epitaxial layer, and has a first through hole penetrating through the passivation layer. The first reflection layer is located on a surface of the passivation layer away from the epitaxial layer, and is electrically connected with the epitaxial layer through the first through hole. The second reflection layer is located in the passivation layer, and is located between the surface of the passivation layer away from the epitaxial layer and a surface of the passivation layer close to the epitaxial layer. A surface of the first reflection layer away from the epitaxial layer has a recess hole exposing the passivation layer. A normal projection of the second reflection layer on the surface of the epitaxial layer overlaps with a normal projection of the recess hole on the surface of the epitaxial layer.

[0007] Optionally, a projection of the recess hole on the surface of the epitaxial layer is located within a projection of the second reflective layer on the surface of the epitaxial layer.

[0008] Optionally, the surface of the first reflective layer has a plurality of spaced recess holes; and the second reflective layer wraps a plurality of spaced metal blocks, the metal blocks corresponding to the recess holes one by one, and a projection of the recess hole on the surface of the epitaxial layer is located within a projection of the corresponding metal block on the surface of the epitaxial layer.

[0009] Optionally, the first reflective layer and the second reflective layer each comprise an Ag layer; or the first reflective layer and the second reflective layer each comprise an adhesion metal layer and an Ag layer, the adhesion metal layer being located on at least one surface of the Ag layer.

[0010] Optionally, the adhesion metal layer comprises a Ti layer.

[0011] Optionally, the light emitting diode further comprises a transparent conductive layer located between the epitaxial layer and the passivation layer, the first through hole exposing the transparent conductive layer, and the first reflective layer is connected with the transparent conductive layer through the first through hole.

[0012] Optionally, the light emitting diode further comprises a protective layer located at least on the surface of the first reflective layer away from the epitaxial layer and in the recess hole.

[0013] Optionally, an area of a projection of the part of the protective layer located in the recess hole on the surface of the epitaxial layer is greater than an area of a projection of the part of the protective layer located on the surface of the first reflective layer on the surface of the epitaxial layer.

[0014] The disclosure provides a preparation method of a light emitting diode, the preparation method comprising: preparing an epitaxial layer; forming a passivation layer and a second reflective layer on a surface of the epitaxial layer, the passivation layer having a first through hole penetrating the passivation layer, the second reflective layer being located in the passivation layer and between a surface of the passivation layer away from the epitaxial layer and a surface of the passivation layer close to the epitaxial layer; forming a first reflective layer on the surface of the epitaxial layer, the first reflective layer being electrically connected with the epitaxial layer through the first through hole, and a surface of the first reflective layer away from the epitaxial layer having a recess hole exposing the passivation layer, and a projection of the second reflective layer on the surface of the epitaxial layer overlapping a projection of the recess hole on the surface of the epitaxial layer.

[0015] Optionally, forming the passivation layer and the second reflective layer on the surface of the epitaxial layer comprises: forming a first silicon oxide layer on the surface of the epitaxial layer; forming a plurality of spaced metal blocks on the surface of the first silicon oxide layer to obtain the second reflective layer, the metal blocks corresponding to the recess holes one by one, and the orthographic projection of the recess hole on the surface of the epitaxial layer being located within the orthographic projection of the corresponding metal block on the surface of the epitaxial layer; forming a second silicon oxide layer covering the second reflective layer on the surface of the first silicon oxide layer, and forming a first through hole penetrating through the second silicon oxide layer to the first silicon oxide layer, the first through hole being spaced from the metal blocks.

[0016] The technical scheme provided by the embodiments of the present disclosure has at least the following beneficial effects:

[0017] The light emitting diode provided by the embodiments of the present disclosure forms the recess hole on the first reflective layer on the surface of the passivation layer, exposes the passivation layer through the recess hole, so that the protective layer on the surface of the first reflective layer can be connected with the passivation layer through the recess hole, thereby increasing the contact area of the protective layer and the passivation layer.

[0018] Compared with the related art, the contact area of the first reflective layer and the passivation layer is reduced, and the contact area of the protective layer and the passivation layer is increased. Since the adhesion of the passivation layer and the protective layer is better than the adhesion of the passivation layer and the first reflective layer, the protective layer is more firmly fixed on the passivation layer, so that the first reflective layer can be wrapped by the protective layer to prevent the first reflective layer from peeling off from the passivation layer, thereby improving the reliability of the light emitting diode.

[0019] Meanwhile, the second reflective layer is also provided, and the orthographic projection of the second reflective layer on the surface of the epitaxial layer overlaps with the orthographic projection of the recess hole on the surface of the epitaxial layer. That is, the second reflective layer at least faces the recess hole, so that the second reflective layer can compensate for the lost reflective area of the first reflective layer due to the opening of the recess hole. Through the complementary mode of the first reflective layer and the second reflective layer, the purpose of the reflective layer covering the epitaxial layer to the greatest extent can be achieved, so as to improve the overall light reflection effect of the reflective layer. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical scheme in the embodiments of the present disclosure, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0021] Figure 1 is a structure schematic diagram of a light emitting diode provided by the related art;

[0022] Figure 2is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0023] Figure 3 is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0024] Figure 4 is a flow chart of a preparation of a light emitting diode provided by an embodiment of the present disclosure;

[0025] Figure 5 is a state diagram of a preparation of a light emitting diode provided by an embodiment of the present disclosure;

[0026] Figure 6 is a state diagram of a preparation of a light emitting diode provided by an embodiment of the present disclosure;

[0027] Figure 7 is a state diagram of a preparation of a light emitting diode provided by an embodiment of the present disclosure.

[0028] The various marks shown in the drawings are described as follows:

[0029] 10, substrate;

[0030] 20, epitaxial layer; 21, first semiconductor layer; 22, multi-quantum well layer; 23, second semiconductor layer;

[0031] 30, passivation layer; 31, first through hole;

[0032] 40, silver mirror reflection layer; 41, first reflection layer; 410, recess;

[0033] 42, second reflection layer; 420, metal block;

[0034] 43, protective layer;

[0035] 50, transparent conductive layer; 51, first insulating layer; 52, second insulating layer;

[0036] 60, electrode;

[0037] 70, pad. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be further described in detail below with reference to the drawings.

[0039] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", "third", and the like, as used in the description and the claims of this disclosure do not have any specific meaning, and are merely used to distinguish one component from another. Similarly, the terms "one", "another", and the like, do not limit the quantity of the mentioned objects, and are merely used to distinguish one component from another. The terms "comprise", "comprising", and the like, mean that the elements listed after the terms are included in the object or method described by the terms, and do not exclude other elements or methods. The terms "connect", "connected", and the like, do not limit the manner of connection to physical or mechanical connection, and can include electrical connection, whether direct or indirect. The terms "upper", "lower", "left", "right", "top", "bottom", and the like, are merely used to indicate relative positional relationships, and can change when the absolute positions of the described objects change.

[0040] Figure 1 is a structural schematic diagram of a light-emitting diode provided by the related art. As shown in Figure 1 The light-emitting diode in the related art includes an epitaxial layer 20, a transparent conductive layer 50, a passivation layer 30, a silver mirror reflection layer 40, and a protective layer 43. The epitaxial layer 20, the transparent conductive layer 50, and the passivation layer 30 are stacked in sequence, and the silver mirror reflection layer 40 is located on a surface of the passivation layer 30 away from the epitaxial layer 20. The passivation layer 30 covers the silver mirror reflection layer 40 to prevent migration of the metal Ag.

[0041] As shown in Figure 1 Most of the surface of the protective layer 43 is connected with the silver mirror reflection layer. Since the adhesion of the metal Ag to the passivation layer 30 is poor, the silver mirror reflection layer is prone to come off from the passivation layer 30.

[0042] The protective layer 43 includes a Ni layer and a TiW layer, and the adhesion of the metals Ni and TiW to the passivation layer 30 is good. However, only a small amount of the surface of the peripheral edge of the protective layer 43 is connected with the passivation layer 30, and thus the protective layer 43 is also difficult to stabilize the silver mirror reflection layer 40 on the passivation layer 30, which can cause the silver mirror reflection layer 40 to peel off from the passivation layer 30, and affect the reliability of the light-emitting diode.

[0043] Therefore, an embodiment of the present disclosure provides a light-emitting diode. Figure 2 is a structural schematic diagram of a light-emitting diode provided by an embodiment of the present disclosure. As shown in Figure 2As shown, the light-emitting diode includes an epitaxial layer 20, a passivation layer 30, a first reflective layer 41, and a protective layer 43. The passivation layer 30 is located on the surface of the epitaxial layer 20 and has a first through-hole 31 penetrating the passivation layer 30.

[0044] like Figure 2 As shown, the first reflective layer 41 is located on the surface of the passivation layer 30 away from the epitaxial layer 20. The first reflective layer 41 is electrically connected to the epitaxial layer 20 through the first via 31. The surface of the first reflective layer 41 away from the epitaxial layer 20 has a recess 410 that exposes the passivation layer 30. The protective layer 43 is located at least on the surface of the first reflective layer 41 away from the epitaxial layer 20 and in the recess 410.

[0045] The light-emitting diode provided in this embodiment forms a recess 410 in the first reflective layer 41 on the surface of the passivation layer 30, exposing the passivation layer 30 through the recess 410. This allows the protective layer 43 on the surface of the first reflective layer 41 to be connected to the passivation layer 30 through the recess 410, thereby increasing the contact area between the protective layer 43 and the passivation layer 30.

[0046] Compared to related technologies, this design reduces the contact area between the first reflective layer 41 and the passivation layer 30, while increasing the contact area between the protective layer 43 and the passivation layer 30. Since the adhesion between the passivation layer 30 and the protective layer 43 is better than that between the passivation layer 30 and the first reflective layer 41, the protective layer 43 is more securely fixed to the passivation layer 30. This allows the protective layer 43 to encapsulate the first reflective layer 41, preventing it from peeling off the passivation layer 30 and improving the reliability of the light-emitting diode.

[0047] Optionally, the area of ​​the orthographic projection of the portion of the first reflective layer 41 located outside the first via 31 onto the surface of the epitaxial layer 20 is smaller than the area of ​​the orthographic projection of the portion of the first reflective layer 41 located inside the first via 31 onto the surface of the epitaxial layer 20.

[0048] Optionally, the area of ​​the orthographic projection of the portion of the protective layer 43 located within the recess 410 onto the surface of the epitaxial layer 20 is greater than the area of ​​the orthographic projection of the portion of the protective layer 43 located on the surface of the first reflective layer 41 onto the surface of the epitaxial layer 20.

[0049] This allows most of the protective layer 43 to fall within the recess 410, enabling it to connect with the passivation layer 30, which has better adhesion, thus improving the bonding reliability of the protective layer 43. Simultaneously, having less of the protective layer 43 adhere to the surface of the first reflective layer 41 also helps to encapsulate the first reflective layer 41, firmly pressing it onto the passivation layer 30 and preventing it from peeling off.

[0050] Exemplarily, a ratio of an area of a normal projection of the part of the protective layer 43 on the surface of the epitaxial layer 20 located in the recess 410 to an area of a normal projection of the part of the protective layer 43 on the surface of the epitaxial layer 20 located on the surface of the first reflective layer 41 can be 1.5 to 4. In this way, it can be ensured that the area of the protective layer 43 in the recess 410 is large enough, thereby enhancing the connection reliability of the protective layer 43 and the passivation layer 30.

[0051] Optionally, as shown in FIG. 4, the light-emitting diode further comprises a second reflective layer 42, the second reflective layer 42 is located in the passivation layer 30, and the second reflective layer 42 is located between the surface of the passivation layer 30 away from the epitaxial layer 20 and the surface of the passivation layer 30 close to the epitaxial layer 20. Figure 2

[0052] Optionally, a normal projection of the second reflective layer 42 on the surface of the epitaxial layer 20 overlaps with a normal projection of the recess 410 on the surface of the epitaxial layer 20.

[0053] In the embodiments of the present disclosure, by setting the second reflective layer 42 and letting the normal projection of the second reflective layer 42 on the surface of the epitaxial layer 20 overlap with the normal projection of the recess 410 on the surface of the epitaxial layer 20, that is, letting the second reflective layer 42 directly face at least part of the recess 410, the second reflective layer 42 can be used to compensate for the reflective area lost by the first reflective layer 41 due to the recess 410. Through the complementary mode of the first reflective layer 41 and the second reflective layer 42, the purpose of the reflective layer covering the epitaxial layer 20 to the greatest extent can be achieved, so as to improve the overall light reflection effect of the reflective layer.

[0054] Optionally, a normal projection of the recess 410 on the surface of the epitaxial layer 20 is located within a normal projection of the second reflective layer 42 on the surface of the epitaxial layer 20.

[0055] Exemplarily, as shown in FIG. 4, the surface of the first reflective layer 41 has a plurality of recesses 410 arranged at intervals. Figure 2

[0056] Exemplarily, as shown in FIG. 4, the second reflective layer 42 located in the passivation layer 30 also wraps a plurality of metal blocks 420 arranged at intervals, and the metal blocks 420 correspond one by one to the recesses 410. Figure 2 Optionally, a normal projection of the recess 410 on the surface of the epitaxial layer 20 is located within a normal projection of the corresponding metal block 420 on the surface of the epitaxial layer 20. That is, the area of the recess 410 is smaller than the area of the metal block 420. In this way, it can be ensured that the normal projections of the first reflective layer 41 and the second reflective layer 42 on the surface of the epitaxial layer 20 can cover most of the surface of the epitaxial layer 20, thereby improving the overall light reflection effect of the reflective layer.

[0057]

[0058] ​​​Optionally, the first reflective layer 41 and the second reflective layer 42 each comprise an Ag layer.

[0059] Since Ag has good reflection effect, setting the Ag layer in the reflective layer can enhance the reflection of the reflective layer to light, and improve the light emission brightness of the light emitting diode.

[0060] For example, the thickness of the Ag layer is 2500 angstroms.

[0061] It should be noted that the thickness of the first reflective layer 41 and the second reflective layer 42 can be the same or different, and the embodiments of the present disclosure are not limited.

[0062] Optionally, the first reflective layer 41 and the second reflective layer 42 each comprise an adhesion metal layer and an Ag layer, and the adhesion metal layer is located on at least one surface of the Ag layer.

[0063] For example, the first reflective layer 41 and the second reflective layer 42 each comprise two adhesion metal layers, and the two adhesion metal layers are respectively located on opposite surfaces of the Ag layer.

[0064] For example, the first reflective layer 41 and the second reflective layer 42 each comprise two adhesion metal layers, and the two adhesion metal layers are respectively located on opposite surfaces of the Ag layer.

[0065] For example, the adhesion metal layer comprises a Ti layer. The metal Ti has good adhesion, and can firmly connect the first reflective layer 41 and the second reflective layer 42 with the passivation layer 30.

[0066] For example, the thickness of the Ag layer is 2500 angstroms.

[0067] For example, the thickness of the Ag layer is 2500 angstroms.

[0068] Optionally, the ratio of the thickness of the second reflective layer 42 to the thickness of the passivation layer 30 is less than or equal to 0.8.

[0069] By setting the ratio of the thickness of the second reflective layer 42 to the thickness of the passivation layer 30 within the above range, the second reflective layer 42 can be prevented from being set too thick, so that the film layer of the passivation layer 30 on both sides of the second reflective layer 42 is too thin, and the passivation layer 30 is easily abraded to expose the second reflective layer 42, causing the problem of short circuit of the light emitting diode.

[0070] For example, the ratio of the thickness of the second reflective layer 42 to the thickness of the passivation layer 30 is 0.5.

[0071] Optionally, the light emitting diode further comprises a transparent conductive layer 50, the transparent conductive layer 50 is located between the epitaxial layer 20 and the passivation layer 30, the first via hole 31 exposes the transparent conductive layer 50, and the first reflective layer 41 is connected with the transparent conductive layer 50 through the first via hole 31.

[0072] Exemplarily, the transparent conductive layer 50 can be an Indium Tin Oxide (ITO) layer. The ITO layer has good transmittance and low resistivity.

[0073] Exemplarily, the transparent conductive layer 50 can be an Indium Zinc Oxide (IZO) layer. The IZO layer has good transmittance and low resistivity.

[0074] Since the ITO layer or the IZO layer has good adhesion with the metal Ag, the ITO layer or the IZO layer is used as the transparent conductive layer 50, so that the first reflective layer 41 is in contact with the ITO. The adhesion of the first reflective layer 41 with other film layers can be improved, and the problem of peeling of the first reflective layer 41 can be effectively avoided.

[0075] Meanwhile, the ITO layer or the IZO layer is used as the transparent conductive layer 50, so that more light can be transmitted from the transparent conductive layer 50, thereby ensuring the light emitting effect. Meanwhile, since the resistivity is low, the first reflective layer 41 is stacked on the transparent conductive layer 50, so that the carriers can be more efficiently conducted from the first reflective layer 41 to the epitaxial layer 20, thereby improving the injection efficiency.

[0076] Exemplarily, the thickness of the transparent conductive layer 50 can be 600 angstroms to 2000 angstroms. For example, the thickness of the transparent conductive layer 50 is 1500 angstroms.

[0077] Optionally, the passivation layer 30 can be at least one of a silicon oxide layer, a titanium oxide layer and an aluminum oxide layer.

[0078] Exemplarily, the passivation layer 30 can be a silicon oxide layer.

[0079] Optionally, as shown in Figure 2 The epitaxial layer 20 comprises a first semiconductor layer 21, a multiple quantum well layer 22 and a second semiconductor layer 23 which are sequentially stacked, and the second semiconductor layer 23 has a groove exposing the first semiconductor layer 21. The passivation layer 30 is also located in the groove, and the passivation layer 30 located in the groove has a via hole exposing the first semiconductor layer 21.

[0080] Optionally, one of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer.

[0081] Exemplarily, the first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0082] Optionally, the n-type layer is an n-type GaN layer doped with silicon. The thickness of the n-type GaN layer can be 0.5 μm to 3 μm.

[0083] Optionally, the multi-quantum well layer 22 comprises InGaN quantum well layers and GaN quantum barrier layers alternately grown. Specifically, the multi-quantum well layer 22 can comprise 3 to 8 periods of InGaN quantum well layers and GaN quantum barrier layers alternately stacked.

[0084] For example, in the embodiment of the present disclosure, the multi-quantum well layer 22 comprises 5 periods of InGaN quantum well layers and GaN quantum barrier layers alternately stacked.

[0085] Optionally, the thickness of the multi-quantum well layer 22 can be 150 nm to 200 nm.

[0086] Optionally, the p-type layer is a p-type GaN layer doped with magnesium. The thickness of the p-type GaN layer can be 0.5 μm to 3 μm.

[0087] In an implementation manner of the present disclosure, as shown in Figure 2 The second reflective layer 42 is located on the second semiconductor layer 23, and the second reflective layer 42 is located outside the groove.

[0088] In the above implementation manner, the second reflective layer 42 is only arranged above the second semiconductor layer 23 and does not extend into the groove. Since the light emitting region of the epitaxial layer 20 is located on the multi-quantum well layer 22, the place with the largest light output on the epitaxial layer 20 is concentrated on the region of the second semiconductor layer 23 on the multi-quantum well layer 22. Therefore, arranging the second reflective layer 42 only above the second semiconductor layer 23 can achieve the purpose of reflecting most of the light, and reduce the preparation area of the second reflective layer 42 and the preparation difficulty.

[0089] Figure 3 is a structure schematic diagram of a light emitting diode provided by an embodiment of the present disclosure. As shown in Figure 3 The light emitting diode further comprises an electrode 60 and a first insulating layer 51. The first insulating layer 51 is located on the passivation layer 30 and the protective layer 43, and extends into the groove and covers the first semiconductor layer 21. The first insulating layer 51 is further provided with a via hole exposing the first semiconductor layer 21 and the protective layer 43.

[0090] As shown in Figure 3 A part of the electrode 60 is located at least in the groove and connected to the first semiconductor layer 21 through the via hole, and the other part of the electrode 60 is located outside the groove and connected to the protective layer 43 through the via hole.

[0091] Exemplarily, the electrode 60 can include at least one of a Cr layer, an Al layer, a Pt layer, and a Ti layer. The reflectivity of these metals is between 60% and 90%.

[0092] Exemplarily, the preparation material of the protective layer 43 can be Ti, TiW, or the like, and the reflectivity of these metals is all below 60%.

[0093] The electrode 60 with reflectivity greater than the protective layer 43 is used to reflect light in the area not covered by the second reflective layer 42 and the first reflective layer 41, so that the light reflection can be maximized, and the light reflection effect of the light emitting diode is improved.

[0094] Optionally, the first insulating layer 51 can be at least one of a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0095] Exemplarily, the first insulating layer 51 can be a silicon oxide layer.

[0096] Optionally, as shown in Figure 3 , the light emitting diode further includes a second insulating layer 52 and a pad 70, the second insulating layer 52 is located on the surface of the first insulating layer 51 and the surface of the electrode 60, the second insulating layer 52 has a via hole exposing the electrode 60, and the pad 70 is located on the second insulating layer 52 and connected to the electrode 60 through the via hole.

[0097] Optionally, the second insulating layer 52 can be at least one of a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0098] Exemplarily, the second insulating layer 52 can be a silicon oxide layer.

[0099] Optionally, the pad 70 includes a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer which are stacked in sequence.

[0100] The thickness of the first Al layer is 8000 angstroms to 12000 angstroms, the thickness of the first Ti layer is 100 angstroms to 500 angstroms, the thickness of the second Al layer is 8000 angstroms to 12000 angstroms, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms, and the thickness of the Au layer is 2000 angstroms to 5000 angstroms.

[0101] For example, the thickness of the first Al layer is 10000 angstroms, the thickness of the first Ti layer is 200 angstroms, the thickness of the second Al layer is 10000 angstroms, the thickness of the second Ti layer is 1000 angstroms, and the thickness of the Au layer is 3000 angstroms.

[0102] Optionally, as shown in Figure 2 , 3 , the light emitting diode further includes a substrate 10, and the epitaxial layer 20 is stacked on the substrate 10.

[0103] Exemplarily, the substrate can be a sapphire substrate. The sapphire substrate has relatively high light transmittance, that is, the substrate is a transparent substrate. In addition, the sapphire material is relatively hard and has stable chemical properties, so that the LED has good light emission effect and stability.

[0104] Figure 4 is a preparation flowchart of a light emitting diode provided by an embodiment of the present disclosure. As shown in the figure, the preparation method comprises the following steps. Figure 4

[0105] Step S11: Preparing an epitaxial layer.

[0106] The process of preparing the epitaxial layer can comprise the following steps.

[0107] Firstly, as shown in the figure, the epitaxial layer 20 grown on the sapphire substrate comprises a first semiconductor layer 21, a multi-quantum well layer 22 and a second semiconductor layer 23 which are sequentially stacked. Figure 5

[0108] In the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0109] Specifically, the baking temperature can be 1000-1200°C, and the pressure in the MOCVD reaction chamber during baking can be 100-200 mbar.

[0110] Exemplarily, the first semiconductor layer 21 can be an n-type layer, and the second semiconductor layer 23 can be a p-type layer.

[0111] Optionally, the n-type layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer can be 0.5-3 μm.

[0112] The growth temperature of the n-type GaN layer can be 1000-1100°C, and the growth pressure of the n-type GaN layer can be 100-300 torr.

[0113] Optionally, the multi-quantum well layer 22 comprises InGaN quantum well layers and GaN quantum barrier layers which are alternately grown. In the embodiment of the present disclosure, the multi-quantum well layer 22 can comprise 3-8 periods of InGaN quantum well layers and GaN quantum barrier layers which are alternately stacked.

[0114] ​​When growing the multi-quantum-well layer 22, the MOCVD reaction chamber pressure was controlled at 200 torr. When growing the InGaN quantum well layer, the reaction chamber temperature was 760℃ to 780℃. When growing the GaN quantum barrier layer, the reaction chamber temperature was 860℃ to 890℃.

[0115] As an example, in an embodiment of this disclosure, the multi-quantum-well layer 22 includes five alternating periods of InGaN quantum-well layers and GaN quantum-barrier layers.

[0116] Optionally, the thickness of the multiple quantum well layer 22 can be from 150 nm to 200 nm.

[0117] Optionally, the p-type layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 3 μm.

[0118] When growing p-type GaN layers, the growth pressure of p-type GaN layers can be from 200 Torr to 600 Torr, and the growth temperature of p-type GaN layers can be from 800℃ to 1000℃.

[0119] The second step is to etch the epitaxial layer 20 to form a groove on the surface of the second semiconductor layer 23 that exposes the first semiconductor layer 21.

[0120] The third step is to form a transparent conductive layer 50 on the surface of the epitaxial layer 20.

[0121] like Figure 5 As shown, specifically, it may include forming a transparent conductive layer 50 on the surface of the second semiconductor layer 23.

[0122] The transparent conductive layer 50 is located outside the groove.

[0123] For example, the transparent conductive layer 50 is an indium tin oxide layer or an indium zinc oxide layer.

[0124] For example, the thickness of the transparent conductive layer 50 is between 100 angstroms and 300 angstroms. For instance, the thickness of the transparent conductive layer 50 is 200 angstroms.

[0125] Step S12: A passivation layer 30 is formed on the surface of the epitaxial layer 20.

[0126] like Figure 6 As shown, the passivation layer 30 has a first through hole 31 that extends through the passivation layer 30.

[0127] The process of preparing the passivation layer 30 may specifically include the following steps:

[0128] The first step is to form a first silicon oxide layer on the surface of the epitaxial layer 20.

[0129] The second step is to form a plurality of spaced metal blocks 420 on the surface of the first silicon oxide layer to obtain the second reflective layer 42.

[0130] The third step is to form a second silicon oxide layer covering the second reflective layer 42 on the surface of the first silicon oxide layer, and to form a first through hole 31 penetrating the first silicon oxide layer on the surface of the second silicon oxide layer.

[0131] The first through hole 31 and the metal block 420 are arranged alternately. That is, the first through hole 31 and the metal block 420 do not overlap, thus avoiding the first through hole 31 being exposed to the metal block 420, which could lead to a short circuit.

[0132] like Figure 6 As shown, the passivation layer 30 formed has a second reflective layer 42 inside, that is, the second reflective layer 42 is located between the surface of the passivation layer 30 away from the epitaxial layer 20 and the surface close to the epitaxial layer 20.

[0133] Step S13: Form a first reflective layer 41 on the surface of the epitaxial layer 20.

[0134] like Figure 7 As shown, a first reflective layer 41 is formed on the surface of the passivation layer 30 away from the epitaxial layer 20. The first reflective layer 41 is connected to the transparent conductive layer 50 through a first via 31, and the surface of the first reflective layer 41 away from the epitaxial layer 20 has a recess 410 that exposes the passivation layer 30.

[0135] In this configuration, the metal block 420 corresponds one-to-one with the recess 410, and the orthographic projection of the recess 410 on the surface of the epitaxial layer 20 is located within the orthographic projection of the corresponding metal block 420 on the surface of the epitaxial layer 20.

[0136] Step S14: Form a protective layer 43 on the surface of the passivation layer 30.

[0137] like Figure 2 As shown, the protective layer 43 is located on the surface of the first reflective layer 41 away from the epitaxial layer 20, inside the recess 410, and on the surface of the passivation layer 30 away from the epitaxial layer 20.

[0138] The following steps may also be included after step S14:

[0139] First, a first insulating layer 51 covering the protective layer 43 is formed on the surface of the passivation layer 30, the first insulating layer 51 is etched and a via hole exposing the protective layer 43 and the bottom of the groove is formed; then, at least two electrodes 60 are formed on the surface of the first insulating layer 51, a part of the electrodes 60 are connected with the first semiconductor layer 21 in the groove through the via hole, and the other part of the electrodes 60 are connected with the protective layer 43 through the via hole; then, a second insulating layer 52 covering the electrodes 60 is formed on the surface of the first insulating layer 51, the second insulating layer 52 is etched and a via hole exposing the electrodes 60 is formed; finally, at least two pads 70 are formed on the surface of the second insulating layer 52, the at least two pads 70 are respectively connected with different electrodes 60 through the via hole.

[0140] The above only describes optional embodiments of the present disclosure and is not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode, characterized by, The light emitting diode comprises an epitaxial layer (20), a passivation layer (30), a first reflective layer (41), a second reflective layer (42) and a protective layer (43); The passivation layer (30) is located on the surface of the epitaxial layer (20), and the passivation layer (30) has a first through hole (31) penetrating through the passivation layer (30); The first reflective layer (41) is located on the surface of the passivation layer (30) away from the epitaxial layer (20), and the first reflective layer (41) is electrically connected with the epitaxial layer (20) through the first through hole (31); The second reflective layer (42) is located in the passivation layer (30) and between the surface of the passivation layer (30) away from the epitaxial layer (20) and the surface of the passivation layer (30) close to the epitaxial layer (20); The surface of the first reflective layer (41) away from the epitaxial layer (20) has a recess hole (410) exposing the passivation layer (30); The orthogonal projection of the second reflective layer (42) on the surface of the epitaxial layer (20) overlaps with the orthogonal projection of the recess hole (410) on the surface of the epitaxial layer (20); The protective layer (43) is located at least in the recess hole (410) and the surface of the first reflective layer (41) away from the epitaxial layer (20).

2. The light emitting diode of claim 1, wherein, The orthogonal projection of the recess hole (410) on the surface of the epitaxial layer (20) is located within the orthogonal projection of the second reflective layer (42) on the surface of the epitaxial layer (20).

3. The light emitting diode of claim 2, wherein, The surface of the first reflective layer (41) has a plurality of spaced recess holes (410); The second reflective layer (42) wraps a plurality of spaced metal blocks (420), the metal blocks (420) correspond one-to-one to the recess holes (410), and the orthogonal projection of the recess hole (410) on the surface of the epitaxial layer (20) is located within the orthogonal projection of the corresponding metal block (420) on the surface of the epitaxial layer (20).

4. The light emitting diode of claim 3, wherein, The first reflective layer (41) and the second reflective layer (42) each comprise an Ag layer; or, The first reflective layer (41) and the second reflective layer (42) each comprise an adhesion metal layer and an Ag layer, and the adhesion metal layer is located on at least one surface of the Ag layer.

5. The light emitting diode of claim 4, wherein, The adhesion metal layer comprises a Ti layer.

6. The light emitting diode according to any one of claims 1 to 5, wherein, The light emitting diode further comprises a transparent conductive layer (50) located between the epitaxial layer (20) and the passivation layer (30), the first through hole (31) exposes the transparent conductive layer (50), and the first reflective layer (41) is connected with the transparent conductive layer (50) through the first through hole (31).

7. The light emitting diode of claim 1, wherein, The area of the orthogonal projection of the part of the protective layer (43) located in the recess hole (410) on the surface of the epitaxial layer (20) is greater than the area of the orthogonal projection of the part of the protective layer (43) located on the surface of the first reflective layer (41) on the surface of the epitaxial layer (20).

8. A method of fabricating a light emitting diode, characterized by, The preparation method comprises: preparing an epitaxial layer (20); A passivation layer (30) and a second reflective layer (42) are formed on the surface of the epitaxial layer (20), the passivation layer (30) has a first through hole (31) penetrating the passivation layer (30), and the second reflective layer (42) is located in the passivation layer (30) and between the surface of the passivation layer (30) away from the epitaxial layer (20) and the surface of the passivation layer (30) close to the epitaxial layer (20); A first reflective layer (41) is formed on the surface of the epitaxial layer (20), the first reflective layer (41) is electrically connected with the epitaxial layer (20) through the first through hole (31), and the surface of the first reflective layer (41) away from the epitaxial layer (20) has a recess hole (410) exposing the passivation layer (30), and the orthographic projection of the second reflective layer (42) on the surface of the epitaxial layer (20) overlaps the orthographic projection of the recess hole (410) on the surface of the epitaxial layer (20); A protective layer (43) is formed in the recess hole (410) and the surface of the first reflective layer (41) away from the epitaxial layer (20).

9. The production method according to claim 8, characterized by, Forming a passivation layer (30) and a second reflective layer (42) on the surface of the epitaxial layer (20) includes: Forming a first silicon oxide layer on the surface of the epitaxial layer (20); Forming a plurality of spaced metal blocks (420) on the surface of the first silicon oxide layer to obtain the second reflective layer (42), the metal blocks (420) correspond to the recess holes (410) one by one, and the orthographic projection of the recess hole (410) on the surface of the epitaxial layer (20) is located within the orthographic projection of the corresponding metal block (420) on the surface of the epitaxial layer (20); Forming a second silicon oxide layer covering the second reflective layer (42) on the surface of the first silicon oxide layer, and forming a first through hole (31) penetrating the first silicon oxide layer on the surface of the second silicon oxide layer, the first through hole (31) is spaced apart from the metal blocks (420).

Images