Display panel and display device

Abstract

The invention discloses a display panel and a display device.The display panel comprises a display area, the display area comprises a first display area and a second display area located on the side, in the second direction, of the first display area, and the display panel further comprises a substrate; the array layer comprises a plurality of first pixel circuit units and second pixel units which are located in the first display area, and a first functional circuit unit which is at least partially located in the second display area; the light-emitting layer comprises a first light-emitting unit located in the first display area and a second light-emitting unit located in the second display area; wherein the first pixel circuit unit is used for driving the first light-emitting unit and comprises a first subunit and a second subunit, and the length of the first subunit is smaller than that of the second subunit in the second direction. According to the display panel provided by the embodiment of the invention, the length of the second subunit is shortened, and a part of space is reserved in the second display area, so that at least part of the first functional circuit unit is located in the second display area, the area of the frame area is reduced, and a narrow frame is realized.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Flat display panels such as Organic Light Emitting Display (OLED) and display panels using light emitting diode (LED) devices have the advantages of high image quality, power saving, thin body and wide application range. They are widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, desktop computers, etc., becoming the mainstream in display devices.

[0003] However, the performance of current display panels still needs to be improved. Summary of the invention

[0004] Embodiments of the present application provide a display panel and a display device, which can reduce the area of ​​the frame region of the display panel, thereby achieving a narrow frame of the display panel.

[0005] In a first aspect, a display panel is provided according to an embodiment of the present application, wherein the display panel comprises a display area, the display area comprises a first display area and a second display area located at least on one side of the first display area along a second direction, the display panel further comprising: a substrate; an array layer, arranged on one side of the substrate, comprising a plurality of first pixel circuit units and second pixel circuit units located in the first display area and a first functional circuit unit at least partially located in the second display area; a light-emitting layer, arranged on a side of the array layer away from the substrate, comprising a first light-emitting unit located in the first display area and a second light-emitting unit located in the second display area; wherein the first pixel circuit unit is used to drive the first light-emitting unit, and the first pixel circuit unit comprises a first subunit and a second subunit, and the length of the first subunit along the second direction is less than the length of the second subunit along the second direction.

[0006] According to one aspect of the embodiments of the present application, the second pixel circuit unit is used to drive the second light emitting unit, and the first subunit is located on a side of the second subunit close to the second display area.

[0007] According to one aspect of an embodiment of the present application, a plurality of first pixel circuit units are arranged along a first direction to form a driving row, a plurality of second pixel circuit units are arranged along the first direction to form a virtual row, and the first direction intersects with the second direction.

[0008] According to one aspect of an embodiment of the present application, at least one driving row is located on the side of the virtual row facing the second display area, and the driving row located on the side of the virtual row facing the second display area is used to drive the first light-emitting unit located on the side of the virtual row facing the second display area.

[0009] According to one aspect of an embodiment of the present application, a plurality of first subunits are arranged along a first direction to form a first drive row, a plurality of second subunits are arranged along the first direction to form a second drive row, and the first drive row is located on a side of the second drive row close to the second display area.

[0010] According to one aspect of an embodiment of the present application, at least one first driving row is located on a side of the virtual row facing the second display area, and is used to drive a first light-emitting unit located on a side of the virtual row facing the second display area.

[0011] According to one aspect of the embodiment of the present application, the virtual row is arranged between two adjacent first driving rows.

[0012] According to one aspect of the embodiment of the present application, the number of virtual rows is one row.

[0013] According to one aspect of the embodiment of the present application, the number of the first driving rows is four.

[0014] According to one aspect of an embodiment of the present application, the first functional circuit unit includes an electrostatic release circuit unit, and multiple electrostatic release circuit units are distributed in sequence in the second display area along the first direction. The first functional circuit unit also includes a multiplexer unit, and multiple multiplexers are distributed in sequence in the second display area along the first direction.

[0015] According to one aspect of an embodiment of the present application, a second display area is arranged on both sides of the first display area along the second direction, an electrostatic release circuit unit is arranged in the second display area on one side of the first display area along the second direction, and a multiplexer unit is arranged in the second display area on the other side of the first display area along the second direction.

[0016] According to one aspect of the embodiments of the present application, the first functional circuit unit is located within the second display area.

[0017] According to one aspect of the embodiment of the present application, a size of the second display area in the second direction is 100 μm.

[0018] According to one aspect of an embodiment of the present application, the first functional circuit unit also includes a column driving circuit unit, and multiple column driving circuit units are distributed in sequence in the second display area along the first direction. The first functional circuit unit also includes a multiplexer unit, and multiple multiplexers are distributed in sequence in the second display area along the first direction.

[0019] According to one aspect of an embodiment of the present application, a second display area is arranged on both sides of the first display area along the second direction, the column driving circuit unit is arranged in the second display area on one side of the first display area along the second direction, and the multiplexer unit is arranged in the second display area on the other side of the first display area along the second direction.

[0020] According to one aspect of the embodiments of the present application, the first functional circuit unit is located within the second display area.

[0021] According to one aspect of the embodiment of the present application, a size of the second display area in the second direction is 100 μm.

[0022] According to one aspect of an embodiment of the present application, the display area also includes a third display area located on at least one side of the first display area along the first direction, the light-emitting layer also includes a third light-emitting unit located in the third display area, the second pixel circuit unit is used to drive the third light-emitting unit, and the array layer also includes a plurality of second functional circuit units at least partially located in the third display area.

[0023] According to one aspect of an embodiment of the present application, a plurality of first pixel circuit units are arranged along the second direction to form a driving column, and a plurality of second pixel circuit units are arranged along the second direction to form a dummy column.

[0024] According to one aspect of an embodiment of the present application, at least one row of driving columns is located on the side of the virtual column facing the third display area, and at least one driving column located on the side of the virtual column facing the third display area is used to drive the first light-emitting unit located on the side of the virtual column facing the third display area.

[0025] According to one aspect of the embodiments of the present application, the second pixel circuit units are arranged along the second direction to form a plurality of virtual columns, the number of the virtual columns is at least four, and the same number of driving columns are arranged between two adjacent virtual columns.

[0026] According to one aspect of the embodiment of the present application, four driving columns are spaced between two adjacent dummy columns.

[0027] According to one aspect of an embodiment of the present application, the second functional circuit unit includes an embedded gate circuit unit, and the embedded gate circuit units are arranged in sequence in the third display area along the second direction.

[0028] According to one aspect of the embodiments of the present application, the second functional circuit unit is located within the third display area.

[0029] According to one aspect of the embodiment of the present application, a size of the third display area along the first direction is 400 μm.

[0030] According to one aspect of the embodiment of the present application, the third light-emitting unit further includes an anode, and the anodes of at least two third light-emitting units are interconnected.

[0031] According to one aspect of the embodiments of the present application, the third light-emitting unit includes a first type of light-emitting unit, a second type of light-emitting unit and a third type of light-emitting unit of different colors, the first type of light-emitting unit and the second type of light-emitting unit are alternately arranged along the second direction to form a first pixel column, a plurality of third type of light-emitting units are arranged along the second direction to form a second pixel column, and the first pixel column and the second pixel column are alternately arranged along the first direction; wherein the anodes of at least one of at least one first type of light-emitting unit from two first pixel columns arranged at intervals, at least one second type of light-emitting unit from two first pixel columns arranged at intervals, and at least one third type of light-emitting unit from two second pixel columns arranged at intervals are interconnected;

[0032] According to one aspect of an embodiment of the present application, two anodes of the first type of light-emitting units from two first pixel columns respectively set at intervals are interconnected, two anodes of the second type of light-emitting units from two first pixel columns respectively set at intervals are interconnected, and two anodes of the third type of light-emitting units from two second pixel columns respectively set at intervals are interconnected.

[0033] According to one aspect of the embodiments of the present application, the display panel further includes a shielding layer, which is disposed between the array layer and the light-emitting unit, and the shielding layer is at least partially located in the second display area.

[0034] According to one aspect of the embodiments of the present application, the shielding layer is located in the display area.

[0035] According to one aspect of the embodiment of the present application, the shielding layer further includes openings corresponding one-to-one to the orthographic projections of the first light-emitting unit and the second light-emitting unit on the array layer.

[0036] According to one aspect of the embodiments of the present application, the display panel further includes a planarization layer disposed on a side of the shielding layer away from the substrate, and the light emitting unit and the shielding layer are insulated by the planarization layer.

[0037] According to one aspect of an embodiment of the present application, it also includes at least one isolation portion arranged in the border area, the border area is arranged around the display area, and the isolation portion is arranged around the light-emitting unit in a closed ring shape.

[0038] According to one aspect of an embodiment of the present application, the isolation portion further includes a first section, a second section, and a third section sequentially arranged in a direction away from the substrate, and an orthographic projection of the second section on the substrate is located within the orthographic projections of the first section and the third section on the substrate.

[0039] According to one aspect of an embodiment of the present application, the display panel includes a plurality of isolation portions, and the plurality of isolation portions are distributed at intervals in a direction away from the display area.

[0040] In a second aspect, a display device is provided according to an embodiment of the present application, comprising a display panel provided in any one of the embodiments of the first aspect.

[0041] The display panel and display device provided in the embodiments of the present application are characterized in that the display panel shortens the length of the second subunit of the first pixel circuit unit along the second direction, frees up at least part of the space in the second display area, so that the first functional circuit unit is at least partially located in the second display area, thereby reducing the area of ​​the border area originally used to place the first functional circuit unit, thereby realizing a narrow border of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The features, advantages and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings.

[0043] Figure 1 It is a planar structural diagram of an array substrate of a display panel in the prior art;

[0044] Figure 2 is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present application;

[0045] Figure 3 yes Figure 2 A partial enlarged view of the arrangement structure of the light-emitting layer of the display panel in the middle P area;

[0046] Figure 4 yes Figure 2 A partial enlarged view of the array layer and part of the light-emitting layer structure of the display panel in the middle P area;

[0047] Figure 5 yes Figure 3 Sectional view at AA in the middle;

[0048] Figure 6 yes Figure 2 A partial enlarged view of the arrangement structure of the light-emitting layer of the display panel in the middle Q region;

[0049] Figure 7 yes Figure 2 A partial enlarged view of the array layer and part of the light-emitting layer structure of the display panel in the middle Q area;

[0050] Figure 8 yes Figure 6 Sectional view at the middle BB;

[0051] Fig. 9 yes Figure 6 A schematic diagram of the local enlarged structure of the N region;

[0052] Fig.10 yes Figure 2 Cross-sectional view at CC.

[0053] in:

[0054] 100-display panel;

[0055] AA-display area; AA1-first display area; AA2-second display area; AA3-third display area; NA-frame area;

[0056] 10-substrate;

[0057] 20-array layer; U1-first pixel circuit unit; U11-first subunit; U12-second subunit; U2-second pixel circuit unit; U3-first functional circuit unit; U4-second functional circuit unit;

[0058] 21-driving row; 211-first driving row; 212-second driving row; 22-virtual row;

[0059] 23 - driving column; 24 - dummy column; 25 - second conductive trace; 26 - third conductive trace;

[0060] 30-light-emitting layer; EU1-first light-emitting unit; EU2-second light-emitting unit; EU3-third light-emitting unit; EU31-first type light-emitting unit; EU32-second type light-emitting unit; EU33-third type light-emitting unit; 31-anode; 32-first pixel column; 33-second pixel column;

[0061] 40-shielding layer; 41-opening;

[0062] 50-planarization layer;

[0063] 60-isolation part; 61-first subdivision; 62-second subdivision; 63-third subdivision;

[0064] X-first direction; Y-second direction.

[0065] In the drawings, the same reference numerals are used for the same components. The drawings are not drawn to scale. DETAILED DESCRIPTION

[0066] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating examples of the present application. In the accompanying drawings and the following description, at least some of the known structures and technologies are not shown to avoid unnecessary ambiguity in the present application; and, for clarity, the size of some structures may be exaggerated. In addition, the features, structures or characteristics described below may be combined in one or more embodiments in any suitable manner.

[0067] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the sentence "comprise..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0068] The directional words appearing in the following description are all directions shown in the figures, and do not limit the specific structure of the display panel and display device of this application. In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0069] Figure 1 The diagram shows a planar structural diagram of an array substrate of a display panel in the prior art.

[0070] In display products such as mobile phones, tablet computers, personal display devices, etc., the pursuit of narrow borders has become an important research direction. In addition to improving the borders of display products from the perspective of packaging technology, the redesign of array circuits also has certain benefits for achieving narrow borders of display products.

[0071] In the prior art, the narrow frame solution achieved by improving the packaging process is actually to improve the process capability, maximize the use of space by reducing the space required for circuit routing and cutting packaging, or achieve narrow frame through bending process. However, the bending process has certain requirements on the material, thickness and flexibility of the film layer that constitutes the internal structure of the display product, and improving the process capability to achieve narrow frame will greatly reduce the process yield, affecting production efficiency.

[0072] In the process solution for narrow bezels, reducing the size of the turning angles at the four corners of the display product has become a key technical node that needs to be broken through. The main reason for limiting the further reduction of the turning angles is that the array circuit occupies a certain space on the four edges of the display product, making it impossible to further narrow the bezel. When the solution is to directly adjust the array circuit located on the four edges, in addition to considering the problem of space layout, it is also necessary to consider the connection problem of the signal lines related to the adjusted array circuit.

[0073] See also Figure 1 In the related art, in addition to the pixel driving circuits arranged in the display area, the non-display area surrounding the display area is used to accommodate other array circuits. The non-display areas on both sides of the display area along the first direction X, i.e., the left and right non-display areas, are used to accommodate the embedded gate circuits (GIP) arranged in the array, and the non-display areas on both sides of the display area along the second direction Y, i.e., the upper non-display area and the lower non-display area, the upper non-display area is used to accommodate the electrostatic discharge circuit (ESD) arranged in the array, and the lower non-display area is used to accommodate the multiplexer (Demux) arranged in the array or the column distribution circuit (CT) in some other display products. The display product is also provided with an emitting common terminal wiring (Emitting Light VSS, ELVSS) on the side of the GIP circuit and the ESD circuit away from the display area, and an emitting power supply wiring (Emitting Light VDD, ELVDD) is also provided on the side of the Demux circuit or the CT circuit close to the display area. The Demux circuit or the CT circuit is also connected to the driver chip (Integrated Circuit, IC) on the side away from the display area.

[0074] In the prior art, the space occupied by the circuit in the non-display area and the pixel driving circuit in the display area in the array circuit interferes with each other, and the circuit in the non-display area cannot be moved closer to the display area, so the frame cannot be further narrowed.

[0075] Due to the inherent circuits and wiring that occupy a certain space in the existing process capabilities and the frame position, the non-display area cannot be further compressed, and the frame of the display product cannot be further narrowed. Among them, it is more difficult to compress the non-display area on both sides of the display area along the second direction Y.

[0076] In order to solve the above problems and for technical considerations, the applicant proposed a new display panel and display device.

[0077] Figure 2FIG. 1 shows a schematic diagram of a planar structure of a display panel 100 provided in an embodiment of the present application. Figure 3 The light emitting layer 30 arrangement structure of the display panel 100 in the P region is shown. Figure 4 The structure of the array layer 20 and part of the light emitting layer 30 of the display panel 100 in the P region is shown. Figure 5 The cross-sectional structure of the display panel 100 along the AA direction is shown.

[0078] See also Figures 2 to 5 In a first aspect, an embodiment of the present application provides a display panel 100, wherein the display panel 100 includes a display area AA, wherein the display area AA includes a first display area AA1 and a second display area AA2 located on at least one side of the first display area AA1 along a second direction Y, and the display panel 100 also includes a substrate 10, an array layer 20 and a light-emitting layer 30.

[0079] The array layer 20 is disposed on one side of the substrate 10, and includes a plurality of first pixel circuit units U1 and second pixel circuit units U2 located in the first display area AA1 and a first functional circuit unit U3 at least partially located in the second display area AA2;

[0080] The light emitting layer 30 is disposed on a side of the array layer 20 away from the substrate 10 , and includes a first light emitting unit EU1 located in the first display area AA1 and a second light emitting unit EU2 located in the second display area AA2 .

[0081] The first pixel circuit unit U1 is used to drive the first light emitting unit EU1, and the first pixel circuit unit U1 includes a first subunit U11 and a second subunit U12. The length of the first subunit U11 along the second direction Y is smaller than the length of the second subunit U12 along the second direction Y.

[0082] The display panel 100 provided in the embodiment of the present application shortens the length of the second subunit U12 of the first pixel circuit unit U1 along the second direction, frees up at least part of the space in the second display area AA2, so that the first functional circuit unit U3 is at least partially located in the second display area AA2, thereby reducing the area of ​​the border area NA originally used to place the first functional circuit unit U3, thereby realizing a narrow border of the display panel 100.

[0083] Optionally, the first display area AA1 covers most of the central area of ​​the display area AA, and the second display area AA2 arranged on at least one side of the first display area AA1 along the second direction Y covers an edge area of ​​the display area AA in the second direction Y.

[0084] Optionally, the second display area AA2 is only disposed on one side of the first display area AA1 along the second direction Y.

[0085] Optionally, the second display area AA2 is disposed on two opposite sides of the first display area AA1 along the second direction Y.

[0086] There are many ways to set the substrate 10. The substrate 10 may include a base material and multiple supporting layers arranged on the base material. The substrate 10 mainly plays a supporting role, and other film layers are stacked on the substrate 10 in sequence. The stacking arrangement mentioned here means that other film layers are arranged in sequence along the thickness direction of the substrate 10.

[0087] The substrate 10 may include a variety of film layer structures, and the specific film layer structure composition of the substrate 10 is not limited in the embodiment of the present application. In addition, the thickness direction of other film layers located on one side of the substrate 10 is usually consistent with the thickness direction of the substrate 10 itself. Therefore, for the convenience of description, the thickness direction of the substrate 10 or the thickness direction of other film layers mentioned in the embodiments of the present application are all in the same direction.

[0088] In the array layer 20, the first pixel circuit unit U1 arranged in the first display area AA1 includes a first sub-unit U11 whose length is compressed along the second direction Y. Therefore, the display area AA can make room for part of the space in the second direction Y to accommodate the first functional circuit unit U3. The first functional circuit unit U3 originally located in the border area NA can be at least partially located in the second display area AA2, thereby further narrowing the width of the border area NA.

[0089] Narrowing the width of the border area NA can be understood as that when the first functional circuit unit U3 is at least partially located in the second display area AA2, the excess space of the border area NA away from the display area AA can be cut away, thereby further narrowing the width of the border area NA.

[0090] In the light emitting layer 30 , the first light emitting unit EU1 located in the first display area AA1 is driven by the first pixel circuit unit U1 .

[0091] In the embodiment of the present application, since the arrangement of the first pixel circuit unit U1, the second pixel circuit unit U2 and the first functional circuit unit U3 in the array layer 20 is changed, the first pixel circuit unit U1 used to drive the first light-emitting unit EU1 is no longer arranged one-to-one with the first light-emitting unit EU1 along the thickness direction of the array layer 20.

[0092] There is a certain offset between the first pixel circuit unit U1 and the first light emitting unit EU1 in the second direction Y. Therefore, the first pixel circuit unit U1 and the first light emitting unit EU1 need to be overlapped by a conductive trace along the second direction Y.

[0093] However, since a first conductive trace needs to be arranged between each first pixel circuit unit U1 and the first light-emitting unit EU1, and the first pixel circuit unit U1 and the first light-emitting unit EU1 are arranged in a plurality of tight arrays, the first conductive traces arranged on the same layer in the same direction may be arranged too densely, which may also cause partial short-circuit defects in the array circuits, thereby affecting the display effect.

[0094] Optionally, the first conductive trace may be disposed on the same layer as the anode 31 of the first light emitting unit EU1 .

[0095] Optionally, the first conductive trace may be disposed in the same layer as the transparent metal layer in the array layer 20 .

[0096] Optionally, the first conductive trace may be disposed in the same layer as the metal trace layer in the array layer 20 .

[0097] Optionally, multiple first conductive traces can be arranged in the same layer as the anode 31 of the first light-emitting unit EU1, the transparent metal layer in the array layer 20, and at least two of the metal trace layers, so that the arrangement spacing of the conductive traces in the same direction is increased, reducing short circuit defects in the array circuit and improving the display effect.

[0098] See also Figure 4 In some embodiments, the second pixel circuit unit U2 is used to drive the second light emitting unit EU2, and the first sub-unit U11 is located on a side of the second sub-unit U12 close to the second display area AA2.

[0099] In these embodiments, the array layer 20 is compressed along the second direction Y by the first sub-unit U11 at the edge of the first display area AA1 close to the second display area AA2 to make room for at least part of the first functional circuit unit U3 .

[0100] The second pixel circuit unit U2 for driving the second light emitting unit EU2 in the second display area AA2 is located in the first display area AA1. The array layer 20 does not need to be provided with a pixel driving circuit for driving the second light emitting unit EU2 in the second display area AA2, which can further free up space for the second display area AA2.

[0101] Optionally, the first conductive trace connecting the first light-emitting unit EU1 and the first pixel circuit unit U1 and the second conductive trace 25 connecting the second light-emitting unit EU2 and the second pixel circuit unit U2 are arranged in different layers. Even if the second conductive trace 25 connecting the second light-emitting unit EU2 and the second pixel circuit unit U2 spans the first display area AA1 and the second display area AA2, it is not easy to have a short circuit defect with other conductive traces in the same direction, thereby improving the reliability of the display panel 100.

[0102] Optionally, the first conductive trace connecting the first light-emitting unit EU1 and the first pixel circuit unit U1 and the second conductive trace 25 connecting the second light-emitting unit EU2 and the second pixel circuit unit U2 are respectively arranged on the same layer as the anode 31 of the first light-emitting unit EU1 and the second light-emitting unit EU2, the metal layer in the array layer 20, and the transparent metal layer in the array layer 20.

[0103] See also Figure 4 In some optional embodiments, a plurality of first pixel circuit units U1 are arranged along a first direction X to form a driving row 21, and a plurality of second pixel circuit units U2 are arranged along the first direction X to form a virtual row 22, and the first direction X intersects with the second direction Y.

[0104] In these optional embodiments, the first pixel circuit unit U1 and the second pixel circuit unit U2 are arranged in a row, which further compresses and saves space and facilitates the second display area AA2 to accommodate at least part of the first functional circuit unit U3.

[0105] Optionally, for clarity of description, the first direction X and the second direction Y are perpendicular to each other.

[0106] The directions are defined as the first direction X and the second direction Y for convenience of description. The embodiment of the present application does not limit the specific settings of the first direction X and the second direction Y. It only needs to ensure that the first direction X and the second direction Y intersect and are not in the same or opposite directions.

[0107] See also Figure 4 In some optional embodiments, at least one driving row 21 is located on the side of the virtual row 22 facing the second display area AA2, and the driving row 21 located on the side of the virtual row 22 facing the second display area AA2 is used to drive the first light-emitting unit EU1 located on the side of the virtual row 22 facing the second display area AA2.

[0108] In these optional embodiments, at least one driving row 21 is arranged on the side of the virtual row 22 facing the second display area AA2 and is used to drive the first light-emitting unit EU1 in the corresponding area, which can shorten the length of the first conductive trace, reduce the voltage drop caused by the length of the first conductive trace, and improve the display effect.

[0109] In addition to the fact that insufficient spacing between the multiple first conductive traces may easily cause short circuit defects, if the offset between the first light-emitting unit EU1 and the first pixel circuit unit U1 is too large and the length of the first conductive trace is too long, it may also cause a large voltage drop in the driving voltage supplied by the array layer 20 to the light-emitting layer 30, which will also affect the display effect.

[0110] In this embodiment, by setting at least one driving row 21 on the side of the virtual row 22 facing the second display area AA2 and the driving row 21 being used to drive the first light-emitting unit EU1 of the corresponding area, at least the offset between the driving row 21 and the corresponding driven first light-emitting unit EU1 can be reduced, thereby shortening the length of part of the first conductive trace, further reducing the voltage drop, and improving the display effect.

[0111] Optionally, a first conductive trace for connecting a driving row 21 disposed on the side of the virtual row 22 facing the second display area AA2 and a corresponding first light-emitting unit EU1, a first conductive trace for connecting a driving row 21 disposed on the side of the virtual row 22 away from the second display area AA2 and a corresponding first light-emitting unit EU1, and a second conductive trace 25 for connecting the virtual row 22 and the second light-emitting unit EU2 are respectively disposed in different layers, thereby further reducing short circuit defects between the conductive traces and improving the display effect.

[0112] Optionally, the first conductive trace or the second conductive trace 25 for connecting the driving row 21 arranged on the side of the virtual row 22 toward the second display area AA2 and the corresponding first light-emitting unit EU1, the first conductive trace for connecting the driving row 21 arranged on the side of the virtual row 22 away from the second display area AA2 and the corresponding first light-emitting unit EU1, and the second conductive trace 25 for connecting the virtual row 22 and the second light-emitting unit EU2 can be respectively arranged on the same layer as the anode 31 of the first light-emitting unit EU1 and the second light-emitting unit EU2, the metal layer of the array layer 20, and the transparent metal layer of the array layer 20.

[0113] Optionally, multiple virtual rows 22 may be arranged at intervals between the driving rows 21. The driving row 21 between two adjacent virtual rows 22 drives the first light-emitting unit EU1 in the corresponding area, which can further shorten the length of the first conductive trace, thereby further reducing the voltage drop and improving the display effect.

[0114] See also Figure 4 In some embodiments, a plurality of first subunits U11 are arranged along the first direction X to form a first driving row 211, a plurality of second subunits U12 are arranged along the first direction X to form a second driving row 212, and the first driving row 211 is located on a side of the second driving row 212 close to the second display area AA2.

[0115] In these embodiments, the first subunit U11 whose length is compressed along the second direction Y is arranged along the first direction X to form the first driving row 211, and the arrangement is more compact. The array layer 20 can further leave some space at the edge of the first display area AA1 close to the second display area AA2, so that the second display area AA2 can further accommodate the first functional circuit unit U3.

[0116] See also Figure 4 In some optional embodiments, at least one first driving row 211 is located on the side of the virtual row 22 facing the second display area AA2, and is used to drive the first light-emitting unit EU1 located on the side of the virtual row 22 facing the second display area AA2.

[0117] In these optional embodiments, the first drive row 211 is arranged on the side of the virtual row 22 facing the second display area AA2. Since the length of the first drive row 211 along the second direction Y is compressed, even if the first drive row 211 is not directly opposite to the first light-emitting unit EU1 in the corresponding area, there is a certain offset between the center position of the first drive row 211 and the center position of the first light-emitting unit EU1 in the corresponding area. The length of the first conductive trace connecting the first drive row 211 and the first light-emitting unit EU1 in the corresponding area can be further shortened, thereby further reducing the voltage drop and improving the display effect.

[0118] Optionally, when the first light emitting unit EU1 in the corresponding area covers the first driving row 211 , it is not necessary to arrange the first conductive trace between the first light emitting unit EU1 and the first driving row 211 , so as to further improve the display effect.

[0119] See also Figure 4 In some optional embodiments, the virtual row 22 is disposed between two adjacent first driving rows 211 .

[0120] In these optional embodiments, the first driving row 211 is formed by compressing the length along the second direction Y. The obtained part of the extra space not only facilitates the second display area AA2 to accommodate the first functional circuit unit U3, but also can make room for the virtual row 22 to be set between two adjacent rows of the first driving rows 211. The length of the first conductive traces of the two adjacent rows of the first driving rows 211 can be shortened, further shortening the overall length of the first conductive traces, thereby further reducing the voltage drop and improving the display effect.

[0121] See also Figure 4 In some optional embodiments, the number of virtual rows 22 is one row.

[0122] In these optional embodiments, the length of the second display area AA2 required to accommodate the first functional circuit unit U3 along the second direction Y is the length of a virtual row 22 along the second direction Y, so only one virtual row 22 is needed to drive the second light-emitting unit EU2 located in the second display area AA2.

[0123] See also Figure 4 In some optional embodiments, the number of the first driving rows 211 is four.

[0124] In these optional embodiments, four first drive rows 211 are obtained by compressing the length of four drive rows 21 along the second direction Y, which can make room in the first display area AA1 for the length of one virtual row 22 along the second direction Y. Therefore, the length of one virtual row 22 along the second direction Y can be made room in the second display area AA2, so that the second display area AA2 has space to accommodate the first functional circuit unit U3.

[0125] In some embodiments, the first functional circuit unit U3 includes an electrostatic release circuit unit, and multiple electrostatic release circuit units are distributed in sequence in the second display area AA2 along the first direction X. The first functional circuit unit U3 also includes a multiplexer unit, and multiple multiplexer units are distributed in sequence in the second display area AA2 along the first direction X.

[0126] In these embodiments, the first functional circuit unit U3 may include an electrostatic discharge circuit unit (ESD) and a demultiplexer unit (Demux). The ESD unit and the Demux unit are sequentially distributed in the second display area AA2 along the first direction X, and are arranged compactly to save space.

[0127] In some optional embodiments, the second display area AA2 is arranged on both sides of the first display area AA1 along the second direction Y, the electrostatic release circuit unit is arranged in the second display area AA2 on one side of the first display area AA1 along the second direction Y, the electrostatic release circuit unit is arranged in the second display area AA2 on one side of the first display area AA1 along the second direction Y, and the multiplexer unit is arranged in the second display area AA2 on the other side of the first display area AA1 along the second direction Y.

[0128] In these optional embodiments, the ESD unit and the Demux unit are respectively arranged in two second display areas AA2 on both sides of the first display area AA1 along the second direction Y. The two are arranged separately, so that the first functional circuit units U3 for different functions can be arranged separately, and the circuit partitioning in the array layer 20 is more reasonable, which is convenient for wiring management.

[0129] In some optional embodiments, the first functional circuit unit U3 is located within the second display area AA2.

[0130] In these optional embodiments, the space freed by shortening the length of the first subunit U11 along the second direction Y can enable the first functional circuit unit U3 to be completely located within the second display area AA2, thereby achieving a borderless design.

[0131] In some optional embodiments, the size of the second display area AA2 in the second direction Y is 100 μm.

[0132] In these optional embodiments, the size of the second display area AA2 along the second direction Y only needs to be 100 μm to accommodate the first functional circuit unit U3 .

[0133] In some embodiments, the first functional circuit unit U3 also includes a column driving circuit unit, and multiple column driving circuit units are distributed in sequence in the second display area AA2 along the first direction X. The first functional circuit unit U3 is distributed in sequence in the second display area AA2 along the first direction X. The first functional circuit unit U3 also includes a multiplexer unit, and multiple multiplexers are distributed in sequence in the second display area AA2 along the first direction X.

[0134] In these embodiments, the first functional circuit unit U3 may include an electrostatic discharge circuit unit (ESD) and a column driver circuit unit (CT). The ESD unit and the CT unit are sequentially distributed in the second display area AA2 along the first direction X, and are compactly arranged to save space.

[0135] In some optional embodiments, a second display area AA2 is arranged on both sides of the first display area AA1 along the second direction Y, the column driving circuit unit is arranged in the second display area AA2 on one side of the first display area AA1 along the second direction Y, and the multiplexer unit is arranged in the second display area AA2 on the other side of the first display area AA1 along the second direction.

[0136] In these optional embodiments, the ESD unit and the CT unit are respectively arranged in two second display areas AA2 on both sides of the first display area AA1 along the second direction Y. The two are arranged separately, so that the first functional circuit units U3 for different functions can be arranged separately, and the circuit partitioning in the array layer 20 is more reasonable, which is convenient for wiring management.

[0137] In some optional embodiments, the first functional circuit unit U3 is located within the second display area AA2.

[0138] In these optional embodiments, the space freed by shortening the length of the first subunit U11 along the second direction Y can enable the first functional circuit unit U3 to be completely located within the second display area AA2, thereby achieving a borderless design.

[0139] In some optional embodiments, the size of the second display area AA2 in the second direction Y is 100 μm.

[0140] In these optional embodiments, the size of the second display area AA2 along the second direction Y only needs to be 100 μm to accommodate the first functional circuit unit U3 .

[0141] Figure 6shows the arrangement structure of the light emitting layer 30 of the Q region display panel 100, Figure 7 The array layer 20 and part of the light emitting layer 30 structure of the Q region display panel 100 are shown. Figure 8 The cross-sectional structure of the display panel 100 along the BB direction is shown.

[0142] See also Figures 6 to 8 In some embodiments, the display area AA also includes a third display area AA3 located on at least one side of the first display area AA1 along the first direction X, the light-emitting layer 30 also includes a third light-emitting unit EU3 located in the third display area AA3, the second pixel circuit unit U2 is used to drive the third light-emitting unit EU3, and the array layer 20 also includes a plurality of second functional circuit units U4 at least partially located in the third display area AA3.

[0143] In these embodiments, the lengths of the first pixel circuit unit U1 and the second pixel circuit unit U2 along the first direction X are compressed as a whole, and the display panel 100 can also accommodate part of the second functional circuit unit U4 in the third display area AA3, thereby further reducing the area of ​​the border area NA originally used to place the second functional circuit unit U4, and further realizing a narrow border of the display panel 100.

[0144] The third display area AA3 disposed on at least one side of the first display area AA1 along the first direction X covers an edge area of ​​the display area in the first direction X.

[0145] Optionally, the third display area AA3 is only disposed on one side of the first display area AA1 along the first direction X.

[0146] Optionally, the third display area AA3 is disposed on two opposite sides of the first display area AA1 along the first direction X.

[0147] In the array layer 20, the lengths of the first pixel circuit unit U1 and the second pixel circuit unit U2 arranged in the first display area AA1 along the first direction X are compressed as a whole. Therefore, the display area AA can make some space in the first direction X to accommodate the first functional circuit unit U3, and the first functional circuit unit U3 originally located in the border area NA can be at least partially located in the second display area AA2, thereby further narrowing the width of the border area NA.

[0148] In some optional embodiments, a plurality of first pixel circuit units U1 are arranged along the second direction Y to form a driving column 23 , and a plurality of second pixel circuit units U2 are arranged along the second direction Y to form a dummy column 24 .

[0149] In these optional embodiments, the first pixel circuit unit U1 and the second pixel circuit unit U2 are arranged in a column, which further compresses and saves space and facilitates the third display area AA3 to accommodate at least part of the second functional circuit unit U4.

[0150] In some optional embodiments, at least one driving column 23 is located on the side of the virtual column 24 facing the third display area AA3, and at least one driving column 23 located on the side of the virtual column 24 facing the third display area AA3 is used to drive the first light-emitting unit EU1 located on the side of the virtual column 24 facing the third display area AA3.

[0151] In these optional embodiments, at least one row of driving columns 23 is arranged on the side of the virtual column 24 facing the third display area AA3 and is used to drive the first light-emitting unit EU1 in the corresponding area, which can shorten the length of the first conductive trace, reduce the voltage drop caused by the length of the first conductive trace, and improve the display effect.

[0152] In this embodiment, by setting at least one driving column 23 on the side of the virtual column 24 facing the third display area AA3 and the driving column 23 being used to drive the first light-emitting unit EU1 of the corresponding area, at least the offset between the driving column 23 and the corresponding driven first light-emitting unit EU1 can be reduced, thereby shortening the length of part of the first conductive trace, further reducing the voltage drop, and improving the display effect.

[0153] In some optional embodiments, the second pixel circuit units U2 are arranged along the second direction Y to form a plurality of dummy columns 24 , the number of the dummy columns 24 is at least four, and the same number of driving columns 23 are arranged between two adjacent dummy columns 24 .

[0154] In these optional embodiments, the length of the third display area AA3 required to accommodate the second functional circuit unit U4 along the first direction X is the length of four virtual columns 24 along the first direction X. Therefore, at least four virtual columns 24 are required to drive the third light-emitting unit EU3 located in the third display area AA3. Multiple virtual columns 24 are arranged at intervals between the driving columns 23. The driving column 23 between two adjacent virtual columns 24 drives the first light-emitting unit EU1 in the corresponding area, which can further shorten the length of the first conductive trace, thereby further reducing the voltage drop and improving the display effect.

[0155] In some optional embodiments, four driving columns 23 are spaced between two adjacent dummy columns 24 .

[0156] In these optional embodiments, by compressing the length of four drive columns 23 along the first direction X, the length of one virtual column 24 along the first direction X can be made available in the first display area AA1, so that the length of four virtual columns 24 along the first direction X can be made available in the second display area AA2, so that the third display area AA3 has space to accommodate the second functional circuit unit U4.

[0157] In some optional embodiments, the second functional circuit unit U4 includes embedded gate circuit units, and the embedded gate circuit units are arranged in sequence in the third display area AA3 along the second direction.

[0158] In these optional embodiments, the second functional circuit unit U4 may include an embedded gate circuit unit (GateIn Panel, GIP), and the GIP units are sequentially distributed in the third display area AA3 along the second direction Y, with a compact arrangement to save more space.

[0159] In some optional embodiments, the second functional circuit unit U4 is located within the third display area AA3.

[0160] In these optional embodiments, by shortening the length of the first pixel circuit unit U1 and the second pixel circuit unit U2 along the first direction X, the second functional circuit unit U4 can be completely located within the third display area AA3, thereby achieving a borderless design.

[0161] In some optional embodiments, a size of the third display area AA3 along the first direction X is 400 μm.

[0162] In these optional embodiments, the size of the third display area AA3 along the second direction Y only needs to be 400 μm to accommodate the second functional circuit unit U4 .

[0163] Fig. 9 Shows Figure 7 The local structure of the N region in .

[0164] See also Fig. 9 In some embodiments, the third light emitting unit EU3 further includes an anode 31 , and the anodes 31 of at least two third light emitting units EU3 are interconnected.

[0165] In these embodiments, by interconnecting the anodes 31 of at least two of the third light-emitting units EU3 located in the third display area AA3 and controlling multiple third light-emitting units EU3 through one anode 31, the number of third conductive traces 26 connecting the second pixel circuit unit U2 and the anode 31 of the third light-emitting unit EU3 is further reduced, thereby reducing the short-circuit defects between the third conductive traces 26 and improving the display effect.

[0166] The third light emitting unit EU3 in the third display area AA3 at the edge of the display area, even if a plurality of third light emitting units EU3 are controlled by one anode 31 so that the overall resolution of the third display area AA3 is slightly lower than that of the first display area AA1, does not affect the overall display effect.

[0167] In some optional embodiments, the third light-emitting unit EU3 includes a first type light-emitting unit EU31, a second type light-emitting unit EU32 and a third type light-emitting unit EU33 of different colors, the first type light-emitting unit EU31 and the second type light-emitting unit EU32 are alternately arranged along the second direction Y to form a first pixel column 32, a plurality of third type light-emitting units EU33 are arranged along the second direction Y to form a second pixel column 33, and the first pixel column 32 and the second pixel column 33 are alternately arranged along the first direction X;

[0168] Among them, the anodes 31 of at least one first-type light-emitting unit EU31 from two first pixel columns 32 respectively arranged at intervals, at least one second-type light-emitting unit EU32 from two first pixel columns 32 respectively arranged at intervals, and at least one third-type light-emitting unit EU33 from two second pixel columns 33 respectively arranged at intervals are interconnected.

[0169] In these optional embodiments, the anodes 31 of the first type light emitting unit EU31 , the second type light emitting unit EU32 and the third type light emitting unit EU33 of different colors are respectively interconnected, so that the display effect of the third display area AA3 is more uniform.

[0170] Optionally, the first type of light-emitting unit EU31 is a red pixel light-emitting unit, the second type of light-emitting unit EU32 is a blue pixel light-emitting unit, and the third type of light-emitting unit EU33 is a green light-emitting unit. The red and blue light-emitting units are arranged in sequence along the second direction Y to form a first pixel column 32, and the green light-emitting units are arranged in sequence along the second direction Y to form a second pixel column 33. The green light-emitting units and the red and blue light-emitting units are arranged in different pixel columns. Such an arrangement can reduce the problem of color overlap or light mixing to a certain extent.

[0171] In some optional embodiments, two anodes 31 of the first type light-emitting units EU31 from two first pixel columns 32 respectively set at intervals are interconnected, two anodes 31 of the second type light-emitting units EU32 from two first pixel columns 32 respectively set at intervals are interconnected, and two anodes 31 of the third type light-emitting units EU33 from two second pixel columns 33 respectively set at intervals are interconnected.

[0172] In these optional embodiments, the anodes 31 of the two third columns of light emitting units in the two second pixel columns 33, a total of four anodes 31, are interconnected into one anode 31, further reducing the number of conductive traces.

[0173] The anodes 31 of a first-type light-emitting unit EU31 and a second-type light-emitting unit EU32 from two columns of first pixel columns 32 are interconnected, and the anodes 31 of two third-column light-emitting units from two columns of second pixel columns 33 are interconnected. The anodes 31 of a total of eight light-emitting units in one pixel group are interconnected and merged into three, further reducing the number of conductive traces.

[0174] Optionally, the anode 31 lines connecting the anodes 31 of the first type of light-emitting units EU31, the anode 31 lines connecting the anodes 31 of the second type of light-emitting units EU32, and the anode 31 lines connecting the anodes 31 of the third type of light-emitting units EU33 are respectively arranged on the same layer as the anode 31, the metal layer of the array layer 20 and the transparent metal layer of the array layer 20, so as to avoid short circuit defects between the anode 31 lines on the same layer due to too dense anode 31 lines.

[0175] See also Figure 5 and Figure 8 In some embodiments, the display panel 100 further includes a shielding layer 40 , which is disposed between the array layer 20 and the light-emitting unit, and the shielding layer 40 is at least partially located in the second display area AA2 .

[0176] In these embodiments, a shielding layer 40 covering at least the second display area AA2 is provided between the array layer 20 and the light emitting unit, thereby shielding the signal crosstalk between the first functional circuit unit U3 and the anode 31 of the second light emitting unit EU2 in the second display area AA2.

[0177] Optionally, the shielding layer 40 may be provided at the same layer as the metal layer in the array layer 20 to save process costs.

[0178] Optionally, the shielding layer 40 may be provided at the same layer as the transparent metal layer in the array layer 20 to save process costs.

[0179] In some optional embodiments, the shielding layer 40 is located in the display area AA.

[0180] In these optional embodiments, the shielding layer 40 covers the entire display area AA, further shielding the signal crosstalk between the anode 31 of the first light emitting unit EU1 in the first display area AA1 and the first pixel circuit unit U1 and the second pixel circuit unit U2, thus achieving better shielding effect.

[0181] In some optional embodiments, the shielding layer 40 further includes openings 41 corresponding one-to-one to the orthographic projections of the first light emitting unit EU1 and the second light emitting unit EU2 on the array layer 20 .

[0182] In these optional embodiments, the shielding layer 40 is provided with an opening 41 to facilitate the passage of connecting wires between the first pixel circuit unit U1 and the first light-emitting unit EU1 and between the second pixel circuit unit U2 and the second light-emitting unit EU2 in the array layer 20, thereby preventing short circuit defects between the shielding layer 40 and the connecting wires.

[0183] Optionally, the connecting wire includes at least one conductive wire, so that the offset first pixel circuit unit U1 and the first light emitting unit EU1 and the second pixel circuit unit U2 and the second light emitting unit EU2 can still be connected.

[0184] In some optional embodiments, the display panel 100 further includes a planarization layer 50 disposed on a side of the shielding layer 40 away from the substrate 10 , and the light emitting unit and the shielding layer 40 are insulated by the planarization layer 50 .

[0185] In these optional embodiments, by setting a planarization layer 50, the side of the shielding layer 40 away from the array layer 20 is flattened, which can facilitate the process steps of continuing to prepare the light-emitting layer 30 on the array layer 20, and can also insulate the shielding layer 40 from the light-emitting layer 30 to prevent short-circuit defects.

[0186] Fig.10 The cross-sectional structure along the CC direction is shown.

[0187] See also Fig.10 In some embodiments, the display panel 100 further includes at least one isolation portion 60 disposed in the border area NA, the border area NA is disposed around the display area, and the isolation portion 60 is disposed around the light-emitting unit in a closed ring shape.

[0188] In these embodiments, the isolation portion 60 is located in the frame area NA instead of the display area AA, which can isolate water vapor and cracks in the frame area NA, thereby reducing the impact of water vapor intrusion on the luminescent material in the display area AA. Therefore, the embodiment of the present application can improve the problem of water vapor and cracks spreading to the display area AA by providing the isolation portion 60 in the frame area NA, thereby improving the sealing performance of the display panel 100.

[0189] See also Fig.10 In some optional embodiments, the isolation portion 60 also includes a first division 61, a second division 62 and a third division 63 which are arranged in sequence along a direction away from the substrate 10, and the orthographic projection of the second division 62 on the substrate 10 is located within the orthographic projections of the first division 61 and the third division 63 on the substrate 10.

[0190] In these optional embodiments, in the display panel 100, when preparing the relevant structures of the display area AA of the display panel 100, when the light-emitting material is disposed on the isolation portion 60, since the orthographic projection areas of the first subdivision 61 and the third subdivision 63 on the substrate 10 are larger than the orthographic projection area of ​​the second subdivision 62 on the substrate 10, the first subdivision 61 is partially suspended, and the light-emitting material has difficulty climbing the slope, which may cause the light-emitting material to break between the first subdivision 61 and the second subdivision 62. Alternatively, if the light-emitting material is not thick enough to be continuous on both sides of the isolation portion 60, the light-emitting material may also break, thereby improving the problem of water vapor or cracks diffusing along the functional layer and improving packaging reliability.

[0191] See also Fig.10 In some optional embodiments, the display panel 100 includes a plurality of isolation portions 60 , and the plurality of isolation portions 60 are spaced apart and distributed in a direction away from the display area AA.

[0192] In these optional embodiments, the number of the isolation parts 60 is more than two, and the more than two isolation parts 60 are spaced apart and distributed in a direction away from the display area AA. Providing a plurality of isolation parts 60 can further improve the sealing effect of the display panel 100.

[0193] In a second aspect, an embodiment of the present application provides a display device, comprising the display panel 100 provided in any one of the embodiments of the first aspect.

[0194] Since the display device provided in the embodiment of the present application includes the display panel 100 provided in the above-mentioned first aspect embodiment, the display device provided in the second aspect embodiment of the present application has the beneficial effects of the display panel 100 provided in the first aspect embodiment, which will not be repeated here.

[0195] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced with equivalents without departing from the scope of the present application. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A display panel, characterized in that: The display panel includes a display area, the display area includes a first display area and a second display area located at least one side of the first display area along a second direction, and the display panel further includes: substrate; an array layer, disposed on one side of the substrate, comprising a plurality of first pixel circuit units and second pixel circuit units located in the first display area and a first functional circuit unit at least partially located in the second display area; a light-emitting layer, disposed on a side of the array layer away from the substrate, comprising a first light-emitting unit located in the first display area and a second light-emitting unit located in the second display area; The first pixel circuit unit is used to drive the first light-emitting unit, and the first pixel circuit unit includes a first subunit and a second subunit, and the length of the first subunit along the second direction is smaller than the length of the second subunit along the second direction.

2. The display panel according to claim 1, characterized in that: The second pixel circuit unit is used to drive the second light emitting unit, and the first subunit is located on a side of the second subunit close to the second display area; Preferably, a plurality of the first pixel circuit units are arranged along a first direction to form a driving row, a plurality of the second pixel circuit units are arranged along the first direction to form a virtual row, and the first direction intersects with the second direction; Preferably, at least one of the driving rows is located on the side of the virtual row facing the second display area, and the driving row located on the side of the virtual row facing the second display area is used to drive the first light-emitting unit located on the side of the virtual row facing the second display area.

3. The display panel according to claim 2, characterized in that: A plurality of the first subunits are arranged along the first direction to form a first driving row, a plurality of the second subunits are arranged along the first direction to form a second driving row, and the first driving row is located on a side of the second driving row close to the second display area; Preferably, at least one of the first driving rows is located on a side of the virtual row facing the second display area, and is used to drive the first light-emitting unit located on a side of the virtual row facing the second display area; Preferably, the virtual row is arranged between two adjacent first driving rows; Preferably, the number of the virtual rows is one row; Preferably, the number of the first driving rows is four.

4. The display panel according to claim 1, characterized in that: The first functional circuit unit includes an electrostatic discharge circuit unit, and a plurality of the electrostatic discharge circuit units are sequentially distributed in the second display area along the first direction. The first functional circuit unit also includes a multiplexer unit, and a plurality of the multiplexer units are sequentially distributed in the second display area along the first direction. Preferably, the second display area is arranged on both sides of the first display area along the second direction, the electrostatic discharge circuit unit is arranged in the second display area on one side of the first display area along the second direction, and the multiplexer unit is arranged in the second display area on the other side of the first display area along the second direction; Preferably, the first functional circuit unit is located within the second display area; Preferably, a size of the second display area in the second direction is 100 μm.

5. The display panel according to claim 1, characterized in that: The first functional circuit unit includes a column driving circuit unit, and a plurality of the column driving circuit units are sequentially distributed in the second display area along the first direction. The first functional circuit unit also includes a multiplexer unit, and a plurality of the multiplexer units are sequentially distributed in the second display area along the first direction. Preferably, the second display area is arranged on both sides of the first display area along the second direction, the column driving circuit unit is arranged in the second display area on one side of the first display area along the second direction, and the multiplexer unit is arranged in the second display area on the other side of the first display area along the second direction; Preferably, the first functional circuit unit is located within the second display area; Preferably, a size of the second display area in the second direction is 100 μm.

6. The display panel according to claim 1, characterized in that: The display area further includes a third display area located at least on one side of the first display area along the first direction, the light-emitting layer further includes a third light-emitting unit located in the third display area, the second pixel circuit unit is used to drive the third light-emitting unit, and the array layer further includes a plurality of second functional circuit units at least partially located in the third display area; Preferably, a plurality of the first pixel circuit units are arranged along the second direction to form a driving column, and a plurality of the second pixel circuit units are arranged along the second direction to form a dummy column; Preferably, at least one row of the driving columns is located on a side of the virtual column facing the third display area, and at least one driving column located on a side of the virtual column facing the third display area is used to drive the first light-emitting unit located on a side of the virtual column facing the third display area; Preferably, the second pixel circuit units are arranged along the second direction to form a plurality of virtual columns, the number of the virtual columns is at least four, and the same number of driving columns are arranged between two adjacent virtual columns; Preferably, there are four drive columns between two adjacent virtual columns; Preferably, the second functional circuit unit comprises an embedded gate circuit unit, and the embedded gate circuit units are arranged in sequence in the third display area along the second direction; Preferably, the second functional circuit unit is located within the third display area; Preferably, a size of the third display area along the first direction is 400 μm.

7. The display panel according to claim 6, characterized in that: The third light emitting unit further comprises an anode, and the anodes of at least two of the third light emitting units are interconnected; Preferably, the third light-emitting unit includes a first type of light-emitting unit, a second type of light-emitting unit and a third type of light-emitting unit of different colors, the first type of light-emitting unit and the second type of light-emitting unit are alternately arranged along the second direction to form a first pixel column, a plurality of the third type of light-emitting units are arranged along the second direction to form a second pixel column, and the first pixel column and the second pixel column are alternately arranged along the first direction; wherein the anodes of at least one of at least one of the first-type light-emitting units from two first pixel columns disposed at intervals, at least one of the second-type light-emitting units from two first pixel columns disposed at intervals, and at least one of the third-type light-emitting units from two second pixel columns disposed at intervals are interconnected; Preferably, the two anodes of the first type of light-emitting units respectively coming from two spaced-apart first pixel columns are interconnected, the two anodes of the second type of light-emitting units respectively coming from two spaced-apart first pixel columns are interconnected, and the two anodes of the third type of light-emitting units respectively coming from two spaced-apart second pixel columns are interconnected.

8. The display panel according to claim 1, characterized in that: The display panel further comprises a shielding layer, which is disposed between the array layer and the light-emitting unit, and at least part of the shielding layer is located in the second display area; Preferably, the shielding layer is located in the display area; Preferably, the shielding layer further includes openings corresponding one-to-one to the orthographic projections of the first light-emitting unit and the second light-emitting unit on the array layer; Preferably, the display panel further comprises a planarization layer arranged on a side of the shielding layer away from the substrate, and the light emitting unit and the shielding layer are insulated by the planarization layer.

9. The display panel according to claim 1, characterized in that: It also includes at least one isolation portion arranged in the frame area, the frame area is arranged around the display area, and the isolation portion is arranged around the light-emitting unit in a closed ring shape; Preferably, the isolation portion further comprises a first sub-portion, a second sub-portion and a third sub-portion sequentially arranged in a direction away from the substrate, and an orthographic projection of the second sub-portion on the substrate is located within the orthographic projections of the first sub-portion and the third sub-portion on the substrate; Preferably, the display panel comprises a plurality of the isolation portions, and the plurality of the isolation portions are distributed at intervals in a direction away from the display area.

10. A display device, characterized in that: The invention comprises a display panel as claimed in any one of claims 1 to 9.

Images